From patchwork Fri Oct 8 11:43:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Horatiu Vultur X-Patchwork-Id: 12545057 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C988CC433EF for ; Fri, 8 Oct 2021 11:43:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9156A60F6D for ; Fri, 8 Oct 2021 11:43:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 9156A60F6D Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CWNgSTpfv1ai6rJpquBdsZ+9cE9Lb8E4n5pM85dvIdc=; b=dHeP/AIDFa0Kmq vOjk8gywt5VnxLrnacJVck0VjXhbCYlywlr4PukF2f+psRADmbmtHndTnghoS/NJ1pSA0cmkVNe4K asYT8PaTTLX/xA4iXrN7JsPBTd22z+ufdcckMoYaxgzo4RXhQj+mkGNGlqQrrl1msqJZ9njuo6TAH 8bSKoftZ7602wx5zbCETQfRiBSTQ12NNtdw4hM0tAUI4InQ+rnkO1Nl57Gv4L7kuVbqN5ly9CA8Yh di8VafJ3JxHw5taeFbUD3lWye3q18pfi0lX07sOKW5bNTwv+nYmRQdFP8R97HoVJlvMPWHJronSY+ NvoBGPNuJsXLgzsX3QKA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mYoGV-002a8v-0U; Fri, 08 Oct 2021 11:42:15 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mYoGR-002a8L-Kt for linux-arm-kernel@lists.infradead.org; Fri, 08 Oct 2021 11:42:13 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1633693331; x=1665229331; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=piSrfSWZYNaHQ8NaybCQJKC/qjLwORsGAJLYIc8A40A=; b=p1/RLsGJ+FgqksIN9o3msi+jYGcKXdGt2BzR7SPm6hrTV5kC1D4ImWWH WU+xN8GiKtMrEj5EGjyO2QSrWkZJPgczNfnEFkwXsCF1W/EjJNl3TGEhd nav4icwwEiZ2K3WjyDvR/NzBD1kos0WuijLDLV2xmDRgD+qAjJTTnCzyo 4p9W8BDiZyF8yw7l29opn6i/XmU1/VFGsoKLrGmtOa1+qUk+TlNKaBUr/ iLqdXZIf6pHu+rM05F3y+PNUc7S6IZ83KVLsHF7staV4JLJSeJYwOPhKi dW3yQ5YDQ4Cl684Ve2wYN2NiYDZz9ONSp2sPeA78MtoZNrSqnGEyE2mdJ A==; IronPort-SDR: pcvvAKGcyIUnHpsYCt1fzTxUb+OY/Nn+vqps41DgbER3xhrlIK1FCyA4JcQmW5/Ysx41X+YZ8G oBtBtNdlC74stfcMBKAyMN8EjGG2RUFl3xO+vOCqiJt5fKSwptjtOsrWERWMytITDN98PfVvdY ZqaPHJeK+SMJzJkpq5YeWupQ5kiYQdW6Ziqp5TZ29bpVysOT7dRtHHv4az3PT6IicjEE8hQjqc LdZvA+UTVMMgg18ZlqH9jpaiKxFoLdjnczikcbsgcW2OHR0jnGKG0fOV3bgppz2pUSmGVxwcEt EX+cESWDzz5dcB3NTGQ3qvGA X-IronPort-AV: E=Sophos;i="5.85,357,1624345200"; d="scan'208";a="147282310" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Oct 2021 04:42:10 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 8 Oct 2021 04:42:10 -0700 Received: from soft-dev3-1.microsemi.net (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 8 Oct 2021 04:42:08 -0700 From: Horatiu Vultur To: , , , , , , , CC: Horatiu Vultur Subject: [PATCH 1/2] dt-bindings: reset: Add lan966x support Date: Fri, 8 Oct 2021 13:43:29 +0200 Message-ID: <20211008114330.1328713-2-horatiu.vultur@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211008114330.1328713-1-horatiu.vultur@microchip.com> References: <20211008114330.1328713-1-horatiu.vultur@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211008_044211_716971_8C193673 X-CRM114-Status: UNSURE ( 9.32 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds support for lan966x. Signed-off-by: Horatiu Vultur --- .../devicetree/bindings/reset/microchip,rst.yaml | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml b/Documentation/devicetree/bindings/reset/microchip,rst.yaml index 370579aeeca1..ab7d9cb25b3f 100644 --- a/Documentation/devicetree/bindings/reset/microchip,rst.yaml +++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml @@ -20,7 +20,11 @@ properties: pattern: "^reset-controller@[0-9a-f]+$" compatible: - const: microchip,sparx5-switch-reset + oneOf: + - items: + - const: microchip,sparx5-switch-reset + - items: + - const: microchip,lan966x-switch-reset reg: items: @@ -37,6 +41,10 @@ properties: $ref: "/schemas/types.yaml#/definitions/phandle" description: syscon used to access CPU reset + cuphy-syscon: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: syscon used to access CuPHY + required: - compatible - reg From patchwork Fri Oct 8 11:43:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Horatiu Vultur X-Patchwork-Id: 12545061 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6226C433EF for ; Fri, 8 Oct 2021 11:44:19 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6DCD060F51 for ; Fri, 8 Oct 2021 11:44:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6DCD060F51 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; 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d="scan'208";a="139528893" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Oct 2021 04:42:13 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 8 Oct 2021 04:42:12 -0700 Received: from soft-dev3-1.microsemi.net (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 8 Oct 2021 04:42:10 -0700 From: Horatiu Vultur To: , , , , , , , CC: Horatiu Vultur Subject: [PATCH 2/2] reset: mchp: sparx5: Extend support for lan966x Date: Fri, 8 Oct 2021 13:43:30 +0200 Message-ID: <20211008114330.1328713-3-horatiu.vultur@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211008114330.1328713-1-horatiu.vultur@microchip.com> References: <20211008114330.1328713-1-horatiu.vultur@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211008_044214_051290_715FE218 X-CRM114-Status: GOOD ( 20.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch extends sparx5 driver to support also the lan966x. The process to reset the switch is the same only it has different offsets. Therefore make the driver more generic and add support for lan966x. Signed-off-by: Horatiu Vultur Reviewed-by: Andrew Lunn --- drivers/reset/Kconfig | 2 +- drivers/reset/reset-microchip-sparx5.c | 62 ++++++++++++++++++++++---- 2 files changed, 55 insertions(+), 9 deletions(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index be799a5abf8a..36ce6c8bcf1e 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -116,7 +116,7 @@ config RESET_LPC18XX config RESET_MCHP_SPARX5 bool "Microchip Sparx5 reset driver" - depends on ARCH_SPARX5 || COMPILE_TEST + depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST default y if SPARX5_SWITCH select MFD_SYSCON help diff --git a/drivers/reset/reset-microchip-sparx5.c b/drivers/reset/reset-microchip-sparx5.c index f01e7db8e83b..61897e23441e 100644 --- a/drivers/reset/reset-microchip-sparx5.c +++ b/drivers/reset/reset-microchip-sparx5.c @@ -13,15 +13,21 @@ #include #include -#define PROTECT_REG 0x84 -#define PROTECT_BIT BIT(10) -#define SOFT_RESET_REG 0x00 -#define SOFT_RESET_BIT BIT(1) +struct reset_props { + u32 protect_reg; + u32 protect_bit; + u32 reset_reg; + u32 reset_bit; + u32 cuphy_reg; + u32 cuphy_bit; +}; struct mchp_reset_context { struct regmap *cpu_ctrl; struct regmap *gcb_ctrl; + struct regmap *cuphy_ctrl; struct reset_controller_dev rcdev; + const struct reset_props *props; }; static struct regmap_config sparx5_reset_regmap_config = { @@ -36,17 +42,29 @@ static int sparx5_switch_reset(struct reset_controller_dev *rcdev, struct mchp_reset_context *ctx = container_of(rcdev, struct mchp_reset_context, rcdev); u32 val; + int err; /* Make sure the core is PROTECTED from reset */ - regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT, PROTECT_BIT); + regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg, + ctx->props->protect_bit, ctx->props->protect_bit); /* Start soft reset */ - regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT); + regmap_write(ctx->gcb_ctrl, ctx->props->reset_reg, + ctx->props->reset_bit); /* Wait for soft reset done */ - return regmap_read_poll_timeout(ctx->gcb_ctrl, SOFT_RESET_REG, val, - (val & SOFT_RESET_BIT) == 0, + err = regmap_read_poll_timeout(ctx->gcb_ctrl, ctx->props->reset_reg, val, + (val & ctx->props->reset_bit) == 0, 1, 100); + if (err) + return err; + + if (!ctx->cuphy_ctrl) + return 0; + + /* Release the reset of internal PHY */ + return regmap_update_bits(ctx->cuphy_ctrl, ctx->props->cuphy_reg, + ctx->props->cuphy_bit, ctx->props->cuphy_bit); } static const struct reset_control_ops sparx5_reset_ops = { @@ -111,17 +129,45 @@ static int mchp_sparx5_reset_probe(struct platform_device *pdev) if (err) return err; + /* This resource is required on lan966x, to take the internal PHYs out + * of reset + */ + err = mchp_sparx5_map_syscon(pdev, "cuphy-syscon", &ctx->cuphy_ctrl); + if (err && err != -ENODEV) + return err; + ctx->rcdev.owner = THIS_MODULE; ctx->rcdev.nr_resets = 1; ctx->rcdev.ops = &sparx5_reset_ops; ctx->rcdev.of_node = dn; + ctx->props = device_get_match_data(&pdev->dev); return devm_reset_controller_register(&pdev->dev, &ctx->rcdev); } +static const struct reset_props reset_props_sparx5 = { + .protect_reg = 0x84, + .protect_bit = BIT(10), + .reset_reg = 0x0, + .reset_bit = BIT(1), +}; + +static const struct reset_props reset_props_lan966x = { + .protect_reg = 0x88, + .protect_bit = BIT(5), + .reset_reg = 0x0, + .reset_bit = BIT(1), + .cuphy_reg = 0x10, + .cuphy_bit = BIT(0), +}; + static const struct of_device_id mchp_sparx5_reset_of_match[] = { { .compatible = "microchip,sparx5-switch-reset", + .data = &reset_props_sparx5, + }, { + .compatible = "microchip,lan966x-switch-reset", + .data = &reset_props_lan966x, }, { } };