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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 01/42] x86/mm: Extend cc_attr to include AMD SEV-SNP Date: Fri, 8 Oct 2021 13:04:12 -0500 Message-ID: <20211008180453.462291-2-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f69b822e-3c8f-48ca-ff9f-08d98a862d39 X-MS-TrafficTypeDiagnostic: MN2PR12MB4125: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3276; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: c0oerZWFtPiW01FNpoJi4zEbzoOdZmDuYowSEE1OkvYzgJMCB8qSJpmCgIgNVi6V6j2cpNCdqdkylHL+X941u4RndZxrfaYDHXLcz1YCilvY3ccy9BEydtWCiZ8l0dvqz2VXD7j4Fm1xVHWJTdsTzhIQdixg5z0MPmtT44kVD++i+CIp2gTteyDkbP1CUkwX+IIE1xYscgmsA2M8yo9VD3VwlBAQQv392yIcvRKuV0sNtNveieBoMLdOysOCTbldS9OrRcnWp90e4U8UAKzudKtRP4QxRvUrAhBA8vfXxa0XfIksRR2dQHn0mCX4OSEN9pfL0p+X7o/9Qk33vZqyUXuKaOwWtrosu1Kk3B7eYhg1BFtQ/5H+fc8sMhl1Hpught/fC416D82okPR7nfLaArwjWWywB84nphiaPJdbYOxJ0mJSHBFXgayjPXn57dDoLLn/pDjN2aCEuSx8r524ctuHNYZqIO5yYoSMp02nkn0oCZg6PMTyG+MfZLIfInxazMVS0wqD2qehhZN1C1Lu0rGgAjwlkYo+Q2Xo956wXhMMmN68RijVCQaqgGa5eimTEdX7Ww0G2lN1ZL3vV4FPxmQFBkvJt7S9NjO04GLTVVHJWchL9ZTgIfE3lG7JMK+0OIDfD1oc/8QxwM9RoIunwN5UhjT/jB2Y0xaO2Cv0T2ggW78GKpIciGcA14YSCSnULEjLAdaYeU9pWqhM1Bj2xhGnPFyDH24T4GZGfghp2Hn0qvcUbh1cCB9LWowNHQgd X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(36756003)(86362001)(47076005)(36860700001)(336012)(82310400003)(54906003)(7696005)(44832011)(2616005)(1076003)(356005)(426003)(81166007)(316002)(4326008)(110136005)(2906002)(5660300002)(26005)(7406005)(186003)(16526019)(8676002)(508600001)(70206006)(70586007)(8936002)(7416002)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:13.7243 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f69b822e-3c8f-48ca-ff9f-08d98a862d39 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT004.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4125 Authentication-Results: imf05.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=ghLCfwB8; spf=pass (imf05.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.237.63 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 5B4655079270 X-Stat-Signature: ekigouc5qfd9gs41x4ftimcuqxq8xdhg X-HE-Tag: 1633716317-700216 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: The CC_ATTR_SEV_SNP can be used by the guest to query whether the SNP - Secure Nested Paging feature is active. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cc_platform.c | 2 ++ arch/x86/mm/mem_encrypt.c | 4 ++++ include/linux/cc_platform.h | 8 ++++++++ 4 files changed, 16 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index a7c413432b33..37589da0282e 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -481,8 +481,10 @@ #define MSR_AMD64_SEV 0xc0010131 #define MSR_AMD64_SEV_ENABLED_BIT 0 #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 +#define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) +#define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f diff --git a/arch/x86/kernel/cc_platform.c b/arch/x86/kernel/cc_platform.c index 03bb2f343ddb..e05310f5ec2f 100644 --- a/arch/x86/kernel/cc_platform.c +++ b/arch/x86/kernel/cc_platform.c @@ -50,6 +50,8 @@ static bool amd_cc_platform_has(enum cc_attr attr) case CC_ATTR_GUEST_STATE_ENCRYPT: return sev_status & MSR_AMD64_SEV_ES_ENABLED; + case CC_ATTR_SEV_SNP: + return sev_status & MSR_AMD64_SEV_SNP_ENABLED; default: return false; } diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c index 23d54b810f08..534c2c82fbec 100644 --- a/arch/x86/mm/mem_encrypt.c +++ b/arch/x86/mm/mem_encrypt.c @@ -433,6 +433,10 @@ static void print_mem_encrypt_feature_info(void) if (cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) pr_cont(" SEV-ES"); + /* Secure Nested Paging */ + if (cc_platform_has(CC_ATTR_SEV_SNP)) + pr_cont(" SEV-SNP"); + pr_cont("\n"); } diff --git a/include/linux/cc_platform.h b/include/linux/cc_platform.h index a075b70b9a70..ef5e2209c9b8 100644 --- a/include/linux/cc_platform.h +++ b/include/linux/cc_platform.h @@ -61,6 +61,14 @@ enum cc_attr { * Examples include SEV-ES. */ CC_ATTR_GUEST_STATE_ENCRYPT, + + /** + * @CC_ATTR_SEV_SNP: Guest SNP is active. + * + * The platform/OS is running as a guest/virtual machine and actively + * using AMD SEV-SNP features. + */ + CC_ATTR_SEV_SNP = 0x100, }; #ifdef CONFIG_ARCH_HAS_CC_PLATFORM From patchwork Fri Oct 8 18:04:13 2021 Content-Type: text/plain; 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David Alan Gilbert" , , , , Brijesh Singh , Venu Busireddy , "Borislav Petkov" Subject: [PATCH v6 02/42] x86/sev: Shorten GHCB terminate macro names Date: Fri, 8 Oct 2021 13:04:13 -0500 Message-ID: <20211008180453.462291-3-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e3b1c6f1-87a1-40d0-b44f-08d98a862e46 X-MS-TrafficTypeDiagnostic: MN2PR12MB3374: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: oRPZEvmWlBz3/pdVt2GjV3C1J2kdwUn2b6AZUJT2RCBbi8hke3znAPCa7kWkyRKPqxNbHaL+WQRoyBcvWxJS+zeYnnsUguYn/pulum5FqcEOj3CiSYiMk6ldTYNvhMMkpUe3AeAGLwMSXNLekeCdG5qxB2Zr9GJQUTA+xGqjPJOh3lk2WcASbg6vrMfrFUnSEB9qX+uicEHkOrzAz/gt/Q/mncExVAJo78Nsew3o7J9ji3cAMqVT7cDt7wRLLdYIUk8RBw/yBVu0Y6AwM4rmm3yGc4sxaz1VvNIUvxAUgun7ZwXNKXZ6egWhoNCsen7lkT+udd9wYTGW7UXvHxNg4MB/mf7hTTpRFYUZwhzLl/4iuYnUXPVDV1FC1r83O137nsFDLGXkXWjbONcQGn6HdM5uyWZJJ6qRt4Zlybqo1O0ebCCiT1sdSRPsXZEJOk+3165rIrPpfHEks6Yp36hPyjGb9Kx+DaiG0upYOwQXQMtZnKjBZCMkrmssFAHCQHVp1ZVpSvRDdYEugMPhM8D8/AduIRiPYVJRl3WEwjod4ZELiJ8aDyZjApoIOOY6EjIRfenMQTnILVij2Il8w3W4ajCThyBJ38yUCDNk2Zvrv+KPI+fRvQ89t0V5IMyh+hh8ZyvF/xfiOXWLnj96hm1j5fvarNfg885s1sJpGhtl9tKQBSRfo0Ql/jehS3YAW1S36Jp4T4KDR5nnxfFBS/WUhdGDUt8TtR29HhDPNlxqkroOthgS8vKdBZ/r7q8Ni/77 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(54906003)(110136005)(86362001)(5660300002)(2906002)(316002)(16526019)(82310400003)(2616005)(186003)(426003)(26005)(7416002)(7406005)(336012)(508600001)(1076003)(8676002)(8936002)(7696005)(70206006)(70586007)(4326008)(44832011)(36860700001)(36756003)(356005)(81166007)(47076005)(83380400001)(2101003)(36900700001);DIR:OUT;SFP:1101; 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dmarc=pass (policy=quarantine) header.from=amd.com X-HE-Tag: 1633716319-464906 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Reviewed-by: Venu Busireddy Suggested-by: Borislav Petkov Signed-off-by: Brijesh Singh --- arch/x86/boot/compressed/sev.c | 6 +++--- arch/x86/include/asm/sev-common.h | 4 ++-- arch/x86/kernel/sev-shared.c | 2 +- arch/x86/kernel/sev.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index 670e998fe930..28bcf04c022e 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -122,7 +122,7 @@ static enum es_result vc_read_mem(struct es_em_ctxt *ctxt, static bool early_setup_sev_es(void) { if (!sev_es_negotiate_protocol()) - sev_es_terminate(GHCB_SEV_ES_REASON_PROTOCOL_UNSUPPORTED); + sev_es_terminate(GHCB_SEV_ES_PROT_UNSUPPORTED); if (set_page_decrypted((unsigned long)&boot_ghcb_page)) return false; @@ -175,7 +175,7 @@ void do_boot_stage2_vc(struct pt_regs *regs, unsigned long exit_code) enum es_result result; if (!boot_ghcb && !early_setup_sev_es()) - sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST); + sev_es_terminate(GHCB_SEV_ES_GEN_REQ); vc_ghcb_invalidate(boot_ghcb); result = vc_init_em_ctxt(&ctxt, regs, exit_code); @@ -202,5 +202,5 @@ void do_boot_stage2_vc(struct pt_regs *regs, unsigned long exit_code) if (result == ES_OK) vc_finish_insn(&ctxt); else if (result != ES_RETRY) - sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST); + sev_es_terminate(GHCB_SEV_ES_GEN_REQ); } diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 2cef6c5a52c2..855b0ec9c4e8 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -68,8 +68,8 @@ (((((u64)reason_set) & GHCB_MSR_TERM_REASON_SET_MASK) << GHCB_MSR_TERM_REASON_SET_POS) | \ ((((u64)reason_val) & GHCB_MSR_TERM_REASON_MASK) << GHCB_MSR_TERM_REASON_POS)) -#define GHCB_SEV_ES_REASON_GENERAL_REQUEST 0 -#define GHCB_SEV_ES_REASON_PROTOCOL_UNSUPPORTED 1 +#define GHCB_SEV_ES_GEN_REQ 0 +#define GHCB_SEV_ES_PROT_UNSUPPORTED 1 #define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK) diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index ff1e82ff52d9..007bc25d265c 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -210,7 +210,7 @@ void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code) fail: /* Terminate the guest */ - sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST); + sev_es_terminate(GHCB_SEV_ES_GEN_REQ); } static enum es_result vc_insn_string_read(struct es_em_ctxt *ctxt, diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 4d0d1c2b65e1..9b3b41a7844f 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -1397,7 +1397,7 @@ DEFINE_IDTENTRY_VC_KERNEL(exc_vmm_communication) show_regs(regs); /* Ask hypervisor to sev_es_terminate */ - sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST); + sev_es_terminate(GHCB_SEV_ES_GEN_REQ); /* If that fails and we get here - just panic */ panic("Returned from Terminate-Request to Hypervisor\n"); @@ -1445,7 +1445,7 @@ bool __init handle_vc_boot_ghcb(struct pt_regs *regs) /* Do initial setup or terminate the guest */ if (unlikely(boot_ghcb == NULL && !sev_es_setup_ghcb())) - sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST); + sev_es_terminate(GHCB_SEV_ES_GEN_REQ); vc_ghcb_invalidate(boot_ghcb); From patchwork Fri Oct 8 18:04:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545893 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9ED4FC433FE for ; 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Fri, 8 Oct 2021 13:05:15 -0500 From: Brijesh Singh To: , , , , , , CC: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , "Vitaly Kuznetsov" , Jim Mattson , "Andy Lutomirski" , Dave Hansen , Sergio Lopez , Peter Gonda , "Peter Zijlstra" , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , "Dr . David Alan Gilbert" , , , , Borislav Petkov Subject: [PATCH v6 03/42] x86/sev: Get rid of excessive use of defines Date: Fri, 8 Oct 2021 13:04:14 -0500 Message-ID: <20211008180453.462291-4-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 896dce4a-da8f-40c8-d560-08d98a862feb X-MS-TrafficTypeDiagnostic: BYAPR12MB2999: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: OfA3jWzl5z6EiSzzEhYoGlf+VtchUnNOBkA+5tNSeIrsACTFV3/9dP2kWUCVBzz/yHPCk4+7IOtJXOq5lIpVs1RSWaTx9pY/+hyiLU4bXXxgXjnqAbk6+mJI7xUxESUUUe93OFdIlhcCMVVrZ1jvAWYVP0A+aa1060SW9/MaliHp9U/GzVE5NQ06a3I+Nuokvkh8oJHZqWsq6rMoy50HJF+n9eutOk+9wydXtbUSYMQiwM6MSxx72qm17IxCiphNnfHYgcPEmOQt9mpvOY860u4JJXlHMUiScBREX/xUoctv2cgfDTd7me4gly3mV1NyfcpAlE1v/Fc2HW/kO822K7huqJFQlZJVvgyzCboEhHuF6bBcj59MMgrzKjB6lqleWiQZTlQMUMbyJxtLpUmSftBb6Gma9gI4quOEOaCmNzboVvR/nE5cAeq5HoMnPISz/e2MsBqfouJ+Sy5762L3h0aBeXYKVuXurMfI2W92BpChpa9cCaVWz+LYXvRGTUz9EkQHWOnf626tNx4PrDiJapTH8baZxuhatH9kZ4r8VA9GOssMvbPCkf33lGNgbHoRDPwS8SbLc/YL6/sSt9/GcyA8PT5SRat5Fjl2jFo83OUkFQeen/MLt7sEfQGbyXI69Ults8/BedAlYY3B5YsjRdVns9S9sCHgxWn7t4/gK61nN9LdEjpRlh0hBbvI1RibsZrvLGNnOxVpmDx5pPwkYhbMY74ccdUbs3gOe3FAMPGlyrN12ICFOhQkb9FmPG+ONdmbxEontwIcs98kIhI5eh40bOsQkJbbiwJInZPztnY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(186003)(508600001)(86362001)(8676002)(36860700001)(5660300002)(83380400001)(16526019)(26005)(316002)(110136005)(426003)(54906003)(336012)(8936002)(2616005)(2906002)(4326008)(81166007)(36756003)(44832011)(7406005)(7416002)(47076005)(70206006)(7696005)(82310400003)(356005)(70586007)(1076003)(26583001)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:18.2442 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 896dce4a-da8f-40c8-d560-08d98a862feb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2999 X-Rspamd-Server: rspam01 X-Rspamd-Queue-Id: 083BD2001507 X-Stat-Signature: r5d19wx3iy5w1dsj5r471f8w5f8ch9m6 Authentication-Results: imf26.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=aZTVUYPV; dmarc=pass (policy=quarantine) header.from=amd.com; spf=pass (imf26.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.93.58 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com X-HE-Tag: 1633716322-164565 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Borislav Petkov Remove all the defines of masks and bit positions for the GHCB MSR protocol and use comments instead which correspond directly to the spec so that following those can be a lot easier and straightforward with the spec opened in parallel to the code. Aligh vertically while at it. No functional changes. Signed-off-by: Borislav Petkov --- arch/x86/include/asm/sev-common.h | 51 +++++++++++++++++-------------- 1 file changed, 28 insertions(+), 23 deletions(-) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 855b0ec9c4e8..aac44c3f839c 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -18,20 +18,19 @@ /* SEV Information Request/Response */ #define GHCB_MSR_SEV_INFO_RESP 0x001 #define GHCB_MSR_SEV_INFO_REQ 0x002 -#define GHCB_MSR_VER_MAX_POS 48 -#define GHCB_MSR_VER_MAX_MASK 0xffff -#define GHCB_MSR_VER_MIN_POS 32 -#define GHCB_MSR_VER_MIN_MASK 0xffff -#define GHCB_MSR_CBIT_POS 24 -#define GHCB_MSR_CBIT_MASK 0xff -#define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \ - ((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) | \ - (((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) | \ - (((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) | \ + +#define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \ + /* GHCBData[63:48] */ \ + ((((_max) & 0xffff) << 48) | \ + /* GHCBData[47:32] */ \ + (((_min) & 0xffff) << 32) | \ + /* GHCBData[31:24] */ \ + (((_cbit) & 0xff) << 24) | \ GHCB_MSR_SEV_INFO_RESP) + #define GHCB_MSR_INFO(v) ((v) & 0xfffUL) -#define GHCB_MSR_PROTO_MAX(v) (((v) >> GHCB_MSR_VER_MAX_POS) & GHCB_MSR_VER_MAX_MASK) -#define GHCB_MSR_PROTO_MIN(v) (((v) >> GHCB_MSR_VER_MIN_POS) & GHCB_MSR_VER_MIN_MASK) +#define GHCB_MSR_PROTO_MAX(v) (((v) >> 48) & 0xffff) +#define GHCB_MSR_PROTO_MIN(v) (((v) >> 32) & 0xffff) /* CPUID Request/Response */ #define GHCB_MSR_CPUID_REQ 0x004 @@ -46,27 +45,33 @@ #define GHCB_CPUID_REQ_EBX 1 #define GHCB_CPUID_REQ_ECX 2 #define GHCB_CPUID_REQ_EDX 3 -#define GHCB_CPUID_REQ(fn, reg) \ - (GHCB_MSR_CPUID_REQ | \ - (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \ - (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS)) +#define GHCB_CPUID_REQ(fn, reg) \ + /* GHCBData[11:0] */ \ + (GHCB_MSR_CPUID_REQ | \ + /* GHCBData[31:12] */ \ + (((unsigned long)(reg) & 0x3) << 30) | \ + /* GHCBData[63:32] */ \ + (((unsigned long)fn) << 32)) /* AP Reset Hold */ -#define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 -#define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 +#define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 +#define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 /* GHCB Hypervisor Feature Request/Response */ -#define GHCB_MSR_HV_FT_REQ 0x080 -#define GHCB_MSR_HV_FT_RESP 0x081 +#define GHCB_MSR_HV_FT_REQ 0x080 +#define GHCB_MSR_HV_FT_RESP 0x081 #define GHCB_MSR_TERM_REQ 0x100 #define GHCB_MSR_TERM_REASON_SET_POS 12 #define GHCB_MSR_TERM_REASON_SET_MASK 0xf #define GHCB_MSR_TERM_REASON_POS 16 #define GHCB_MSR_TERM_REASON_MASK 0xff -#define GHCB_SEV_TERM_REASON(reason_set, reason_val) \ - (((((u64)reason_set) & GHCB_MSR_TERM_REASON_SET_MASK) << GHCB_MSR_TERM_REASON_SET_POS) | \ - ((((u64)reason_val) & GHCB_MSR_TERM_REASON_MASK) << GHCB_MSR_TERM_REASON_POS)) + +#define GHCB_SEV_TERM_REASON(reason_set, reason_val) \ + /* GHCBData[15:12] */ \ + (((((u64)reason_set) & 0xf) << 12) | \ + /* GHCBData[23:16] */ \ + ((((u64)reason_val) & 0xff) << 16)) #define GHCB_SEV_ES_GEN_REQ 0 #define GHCB_SEV_ES_PROT_UNSUPPORTED 1 From patchwork Fri Oct 8 18:04:15 2021 Content-Type: text/plain; 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David Alan Gilbert" , , , , Borislav Petkov , Brijesh Singh Subject: [PATCH v6 04/42] x86/head64: Carve out the guest encryption postprocessing into a helper Date: Fri, 8 Oct 2021 13:04:15 -0500 Message-ID: <20211008180453.462291-5-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a51d2e90-7c2b-4d66-66a4-08d98a86307c X-MS-TrafficTypeDiagnostic: MN2PR12MB3535: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RY4XK6v8CxPo2OpCraQ4Uo4iGRZDbMG5koLM57oQEXlLVgkAiejpuN+DUSsLWD3Rtg/UWaaOQgB66hcDPIMiz0t1xymFUnK2Vy8bEBFQzbB77TJXA44tbbaTp5tcu9oY//I27sxLBhZzKM/Ezfb2d64zU847DvfnYxOmIgefxshZ+4F99Ww1BIpOBByVUUiOJPu39rGC8F82ckwEzyiiruYh5NqAfhw04saT4SSV7M4kxcRM+tFm/344jNEtCRO06nGcH5LJez6ePVt+pkZIo8Zn9btJl7E1DRWFW02TI5aW2waIX3tVXik4YBkskjtC8nA0Jf/KLtvrJ0CzrJ7m/KKRqI12BcMKm8DQoiNKdGqoRQh1/oWdtjCCQKdBl0pol9kezvkMLCIXTycJePAHA2MHUf+YN2dKKDCh1TyLVOJI6L8zGo4uuSrrO/wDu+m+PxX1sQWKLAfXyFy4pKm9f2uTwlH0Vh3Pc533g6uXqOLnqPo+VADA9O/lPcKWDct8Hn52jljtFimh1K7GJAg1yDOjyzw2bADy7pd26prCEAe7Tvd0l8f0Su7AxynRy0g5cVKq43ZO7UbU+HsbxPzqj8ONUsazAKKTXamTzsvguW+9Ng/zF5ZGqTsHLz6ziECBEHtKkvu7FhR12D4Lkv2ZzRklzQp/CnmPZLCJfv4UQqmxdgpnE5dAPTFc3Ul5OJBEt+tcp3xLCXe41TfVyvpd60pEIgDkk0nQITxfx/W7n87Xus5lV/05lo4UYtfcMsDT X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(8676002)(2616005)(47076005)(2906002)(110136005)(54906003)(81166007)(82310400003)(426003)(1076003)(5660300002)(356005)(36756003)(336012)(316002)(4326008)(508600001)(70206006)(36860700001)(8936002)(86362001)(70586007)(26005)(83380400001)(44832011)(7696005)(7416002)(16526019)(186003)(7406005)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:19.1916 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a51d2e90-7c2b-4d66-66a4-08d98a86307c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3535 X-Rspamd-Queue-Id: 535B65078477 X-Stat-Signature: 4rom1rqzcgxwqhhcnarrh4etuxmt658m Authentication-Results: imf05.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=pck95LE0; spf=pass (imf05.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.237.56 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam06 X-HE-Tag: 1633716328-909877 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Borislav Petkov Carve it out so that it is abstracted out of the main boot path. All other encrypted guest-relevant processing should be placed in there. No functional changes. Signed-off-by: Borislav Petkov Signed-off-by: Brijesh Singh --- arch/x86/kernel/head64.c | 60 +++++++++++++++++++++------------------- 1 file changed, 31 insertions(+), 29 deletions(-) diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c index fc5371a7e9d1..3be9dd213dad 100644 --- a/arch/x86/kernel/head64.c +++ b/arch/x86/kernel/head64.c @@ -126,6 +126,36 @@ static bool __head check_la57_support(unsigned long physaddr) } #endif +static unsigned long sme_postprocess_startup(struct boot_params *bp, pmdval_t *pmd) +{ + unsigned long vaddr, vaddr_end; + int i; + + /* Encrypt the kernel and related (if SME is active) */ + sme_encrypt_kernel(bp); + + /* + * Clear the memory encryption mask from the .bss..decrypted section. + * The bss section will be memset to zero later in the initialization so + * there is no need to zero it after changing the memory encryption + * attribute. + */ + if (sme_get_me_mask()) { + vaddr = (unsigned long)__start_bss_decrypted; + vaddr_end = (unsigned long)__end_bss_decrypted; + for (; vaddr < vaddr_end; vaddr += PMD_SIZE) { + i = pmd_index(vaddr); + pmd[i] -= sme_get_me_mask(); + } + } + + /* + * Return the SME encryption mask (if SME is active) to be used as a + * modifier for the initial pgdir entry programmed into CR3. + */ + return sme_get_me_mask(); +} + /* Code in __startup_64() can be relocated during execution, but the compiler * doesn't have to generate PC-relative relocations when accessing globals from * that function. Clang actually does not generate them, which leads to @@ -135,7 +165,6 @@ static bool __head check_la57_support(unsigned long physaddr) unsigned long __head __startup_64(unsigned long physaddr, struct boot_params *bp) { - unsigned long vaddr, vaddr_end; unsigned long load_delta, *p; unsigned long pgtable_flags; pgdval_t *pgd; @@ -276,34 +305,7 @@ unsigned long __head __startup_64(unsigned long physaddr, */ *fixup_long(&phys_base, physaddr) += load_delta - sme_get_me_mask(); - /* Encrypt the kernel and related (if SME is active) */ - sme_encrypt_kernel(bp); - - /* - * Clear the memory encryption mask from the .bss..decrypted section. - * The bss section will be memset to zero later in the initialization so - * there is no need to zero it after changing the memory encryption - * attribute. - * - * This is early code, use an open coded check for SME instead of - * using cc_platform_has(). This eliminates worries about removing - * instrumentation or checking boot_cpu_data in the cc_platform_has() - * function. - */ - if (sme_get_me_mask()) { - vaddr = (unsigned long)__start_bss_decrypted; - vaddr_end = (unsigned long)__end_bss_decrypted; - for (; vaddr < vaddr_end; vaddr += PMD_SIZE) { - i = pmd_index(vaddr); - pmd[i] -= sme_get_me_mask(); - } - } - - /* - * Return the SME encryption mask (if SME is active) to be used as a - * modifier for the initial pgdir entry programmed into CR3. - */ - return sme_get_me_mask(); + return sme_postprocess_startup(bp, pmd); } unsigned long __startup_secondary_64(void) From patchwork Fri Oct 8 18:04:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545895 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E42ABC433FE for ; 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Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , "Vitaly Kuznetsov" , Jim Mattson , "Andy Lutomirski" , Dave Hansen , Sergio Lopez , Peter Gonda , "Peter Zijlstra" , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , "Dr . David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 05/42] x86/sev: Define the Linux specific guest termination reasons Date: Fri, 8 Oct 2021 13:04:16 -0500 Message-ID: <20211008180453.462291-6-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d5ef2a0c-9267-4511-dc6c-08d98a863192 X-MS-TrafficTypeDiagnostic: BY5PR12MB3667: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5mbbceMXCWiBi8p6zpzr2M2LtOWkrGxzBcKYupVImpFmrgyGliR8wERc6eFD8ANyc+m7rlb3FrOfn4CAUyseHjCunpr9DKYKAJ+wdipKsZwIU2bOcBcVQdjZfkmyeJ8SUgLVK6p/9pIPhth3N0lcqP0WpcLkvdApMBtfYbnZ78NudR+fQS1LecmNmqADqd1Kh8flyjOKdiFcoCLwM1WexspHSQ1biOW6sD10nuskcaKaFTEkVbuzGUrcix8+9udlEusFKAMWbeQtQ5EE7P2BWAMCQg/hf32dVQWFVR6m1OLs/n1rMcO3Iri+kB7yLND7y43A1jqi3v8xWDmhNiuTDbCfGxG1wfs0nxH2mwc4w6kawO/q/aKP07HbHizNP3DFw/ONilAxQFFT0Hu/fnUxvLBdc/bG1G54nxIPmdf+Tl2XzE0vMXabTXmtnZ8yCwyxpglUZFWpKi6s7QQEncCkN0JXgil+qYMC/+k1sR3WMffmmqOTyOqvpyxNrokE4ZXAlDxPIV7NdN82rzRu+C7AN35LqHZ7F2EdqsB+xNeuKf8OKnhT32g9V3N6V/2kwFtXNMGH6oPyJYNstclH1VucvuaC9Gs8rEUswbw7Bn5H1z7HoyDpy1QUs81cLE/5kAl2B3On98fApnQrZCDtNSt1zu7MoDCtrvv7/0LnsPcWu68n1hCVMtFJ3WRpzw7+eNe3fDyyS9pmPOks1Ni5r7Su0N8h4ZKfqeSTKNetG/zQujqjMMJysccrLdVgWhkJZHlJ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(70206006)(2906002)(508600001)(4326008)(7416002)(36860700001)(70586007)(82310400003)(47076005)(8936002)(44832011)(356005)(16526019)(186003)(1076003)(81166007)(54906003)(2616005)(110136005)(316002)(26005)(5660300002)(36756003)(8676002)(7696005)(426003)(83380400001)(7406005)(86362001)(336012)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:20.9925 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d5ef2a0c-9267-4511-dc6c-08d98a863192 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3667 X-Rspamd-Queue-Id: CB0557000091 X-Stat-Signature: bd85mn9cieo3ufkbquwhrddpu9zimor1 Authentication-Results: imf27.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=B9Vh8+3L; spf=pass (imf27.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.223.80 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam06 X-HE-Tag: 1633716325-998778 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: GHCB specification defines the reason code for reason set 0. The reason codes defined in the set 0 do not cover all possible causes for a guest to request termination. The reason set 1 to 255 is reserved for the vendor-specific codes. Reseve the reason set 1 for the Linux guest. Define an error codes for reason set 1. While at it, change the sev_es_terminate() to accept the reason set parameter. Signed-off-by: Brijesh Singh --- arch/x86/boot/compressed/sev.c | 6 +++--- arch/x86/include/asm/sev-common.h | 8 ++++++++ arch/x86/kernel/sev-shared.c | 11 ++++------- arch/x86/kernel/sev.c | 4 ++-- 4 files changed, 17 insertions(+), 12 deletions(-) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index 28bcf04c022e..7760959fe96d 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -122,7 +122,7 @@ static enum es_result vc_read_mem(struct es_em_ctxt *ctxt, static bool early_setup_sev_es(void) { if (!sev_es_negotiate_protocol()) - sev_es_terminate(GHCB_SEV_ES_PROT_UNSUPPORTED); + sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_PROT_UNSUPPORTED); if (set_page_decrypted((unsigned long)&boot_ghcb_page)) return false; @@ -175,7 +175,7 @@ void do_boot_stage2_vc(struct pt_regs *regs, unsigned long exit_code) enum es_result result; if (!boot_ghcb && !early_setup_sev_es()) - sev_es_terminate(GHCB_SEV_ES_GEN_REQ); + sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ); vc_ghcb_invalidate(boot_ghcb); result = vc_init_em_ctxt(&ctxt, regs, exit_code); @@ -202,5 +202,5 @@ void do_boot_stage2_vc(struct pt_regs *regs, unsigned long exit_code) if (result == ES_OK) vc_finish_insn(&ctxt); else if (result != ES_RETRY) - sev_es_terminate(GHCB_SEV_ES_GEN_REQ); + sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ); } diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index aac44c3f839c..3278ee578937 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -73,9 +73,17 @@ /* GHCBData[23:16] */ \ ((((u64)reason_val) & 0xff) << 16)) +/* Error codes from reason set 0 */ +#define SEV_TERM_SET_GEN 0 #define GHCB_SEV_ES_GEN_REQ 0 #define GHCB_SEV_ES_PROT_UNSUPPORTED 1 +/* Linux-specific reason codes (used with reason set 1) */ +#define SEV_TERM_SET_LINUX 1 +#define GHCB_TERM_REGISTER 0 /* GHCB GPA registration failure */ +#define GHCB_TERM_PSC 1 /* Page State Change failure */ +#define GHCB_TERM_PVALIDATE 2 /* Pvalidate failure */ + #define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK) #endif diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index 007bc25d265c..a010d6b41a04 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -24,15 +24,12 @@ static bool __init sev_es_check_cpu_features(void) return true; } -static void __noreturn sev_es_terminate(unsigned int reason) +static void __noreturn sev_es_terminate(unsigned int set, unsigned int reason) { u64 val = GHCB_MSR_TERM_REQ; - /* - * Tell the hypervisor what went wrong - only reason-set 0 is - * currently supported. - */ - val |= GHCB_SEV_TERM_REASON(0, reason); + /* Tell the hypervisor what went wrong. */ + val |= GHCB_SEV_TERM_REASON(set, reason); /* Request Guest Termination from Hypvervisor */ sev_es_wr_ghcb_msr(val); @@ -210,7 +207,7 @@ void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code) fail: /* Terminate the guest */ - sev_es_terminate(GHCB_SEV_ES_GEN_REQ); + sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ); } static enum es_result vc_insn_string_read(struct es_em_ctxt *ctxt, diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 9b3b41a7844f..427b1c6d08a8 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -1397,7 +1397,7 @@ DEFINE_IDTENTRY_VC_KERNEL(exc_vmm_communication) show_regs(regs); /* Ask hypervisor to sev_es_terminate */ - sev_es_terminate(GHCB_SEV_ES_GEN_REQ); + sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ); /* If that fails and we get here - just panic */ panic("Returned from Terminate-Request to Hypervisor\n"); @@ -1445,7 +1445,7 @@ bool __init handle_vc_boot_ghcb(struct pt_regs *regs) /* Do initial setup or terminate the guest */ if (unlikely(boot_ghcb == NULL && !sev_es_setup_ghcb())) - sev_es_terminate(GHCB_SEV_ES_GEN_REQ); + sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ); vc_ghcb_invalidate(boot_ghcb); From patchwork Fri Oct 8 18:04:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545897 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 575CCC433F5 for ; Fri, 8 Oct 2021 18:05:30 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 073CD61037 for ; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 06/42] x86/sev: Save the negotiated GHCB version Date: Fri, 8 Oct 2021 13:04:17 -0500 Message-ID: <20211008180453.462291-7-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 10ea1a30-7b69-4ee4-753c-08d98a8632cc X-MS-TrafficTypeDiagnostic: BYAPR12MB2774: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: IXD2g9+FejMW02FPgmDB+F5T3GkR1BC0+iWVsRqVHtmvb/eeBXw85M1ewyM6G9+LsGQ4TaGr0wG14yE5ZGcSrrvPNUKCTHOrI4jF0pFq/WQBzDCuA2CSfbDLcmOdwP2WNsmssgJJaa0sh4szW5ASuzgDpSjqJfIGLchV/QFHD9VFSzXQCYmdRWidbsBboqvtYvxfarwYUwHC6raDL4fmPxNtWKHFoqlm5x0eiLsuLRHkLvzy9tySA+99uCDClQabDyBGOIVRu/WUdG8qU025K78cGobVY3AX7NzNzDfirOZItYv3dHvPtRK1IwsqrYpCPgiX8QyiKtR7fZLN0nup7Ro5/UbePMqtcq63oNHhCaOcXria8TCPMsZU7xlak3HLduMTGK+gZMLnrI+mKg6v/CHGQr6Zh0rRyic439MIHaZmT5zTYQAr/E6iW8NbRbsMdowYPAciW5h1R5eurq3vleaK8CbQvwRY+/TAzE0B0AvzEBhOBcNjYRbbY2/K4cG0IoSZF8KHuaxOpLIMZLIGTlH8tayXiFhx9ZVj26L2f8WpuqZMfK95RIJF0QRcAiFX6yaY/oKKhTLJ5kKYcATw2VELjnnJ8clSYzZUsDjnWl+ZOJZSANRNyphhRyrWvT2rS53Tp1FNxT4M1xcd5zINVAr1yMlp8k7ayHvWOjrw6eLiykt3JCGiIXq0z3i5w7HPUVrNAcwZnDhM3YOGDTwuXV5y8+ojgIP2+hrfq6Uxy5/p+uSfCwf29E2H2NHwNZgC X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(336012)(426003)(7416002)(8676002)(44832011)(2616005)(1076003)(82310400003)(54906003)(47076005)(36756003)(7696005)(83380400001)(4326008)(70206006)(70586007)(316002)(110136005)(8936002)(7406005)(36860700001)(2906002)(81166007)(508600001)(26005)(5660300002)(356005)(16526019)(6666004)(186003)(86362001)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:23.0657 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 10ea1a30-7b69-4ee4-753c-08d98a8632cc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2774 Authentication-Results: imf25.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=vqHRNZeE; spf=pass (imf25.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.92.47 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 0A9C2B000E18 X-Stat-Signature: t1hhquqj3615qfet87xb44dtzw1mz1zq X-HE-Tag: 1633716326-996236 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: The SEV-ES guest calls the sev_es_negotiate_protocol() to negotiate the GHCB protocol version before establishing the GHCB. Cache the negotiated GHCB version so that it can be used later. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/sev.h | 2 +- arch/x86/kernel/sev-shared.c | 17 ++++++++++++++--- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index fa5cd05d3b5b..7ec91b1359df 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -12,7 +12,7 @@ #include #include -#define GHCB_PROTO_OUR 0x0001UL +#define GHCB_PROTOCOL_MIN 1ULL #define GHCB_PROTOCOL_MAX 1ULL #define GHCB_DEFAULT_USAGE 0ULL diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index a010d6b41a04..0eb22528ec87 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -14,6 +14,15 @@ #define has_cpuflag(f) boot_cpu_has(f) #endif +/* + * Since feature negotiation related variables are set early in the boot + * process they must reside in the .data section so as not to be zeroed + * out when the .bss section is later cleared. + * + * GHCB protocol version negotiated with the hypervisor. + */ +static u16 __ro_after_init ghcb_version; + static bool __init sev_es_check_cpu_features(void) { if (!has_cpuflag(X86_FEATURE_RDRAND)) { @@ -51,10 +60,12 @@ static bool sev_es_negotiate_protocol(void) if (GHCB_MSR_INFO(val) != GHCB_MSR_SEV_INFO_RESP) return false; - if (GHCB_MSR_PROTO_MAX(val) < GHCB_PROTO_OUR || - GHCB_MSR_PROTO_MIN(val) > GHCB_PROTO_OUR) + if (GHCB_MSR_PROTO_MAX(val) < GHCB_PROTOCOL_MIN || + GHCB_MSR_PROTO_MIN(val) > GHCB_PROTOCOL_MAX) return false; + ghcb_version = min_t(size_t, GHCB_MSR_PROTO_MAX(val), GHCB_PROTOCOL_MAX); + return true; } @@ -99,7 +110,7 @@ static enum es_result sev_es_ghcb_hv_call(struct ghcb *ghcb, enum es_result ret; /* Fill in protocol and format specifiers */ - ghcb->protocol_version = GHCB_PROTOCOL_MAX; + ghcb->protocol_version = ghcb_version; ghcb->ghcb_usage = GHCB_DEFAULT_USAGE; ghcb_set_sw_exit_code(ghcb, exit_code); From patchwork Fri Oct 8 18:04:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545901 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43E16C433F5 for ; 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Fri, 8 Oct 2021 13:05:22 -0500 From: Brijesh Singh To: , , , , , , CC: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , "Vitaly Kuznetsov" , Jim Mattson , "Andy Lutomirski" , Dave Hansen , Sergio Lopez , Peter Gonda , "Peter Zijlstra" , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , "Dr . David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 07/42] x86/sev: Add support for hypervisor feature VMGEXIT Date: Fri, 8 Oct 2021 13:04:18 -0500 Message-ID: <20211008180453.462291-8-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a2a6dc50-805c-402c-aa17-08d98a863417 X-MS-TrafficTypeDiagnostic: MN2PR12MB3101: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3826; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ITiSXKgSygPMjaXP0E6okn6zY8mjdfVrKUKpI4kFXFDUejqpvvdOIJdzs+AgDmTcJINjFhIG+BDOI4AWcc9czP4RNAF0cX3XJFgvXI92lpYPkuguBKFfegc+DNEsN2DeFnue6f1usF0bX4YYJ6GktWsgK8F/qyVwG0WPWVjBGDzuckXlRzKd3Tk/AttraD9FA4ioyplT68ZXCXW6wxyBKrcfDzZB0bCwd4jiNT9utdE0IukJGOAAZEG7aZ5w0rM3LwnEBODxHH5oPicjBDfKTNkqvPz4laRy1J0gHBcjVxexlXfJdNK8MQ41aSbyT5pldiHOr5c8DMVKce+snXpebPgpW8PSysp0zkW39/OmU1ABWg3VlGTYuMD2HoojX1ycZTwMX0Ovd0l95KPF+7/uIQnMMlUratUEo+dkfIeH/8oqxNB3634uzoAW9wH3bZRfhJCKtStecOtE292XhBQZMc2ICJKAF/jGt4ZpCZLlnbRA7xjdbfbhEYeIcETt3o1F+o1clq9NeIkjtLZBrCYd8bwVxenBfVmBpvlQsvEw4yBKk79yFbQKBTNfyN76OZHd3PGJ/69xI+nHwa/jQfAQvTrIt61Jj+lpvMUTLuuwN+gB8pwAqVThEzoYrRMeA3nylLD21IYwonePA3EUk8q7RxGMPm/9qr4IVbTL4mXVmfTH0fyLrFVvuqLePrZltny6eD7RhHswBxcpZ1kYAGtY/2MUMF2XmJzgwyzSrPOLFpPlfXNPi8pzw8BO6LfHN2Da X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(44832011)(54906003)(82310400003)(336012)(7416002)(8936002)(2616005)(508600001)(7406005)(4326008)(1076003)(426003)(36756003)(5660300002)(36860700001)(6666004)(110136005)(7696005)(86362001)(81166007)(70206006)(186003)(26005)(47076005)(16526019)(70586007)(2906002)(356005)(83380400001)(8676002)(316002)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:25.2213 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a2a6dc50-805c-402c-aa17-08d98a863417 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3101 X-Rspamd-Server: rspam02 X-Rspamd-Queue-Id: D1B953001438 X-Stat-Signature: 5iksaqcnk3ksgkn9xme34y9cowqcnmod Authentication-Results: imf08.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=nqow43rQ; spf=pass (imf08.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.96.77 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-HE-Tag: 1633716330-757535 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Version 2 of GHCB specification introduced advertisement of a features that are supported by the hypervisor. Add support to query the HV features on boot. Version 2 of GHCB specification adds several new NAEs, most of them are optional except the hypervisor feature. Now that hypervisor feature NAE is implemented, so bump the GHCB maximum support protocol version. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/sev-common.h | 3 +++ arch/x86/include/asm/sev.h | 2 +- arch/x86/include/uapi/asm/svm.h | 2 ++ arch/x86/kernel/sev-shared.c | 30 ++++++++++++++++++++++++++++++ 4 files changed, 36 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 3278ee578937..891569c07ed7 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -60,6 +60,9 @@ /* GHCB Hypervisor Feature Request/Response */ #define GHCB_MSR_HV_FT_REQ 0x080 #define GHCB_MSR_HV_FT_RESP 0x081 +#define GHCB_MSR_HV_FT_RESP_VAL(v) \ + /* GHCBData[63:12] */ \ + (((u64)(v) & GENMASK_ULL(63, 12)) >> 12) #define GHCB_MSR_TERM_REQ 0x100 #define GHCB_MSR_TERM_REASON_SET_POS 12 diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 7ec91b1359df..134a7c9d91b6 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -13,7 +13,7 @@ #include #define GHCB_PROTOCOL_MIN 1ULL -#define GHCB_PROTOCOL_MAX 1ULL +#define GHCB_PROTOCOL_MAX 2ULL #define GHCB_DEFAULT_USAGE 0ULL #define VMGEXIT() { asm volatile("rep; vmmcall\n\r"); } diff --git a/arch/x86/include/uapi/asm/svm.h b/arch/x86/include/uapi/asm/svm.h index efa969325ede..b0ad00f4c1e1 100644 --- a/arch/x86/include/uapi/asm/svm.h +++ b/arch/x86/include/uapi/asm/svm.h @@ -108,6 +108,7 @@ #define SVM_VMGEXIT_AP_JUMP_TABLE 0x80000005 #define SVM_VMGEXIT_SET_AP_JUMP_TABLE 0 #define SVM_VMGEXIT_GET_AP_JUMP_TABLE 1 +#define SVM_VMGEXIT_HV_FEATURES 0x8000fffd #define SVM_VMGEXIT_UNSUPPORTED_EVENT 0x8000ffff /* Exit code reserved for hypervisor/software use */ @@ -218,6 +219,7 @@ { SVM_VMGEXIT_NMI_COMPLETE, "vmgexit_nmi_complete" }, \ { SVM_VMGEXIT_AP_HLT_LOOP, "vmgexit_ap_hlt_loop" }, \ { SVM_VMGEXIT_AP_JUMP_TABLE, "vmgexit_ap_jump_table" }, \ + { SVM_VMGEXIT_HV_FEATURES, "vmgexit_hypervisor_feature" }, \ { SVM_EXIT_ERR, "invalid_guest_state" } diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index 0eb22528ec87..8ee27d07c1cd 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -23,6 +23,9 @@ */ static u16 __ro_after_init ghcb_version; +/* Bitmap of SEV features supported by the hypervisor */ +static u64 __ro_after_init sev_hv_features; + static bool __init sev_es_check_cpu_features(void) { if (!has_cpuflag(X86_FEATURE_RDRAND)) { @@ -48,6 +51,30 @@ static void __noreturn sev_es_terminate(unsigned int set, unsigned int reason) asm volatile("hlt\n" : : : "memory"); } +/* + * The hypervisor features are available from GHCB version 2 onward. + */ +static bool get_hv_features(void) +{ + u64 val; + + sev_hv_features = 0; + + if (ghcb_version < 2) + return false; + + sev_es_wr_ghcb_msr(GHCB_MSR_HV_FT_REQ); + VMGEXIT(); + + val = sev_es_rd_ghcb_msr(); + if (GHCB_RESP_CODE(val) != GHCB_MSR_HV_FT_RESP) + return false; + + sev_hv_features = GHCB_MSR_HV_FT_RESP_VAL(val); + + return true; +} + static bool sev_es_negotiate_protocol(void) { u64 val; @@ -66,6 +93,9 @@ static bool sev_es_negotiate_protocol(void) ghcb_version = min_t(size_t, GHCB_MSR_PROTO_MAX(val), GHCB_PROTOCOL_MAX); + if (!get_hv_features()) + return false; + return true; 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Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , "Vitaly Kuznetsov" , Jim Mattson , "Andy Lutomirski" , Dave Hansen , Sergio Lopez , Peter Gonda , "Peter Zijlstra" , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , "Dr . David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 08/42] x86/sev-es: initialize sev_status/features within #VC handler Date: Fri, 8 Oct 2021 13:04:19 -0500 Message-ID: <20211008180453.462291-9-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 27db9027-eae2-420a-048a-08d98a863615 X-MS-TrafficTypeDiagnostic: SN6PR12MB2816: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jHE2kKm7pA8JWjCBhB9VO6n+tbmKXlwqAdqhjFdC97R9poAx0zwh8IBqe9w2hxl5IGrhtcd8Iuf5TPRfXATVnZVrNqKx7/WQfUPX4kIVutNLJ/MFnm0rvguh5RL+4fJtuzmaoVnLZgMnWE1k4MKC/IV27h5PKeP8GQIX7bY7cEd2kd6dplua/1aXgbxIKPDN1VKEu/WULYY6kqCuaJY903R3I2MxEWYXimEDUVQrPxlgVyfzpdU37wPYMOjENXD1bMi4rixxoQ0pWeqKQxo/SgfCEvsTIf33oh7TuWp9KKqPg3nv3w6S1V7OSyurnGjx9QcR4f9UHkCCCatzum8tDcqWDbLT8lNvIU1EhOZCpX9GdEb23qp+J80unytJcdehe2pD6eIQ5x4gy3KR3eylFBzcuErG3ozz2xKTWO2k9CZBBdzrnXTPdFOrlpVwWShGcLlnXfHqxyY7MEVddZAxKgROG91UJTdGH0SZ3N3V/UtzX3s6F41sdRC08BkmBLkoneMRF8D+qNo1hv0qOZb8eP3MSR59KcbxXIIBzj8PEYbsSqYtOCnhFCw7wFn0Km/JfT+u+jDizSYNTba9PjWw3Q9Whg096mH3ihT2e98j7mOxdNfpa8m4YZB8d928mT7qSxHg/IlEIo2rH9mt088X3025SIRqskNAOqA6NfSQByanP3b0TBSJ/bd15GAMQ9m+LmnABvofiwmLmfLparDKLRmDrgc4HIxXbcuGqATB/819sO9/KWT3kthMUX4ZzQYw X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(186003)(110136005)(54906003)(2906002)(26005)(8936002)(7696005)(8676002)(44832011)(70586007)(316002)(426003)(5660300002)(4326008)(16526019)(7406005)(336012)(83380400001)(82310400003)(81166007)(2616005)(47076005)(36860700001)(70206006)(508600001)(1076003)(86362001)(356005)(36756003)(6666004)(7416002)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:28.5594 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 27db9027-eae2-420a-048a-08d98a863615 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2816 X-Rspamd-Queue-Id: 330742878 X-Stat-Signature: y8gc89pbnwnj1mtdsn1zinb7fp177fy7 Authentication-Results: imf22.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=txIak1DW; spf=pass (imf22.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.243.54 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam06 X-HE-Tag: 1633716335-289459 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Michael Roth Generally access to MSR_AMD64_SEV is only safe if the 0x8000001F CPUID leaf indicates SEV support. With SEV-SNP, CPUID responses from the hypervisor are not considered trustworthy, particularly for 0x8000001F. SEV-SNP provides a firmware-validated CPUID table to use as an alternative, but prior to checking MSR_AMD64_SEV there are no guarantees that this is even an SEV-SNP guest. Rather than relying on these CPUID values early on, allow SEV-ES and SEV-SNP guests to instead use a cpuid instruction to trigger a #VC and have it cache MSR_AMD64_SEV in sev_status, since it is known to be safe to access MSR_AMD64_SEV if a #VC has triggered. Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- arch/x86/kernel/sev-shared.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index 8ee27d07c1cd..2796c524d174 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -191,6 +191,20 @@ void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code) if (exit_code != SVM_EXIT_CPUID) goto fail; + /* + * A #VC implies that either SEV-ES or SEV-SNP are enabled, so the SEV + * MSR is also available. Go ahead and initialize sev_status here to + * allow SEV features to be checked without relying solely on the SEV + * cpuid bit to indicate whether it is safe to do so. + */ + if (!sev_status) { + unsigned long lo, hi; + + asm volatile("rdmsr" : "=a" (lo), "=d" (hi) + : "c" (MSR_AMD64_SEV)); + sev_status = (hi << 32) | lo; + } + sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_EAX)); VMGEXIT(); val = sev_es_rd_ghcb_msr(); From patchwork Fri Oct 8 18:04:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545905 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D188C433F5 for ; Fri, 8 Oct 2021 18:05:40 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 2097860F9D for ; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 09/42] x86/sev: Check SEV-SNP features support Date: Fri, 8 Oct 2021 13:04:20 -0500 Message-ID: <20211008180453.462291-10-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a4ca3b02-8edc-4edd-2689-08d98a863891 X-MS-TrafficTypeDiagnostic: MN2PR12MB4157: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lVMgLVl8ijagWv2Ct/uOtn9J2GixkcaxybQCCnto+e9TZalYeRSCt7dmn6WnRiUL21HrFmUOUhgYTlc7pAiOtJgHNzZLzO9w9IefHvlTwnhSJmqakIGwHYLTp5BZsAV3k0Pbris8EfnjprWfqYFm1eg6LHnyBluod8q2ET+7YGiXcVpE3iDQgjNYxZPCcHEkRrwlRcGs7O4prC08StOs+PmtMlXBJkVsrQsO+N+jHU0ZDs1jjOJHpOf+zxBmAgMIxLjAo4Oak7ol35Tr2jqHdmFrkvNpDDCUhaCAWn5G2H4F7ewqsrvi+2IqeqU3tTihODE4xNbSqtr3BzzKqLNS5O5bpN8yhuqNABOvt2CrOzS7EO7Uvo5RnuF/yBKheEfQxp2FHCUFZjVg1ZDKxMIgOCNG7xh2yCQlYAdqJFs9weUNC4Ehv+7/P0ZpDyU8oQHakcMGGI0lPQIdGc1HRtwINDN3WsdaAJE9f+KStmCmOXWLLF5Aw2QiYgIToVZzDwgfIzI8VTiijUyTPoG6gL3f6kMLWt8Qhlaeu/1nqqWBg9gowyuh1BDiVq3k+9iODfyzobkvV/rfzK4NR5e1Q+TRF8AT6ljiOq8jTNIVLbaZtVo/KQe45EY3Ikz4pQOwQFVmmzSq2llhv0vg8jdR162iF4AXowxoVCiwgU5NtlA76ZRBQXl/HI/noBQOBBRFlc8rhLZ/G00qCwzdj9iXUw8wEmDE0hk3nM33pZeHzgIS7xUeD915N3MCL2ZtMdahg+yI X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(54906003)(7416002)(4326008)(44832011)(7406005)(70206006)(36860700001)(8936002)(47076005)(110136005)(5660300002)(6666004)(7696005)(316002)(8676002)(36756003)(70586007)(82310400003)(336012)(508600001)(426003)(2616005)(83380400001)(2906002)(26005)(186003)(16526019)(1076003)(356005)(81166007)(86362001)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:32.7401 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a4ca3b02-8edc-4edd-2689-08d98a863891 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4157 X-Rspamd-Server: rspam03 X-Rspamd-Queue-Id: 7308D1001CBF X-Stat-Signature: wo9dxsub7g96gnmuqib3c8qejhj41arj Authentication-Results: imf07.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=f0NlTBHz; dmarc=pass (policy=quarantine) header.from=amd.com; spf=pass (imf07.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.220.74 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com X-HE-Tag: 1633716337-704011 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Version 2 of the GHCB specification added the advertisement of features that are supported by the hypervisor. If hypervisor supports the SEV-SNP then it must set the SEV-SNP features bit to indicate that the base SEV-SNP is supported. Check the SEV-SNP feature while establishing the GHCB, if failed, terminate the guest. Signed-off-by: Brijesh Singh --- arch/x86/boot/compressed/sev.c | 16 ++++++++++++++-- arch/x86/include/asm/sev-common.h | 3 +++ arch/x86/kernel/sev.c | 8 ++++++-- 3 files changed, 23 insertions(+), 4 deletions(-) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index 7760959fe96d..8b0f892c072b 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -119,11 +119,23 @@ static enum es_result vc_read_mem(struct es_em_ctxt *ctxt, /* Include code for early handlers */ #include "../../kernel/sev-shared.c" -static bool early_setup_sev_es(void) +static inline bool sev_snp_enabled(void) +{ + return sev_status & MSR_AMD64_SEV_SNP_ENABLED; +} + +static bool do_early_sev_setup(void) { if (!sev_es_negotiate_protocol()) sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_PROT_UNSUPPORTED); + /* + * If SEV-SNP is enabled, then check if the hypervisor supports the SEV-SNP + * features. + */ + if (sev_snp_enabled() && !(sev_hv_features & GHCB_HV_FT_SNP)) + sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SNP_UNSUPPORTED); + if (set_page_decrypted((unsigned long)&boot_ghcb_page)) return false; @@ -174,7 +186,7 @@ void do_boot_stage2_vc(struct pt_regs *regs, unsigned long exit_code) struct es_em_ctxt ctxt; enum es_result result; - if (!boot_ghcb && !early_setup_sev_es()) + if (!boot_ghcb && !do_early_sev_setup()) sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ); vc_ghcb_invalidate(boot_ghcb); diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 891569c07ed7..f80a3cde2086 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -64,6 +64,8 @@ /* GHCBData[63:12] */ \ (((u64)(v) & GENMASK_ULL(63, 12)) >> 12) +#define GHCB_HV_FT_SNP BIT_ULL(0) + #define GHCB_MSR_TERM_REQ 0x100 #define GHCB_MSR_TERM_REASON_SET_POS 12 #define GHCB_MSR_TERM_REASON_SET_MASK 0xf @@ -80,6 +82,7 @@ #define SEV_TERM_SET_GEN 0 #define GHCB_SEV_ES_GEN_REQ 0 #define GHCB_SEV_ES_PROT_UNSUPPORTED 1 +#define GHCB_SNP_UNSUPPORTED 2 /* Linux-specific reason codes (used with reason set 1) */ #define SEV_TERM_SET_LINUX 1 diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 427b1c6d08a8..2290fbcc1844 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -631,12 +631,16 @@ static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt) * This function runs on the first #VC exception after the kernel * switched to virtual addresses. */ -static bool __init sev_es_setup_ghcb(void) +static bool __init setup_ghcb(void) { /* First make sure the hypervisor talks a supported protocol. */ if (!sev_es_negotiate_protocol()) return false; + /* If SNP is active, make sure that hypervisor supports the feature. */ + if (cc_platform_has(CC_ATTR_SEV_SNP) && !(sev_hv_features & GHCB_HV_FT_SNP)) + sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SNP_UNSUPPORTED); + /* * Clear the boot_ghcb. The first exception comes in before the bss * section is cleared. @@ -1444,7 +1448,7 @@ bool __init handle_vc_boot_ghcb(struct pt_regs *regs) enum es_result result; /* Do initial setup or terminate the guest */ - if (unlikely(boot_ghcb == NULL && !sev_es_setup_ghcb())) + if (unlikely(!boot_ghcb && !setup_ghcb())) sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ); vc_ghcb_invalidate(boot_ghcb); From patchwork Fri Oct 8 18:04:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545907 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CA50C433FE for ; Fri, 8 Oct 2021 18:05:43 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id D1C4160296 for ; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 10/42] x86/sev: Add a helper for the PVALIDATE instruction Date: Fri, 8 Oct 2021 13:04:21 -0500 Message-ID: <20211008180453.462291-11-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5e40c6e2-dd18-4162-82df-08d98a8639b6 X-MS-TrafficTypeDiagnostic: BY5PR12MB3668: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Uxe+LrwrUTTh5hbf0DpP3+c/Ey/vV+xUKu+HoXTrV7yqoHhKJFdooa6Vx53+0SWQyGgu7dAlWnv2xxzfTCu+KYCXiTf8+V6+pKgq93h+GvN20X3QwgovddwPTE7+Iz8LdT8xRodNACIFjCSX0f801WLy1SPQHv43CXnXmxX64PDXkJxO5RhtcYJJE8PvYfapzGCTWCcENoAU5DkBgV0SYPAZEQFda+dbiF6QdD3sxZPh5K1WfuhTXNqk3BUcZlMVPtUsdSwnSVvSEKKyRX3dIgg/M8bDrco3CSK0hUmhVKD8WvkCR7gD1dNwfJRzRQ4porgYfjX/KODXGceali8N0OZFz6SvwaZUoq74S4IpqnI24wtqJLKJqNS2g/Aj6CHEVmG0bdEi4bbDdfd4WMYMAsoa/LqPyzuMrDUb3YkmiMlaY2/Qlykv6llryUfyMD2/6GVKIz+7WnJAaKwF3RntFn/nNom5VrCuaUetRv+FRHCrrjQKguT9+1wGNrjsK5x07Oexaroy/PoCat3tnd+qERmNP71wpd3r++a62OMDVSo/Jv9/pe1ez/rg1unwi3fk7j/ydMTjPHZ+QFEJ3An8Hx1r0MVvLPFISh6qhy/0hf3lvYZ+d//NpypO9k6YLYUcnbwUvblUWZrEfaGaoVAs72+FYDbCTqKKOSlx+2wHz3mdnX//SLH+lzOifB8PFjMFANchgvGMo6cZ7vwuPj3XuS/s2W3Oq8p8PIHMOZ0Bad4UW3lj6VsvPIYJy2WO2582 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(70206006)(81166007)(2906002)(356005)(70586007)(36756003)(7696005)(54906003)(5660300002)(1076003)(316002)(6666004)(83380400001)(44832011)(508600001)(7416002)(4326008)(47076005)(82310400003)(36860700001)(2616005)(336012)(86362001)(186003)(16526019)(26005)(8676002)(110136005)(426003)(8936002)(7406005)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:34.6499 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5e40c6e2-dd18-4162-82df-08d98a8639b6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3668 Authentication-Results: imf16.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=JrpB3V6t; spf=pass (imf16.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.244.87 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: AD235F00235F X-Stat-Signature: 6sje4ddzff8fzi5dfphzhjh7bgba3itf X-HE-Tag: 1633716339-987328 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: An SNP-active guest uses the PVALIDATE instruction to validate or rescind the validation of a guest page’s RMP entry. Upon completion, a return code is stored in EAX and rFLAGS bits are set based on the return code. If the instruction completed successfully, the CF indicates if the content of the RMP were changed or not. See AMD APM Volume 3 for additional details. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/sev.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 134a7c9d91b6..b308815a2c01 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -59,6 +59,9 @@ extern void vc_no_ghcb(void); extern void vc_boot_ghcb(void); extern bool handle_vc_boot_ghcb(struct pt_regs *regs); +/* Software defined (when rFlags.CF = 1) */ +#define PVALIDATE_FAIL_NOUPDATE 255 + #ifdef CONFIG_AMD_MEM_ENCRYPT extern struct static_key_false sev_es_enable_key; extern void __sev_es_ist_enter(struct pt_regs *regs); @@ -81,12 +84,30 @@ static __always_inline void sev_es_nmi_complete(void) __sev_es_nmi_complete(); } extern int __init sev_es_efi_map_ghcbs(pgd_t *pgd); +static inline int pvalidate(unsigned long vaddr, bool rmp_psize, bool validate) +{ + bool no_rmpupdate; + int rc; + + /* "pvalidate" mnemonic support in binutils 2.36 and newer */ + asm volatile(".byte 0xF2, 0x0F, 0x01, 0xFF\n\t" + CC_SET(c) + : CC_OUT(c) (no_rmpupdate), "=a"(rc) + : "a"(vaddr), "c"(rmp_psize), "d"(validate) + : "memory", "cc"); + + if (no_rmpupdate) + return PVALIDATE_FAIL_NOUPDATE; + + return rc; +} #else static inline void sev_es_ist_enter(struct pt_regs *regs) { } static inline void sev_es_ist_exit(void) { } static inline int sev_es_setup_ap_jump_table(struct real_mode_header *rmh) { return 0; } static inline void sev_es_nmi_complete(void) { } static inline int sev_es_efi_map_ghcbs(pgd_t *pgd) { return 0; } +static inline int pvalidate(unsigned long vaddr, bool rmp_psize, bool validate) { return 0; } #endif #endif From patchwork Fri Oct 8 18:04:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545911 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B050C43217 for ; Fri, 8 Oct 2021 18:05:48 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 02A2060296 for ; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 11/42] x86/sev: Check the vmpl level Date: Fri, 8 Oct 2021 13:04:22 -0500 Message-ID: <20211008180453.462291-12-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 96049c67-df7a-414c-789f-08d98a863ab3 X-MS-TrafficTypeDiagnostic: DM5PR12MB1705: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nE1enjAfYirkB8rIxAC80Nceu7D33dyrweJsHFJ3v8bG4KcAVHFdFJBA9DSBNw206MdFZWdVP3jmj2jxKKE5U5iE6Jo64q2R2IcJFQheo1/FJNIMirOtjq1i+tMltYOGA/YsLet+mcJ40HncnBp4lh7TAGonrkVtc6hC3MaqnQ5aI4ZRPr+bkhcUbZeFct2uUfB5NF3zJfvPAoys3LEvQZ0N/MAkcHe4uW7j1NN5TFh1TjT9rGX8kTd7fboAvZUwwlSilGAsYQL3iLTovSLkGW0e6lDVvR89NjSCHhmaYCfh74nDljJ1CzhUl99D5s50S5nyDEnbkksrsTA52ge7p1dKLx2qDlaOKpt3aIuPX3sZpkICKZ5WAntdFthrHsK+aIPoWc1mH+sjO4isNpXIQrtykyLy7hfLCg+E+vxBy+Lkvv4CDS6yECTO4NyvkGDP7M+wwAkk4mqdVNWVRYyijNJxGFXUtGEHhFn6pRA6BbF3dWnVzJmOUJSvrzfwTT6zlNz53+/lWlOFUsQlavc0hAefULI++FojuFdVFnvDc6X0EJ6G5RLNrTdcmq8Ttog1McdynFXe2WBvqwTYMOev0kUkMGZ7g3w1RgRZ5ROl5EenoBvCYmTuN4PBfDcqVMqsW7mTo3ObxrZ3Lou2BEeTayo4Kdt/PLFh/NenNx/tu4OZ4EVqjmmYU5dMgqALaE+qFd/+ztU0cXudhZon/jVHpZk+xamwodIsbJ7iVlL9igzcQofSJMtKtEuoOnHrEGPb X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(426003)(47076005)(44832011)(83380400001)(8936002)(36756003)(508600001)(336012)(356005)(70586007)(70206006)(82310400003)(2616005)(36860700001)(26005)(86362001)(8676002)(54906003)(7406005)(7416002)(2906002)(81166007)(16526019)(4326008)(186003)(110136005)(7696005)(316002)(5660300002)(6666004)(1076003)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:36.3199 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96049c67-df7a-414c-789f-08d98a863ab3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1705 X-Rspamd-Server: rspam02 X-Rspamd-Queue-Id: 924EE30008DD X-Stat-Signature: ucoae1uqrxr9ed648885551jiuxf4qhn Authentication-Results: imf09.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=hrNaEuY+; spf=pass (imf09.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.236.89 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-HE-Tag: 1633716340-574081 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Virtual Machine Privilege Level (VMPL) is an optional feature in the SEV-SNP architecture, which allows a guest VM to divide its address space into four levels. The level can be used to provide the hardware isolated abstraction layers with a VM. The VMPL0 is the highest privilege, and VMPL3 is the least privilege. Certain operations must be done by the VMPL0 software, such as: * Validate or invalidate memory range (PVALIDATE instruction) * Allocate VMSA page (RMPADJUST instruction when VMSA=1) The initial SEV-SNP support assumes that the guest kernel is running on VMPL0. Let's add a check to make sure that kernel is running at VMPL0 before continuing the boot. There is no easy method to query the current VMPL level, so use the RMPADJUST instruction to determine whether its booted at the VMPL0. Signed-off-by: Brijesh Singh --- arch/x86/boot/compressed/sev.c | 41 ++++++++++++++++++++++++++++--- arch/x86/include/asm/sev-common.h | 1 + arch/x86/include/asm/sev.h | 3 +++ 3 files changed, 42 insertions(+), 3 deletions(-) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index 8b0f892c072b..cf24cc2af40a 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -124,6 +124,36 @@ static inline bool sev_snp_enabled(void) return sev_status & MSR_AMD64_SEV_SNP_ENABLED; } +static bool is_vmpl0(void) +{ + u64 attrs, va; + int err; + + /* + * There is no straightforward way to query the current VMPL level. The + * simplest method is to use the RMPADJUST instruction to change a page + * permission to a VMPL level-1, and if the guest kernel is launched at + * a level <= 1, then RMPADJUST instruction will return an error. + */ + attrs = 1; + + /* + * Any page aligned virtual address is sufficent to test the VMPL level. + * The boot_ghcb_page is page aligned memory, so lets use for the test. + */ + va = (u64)&boot_ghcb_page; + + /* Instruction mnemonic supported in binutils versions v2.36 and later */ + asm volatile (".byte 0xf3,0x0f,0x01,0xfe\n\t" + : "=a" (err) + : "a" (va), "c" (RMP_PG_SIZE_4K), "d" (attrs) + : "memory", "cc"); + if (err) + return false; + + return true; +} + static bool do_early_sev_setup(void) { if (!sev_es_negotiate_protocol()) @@ -131,10 +161,15 @@ static bool do_early_sev_setup(void) /* * If SEV-SNP is enabled, then check if the hypervisor supports the SEV-SNP - * features. + * features and is launched at VMPL-0 level. */ - if (sev_snp_enabled() && !(sev_hv_features & GHCB_HV_FT_SNP)) - sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SNP_UNSUPPORTED); + if (sev_snp_enabled()) { + if (!(sev_hv_features & GHCB_HV_FT_SNP)) + sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SNP_UNSUPPORTED); + + if (!is_vmpl0()) + sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_NOT_VMPL0); + } if (set_page_decrypted((unsigned long)&boot_ghcb_page)) return false; diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index f80a3cde2086..d426c30ae7b4 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -89,6 +89,7 @@ #define GHCB_TERM_REGISTER 0 /* GHCB GPA registration failure */ #define GHCB_TERM_PSC 1 /* Page State Change failure */ #define GHCB_TERM_PVALIDATE 2 /* Pvalidate failure */ +#define GHCB_TERM_NOT_VMPL0 3 /* SNP guest is not running at VMPL-0 */ #define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK) diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index b308815a2c01..242af1154e49 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -62,6 +62,9 @@ extern bool handle_vc_boot_ghcb(struct pt_regs *regs); /* Software defined (when rFlags.CF = 1) */ #define PVALIDATE_FAIL_NOUPDATE 255 +/* RMP page size */ +#define RMP_PG_SIZE_4K 0 + #ifdef CONFIG_AMD_MEM_ENCRYPT extern struct static_key_false sev_es_enable_key; extern void __sev_es_ist_enter(struct pt_regs *regs); From patchwork Fri Oct 8 18:04:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545909 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDF0BC433FE for ; Fri, 8 Oct 2021 18:05:45 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 6357F60F9D for ; Fri, 8 Oct 2021 18:05:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6357F60F9D Authentication-Results: mail.kernel.org; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 12/42] x86/compressed: Add helper for validating pages in the decompression stage Date: Fri, 8 Oct 2021 13:04:23 -0500 Message-ID: <20211008180453.462291-13-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c4df35a0-3ff2-4679-c5e3-08d98a863ad2 X-MS-TrafficTypeDiagnostic: DM6PR12MB4452: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qEFfQBDmCn0qDJoJh7L3c62UnqPGuNVuRPt2GlsjrnkMnCTFWV3OrUT6WlSlIaHawSFIay+LN/nNLy2CB2UDOQekOXLrKQrOW9LZFy2V9Hiv7N8pAdFpteQacKQpc26hReoxDBu/erCe8Q7F61oX4DuwHURkARW0d+nGuboD1uxb7mtXnKkQxkkCpB29cpUKfjc8UM6TGxj99iOMmc8iW50zE2R46Mh1ZKTrlK5z9B6cQq0lIXhMeZ1ttTKBRshdDkocCsYvJ1aN+NRD7meLVPmfrjGcDUsUbnYzaVDRuCiZxZzuUXSLSqNDITMV5dU9OjPt3f+ysrW1KO3AXGhrJLccVgKbHmn/r1atG3DoHuvJeBP2T/HUrXM+NNiMlaFBYzLt0+o1IGnGVWW5mhPveNl+8fhtoB3HTaZU0ZDF8ieTkLOMYj1xKBAaGwpdyKOUCZNGum3Yem98KiJr2KJTda2ioeeAIuK8td0p6I9nETAKaMV+zeob1fL5wofhaAOtiTbp0MzSfJy/Q0Zse+qBcihvRi6ZXXuxBy05hBPJE0Nr1hkCAA5qnQS/W2yOUKkK9N1nvabYv1kN1jA4kf+Nl0deX6vS0afmmLICr7dx9pwLCCu4IJhnFjE938VYtY4c5AKBkzHtmPaRC7XdfhtB16OGjztMbO7ArcA351Dy/2g/SGKBOrXycFuq1AEs47G0qBzY73alYJizcT0KWjeUFZMMFwit9LvaFtCOI5HmZgqC3GM7pCwXprX9mPd1Wa7O X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(7696005)(26005)(7416002)(7406005)(186003)(5660300002)(83380400001)(8676002)(16526019)(8936002)(508600001)(82310400003)(6666004)(86362001)(47076005)(70586007)(1076003)(70206006)(426003)(2616005)(36860700001)(81166007)(316002)(4326008)(2906002)(44832011)(336012)(110136005)(36756003)(54906003)(356005)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:36.5199 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4df35a0-3ff2-4679-c5e3-08d98a863ad2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4452 X-Rspamd-Queue-Id: 0FA37B001390 X-Stat-Signature: xknnrw3ks4118nq7ebs1s7qeb8ngorrf Authentication-Results: imf24.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b="bReNwj/J"; spf=pass (imf24.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.223.81 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam06 X-HE-Tag: 1633716339-501559 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Many of the integrity guarantees of SEV-SNP are enforced through the Reverse Map Table (RMP). Each RMP entry contains the GPA at which a particular page of DRAM should be mapped. The VMs can request the hypervisor to add pages in the RMP table via the Page State Change VMGEXIT defined in the GHCB specification. Inside each RMP entry is a Validated flag; this flag is automatically cleared to 0 by the CPU hardware when a new RMP entry is created for a guest. Each VM page can be either validated or invalidated, as indicated by the Validated flag in the RMP entry. Memory access to a private page that is not validated generates a #VC. A VM must use PVALIDATE instruction to validate the private page before using it. To maintain the security guarantee of SEV-SNP guests, when transitioning pages from private to shared, the guest must invalidate the pages before asking the hypervisor to change the page state to shared in the RMP table. After the pages are mapped private in the page table, the guest must issue a page state change VMGEXIT to make the pages private in the RMP table and validate it. On boot, BIOS should have validated the entire system memory. During the kernel decompression stage, the VC handler uses the set_memory_decrypted() to make the GHCB page shared (i.e clear encryption attribute). And while exiting from the decompression, it calls the set_page_encrypted() to make the page private. Add sev_snp_set_page_{private,shared}() helper that is used by the set_memory_{decrypt,encrypt}() to change the page state in the RMP table. Signed-off-by: Brijesh Singh --- arch/x86/boot/compressed/ident_map_64.c | 18 ++++++++++- arch/x86/boot/compressed/misc.h | 6 ++++ arch/x86/boot/compressed/sev.c | 41 +++++++++++++++++++++++++ arch/x86/include/asm/sev-common.h | 26 ++++++++++++++++ 4 files changed, 90 insertions(+), 1 deletion(-) diff --git a/arch/x86/boot/compressed/ident_map_64.c b/arch/x86/boot/compressed/ident_map_64.c index f7213d0943b8..3cf7a7575f5c 100644 --- a/arch/x86/boot/compressed/ident_map_64.c +++ b/arch/x86/boot/compressed/ident_map_64.c @@ -275,15 +275,31 @@ static int set_clr_page_flags(struct x86_mapping_info *info, * Changing encryption attributes of a page requires to flush it from * the caches. */ - if ((set | clr) & _PAGE_ENC) + if ((set | clr) & _PAGE_ENC) { clflush_page(address); + /* + * If the encryption attribute is being cleared, then change + * the page state to shared in the RMP table. + */ + if (clr) + snp_set_page_shared(pte_pfn(*ptep) << PAGE_SHIFT); + } + /* Update PTE */ pte = *ptep; pte = pte_set_flags(pte, set); pte = pte_clear_flags(pte, clr); set_pte(ptep, pte); + /* + * If the encryption attribute is being set, then change the page state to + * private in the RMP entry. The page state must be done after the PTE + * is updated. + */ + if (set & _PAGE_ENC) + snp_set_page_private(pte_pfn(*ptep) << PAGE_SHIFT); + /* Flush TLB after changing encryption attribute */ write_cr3(top_level_pgt); diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/misc.h index 31139256859f..822e0c254b9a 100644 --- a/arch/x86/boot/compressed/misc.h +++ b/arch/x86/boot/compressed/misc.h @@ -121,12 +121,18 @@ void set_sev_encryption_mask(void); #ifdef CONFIG_AMD_MEM_ENCRYPT void sev_es_shutdown_ghcb(void); extern bool sev_es_check_ghcb_fault(unsigned long address); +void snp_set_page_private(unsigned long paddr); +void snp_set_page_shared(unsigned long paddr); + #else static inline void sev_es_shutdown_ghcb(void) { } static inline bool sev_es_check_ghcb_fault(unsigned long address) { return false; } +static inline void snp_set_page_private(unsigned long paddr) { } +static inline void snp_set_page_shared(unsigned long paddr) { } + #endif /* acpi.c */ diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index cf24cc2af40a..c644f260098e 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -154,6 +154,47 @@ static bool is_vmpl0(void) return true; } +static void __page_state_change(unsigned long paddr, enum psc_op op) +{ + u64 val; + + if (!sev_snp_enabled()) + return; + + /* + * If private -> shared then invalidate the page before requesting the + * state change in the RMP table. + */ + if (op == SNP_PAGE_STATE_SHARED && pvalidate(paddr, RMP_PG_SIZE_4K, 0)) + sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PVALIDATE); + + /* Issue VMGEXIT to change the page state in RMP table. */ + sev_es_wr_ghcb_msr(GHCB_MSR_PSC_REQ_GFN(paddr >> PAGE_SHIFT, op)); + VMGEXIT(); + + /* Read the response of the VMGEXIT. */ + val = sev_es_rd_ghcb_msr(); + if ((GHCB_RESP_CODE(val) != GHCB_MSR_PSC_RESP) || GHCB_MSR_PSC_RESP_VAL(val)) + sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PSC); + + /* + * Now that page is added in the RMP table, validate it so that it is + * consistent with the RMP entry. + */ + if (op == SNP_PAGE_STATE_PRIVATE && pvalidate(paddr, RMP_PG_SIZE_4K, 1)) + sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PVALIDATE); +} + +void snp_set_page_private(unsigned long paddr) +{ + __page_state_change(paddr, SNP_PAGE_STATE_PRIVATE); +} + +void snp_set_page_shared(unsigned long paddr) +{ + __page_state_change(paddr, SNP_PAGE_STATE_SHARED); +} + static bool do_early_sev_setup(void) { if (!sev_es_negotiate_protocol()) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index d426c30ae7b4..1c76b6b775cc 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -57,6 +57,32 @@ #define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 #define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 +/* + * SNP Page State Change Operation + * + * GHCBData[55:52] - Page operation: + * 0x0001 – Page assignment, Private + * 0x0002 – Page assignment, Shared + */ +enum psc_op { + SNP_PAGE_STATE_PRIVATE = 1, + SNP_PAGE_STATE_SHARED, +}; + +#define GHCB_MSR_PSC_REQ 0x014 +#define GHCB_MSR_PSC_REQ_GFN(gfn, op) \ + /* GHCBData[55:52] */ \ + (((u64)((op) & 0xf) << 52) | \ + /* GHCBData[51:12] */ \ + ((u64)((gfn) & GENMASK_ULL(39, 0)) << 12) | \ + /* GHCBData[11:0] */ \ + GHCB_MSR_PSC_REQ) + +#define GHCB_MSR_PSC_RESP 0x015 +#define GHCB_MSR_PSC_RESP_VAL(val) \ + /* GHCBData[63:32] */ \ + (((u64)(val) & GENMASK_ULL(63, 32)) >> 32) + /* GHCB Hypervisor Feature Request/Response */ #define GHCB_MSR_HV_FT_REQ 0x080 #define GHCB_MSR_HV_FT_RESP 0x081 From patchwork Fri Oct 8 18:04:24 2021 Content-Type: text/plain; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 13/42] x86/compressed: Register GHCB memory when SEV-SNP is active Date: Fri, 8 Oct 2021 13:04:24 -0500 Message-ID: <20211008180453.462291-14-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 395962ef-770c-4e4f-f92a-08d98a863b3f X-MS-TrafficTypeDiagnostic: BL0PR12MB2546: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: s4aH9hABK7SDzIGv0ljydBgqbPePL728Bl7pXvhh/7CefEPyUHuCjlnz/o/H9cB8UtGGmyPkRvTtfn1uvqJv6F0OFE0MoPDx3koMu7Uzjyym2Si54XuaSISKSMfe+f2gFgtEFiNnyVRcvA2tMcyq/fj0IUSCGXBsIsyrVpNiijrSXNJ+RjaLJDQep882FdRDlujaTPTL+6BBzmG9wequIkSTmfaWnEpBmi4561aj99Gupqfb27J7K1IWzE9dbEw+eavmzoKImpdLZHxXk2Q3DvDnXsh9lbeDY6BQcxAT+HFDjAf4aofxFog+bX+Xrcq2I/GCTsLjZlJrYPSTS/jKnQYqHvlIqITvzFnCRxV57b2094OZhohRyGv98wXTFdyhl6gNLsq+VFjEc6KivOnyjnaao4AAmqCGqqt1ByHmzEpDDcKoxT/jq+yA1NT+JoT9yIvMvBsgMBE7VuRyaoy9D5apJPsXDuSdi2z9xme39oSxTnQFm2RhN6PkP+CLVEJuAQe5Sbu0cQxs5/YTadTDmdwgX+WGuIJjojlLXomAT3kpCJ5g1exWK3RkW+l7bKaFRn41IZa5GknIz4XBVqzcHleBU9zXYs/hPvDqLk1EMeBCH3Ivw2H9Yfv7NNlg5sIhnGunq6iMibu2D/p5HHolZJaIKgI0KcR2FeqGqZLrnyPK5TfRfDyzphFT21CzxA2CxPbf1dvxCEMdgIsW7l34vyq4d4MyAmQ1sk4NG/8ddP8xl2gEzJLeJvRTThioTjxa X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(8936002)(2906002)(36860700001)(82310400003)(1076003)(186003)(26005)(16526019)(508600001)(86362001)(8676002)(6666004)(36756003)(7696005)(4326008)(336012)(70206006)(47076005)(2616005)(70586007)(316002)(426003)(7406005)(7416002)(356005)(110136005)(44832011)(5660300002)(54906003)(81166007)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:37.2397 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 395962ef-770c-4e4f-f92a-08d98a863b3f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB2546 Authentication-Results: imf03.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b="jq4b/NHV"; spf=pass (imf03.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.220.79 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: B9E7930007AA X-Stat-Signature: 8j8iey4ixu7df7w5y5hn584rtsm3e9r7 X-HE-Tag: 1633716342-188043 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: The SEV-SNP guest is required to perform GHCB GPA registration. This is because the hypervisor may prefer that a guest use a consistent and/or specific GPA for the GHCB associated with a vCPU. For more information, see the GHCB specification. If hypervisor can not work with the guest provided GPA then terminate the guest boot. Signed-off-by: Brijesh Singh --- arch/x86/boot/compressed/sev.c | 4 ++++ arch/x86/include/asm/sev-common.h | 13 +++++++++++++ arch/x86/kernel/sev-shared.c | 16 ++++++++++++++++ 3 files changed, 33 insertions(+) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index c644f260098e..e8308ada610d 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -223,6 +223,10 @@ static bool do_early_sev_setup(void) /* Initialize lookup tables for the instruction decoder */ inat_init_tables(); + /* SEV-SNP guest requires the GHCB GPA must be registered */ + if (sev_snp_enabled()) + snp_register_ghcb_early(__pa(&boot_ghcb_page)); + return true; } diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 1c76b6b775cc..b82fff9d607b 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -57,6 +57,19 @@ #define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 #define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 +/* GHCB GPA Register */ +#define GHCB_MSR_REG_GPA_REQ 0x012 +#define GHCB_MSR_REG_GPA_REQ_VAL(v) \ + /* GHCBData[63:12] */ \ + (((u64)((v) & GENMASK_ULL(51, 0)) << 12) | \ + /* GHCBData[11:0] */ \ + GHCB_MSR_REG_GPA_REQ) + +#define GHCB_MSR_REG_GPA_RESP 0x013 +#define GHCB_MSR_REG_GPA_RESP_VAL(v) \ + /* GHCBData[63:12] */ \ + (((u64)(v) & GENMASK_ULL(63, 12)) >> 12) + /* * SNP Page State Change Operation * diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index 2796c524d174..2b53b622108f 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -75,6 +75,22 @@ static bool get_hv_features(void) return true; } +static void snp_register_ghcb_early(unsigned long paddr) +{ + unsigned long pfn = paddr >> PAGE_SHIFT; + u64 val; + + sev_es_wr_ghcb_msr(GHCB_MSR_REG_GPA_REQ_VAL(pfn)); + VMGEXIT(); + + val = sev_es_rd_ghcb_msr(); + + /* If the response GPA is not ours then abort the guest */ + if ((GHCB_RESP_CODE(val) != GHCB_MSR_REG_GPA_RESP) || + (GHCB_MSR_REG_GPA_RESP_VAL(val) != pfn)) + sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_REGISTER); +} + static bool sev_es_negotiate_protocol(void) { u64 val; From patchwork Fri Oct 8 18:04:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545913 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDBEAC433F5 for ; Fri, 8 Oct 2021 18:05:50 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 9DCBC60F9D for ; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 14/42] x86/sev: Register GHCB memory when SEV-SNP is active Date: Fri, 8 Oct 2021 13:04:25 -0500 Message-ID: <20211008180453.462291-15-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 94c36b73-d3e5-43ce-d6bd-08d98a863b56 X-MS-TrafficTypeDiagnostic: CH0PR12MB5139: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3968; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SwAqsLsYHP/Czps7/+X4RbhAOo0YNwRjzxnR6KtSwjbW6T1YaSljUH3cS2QT/oJ0DPfOGHp0BYQgCYKvrObtg1mqQewIa9ZWXuVqBbB5uhfF+TD4lvuVKEqA6POdUEDUf25DZJkC8AnoWykXWY8Y5tNsXSqIZ9hH0rMAYvudRqrbOlDf0kYEdUGapCX4h3a4OOWkAPVube2dEG7E3PmuETfdbaTXboJGPR2AWHZ+MxSetLiadWPUFJEexNguWOIguxc4WSPjcDN20/dV2a5CFINdrCxu8G89mqlXubkA5z8qunXoZZUY515CwmcaHM8WvUN8LypMozoMOIXSLcZ0eyWEv04BfR+BLHjtnwDsbNYbtFDWECCXy82mSSyBi8SDtDLUpD0SHVTK7BYO8P1v6qu9WpMg1jBJj0irUE/dihFcyXlyYWfo72sQ679COZLW9kUi9iwfqa3MC75Qf8LS0Aont0doL9exzosN3wv6RqOw+Du7riEtLaJGXzNUPko/1u9a5VzC3jL2r9jUjOCZym69YXHdDwoceUv1TI4WeWn0n8PMGqShvGUna5lzjtLHNMcuMxjH+PdK9wajIQXCNQ1XjfgNyqGEyRpmDxqUTQ+m3/rvOdL0dUe4CrdzW+ZWfX+6g8cx+S0g61EL31QeRqBScyV9kCMFgeBPGXdoJrvdhihQSolmFdOgwYDnlnTX/AWGxuytcIgZ4hn71a6tToKu90iXUJm4owiwCjlIDlG70infVmC8wi8c7+AF2Zlo X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(47076005)(356005)(44832011)(54906003)(70586007)(7406005)(86362001)(508600001)(316002)(7416002)(36860700001)(70206006)(186003)(81166007)(8676002)(16526019)(83380400001)(110136005)(26005)(4326008)(82310400003)(2616005)(1076003)(5660300002)(2906002)(36756003)(336012)(8936002)(426003)(7696005)(6666004)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:37.3904 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 94c36b73-d3e5-43ce-d6bd-08d98a863b56 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5139 X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: EABA7600440C X-Stat-Signature: ukt9sxrbejphtz7qanps3z3uzkayhojh Authentication-Results: imf10.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=SfSFaMFw; dmarc=pass (policy=quarantine) header.from=amd.com; spf=pass (imf10.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.236.43 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com X-HE-Tag: 1633716341-500288 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: The SEV-SNP guest is required to perform GHCB GPA registration. This is because the hypervisor may prefer that a guest use a consistent and/or specific GPA for the GHCB associated with a vCPU. For more information, see the GHCB specification section GHCB GPA Registration. During the boot, init_ghcb() allocates a per-cpu GHCB page. On very first VC exception, the exception handler switch to using the per-cpu GHCB page allocated during the init_ghcb(). The GHCB page must be registered in the current vcpu context. Signed-off-by: Brijesh Singh --- arch/x86/kernel/sev.c | 124 +++++++++++++++++++++++++----------------- 1 file changed, 75 insertions(+), 49 deletions(-) diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 2290fbcc1844..4c891d5d9651 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -77,6 +77,13 @@ struct sev_es_runtime_data { * is currently unsupported in SEV-ES guests. */ unsigned long dr7; + + /* + * SEV-SNP requires that the GHCB must be registered before using it. + * The flag below will indicate whether the GHCB is registered, if its + * not registered then sev_es_get_ghcb() will perform the registration. + */ + bool snp_ghcb_registered; }; struct ghcb_state { @@ -160,55 +167,6 @@ void noinstr __sev_es_ist_exit(void) this_cpu_write(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC], *(unsigned long *)ist); } -/* - * Nothing shall interrupt this code path while holding the per-CPU - * GHCB. The backup GHCB is only for NMIs interrupting this path. - * - * Callers must disable local interrupts around it. - */ -static noinstr struct ghcb *__sev_get_ghcb(struct ghcb_state *state) -{ - struct sev_es_runtime_data *data; - struct ghcb *ghcb; - - WARN_ON(!irqs_disabled()); - - data = this_cpu_read(runtime_data); - ghcb = &data->ghcb_page; - - if (unlikely(data->ghcb_active)) { - /* GHCB is already in use - save its contents */ - - if (unlikely(data->backup_ghcb_active)) { - /* - * Backup-GHCB is also already in use. There is no way - * to continue here so just kill the machine. To make - * panic() work, mark GHCBs inactive so that messages - * can be printed out. - */ - data->ghcb_active = false; - data->backup_ghcb_active = false; - - instrumentation_begin(); - panic("Unable to handle #VC exception! GHCB and Backup GHCB are already in use"); - instrumentation_end(); - } - - /* Mark backup_ghcb active before writing to it */ - data->backup_ghcb_active = true; - - state->ghcb = &data->backup_ghcb; - - /* Backup GHCB content */ - *state->ghcb = *ghcb; - } else { - state->ghcb = NULL; - data->ghcb_active = true; - } - - return ghcb; -} - /* Needed in vc_early_forward_exception */ void do_early_exception(struct pt_regs *regs, int trapnr); @@ -464,6 +422,69 @@ static enum es_result vc_slow_virt_to_phys(struct ghcb *ghcb, struct es_em_ctxt /* Include code shared with pre-decompression boot stage */ #include "sev-shared.c" +static void snp_register_ghcb(struct sev_es_runtime_data *data, unsigned long paddr) +{ + if (data->snp_ghcb_registered) + return; + + snp_register_ghcb_early(paddr); + + data->snp_ghcb_registered = true; +} + +/* + * Nothing shall interrupt this code path while holding the per-CPU + * GHCB. The backup GHCB is only for NMIs interrupting this path. + * + * Callers must disable local interrupts around it. + */ +static noinstr struct ghcb *__sev_get_ghcb(struct ghcb_state *state) +{ + struct sev_es_runtime_data *data; + struct ghcb *ghcb; + + WARN_ON(!irqs_disabled()); + + data = this_cpu_read(runtime_data); + ghcb = &data->ghcb_page; + + if (unlikely(data->ghcb_active)) { + /* GHCB is already in use - save its contents */ + + if (unlikely(data->backup_ghcb_active)) { + /* + * Backup-GHCB is also already in use. There is no way + * to continue here so just kill the machine. To make + * panic() work, mark GHCBs inactive so that messages + * can be printed out. + */ + data->ghcb_active = false; + data->backup_ghcb_active = false; + + instrumentation_begin(); + panic("Unable to handle #VC exception! GHCB and Backup GHCB are already in use"); + instrumentation_end(); + } + + /* Mark backup_ghcb active before writing to it */ + data->backup_ghcb_active = true; + + state->ghcb = &data->backup_ghcb; + + /* Backup GHCB content */ + *state->ghcb = *ghcb; + } else { + state->ghcb = NULL; + data->ghcb_active = true; + } + + /* SEV-SNP guest requires that GHCB must be registered. */ + if (cc_platform_has(CC_ATTR_SEV_SNP)) + snp_register_ghcb(data, __pa(ghcb)); + + return ghcb; +} + static noinstr void __sev_put_ghcb(struct ghcb_state *state) { struct sev_es_runtime_data *data; @@ -650,6 +671,10 @@ static bool __init setup_ghcb(void) /* Alright - Make the boot-ghcb public */ boot_ghcb = &boot_ghcb_page; + /* SEV-SNP guest requires that GHCB GPA must be registered. */ + if (cc_platform_has(CC_ATTR_SEV_SNP)) + snp_register_ghcb_early(__pa(&boot_ghcb_page)); + return true; } @@ -739,6 +764,7 @@ static void __init init_ghcb(int cpu) data->ghcb_active = false; data->backup_ghcb_active = false; + data->snp_ghcb_registered = false; } void __init sev_es_init_vc_handling(void) From patchwork Fri Oct 8 18:04:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545917 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 990C3C433FE for ; Fri, 8 Oct 2021 18:05:55 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 4D28061027 for ; Fri, 8 Oct 2021 18:05:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4D28061027 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=amd.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvack.org Received: by kanga.kvack.org (Postfix) id D2C8F940013; Fri, 8 Oct 2021 14:05:44 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id CB4A9940008; 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David Alan Gilbert" , , , , Borislav Petkov , Brijesh Singh Subject: [PATCH v6 15/42] x86/sev: Remove do_early_exception() forward declarations Date: Fri, 8 Oct 2021 13:04:26 -0500 Message-ID: <20211008180453.462291-16-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 797cb669-f0b0-431e-579e-08d98a863be6 X-MS-TrafficTypeDiagnostic: MN2PR12MB4127: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3513; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: XVg3X9nkc5PhDrYPzU265xE3EK8yofJTpx3ZrYl1Zsk0FHvbAgKjqytZOg6ZtQioMTiv37bLVliZMIm7SM0N+tV60VJr9FUsssJd1+KHTIY9+gsQfYA3Mko3OcTzC0vDXTJDKU95LZZVzSkn0UmEJ9M45hHr629RppAsMSPPwgx+gIYsmuMnUH4JzI3KeXvm9RB+gH8r0Nyt23z6858wzRPO/2ZjLKoiXJwUtLdi6eZaEfH2yrboGBkZyk3EccEFRgAZkF/seG+uanm5gkZ0yfFTsnWMg6PmDuYPBbBv20+ez0hJhy4BHEkNDTVba5pdZVa4/2LstPUHX+sj7ECE3hccSZueyEIiOUH3i4PXcPLhczdgZSCw4W3e4XoI4S54g+HdhaM/JJz9PQw53kbLpm/tHX8tuyAKPTz6HD+f1sUwkFCdvvVUUoAmrhw6jHb5Oh+I+QcLOa4iIl7NKjvqL6ulVm+ZT+S/XJy7mQ6tBfG4rwAcBQSo6CE/zYDXhJeHaBXiIRzKtXWmF+kkxZg72G0zz6sjhQxhl0qefEtCmUZZH4EUe6N3gj7zxwYEwfnQodf6bK8yNLJYaTQYc5L5o78L+yADTl7764ooQyo7sGw2xpGVS/H5qum+Wf0BSyObjsDKVyKDkpIz5cfFMNmUxp2vfHznTdVViqurvXJnY8cE8v3XWBm/Ev8QvCNa4MM4eKxgTJj+Q5B7eDwumOgqnM9+2nqsTKJqfxxhfwqa5rWo0czS9XVVMMRxYwk2npvh X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(1076003)(336012)(426003)(47076005)(36756003)(81166007)(356005)(82310400003)(83380400001)(2906002)(2616005)(6666004)(36860700001)(316002)(70206006)(86362001)(16526019)(5660300002)(26005)(8936002)(186003)(7696005)(4326008)(44832011)(54906003)(70586007)(7416002)(7406005)(8676002)(110136005)(508600001)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:38.3308 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 797cb669-f0b0-431e-579e-08d98a863be6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4127 X-Rspamd-Server: rspam01 X-Rspamd-Queue-Id: F1552103C5D3 X-Stat-Signature: mcb597zsk5akhqd9q8nj7qaabfgo67zn Authentication-Results: imf13.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b="PwG2oZ/w"; dmarc=pass (policy=quarantine) header.from=amd.com; spf=pass (imf13.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.236.43 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com X-HE-Tag: 1633716343-114042 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Borislav Petkov There's a perfectly fine prototype in the asm/setup.h header. Use it. No functional changes. Signed-off-by: Borislav Petkov Signed-off-by: Brijesh Singh --- arch/x86/kernel/sev.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 4c891d5d9651..ad3fefb741e1 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -93,9 +94,6 @@ struct ghcb_state { static DEFINE_PER_CPU(struct sev_es_runtime_data*, runtime_data); DEFINE_STATIC_KEY_FALSE(sev_es_enable_key); -/* Needed in vc_early_forward_exception */ -void do_early_exception(struct pt_regs *regs, int trapnr); - static __always_inline bool on_vc_stack(struct pt_regs *regs) { unsigned long sp = regs->sp; @@ -167,9 +165,6 @@ void noinstr __sev_es_ist_exit(void) this_cpu_write(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC], *(unsigned long *)ist); } -/* Needed in vc_early_forward_exception */ -void do_early_exception(struct pt_regs *regs, int trapnr); - static inline u64 sev_es_rd_ghcb_msr(void) { return __rdmsr(MSR_AMD64_SEV_ES_GHCB); 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 16/42] x86/sev: Add helper for validating pages in early enc attribute changes Date: Fri, 8 Oct 2021 13:04:27 -0500 Message-ID: <20211008180453.462291-17-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7b1d78fa-c4fd-489f-708f-08d98a863d35 X-MS-TrafficTypeDiagnostic: DM6PR12MB3306: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3044; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +G6PBfAwOlDcjOeR7PzsmEqDeaIt13MKCJoiIiAmjgGOgyrzn+03j7eawIONenLi0NCfrsvmrlOGhqP9Uu24rZW6ioMOWXYBOefsvjvpIcANeTcY3wuaNw3/t04AfULTAECCKHms0D5UoXvrt6ueHESV4wt1WNgEc40QwhsdSmJxjm8Ij8RURUNJd6gTWWc9oR+7KwMCryZJVx/tav3jRWAqkGDfK/hOs30JD0RWOgdXYoCkDjypWcfpY0aj5mYSDQv/h0c2pubhtkhyKlJCKAOCE5ZaMNVxmnFjcC1parJ2eu4O2Aw5ULKXPjNwtaQPqTXtCmqiyOhl7Ofz7zeZkeaisDw0vlygDhAc8+WFIpxf5wJ1RhoQvIn7vPoooDI/SlM6qGeGDERapAYaeBvl6k5gP3f/1RwLHEJrUAXf7kpyN9VUizTAp3D3MQ/x8wDdUfcCeBkF1rpKEVJafmoVl4GD0CY8CKw9FX20nVkEXSshZTOZqrDFi/0+uHXmW8+OEY2qhieSKRZgJ6AD6f3XWP5SeLi8SiOu43uoXihArmInUgl2E0NR3FPmIUNcmVtspKY5CYwxpgE8k3SKnFwtMWk3e+AnFYhoXHvm1g+EmRnJTUkWeNMM10UT/FcP3OHnxJOVN+Yoxw5HoWhk3rggnDFv3GoB8O0jFU7LnVM92ERXxOJ1srxNssuvrit9epujaLKlpTZ77zdFbTd5htGd9JVya7Y9sFsdk0VZvUxt45gxJdyVkFR4YtplOTNhLpJ8 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(7406005)(7416002)(26005)(70206006)(36860700001)(81166007)(70586007)(86362001)(44832011)(508600001)(5660300002)(8936002)(4326008)(356005)(36756003)(110136005)(316002)(54906003)(7696005)(82310400003)(8676002)(6666004)(2906002)(83380400001)(2616005)(426003)(47076005)(1076003)(16526019)(336012)(186003)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:40.5169 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7b1d78fa-c4fd-489f-708f-08d98a863d35 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3306 X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: 5ECCE9001A9F X-Stat-Signature: uzbdt6yqz58161fcezt38d4rdt6he5y7 Authentication-Results: imf29.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=kdY56mMB; dmarc=pass (policy=quarantine) header.from=amd.com; spf=pass (imf29.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.212.69 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com X-HE-Tag: 1633716345-7172 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: The early_set_memory_{encrypt,decrypt}() are used for changing the page from decrypted (shared) to encrypted (private) and vice versa. When SEV-SNP is active, the page state transition needs to go through additional steps. If the page is transitioned from shared to private, then perform the following after the encryption attribute is set in the page table: 1. Issue the page state change VMGEXIT to add the page as a private in the RMP table. 2. Validate the page after its successfully added in the RMP table. To maintain the security guarantees, if the page is transitioned from private to shared, then perform the following before clearing the encryption attribute from the page table. 1. Invalidate the page. 2. Issue the page state change VMGEXIT to make the page shared in the RMP table. The early_set_memory_{encrypt,decrypt} can be called before the GHCB is setup, use the SNP page state MSR protocol VMGEXIT defined in the GHCB specification to request the page state change in the RMP table. While at it, add a helper snp_prep_memory() that can be used outside the sev specific files to change the page state for a specified memory range. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/sev.h | 10 ++++ arch/x86/kernel/sev.c | 102 +++++++++++++++++++++++++++++++++++++ arch/x86/mm/mem_encrypt.c | 51 +++++++++++++++++-- 3 files changed, 159 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 242af1154e49..ecd8cd8c5908 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -104,6 +104,11 @@ static inline int pvalidate(unsigned long vaddr, bool rmp_psize, bool validate) return rc; } +void __init early_snp_set_memory_private(unsigned long vaddr, unsigned long paddr, + unsigned int npages); +void __init early_snp_set_memory_shared(unsigned long vaddr, unsigned long paddr, + unsigned int npages); +void __init snp_prep_memory(unsigned long paddr, unsigned int sz, enum psc_op op); #else static inline void sev_es_ist_enter(struct pt_regs *regs) { } static inline void sev_es_ist_exit(void) { } @@ -111,6 +116,11 @@ static inline int sev_es_setup_ap_jump_table(struct real_mode_header *rmh) { ret static inline void sev_es_nmi_complete(void) { } static inline int sev_es_efi_map_ghcbs(pgd_t *pgd) { return 0; } static inline int pvalidate(unsigned long vaddr, bool rmp_psize, bool validate) { return 0; } +static inline void __init +early_snp_set_memory_private(unsigned long vaddr, unsigned long paddr, unsigned int npages) { } +static inline void __init +early_snp_set_memory_shared(unsigned long vaddr, unsigned long paddr, unsigned int npages) { } +static inline void __init snp_prep_memory(unsigned long paddr, unsigned int sz, enum psc_op op) { } #endif #endif diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index ad3fefb741e1..488011479678 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -553,6 +553,108 @@ static u64 get_jump_table_addr(void) return ret; } +static void pvalidate_pages(unsigned long vaddr, unsigned int npages, bool validate) +{ + unsigned long vaddr_end; + int rc; + + vaddr = vaddr & PAGE_MASK; + vaddr_end = vaddr + (npages << PAGE_SHIFT); + + while (vaddr < vaddr_end) { + rc = pvalidate(vaddr, RMP_PG_SIZE_4K, validate); + if (WARN(rc, "Failed to validate address 0x%lx ret %d", vaddr, rc)) + sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PVALIDATE); + + vaddr = vaddr + PAGE_SIZE; + } +} + +static void __init early_set_page_state(unsigned long paddr, unsigned int npages, enum psc_op op) +{ + unsigned long paddr_end; + u64 val; + + paddr = paddr & PAGE_MASK; + paddr_end = paddr + (npages << PAGE_SHIFT); + + while (paddr < paddr_end) { + /* + * Use the MSR protocol because this function can be called before the GHCB + * is established. + */ + sev_es_wr_ghcb_msr(GHCB_MSR_PSC_REQ_GFN(paddr >> PAGE_SHIFT, op)); + VMGEXIT(); + + val = sev_es_rd_ghcb_msr(); + + if (WARN(GHCB_RESP_CODE(val) != GHCB_MSR_PSC_RESP, + "Wrong PSC response code: 0x%x\n", + (unsigned int)GHCB_RESP_CODE(val))) + goto e_term; + + if (WARN(GHCB_MSR_PSC_RESP_VAL(val), + "Failed to change page state to '%s' paddr 0x%lx error 0x%llx\n", + op == SNP_PAGE_STATE_PRIVATE ? "private" : "shared", + paddr, GHCB_MSR_PSC_RESP_VAL(val))) + goto e_term; + + paddr = paddr + PAGE_SIZE; + } + + return; + +e_term: + sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PSC); +} + +void __init early_snp_set_memory_private(unsigned long vaddr, unsigned long paddr, + unsigned int npages) +{ + if (!cc_platform_has(CC_ATTR_SEV_SNP)) + return; + + /* + * Ask the hypervisor to mark the memory pages as private in the RMP + * table. + */ + early_set_page_state(paddr, npages, SNP_PAGE_STATE_PRIVATE); + + /* Validate the memory pages after they've been added in the RMP table. */ + pvalidate_pages(vaddr, npages, 1); +} + +void __init early_snp_set_memory_shared(unsigned long vaddr, unsigned long paddr, + unsigned int npages) +{ + if (!cc_platform_has(CC_ATTR_SEV_SNP)) + return; + + /* + * Invalidate the memory pages before they are marked shared in the + * RMP table. + */ + pvalidate_pages(vaddr, npages, 0); + + /* Ask hypervisor to mark the memory pages shared in the RMP table. */ + early_set_page_state(paddr, npages, SNP_PAGE_STATE_SHARED); +} + +void __init snp_prep_memory(unsigned long paddr, unsigned int sz, enum psc_op op) +{ + unsigned long vaddr, npages; + + vaddr = (unsigned long)__va(paddr); + npages = PAGE_ALIGN(sz) >> PAGE_SHIFT; + + if (op == SNP_PAGE_STATE_PRIVATE) + early_snp_set_memory_private(vaddr, paddr, npages); + else if (op == SNP_PAGE_STATE_SHARED) + early_snp_set_memory_shared(vaddr, paddr, npages); + else + WARN(1, "invalid memory op %d\n", op); +} + int sev_es_setup_ap_jump_table(struct real_mode_header *rmh) { u16 startup_cs, startup_ip; diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c index 534c2c82fbec..d01bb95f7aef 100644 --- a/arch/x86/mm/mem_encrypt.c +++ b/arch/x86/mm/mem_encrypt.c @@ -31,6 +31,7 @@ #include #include #include +#include #include "mm_internal.h" @@ -49,6 +50,34 @@ EXPORT_SYMBOL_GPL(sev_enable_key); /* Buffer used for early in-place encryption by BSP, no locking needed */ static char sme_early_buffer[PAGE_SIZE] __initdata __aligned(PAGE_SIZE); +/* + * When SNP is active, change the page state from private to shared before + * copying the data from the source to destination and restore after the copy. + * This is required because the source address is mapped as decrypted by the + * caller of the routine. + */ +static inline void __init snp_memcpy(void *dst, void *src, size_t sz, + unsigned long paddr, bool decrypt) +{ + unsigned long npages = PAGE_ALIGN(sz) >> PAGE_SHIFT; + + if (!cc_platform_has(CC_ATTR_SEV_SNP) || !decrypt) { + memcpy(dst, src, sz); + return; + } + + /* + * With SNP, the paddr needs to be accessed decrypted, mark the page + * shared in the RMP table before copying it. + */ + early_snp_set_memory_shared((unsigned long)__va(paddr), paddr, npages); + + memcpy(dst, src, sz); + + /* Restore the page state after the memcpy. */ + early_snp_set_memory_private((unsigned long)__va(paddr), paddr, npages); +} + /* * This routine does not change the underlying encryption setting of the * page(s) that map this memory. It assumes that eventually the memory is @@ -97,8 +126,8 @@ static void __init __sme_early_enc_dec(resource_size_t paddr, * Use a temporary buffer, of cache-line multiple size, to * avoid data corruption as documented in the APM. */ - memcpy(sme_early_buffer, src, len); - memcpy(dst, sme_early_buffer, len); + snp_memcpy(sme_early_buffer, src, len, paddr, enc); + snp_memcpy(dst, sme_early_buffer, len, paddr, !enc); early_memunmap(dst, len); early_memunmap(src, len); @@ -273,14 +302,28 @@ static void __init __set_clr_pte_enc(pte_t *kpte, int level, bool enc) clflush_cache_range(__va(pa), size); /* Encrypt/decrypt the contents in-place */ - if (enc) + if (enc) { sme_early_encrypt(pa, size); - else + } else { sme_early_decrypt(pa, size); + /* + * ON SNP, the page state in the RMP table must happen + * before the page table updates. + */ + early_snp_set_memory_shared((unsigned long)__va(pa), pa, 1); + } + /* Change the page encryption mask. */ new_pte = pfn_pte(pfn, new_prot); set_pte_atomic(kpte, new_pte); + + /* + * If page is set encrypted in the page table, then update the RMP table to + * add this page as private. + */ + if (enc) + early_snp_set_memory_private((unsigned long)__va(pa), pa, 1); } static int __init early_set_memory_enc_dec(unsigned long vaddr, From patchwork Fri Oct 8 18:04:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545921 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CE64C433EF for ; Fri, 8 Oct 2021 18:06:00 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 47A9F61027 for ; Fri, 8 Oct 2021 18:06:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 47A9F61027 Authentication-Results: mail.kernel.org; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 17/42] x86/kernel: Make the bss.decrypted section shared in RMP table Date: Fri, 8 Oct 2021 13:04:28 -0500 Message-ID: <20211008180453.462291-18-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d1c0c9a6-e782-4219-79db-08d98a863e13 X-MS-TrafficTypeDiagnostic: DM6PR12MB4730: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FQjxJoPFrTwdvpE3ity4TgTdEF60Twyg9bxKQ0+DFz/wKCTpMbUEuEVO5PomqDHyz2Zkql5RycDhU3G6fPMoEACAKqJ6skXcaSZL3vtrS8G29yhpUVsDN6InxDOXd1mJywziyPhvs3a5QkM8Sf4gojMsFnBOllsCkiizPWSWfk1qPMCof2PTcv5ClQ8mlq81n/RrY1JNuxyMhA9jeThnivKY4H6BCzYP3EfYGmSDxS9lXDcx4PlA8Irdij/Xawgx4P7S/PV+DpmB0MJi3uNl570W9EdmTVf+J8kV0t4KJI/jk3Qa5OQVs9fbuZtGpkVlI9uvaiuED9mXUC9gJnE5roTCKnHjaURguN2TAQYT1axjWM/DwVzCedJk1zN3YxDrgNTk1j5L+jlvZCWhOZ1RwsUqSE1HcWrg+UFlVYhOwjfNYUgOv8I82gd/LJMJAzvy22PDOG61OEGpaG18xTQk9iWik5HgxrL5ZQiJFqr/bUjRcRHkeRNmyUBSiUPYll0ZDcf0hTkIAZ1rwpCzquTJPf+Te8KTkzTMAiD0ByGXeWVBeeEavOO/RzOswKmUC8r381wXQ0/dfzJCw4/Mjhzim9VsmxicFc2Lr9p+aDv3LWProIuZGhlZQWp3cxToau+FZHZUfXVIXQfebOkFtELyt/qyVTwQWKLez3zoW+2RRuk6RyvXS7eIjvgZ1A06PGvZ6q1VCYjDEoYAQwyvh/6YANbX+FlWkKG2jN3kIyvwelBc/7Ressl6wW++GqVCEccJ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(2906002)(70586007)(81166007)(6666004)(7406005)(83380400001)(7696005)(7416002)(426003)(336012)(2616005)(316002)(26005)(110136005)(186003)(4326008)(36756003)(8676002)(8936002)(82310400003)(54906003)(44832011)(36860700001)(86362001)(508600001)(16526019)(356005)(1076003)(70206006)(47076005)(5660300002)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:41.9711 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d1c0c9a6-e782-4219-79db-08d98a863e13 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4730 X-Rspamd-Queue-Id: 5E2416004408 X-Stat-Signature: 71pqu61a43waarcitqf7fha1ppcq7n13 Authentication-Results: imf10.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=cPdJ7kJN; spf=pass (imf10.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.92.40 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam06 X-HE-Tag: 1633716346-578418 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: The encryption attribute for the bss.decrypted region is cleared in the initial page table build. This is because the section contains the data that need to be shared between the guest and the hypervisor. When SEV-SNP is active, just clearing the encryption attribute in the page table is not enough. The page state need to be updated in the RMP table. Signed-off-by: Brijesh Singh --- arch/x86/kernel/head64.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c index 3be9dd213dad..3c0bfed3b58e 100644 --- a/arch/x86/kernel/head64.c +++ b/arch/x86/kernel/head64.c @@ -143,7 +143,14 @@ static unsigned long sme_postprocess_startup(struct boot_params *bp, pmdval_t *p if (sme_get_me_mask()) { vaddr = (unsigned long)__start_bss_decrypted; vaddr_end = (unsigned long)__end_bss_decrypted; + for (; vaddr < vaddr_end; vaddr += PMD_SIZE) { + /* + * When SEV-SNP is active then transition the page to shared in the RMP + * table so that it is consistent with the page table attribute change. + */ + early_snp_set_memory_shared(__pa(vaddr), __pa(vaddr), PTRS_PER_PMD); + i = pmd_index(vaddr); pmd[i] -= sme_get_me_mask(); } From patchwork Fri Oct 8 18:04:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545925 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E79A0C4332F for ; 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Fri, 8 Oct 2021 13:05:40 -0500 From: Brijesh Singh To: , , , , , , CC: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , "Vitaly Kuznetsov" , Jim Mattson , "Andy Lutomirski" , Dave Hansen , Sergio Lopez , Peter Gonda , "Peter Zijlstra" , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , "Dr . David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 18/42] x86/kernel: Validate rom memory before accessing when SEV-SNP is active Date: Fri, 8 Oct 2021 13:04:29 -0500 Message-ID: <20211008180453.462291-19-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f5f00308-1a13-4799-79a8-08d98a863f6f X-MS-TrafficTypeDiagnostic: MN2PR12MB3421: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Lr7pVCE6AIGvmAIkREMxXFSVk/N2lYDiu1UdEmWG19xU+uKaaDqQNvh77ymTlIW+YNXVEcJhXxjtoLEsxyGCdEFyHeUdqeGYQsPEiVBv8OKte7d1nHFJfu4sCy+9wUf7+K/NOUj9+1S2bVp+Mnsme4zgR3y/VHEMYA/czFmdm/G9X85Ur++qa/e41LmotASOAFcPo4qpgavXovKoTRvlHkuj6eDu7e5eVULXsgTFwZapBzmzAlZ6NbDxjmhKj8AN+Ao3bYYUaktZt0KfBDzV4mb9/cDyGZPeJniaKo1LpDrR8rvIJ0Jwt2Ud5gCfCTaaHfivV1yYcX1uY/X+UwnmJHIBE9VFA6lHO6lSQfbxUDL4BoJAWgslurNKLoNmDOBYcI6CdNLf2OVOCrN9ACGuMmc1ZYzkXykNyEiE/CWAXbkMZKxFlJWtbKMXHyLj2i8pUzthEFJaR2exSf8bDrxLzfoB6abHlZEtfvIL3cZJhj/f34qhfOhD0baLiPjeylvZvb3sQK0lP1NJby2v39ZhtFyIWFW1taeJBxjDCkHukRYDnh/eiU9J60HZzS+ht9m5g4Deh/OOF9xYAF9hchRvHdJsCKKMU96olcwagm86SWoifhOFo/r1dhmWRR8p89lV732T3cgpLl6LYHOil87XThnBRKT30RvoBT5PesT7bltuGLIwOMUBAlWsHgCpoWLWNOK+NsXkELft459i3AsdXnwBhKv75El61CwiBuhgAtvO/NZ3W7R7L8QOiZrkcdpP X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(1076003)(2906002)(356005)(8676002)(186003)(8936002)(81166007)(54906003)(82310400003)(70206006)(70586007)(5660300002)(316002)(110136005)(4326008)(336012)(426003)(16526019)(15650500001)(508600001)(6666004)(7696005)(26005)(7416002)(36756003)(36860700001)(44832011)(2616005)(47076005)(86362001)(83380400001)(7406005)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:44.2507 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f5f00308-1a13-4799-79a8-08d98a863f6f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3421 Authentication-Results: imf28.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=IBnr2qD6; spf=pass (imf28.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.243.73 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 0CD5E9001372 X-Stat-Signature: q5sb7iczqxiokrzomurisx41azx5sdoz X-HE-Tag: 1633716350-631427 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: The probe_roms() access the memory range (0xc0000 - 0x10000) to probe various ROMs. The memory range is not part of the E820 system RAM range. The memory range is mapped as private (i.e encrypted) in page table. When SEV-SNP is active, all the private memory must be validated before the access. The ROM range was not part of E820 map, so the guest BIOS did not validate it. An access to invalidated memory will cause a VC exception. The guest does not support handling not-validated VC exception yet, so validate the ROM memory regions before it is accessed. Signed-off-by: Brijesh Singh --- arch/x86/kernel/probe_roms.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/probe_roms.c b/arch/x86/kernel/probe_roms.c index 9e1def3744f2..9c09df86d167 100644 --- a/arch/x86/kernel/probe_roms.c +++ b/arch/x86/kernel/probe_roms.c @@ -21,6 +21,7 @@ #include #include #include +#include static struct resource system_rom_resource = { .name = "System ROM", @@ -197,11 +198,21 @@ static int __init romchecksum(const unsigned char *rom, unsigned long length) void __init probe_roms(void) { - const unsigned char *rom; unsigned long start, length, upper; + const unsigned char *rom; unsigned char c; int i; + /* + * The ROM memory is not part of the E820 system RAM and is not pre-validated + * by the BIOS. The kernel page table maps the ROM region as encrypted memory, + * the SEV-SNP requires the encrypted memory must be validated before the + * access. Validate the ROM before accessing it. + */ + snp_prep_memory(video_rom_resource.start, + ((system_rom_resource.end + 1) - video_rom_resource.start), + SNP_PAGE_STATE_PRIVATE); + /* video rom */ upper = adapter_rom_resources[0].start; for (start = video_rom_resource.start; start < upper; start += 2048) { From patchwork Fri Oct 8 18:04:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545923 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CE3FC433EF for ; Fri, 8 Oct 2021 18:06:03 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id EF58761027 for ; Fri, 8 Oct 2021 18:06:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org EF58761027 Authentication-Results: mail.kernel.org; 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Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , "Vitaly Kuznetsov" , Jim Mattson , "Andy Lutomirski" , Dave Hansen , Sergio Lopez , Peter Gonda , "Peter Zijlstra" , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , "Dr . David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 19/42] x86/mm: Add support to validate memory when changing C-bit Date: Fri, 8 Oct 2021 13:04:30 -0500 Message-ID: <20211008180453.462291-20-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 41112e17-7e5e-44a2-d518-08d98a864017 X-MS-TrafficTypeDiagnostic: DM5PR1201MB0091: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4B1KNP604xwWL2WHXc4RX8AyaPy2bILhkiklfNT+1LvXQ+N0fGftVv0cpbgon/gBU5bhaiFU7p2HxUggKwfcEc8jvSypjq3Qi3Yh9diXBnkla/33C+hL8g5QrB4pjKvfIOdpwuXymnvas27eWILX44xEjw+XyR3klFEE/NCNlKkcuJva9TrakZasEqaZNScAAs0hrAs4gUey1T6N04gBw2RzUQ85hdhXdBN0MbypxOJKFxqFgv7yK7RsrGWoe8tse/aaAtutaTGmR/aMv+lwpQWjiNe3ViLHkIcsSO2aKnHKTEaoy+PG2L2HkJm4S5cYxadH6yY+gu2P1ryYoyaCo1wNPt+pJWBL+YCMHjGLLXK9xDoFBFFmfleaKHmhzaRmAduoh2q7FbGwrbvv25Opu9y3Sbc3JJ4tgfYBaDpgdXC+OcW4wzMhGhh+uHwlnTvmFYaLSbZt+KgM7ojuyq5RA+KiRODZd34cm2PNRScoxbp2MYQCGWhmJyNsoAZiPlJspz1cEUbMXy+zXdUEYGNZQMTFf1nHpphJbHEFISA/L65P3boSXtqIHyDTslUfdvdVZFLL+/u6zavaHC5IhZ5R5pSI5USOUxTSrOfU+XxbQu1OhA+g5EtWhcEYLPgVE+BesGhVGuvg62hMMO94EyasbRI/mAlwdFfZymCNbPwNf1P8ulRXS9KfVipc4ou4xqYVnSHS3R1R6Lrs9goxE/kOFlJo6SPn73+nX9yLKbrJMrDql9p80UOG3yCBBJD69yvj X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(26005)(86362001)(47076005)(6666004)(15650500001)(7416002)(2906002)(5660300002)(8936002)(4326008)(186003)(426003)(8676002)(81166007)(336012)(356005)(2616005)(44832011)(16526019)(7696005)(36756003)(316002)(54906003)(70586007)(110136005)(508600001)(70206006)(82310400003)(7406005)(83380400001)(36860700001)(1076003)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:45.3551 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41112e17-7e5e-44a2-d518-08d98a864017 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0091 X-Rspamd-Server: rspam03 X-Rspamd-Queue-Id: A9371801B0FD X-Stat-Signature: jkskcih4n965a83dk8b3dyzzg49jj1tf Authentication-Results: imf06.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=B86sHuVT; dmarc=pass (policy=quarantine) header.from=amd.com; spf=pass (imf06.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.223.41 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com X-HE-Tag: 1633716350-740196 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: The set_memory_{encrypt,decrypt}() are used for changing the pages from decrypted (shared) to encrypted (private) and vice versa. When SEV-SNP is active, the page state transition needs to go through additional steps. If the page is transitioned from shared to private, then perform the following after the encryption attribute is set in the page table: 1. Issue the page state change VMGEXIT to add the memory region in the RMP table. 2. Validate the memory region after the RMP entry is added. To maintain the security guarantees, if the page is transitioned from private to shared, then perform the following before encryption attribute is removed from the page table: 1. Invalidate the page. 2. Issue the page state change VMGEXIT to remove the page from RMP table. To change the page state in the RMP table, use the Page State Change VMGEXIT defined in the GHCB specification. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/sev-common.h | 22 ++++ arch/x86/include/asm/sev.h | 4 + arch/x86/include/uapi/asm/svm.h | 2 + arch/x86/kernel/sev.c | 165 ++++++++++++++++++++++++++++++ arch/x86/mm/pat/set_memory.c | 15 +++ 5 files changed, 208 insertions(+) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index b82fff9d607b..c2c5d60f0da0 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -105,6 +105,28 @@ enum psc_op { #define GHCB_HV_FT_SNP BIT_ULL(0) +/* SNP Page State Change NAE event */ +#define VMGEXIT_PSC_MAX_ENTRY 253 + +struct psc_hdr { + u16 cur_entry; + u16 end_entry; + u32 reserved; +} __packed; + +struct psc_entry { + u64 cur_page : 12, + gfn : 40, + operation : 4, + pagesize : 1, + reserved : 7; +} __packed; + +struct snp_psc_desc { + struct psc_hdr hdr; + struct psc_entry entries[VMGEXIT_PSC_MAX_ENTRY]; +} __packed; + #define GHCB_MSR_TERM_REQ 0x100 #define GHCB_MSR_TERM_REASON_SET_POS 12 #define GHCB_MSR_TERM_REASON_SET_MASK 0xf diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index ecd8cd8c5908..005f230d0406 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -109,6 +109,8 @@ void __init early_snp_set_memory_private(unsigned long vaddr, unsigned long padd void __init early_snp_set_memory_shared(unsigned long vaddr, unsigned long paddr, unsigned int npages); void __init snp_prep_memory(unsigned long paddr, unsigned int sz, enum psc_op op); +void snp_set_memory_shared(unsigned long vaddr, unsigned int npages); +void snp_set_memory_private(unsigned long vaddr, unsigned int npages); #else static inline void sev_es_ist_enter(struct pt_regs *regs) { } static inline void sev_es_ist_exit(void) { } @@ -121,6 +123,8 @@ early_snp_set_memory_private(unsigned long vaddr, unsigned long paddr, unsigned static inline void __init early_snp_set_memory_shared(unsigned long vaddr, unsigned long paddr, unsigned int npages) { } static inline void __init snp_prep_memory(unsigned long paddr, unsigned int sz, enum psc_op op) { } +static inline void snp_set_memory_shared(unsigned long vaddr, unsigned int npages) { } +static inline void snp_set_memory_private(unsigned long vaddr, unsigned int npages) { } #endif #endif diff --git a/arch/x86/include/uapi/asm/svm.h b/arch/x86/include/uapi/asm/svm.h index b0ad00f4c1e1..0dcdb6e0c913 100644 --- a/arch/x86/include/uapi/asm/svm.h +++ b/arch/x86/include/uapi/asm/svm.h @@ -108,6 +108,7 @@ #define SVM_VMGEXIT_AP_JUMP_TABLE 0x80000005 #define SVM_VMGEXIT_SET_AP_JUMP_TABLE 0 #define SVM_VMGEXIT_GET_AP_JUMP_TABLE 1 +#define SVM_VMGEXIT_PSC 0x80000010 #define SVM_VMGEXIT_HV_FEATURES 0x8000fffd #define SVM_VMGEXIT_UNSUPPORTED_EVENT 0x8000ffff @@ -219,6 +220,7 @@ { SVM_VMGEXIT_NMI_COMPLETE, "vmgexit_nmi_complete" }, \ { SVM_VMGEXIT_AP_HLT_LOOP, "vmgexit_ap_hlt_loop" }, \ { SVM_VMGEXIT_AP_JUMP_TABLE, "vmgexit_ap_jump_table" }, \ + { SVM_VMGEXIT_PSC, "vmgexit_page_state_change" }, \ { SVM_VMGEXIT_HV_FEATURES, "vmgexit_hypervisor_feature" }, \ { SVM_EXIT_ERR, "invalid_guest_state" } diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 488011479678..80fdfd83770a 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -655,6 +655,171 @@ void __init snp_prep_memory(unsigned long paddr, unsigned int sz, enum psc_op op WARN(1, "invalid memory op %d\n", op); } +static int vmgexit_psc(struct snp_psc_desc *desc) +{ + int cur_entry, end_entry, ret; + struct snp_psc_desc *data; + struct ghcb_state state; + struct ghcb *ghcb; + struct psc_hdr *hdr; + unsigned long flags; + + local_irq_save(flags); + + ghcb = __sev_get_ghcb(&state); + if (unlikely(!ghcb)) + panic("SEV-SNP: Failed to get GHCB\n"); + + /* Copy the input desc into GHCB shared buffer */ + data = (struct snp_psc_desc *)ghcb->shared_buffer; + memcpy(ghcb->shared_buffer, desc, sizeof(*desc)); + + hdr = &data->hdr; + cur_entry = hdr->cur_entry; + end_entry = hdr->end_entry; + + /* + * As per the GHCB specification, the hypervisor can resume the guest + * before processing all the entries. Checks whether all the entries + * are processed. If not, then keep retrying. + * + * The stragtegy here is to wait for the hypervisor to change the page + * state in the RMP table before guest access the memory pages. If the + * page state was not successful, then later memory access will result + * in the crash. + */ + while (hdr->cur_entry <= hdr->end_entry) { + ghcb_set_sw_scratch(ghcb, (u64)__pa(data)); + + ret = sev_es_ghcb_hv_call(ghcb, NULL, SVM_VMGEXIT_PSC, 0, 0); + + /* + * Page State Change VMGEXIT can pass error code through + * exit_info_2. + */ + if (WARN(ret || ghcb->save.sw_exit_info_2, + "SEV-SNP: PSC failed ret=%d exit_info_2=%llx\n", + ret, ghcb->save.sw_exit_info_2)) { + ret = 1; + goto out; + } + + /* + * Sanity check that entry processing is not going backward. + * This will happen only if hypervisor is tricking us. + */ + if (WARN(hdr->end_entry > end_entry || cur_entry > hdr->cur_entry, +"SEV-SNP: PSC processing going backward, end_entry %d (got %d) cur_entry %d (got %d)\n", + end_entry, hdr->end_entry, cur_entry, hdr->cur_entry)) { + ret = 1; + goto out; + } + + /* Verify that reserved bit is not set */ + if (WARN(hdr->reserved, "Reserved bit is set in the PSC header\n")) { + ret = 1; + goto out; + } + } + +out: + __sev_put_ghcb(&state); + local_irq_restore(flags); + + return 0; +} + +static void __set_page_state(struct snp_psc_desc *data, unsigned long vaddr, + unsigned long vaddr_end, int op) +{ + struct psc_hdr *hdr; + struct psc_entry *e; + unsigned long pfn; + int i; + + hdr = &data->hdr; + e = data->entries; + + memset(data, 0, sizeof(*data)); + i = 0; + + while (vaddr < vaddr_end) { + if (is_vmalloc_addr((void *)vaddr)) + pfn = vmalloc_to_pfn((void *)vaddr); + else + pfn = __pa(vaddr) >> PAGE_SHIFT; + + e->gfn = pfn; + e->operation = op; + hdr->end_entry = i; + + /* + * The GHCB specification provides the flexibility to + * use either 4K or 2MB page size in the RMP table. + * The current SNP support does not keep track of the + * page size used in the RMP table. To avoid the + * overlap request, use the 4K page size in the RMP + * table. + */ + e->pagesize = RMP_PG_SIZE_4K; + + vaddr = vaddr + PAGE_SIZE; + e++; + i++; + } + + if (vmgexit_psc(data)) + sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PSC); +} + +static void set_page_state(unsigned long vaddr, unsigned int npages, int op) +{ + unsigned long vaddr_end, next_vaddr; + struct snp_psc_desc *desc; + + vaddr = vaddr & PAGE_MASK; + vaddr_end = vaddr + (npages << PAGE_SHIFT); + + desc = kmalloc(sizeof(*desc), GFP_KERNEL_ACCOUNT); + if (!desc) + panic("SEV-SNP: failed to allocate memory for PSC descriptor\n"); + + while (vaddr < vaddr_end) { + /* + * Calculate the last vaddr that can be fit in one + * struct snp_psc_desc. + */ + next_vaddr = min_t(unsigned long, vaddr_end, + (VMGEXIT_PSC_MAX_ENTRY * PAGE_SIZE) + vaddr); + + __set_page_state(desc, vaddr, next_vaddr, op); + + vaddr = next_vaddr; + } + + kfree(desc); +} + +void snp_set_memory_shared(unsigned long vaddr, unsigned int npages) +{ + if (!cc_platform_has(CC_ATTR_SEV_SNP)) + return; + + pvalidate_pages(vaddr, npages, 0); + + set_page_state(vaddr, npages, SNP_PAGE_STATE_SHARED); +} + +void snp_set_memory_private(unsigned long vaddr, unsigned int npages) +{ + if (!cc_platform_has(CC_ATTR_SEV_SNP)) + return; + + set_page_state(vaddr, npages, SNP_PAGE_STATE_PRIVATE); + + pvalidate_pages(vaddr, npages, 1); +} + int sev_es_setup_ap_jump_table(struct real_mode_header *rmh) { u16 startup_cs, startup_ip; diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c index 527957586f3c..ffe51944606a 100644 --- a/arch/x86/mm/pat/set_memory.c +++ b/arch/x86/mm/pat/set_memory.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "../mm_internal.h" @@ -2010,8 +2011,22 @@ static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc) */ cpa_flush(&cpa, !this_cpu_has(X86_FEATURE_SME_COHERENT)); + /* + * To maintain the security gurantees of SEV-SNP guest invalidate the memory + * before clearing the encryption attribute. + */ + if (!enc) + snp_set_memory_shared(addr, numpages); + ret = __change_page_attr_set_clr(&cpa, 1); + /* + * Now that memory is mapped encrypted in the page table, validate it + * so that is consistent with the above page state. + */ + if (!ret && enc) + snp_set_memory_private(addr, numpages); + /* * After changing the encryption attribute, we need to flush TLBs again * in case any speculative TLB caching occurred (but no need to flush From patchwork Fri Oct 8 18:04:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44B5EC4332F for ; Fri, 8 Oct 2021 18:06:08 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id F041260F9D for ; Fri, 8 Oct 2021 18:06:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org F041260F9D Authentication-Results: mail.kernel.org; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 20/42] KVM: SVM: Define sev_features and vmpl field in the VMSA Date: Fri, 8 Oct 2021 13:04:31 -0500 Message-ID: <20211008180453.462291-21-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 57da81fe-7204-43b5-510f-08d98a8640dd X-MS-TrafficTypeDiagnostic: SJ0PR12MB5503: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9QyIvTMhR2QSCIKeubuPeFyboEk83ny6w/4JlbPP17a1LLF5jK1cYmlGRbzQ5FxHv10abW93hzuRZR+yJpy3PzY2t0vDsY3TqYU5XKb8ywkzcEY7t756h8+63qysOjdo351+1Ys4CFMuvq9A0NHgGo++DBPHucHOpiPaAysnLFOQHp/P1ZIUzG1ENltBBE3jd7+LxdkyaG7OAnrwEpnRkwpIuG6einQQoT110n/mfQQjpBaNpNyGwN39nA4H+O9yT+z6MSwvCdn2FuslTFgv7g+h/6rbGPfXA1sPR9KgvkiiFw9nJz3ozb4YA6AyuuBEnfq5FMPyoo78SWCm0/wd1jvIdkYfPg19efnzq14raRo1zsFGTXICF5IuAQCMF7qpsu7TXeBfmyDf0ZFgn8Pv1UwcmonAViqVsN1vE4SEn6BpSKzmvds0N341mORbZz65MmFZP0PGB01Pyx25MGimePynulxWypV+ZFpigZrHI+0MipEajZ8VIPAH8W25j1yFaHwXSSfFhWo/eGynq+J1v5RtLAjJuAgTOYax2ryMNBoHDakmOL2R/cd0xn95PuQMPtgGMp2B5IUoGP6+uKz3fMUpyLNzLbaynkYem6a6pSSrP4VrVY0fU8JcS+/rFsCaDmhNKAltRBzQoHM1RFdm4ygJ0f8x5crour/sLHisWTkbfajnuN2CWZ+tQsDKfeb760Uyq1R77e4GDBPJHABJJzxBXBanplErqyq2w4WPqRqBDcd1RBDgtkyjRxgqh3o9 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(426003)(8676002)(26005)(54906003)(4326008)(5660300002)(8936002)(7696005)(2616005)(110136005)(6666004)(82310400003)(70206006)(508600001)(83380400001)(70586007)(336012)(47076005)(1076003)(36860700001)(316002)(36756003)(81166007)(2906002)(86362001)(186003)(356005)(7406005)(16526019)(7416002)(44832011)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:46.6503 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 57da81fe-7204-43b5-510f-08d98a8640dd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5503 Authentication-Results: imf21.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=GkZiEOHs; spf=pass (imf21.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.101.72 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: AA52AD03E854 X-Stat-Signature: 7kmgh98sxk333ex91x6hcewudm9fu1em X-HE-Tag: 1633716351-140087 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: The hypervisor uses the sev_features field (offset 3B0h) in the Save State Area to control the SEV-SNP guest features such as SNPActive, vTOM, ReflectVC etc. An SEV-SNP guest can read the SEV_FEATURES fields through the SEV_STATUS MSR. While at it, update the dump_vmcb() to log the VMPL level. See APM2 Table 15-34 and B-4 for more details. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/svm.h | 6 ++++-- arch/x86/kvm/svm/svm.c | 4 ++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index b00dbc5fac2b..7c9cf4f3c164 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -238,7 +238,8 @@ struct vmcb_save_area { struct vmcb_seg ldtr; struct vmcb_seg idtr; struct vmcb_seg tr; - u8 reserved_1[43]; + u8 reserved_1[42]; + u8 vmpl; u8 cpl; u8 reserved_2[4]; u64 efer; @@ -303,7 +304,8 @@ struct vmcb_save_area { u64 sw_exit_info_1; u64 sw_exit_info_2; u64 sw_scratch; - u8 reserved_11[56]; + u64 sev_features; + u8 reserved_11[48]; u64 xcr0; u8 valid_bitmap[16]; u64 x87_state_gpa; diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index aa4828274557..2b932e074256 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -3210,8 +3210,8 @@ static void dump_vmcb(struct kvm_vcpu *vcpu) "tr:", save01->tr.selector, save01->tr.attrib, save01->tr.limit, save01->tr.base); - pr_err("cpl: %d efer: %016llx\n", - save->cpl, save->efer); + pr_err("vmpl: %d cpl: %d efer: %016llx\n", + save->vmpl, save->cpl, save->efer); pr_err("%-15s %016llx %-13s %016llx\n", "cr0:", save->cr0, "cr2:", save->cr2); pr_err("%-15s %016llx %-13s %016llx\n", From patchwork Fri Oct 8 18:04:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545929 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECCADC433F5 for ; Fri, 8 Oct 2021 18:06:10 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 8D68161029 for ; Fri, 8 Oct 2021 18:06:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 8D68161029 Authentication-Results: mail.kernel.org; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 21/42] KVM: SVM: Create a separate mapping for the SEV-ES save area Date: Fri, 8 Oct 2021 13:04:32 -0500 Message-ID: <20211008180453.462291-22-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7a146aea-f343-4c47-2f6f-08d98a86422d X-MS-TrafficTypeDiagnostic: CH0PR12MB5187: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QqxSWvBXflfmErCt8l9iFDMSm8T1Wueqi81XzFbmKPGwU4hkU5MZ/Hw5C6jOj2POif8DawlsyCAe7Wj1dNPC5psfKsbffLKFn+0lWehmb+Fwen46t5SzA7FspDVTGyOlwSQ/BFP/KNTXhTLpuH2Rel/wqgCJYohSKmiB6HZSbppaBoPuY8SRpBJJo3ApwQe/SsA7tpmJ4vmmeP6uDdBC3YA4AENSjfTlTPkD9bfAB14F+BLGnhZVOaJjfeKUKfiGBuhOzVii6jCHMl2WbZSgkGEqZ5pK4DPvESTNOoGGag7i0HsHP9WhTOiP7G/nPfmYznlxmHqzK3CHQxjqDYBQDZw5rbloDNJv7qJQggMyCFB/8gtdGFTwRXAWxj03ceLTstwg8Zmmo37mycSIbJD1FGRH33fkiNdOmAwLaRgpsjtDNG/m2sV/VbW86S/DJy3GPeoEfp6wE1+tpciq8vi94CfTdPd3L+oMhXLPA/k/5RRaQXsz8tR28DAvteE6ZsFoN+7NAyC9ndKiAHnY0mXfAisuLasG+6S7Gp+kyWYVLWcIHDzS8aqRlADtgaKC3AkOwdr2hyjSq2s7jDSLUuxhUj0MSjh6hkpC/grWTIGfRboEla5UJT23WFKuODlfrXg5J6PbSoccsDHw8xIfL8e4zLRv+232U2TScVAwP6J88uYRk69LAAWumazEIs3EWcZbBD7nkAR08naoirjkEztb93tUZ1UOKApyNmVJWPu5Fh3nURXl9yRAtVObyIGgwlBS X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(86362001)(8936002)(70206006)(7406005)(5660300002)(7696005)(83380400001)(356005)(2906002)(316002)(110136005)(54906003)(7416002)(47076005)(336012)(81166007)(36860700001)(82310400003)(2616005)(426003)(8676002)(44832011)(26005)(16526019)(186003)(6666004)(36756003)(1076003)(70586007)(4326008)(508600001)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:48.8505 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a146aea-f343-4c47-2f6f-08d98a86422d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5187 X-Rspamd-Queue-Id: 312D21001CB3 X-Stat-Signature: 43hugxqy5xtihi7sfpqkdtarpcxux34x Authentication-Results: imf07.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=KZu5nHD4; spf=pass (imf07.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.243.76 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam06 X-HE-Tag: 1633716353-635013 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Tom Lendacky The save area for SEV-ES/SEV-SNP guests, as used by the hardware, is different from the save area of a non SEV-ES/SEV-SNP guest. This is the first step in defining the multiple save areas to keep them separate and ensuring proper operation amongst the different types of guests. Create an SEV-ES/SEV-SNP save area and adjust usage to the new save area definition where needed. Signed-off-by: Tom Lendacky Signed-off-by: Brijesh Singh --- arch/x86/include/asm/svm.h | 83 +++++++++++++++++++++++++++++--------- arch/x86/kvm/svm/sev.c | 24 +++++------ arch/x86/kvm/svm/svm.h | 2 +- 3 files changed, 77 insertions(+), 32 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 7c9cf4f3c164..0df489a70945 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -227,6 +227,7 @@ struct vmcb_seg { u64 base; } __packed; +/* Save area definition for legacy and SEV-MEM guests */ struct vmcb_save_area { struct vmcb_seg es; struct vmcb_seg cs; @@ -243,8 +244,58 @@ struct vmcb_save_area { u8 cpl; u8 reserved_2[4]; u64 efer; + u8 reserved_3[112]; + u64 cr4; + u64 cr3; + u64 cr0; + u64 dr7; + u64 dr6; + u64 rflags; + u64 rip; + u8 reserved_4[88]; + u64 rsp; + u64 s_cet; + u64 ssp; + u64 isst_addr; + u64 rax; + u64 star; + u64 lstar; + u64 cstar; + u64 sfmask; + u64 kernel_gs_base; + u64 sysenter_cs; + u64 sysenter_esp; + u64 sysenter_eip; + u64 cr2; + u8 reserved_5[32]; + u64 g_pat; + u64 dbgctl; + u64 br_from; + u64 br_to; + u64 last_excp_from; + u64 last_excp_to; + u8 reserved_6[72]; + u32 spec_ctrl; /* Guest version of SPEC_CTRL at 0x2E0 */ +} __packed; + +/* Save area definition for SEV-ES and SEV-SNP guests */ +struct sev_es_save_area { + struct vmcb_seg es; + struct vmcb_seg cs; + struct vmcb_seg ss; + struct vmcb_seg ds; + struct vmcb_seg fs; + struct vmcb_seg gs; + struct vmcb_seg gdtr; + struct vmcb_seg ldtr; + struct vmcb_seg idtr; + struct vmcb_seg tr; + u8 reserved_1[43]; + u8 cpl; + u8 reserved_2[4]; + u64 efer; u8 reserved_3[104]; - u64 xss; /* Valid for SEV-ES only */ + u64 xss; u64 cr4; u64 cr3; u64 cr0; @@ -272,22 +323,14 @@ struct vmcb_save_area { u64 br_to; u64 last_excp_from; u64 last_excp_to; - - /* - * The following part of the save area is valid only for - * SEV-ES guests when referenced through the GHCB or for - * saving to the host save area. - */ - u8 reserved_7[72]; - u32 spec_ctrl; /* Guest version of SPEC_CTRL at 0x2E0 */ - u8 reserved_7b[4]; + u8 reserved_7[80]; u32 pkru; - u8 reserved_7a[20]; - u64 reserved_8; /* rax already available at 0x01f8 */ + u8 reserved_9[20]; + u64 reserved_10; /* rax already available at 0x01f8 */ u64 rcx; u64 rdx; u64 rbx; - u64 reserved_9; /* rsp already available at 0x01d8 */ + u64 reserved_11; /* rsp already available at 0x01d8 */ u64 rbp; u64 rsi; u64 rdi; @@ -299,21 +342,21 @@ struct vmcb_save_area { u64 r13; u64 r14; u64 r15; - u8 reserved_10[16]; + u8 reserved_12[16]; u64 sw_exit_code; u64 sw_exit_info_1; u64 sw_exit_info_2; u64 sw_scratch; u64 sev_features; - u8 reserved_11[48]; + u8 reserved_13[48]; u64 xcr0; u8 valid_bitmap[16]; u64 x87_state_gpa; } __packed; struct ghcb { - struct vmcb_save_area save; - u8 reserved_save[2048 - sizeof(struct vmcb_save_area)]; + struct sev_es_save_area save; + u8 reserved_save[2048 - sizeof(struct sev_es_save_area)]; u8 shared_buffer[2032]; @@ -323,13 +366,15 @@ struct ghcb { } __packed; -#define EXPECTED_VMCB_SAVE_AREA_SIZE 1032 +#define EXPECTED_VMCB_SAVE_AREA_SIZE 740 +#define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1032 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024 #define EXPECTED_GHCB_SIZE PAGE_SIZE static inline void __unused_size_checks(void) { BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE); + BUILD_BUG_ON(sizeof(struct sev_es_save_area) != EXPECTED_SEV_ES_SAVE_AREA_SIZE); BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE); BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE); } @@ -399,7 +444,7 @@ struct vmcb { /* GHCB Accessor functions */ #define GHCB_BITMAP_IDX(field) \ - (offsetof(struct vmcb_save_area, field) / sizeof(u64)) + (offsetof(struct sev_es_save_area, field) / sizeof(u64)) #define DEFINE_GHCB_ACCESSORS(field) \ static inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \ diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index c36b5fe4c27c..4d3c5b302586 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -551,12 +551,20 @@ static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp) static int sev_es_sync_vmsa(struct vcpu_svm *svm) { - struct vmcb_save_area *save = &svm->vmcb->save; + struct sev_es_save_area *save = svm->vmsa; /* Check some debug related fields before encrypting the VMSA */ - if (svm->vcpu.guest_debug || (save->dr7 & ~DR7_FIXED_1)) + if (svm->vcpu.guest_debug || (svm->vmcb->save.dr7 & ~DR7_FIXED_1)) return -EINVAL; + /* + * SEV-ES will use a VMSA that is pointed to by the VMCB, not + * the traditional VMSA that is part of the VMCB. Copy the + * traditional VMSA as it has been built so far (in prep + * for LAUNCH_UPDATE_VMSA) to be the initial SEV-ES state. + */ + memcpy(save, &svm->vmcb->save, sizeof(svm->vmcb->save)); + /* Sync registgers */ save->rax = svm->vcpu.arch.regs[VCPU_REGS_RAX]; save->rbx = svm->vcpu.arch.regs[VCPU_REGS_RBX]; @@ -584,14 +592,6 @@ static int sev_es_sync_vmsa(struct vcpu_svm *svm) save->xss = svm->vcpu.arch.ia32_xss; save->dr6 = svm->vcpu.arch.dr6; - /* - * SEV-ES will use a VMSA that is pointed to by the VMCB, not - * the traditional VMSA that is part of the VMCB. Copy the - * traditional VMSA as it has been built so far (in prep - * for LAUNCH_UPDATE_VMSA) to be the initial SEV-ES state. - */ - memcpy(svm->vmsa, save, sizeof(*save)); - return 0; } @@ -2645,7 +2645,7 @@ void sev_es_create_vcpu(struct vcpu_svm *svm) void sev_es_prepare_guest_switch(struct vcpu_svm *svm, unsigned int cpu) { struct svm_cpu_data *sd = per_cpu(svm_data, cpu); - struct vmcb_save_area *hostsa; + struct sev_es_save_area *hostsa; /* * As an SEV-ES guest, hardware will restore the host state on VMEXIT, @@ -2655,7 +2655,7 @@ void sev_es_prepare_guest_switch(struct vcpu_svm *svm, unsigned int cpu) vmsave(__sme_page_pa(sd->save_area)); /* XCR0 is restored on VMEXIT, save the current host value */ - hostsa = (struct vmcb_save_area *)(page_address(sd->save_area) + 0x400); + hostsa = (struct sev_es_save_area *)(page_address(sd->save_area) + 0x400); hostsa->xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); /* PKRU is restored on VMEXIT, save the current host value */ diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 58350deb428b..689d99cd7b9d 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -184,7 +184,7 @@ struct vcpu_svm { } shadow_msr_intercept; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 22/42] KVM: SVM: Create a separate mapping for the GHCB save area Date: Fri, 8 Oct 2021 13:04:33 -0500 Message-ID: <20211008180453.462291-23-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 96db19f3-0c7a-41a8-72f9-08d98a864386 X-MS-TrafficTypeDiagnostic: CH2PR12MB4937: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ftWy88xQ7tmCWZFMyQQSZKMQdSZwEH9ZGO5D7rHstWiwhOeP/PLyxpy9615qqqI/yIrU/cFlBRT1dC98uynXWJ/tMmSxBcaXOecJ5VfuW1R0RiZ/NQDFliieq44CAULlD2GZxi9gwGa5hlLZzU5nPm5oO0BSHWokVRFxpqn1oOGX/y5/KIVnPsbkVBd1xOWO1Iwycq6w/g89YVlB3QkUSfcMhJR5Il9xcMX38bcIo/WRug7OfhKuQlviykgTkAunKmvzgQ/QJMVu3oy4ndvvCi8RU8Zfa9IdHzNrXWV+xko9nqHDvsNumOQe1EGPbhqxb2mggRtwN84AU9AKhD+4wORoJ1FSUOQvQBCup+9JFvKoh+VkiU3wgN1aGeNeu6NDawLZqfRqjrJmdyGHr9fYV9UD/cFpvfB2Iid3SeGwg9dJHjTzAvy6FYTzBpuU3ape2hlDxJRyiULpvbFMOwzA0boRgl+fB1+4n8qXs5KlLuxPQ809YUO0MucWfZtyWsXykbc/X3Co/Q3UZp6xApMVbcj7SfJWvt3vfu2Z3/h6kGUPURuDHwMySQ+xY7ENe5BzOvGiM0PkJpLYa5MSD3ELN7e2umO/3cO/cFu5N/WLgsJg0i6i+a/s+knmeaBaOhNbO3Ow42b0JdELU5MM+CIvw6GdOz81suRhgyYMljETpGROl9InDm+L6lkI7P3wy44c6t2tzrTZutftPGafy/G/I9Lp0fu3Gw8lLBMT2kH0VNvNrxgKF5+ilTfi12sVO01p X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(186003)(110136005)(54906003)(7406005)(1076003)(16526019)(7416002)(7696005)(70206006)(26005)(8936002)(356005)(2906002)(70586007)(81166007)(6666004)(4326008)(44832011)(83380400001)(426003)(5660300002)(508600001)(316002)(2616005)(86362001)(336012)(8676002)(36860700001)(47076005)(36756003)(82310400003)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:51.1122 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96db19f3-0c7a-41a8-72f9-08d98a864386 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4937 X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: A37B0D0020D8 X-Stat-Signature: tpph5sadk3bhutpe1jq6stb4t49s8mfk Authentication-Results: imf15.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=gIe0RU6Z; dmarc=pass (policy=quarantine) header.from=amd.com; spf=pass (imf15.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.237.74 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com X-HE-Tag: 1633716355-445555 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Tom Lendacky The initial implementation of the GHCB spec was based on trying to keep the register state offsets the same relative to the VM save area. However, the save area for SEV-ES has changed within the hardware causing the relation between the SEV-ES save area to change relative to the GHCB save area. This is the second step in defining the multiple save areas to keep them separate and ensuring proper operation amongst the different types of guests. Create a GHCB save area that matches the GHCB specification. Signed-off-by: Tom Lendacky Signed-off-by: Brijesh Singh --- arch/x86/include/asm/svm.h | 48 +++++++++++++++++++++++++++++++++++--- 1 file changed, 45 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 0df489a70945..4a4de2454ca3 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -354,9 +354,49 @@ struct sev_es_save_area { u64 x87_state_gpa; } __packed; +struct ghcb_save_area { + u8 reserved_1[203]; + u8 cpl; + u8 reserved_2[116]; + u64 xss; + u8 reserved_3[24]; + u64 dr7; + u8 reserved_4[16]; + u64 rip; + u8 reserved_5[88]; + u64 rsp; + u8 reserved_6[24]; + u64 rax; + u8 reserved_7[264]; + u64 rcx; + u64 rdx; + u64 rbx; + u8 reserved_8[8]; + u64 rbp; + u64 rsi; + u64 rdi; + u64 r8; + u64 r9; + u64 r10; + u64 r11; + u64 r12; + u64 r13; + u64 r14; + u64 r15; + u8 reserved_9[16]; + u64 sw_exit_code; + u64 sw_exit_info_1; + u64 sw_exit_info_2; + u64 sw_scratch; + u8 reserved_10[56]; + u64 xcr0; + u8 valid_bitmap[16]; + u64 x87_state_gpa; +} __packed; + struct ghcb { - struct sev_es_save_area save; - u8 reserved_save[2048 - sizeof(struct sev_es_save_area)]; + struct ghcb_save_area save; + u8 reserved_save[2048 - sizeof(struct ghcb_save_area)]; u8 shared_buffer[2032]; @@ -367,6 +407,7 @@ struct ghcb { #define EXPECTED_VMCB_SAVE_AREA_SIZE 740 +#define EXPECTED_GHCB_SAVE_AREA_SIZE 1032 #define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1032 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024 #define EXPECTED_GHCB_SIZE PAGE_SIZE @@ -374,6 +415,7 @@ struct ghcb { static inline void __unused_size_checks(void) { BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE); + BUILD_BUG_ON(sizeof(struct ghcb_save_area) != EXPECTED_GHCB_SAVE_AREA_SIZE); BUILD_BUG_ON(sizeof(struct sev_es_save_area) != EXPECTED_SEV_ES_SAVE_AREA_SIZE); BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE); BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE); @@ -444,7 +486,7 @@ struct vmcb { /* GHCB Accessor functions */ #define GHCB_BITMAP_IDX(field) \ - (offsetof(struct sev_es_save_area, field) / sizeof(u64)) + (offsetof(struct ghcb_save_area, field) / sizeof(u64)) #define DEFINE_GHCB_ACCESSORS(field) \ static inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \ From patchwork Fri Oct 8 18:04:34 2021 Content-Type: text/plain; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 23/42] KVM: SVM: Update the SEV-ES save area mapping Date: Fri, 8 Oct 2021 13:04:34 -0500 Message-ID: <20211008180453.462291-24-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9e37336b-e18d-4389-130b-08d98a86448b X-MS-TrafficTypeDiagnostic: MWHPR12MB1648: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CtnGNw8ostUWOEoanhbdw03SkwOV0W1uJf6kNTaEMBoYhXJ8c9xPrjcKxR3b/dvdF2aPOPb7KiBIb1RoqrE83XkABBgYTdHw1S+5TqGrAhjwgIkePbPRVxUzPO7FNXCZmzXtVmN688TXvgicd5KlfEO1o8UTBQL8dn/77m0JDyhgMLy35VW7AUv142qBupL03+h1lhyUs42Ll9Qej6NNxcnuirLEiRWqqDIeXrP+yNVorU2o4mU3IwBcbVivlXVXKH+KpGWHk1QYTV7CB8CS+yB1eM0a06SQ+bIhrIAKBU/nXDnYHAzTFObpPelxX/vlJO+iyJBcwULNQiBcFofrQmTkj3tPXTErTXkhO/5sjtVEMkq8OREH8cMKlsnoYfPiEkaoj095G2P3tRS+KHEXV48YOKm/cWTMr0zQsh8q64WV6xZUw2Zx0pBq0ipM60yaNh+IoFXgNNOVtIk0IiW6/yaR+Xx9kvVge15fawrjG3e5ksSe+9lLVdT+xU/XyZzQfWCEOKMRJy/4okuTI+MD5JypK1bSN3EfiMYcAycOR9NHkmHLJ97QZezewNLcacJpD+sRbfs7+y26gAFFTlCJiCAO1gm0+7WjG7LxkTcag6o/fHuCUll6reqWBJUwQaFUxdw2duDzj+muzh8DrvLa+J9izn7P8dF9fZ3+w7AmEc7ajVyURkwG6yhCH0zGYnSaGgdPzL7wX+mABf5lrs1fPZcJxWBSt1HWVnH/pr0ehbzTACe3jHPHv+Pu4iSMaqdH X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(15650500001)(8936002)(47076005)(54906003)(508600001)(83380400001)(110136005)(36860700001)(356005)(316002)(81166007)(16526019)(336012)(6666004)(186003)(70586007)(1076003)(5660300002)(4326008)(86362001)(426003)(2906002)(70206006)(36756003)(7406005)(44832011)(8676002)(7696005)(7416002)(26005)(82310400003)(2616005)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:52.8212 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9e37336b-e18d-4389-130b-08d98a86448b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1648 X-Rspamd-Server: rspam03 X-Rspamd-Queue-Id: A02B4B000BE0 X-Stat-Signature: c3kbtngwjujqqomts5ajgehm68tfdq91 Authentication-Results: imf24.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=azAVqVgR; dmarc=pass (policy=quarantine) header.from=amd.com; spf=pass (imf24.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.92.48 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com X-HE-Tag: 1633716357-456066 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Tom Lendacky This is the final step in defining the multiple save areas to keep them separate and ensuring proper operation amongst the different types of guests. Update the SEV-ES/SEV-SNP save area to match the APM. This save area will be used for the upcoming SEV-SNP AP Creation NAE event support. Signed-off-by: Tom Lendacky Signed-off-by: Brijesh Singh --- arch/x86/include/asm/svm.h | 66 +++++++++++++++++++++++++++++--------- 1 file changed, 50 insertions(+), 16 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 4a4de2454ca3..c75f46cf27db 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -290,7 +290,13 @@ struct sev_es_save_area { struct vmcb_seg ldtr; struct vmcb_seg idtr; struct vmcb_seg tr; - u8 reserved_1[43]; + u64 vmpl0_ssp; + u64 vmpl1_ssp; + u64 vmpl2_ssp; + u64 vmpl3_ssp; + u64 u_cet; + u8 reserved_1[2]; + u8 vmpl; u8 cpl; u8 reserved_2[4]; u64 efer; @@ -303,9 +309,19 @@ struct sev_es_save_area { u64 dr6; u64 rflags; u64 rip; - u8 reserved_4[88]; + u64 dr0; + u64 dr1; + u64 dr2; + u64 dr3; + u64 dr0_addr_mask; + u64 dr1_addr_mask; + u64 dr2_addr_mask; + u64 dr3_addr_mask; + u8 reserved_4[24]; u64 rsp; - u8 reserved_5[24]; + u64 s_cet; + u64 ssp; + u64 isst_addr; u64 rax; u64 star; u64 lstar; @@ -316,7 +332,7 @@ struct sev_es_save_area { u64 sysenter_esp; u64 sysenter_eip; u64 cr2; - u8 reserved_6[32]; + u8 reserved_5[32]; u64 g_pat; u64 dbgctl; u64 br_from; @@ -325,12 +341,12 @@ struct sev_es_save_area { u64 last_excp_to; u8 reserved_7[80]; u32 pkru; - u8 reserved_9[20]; - u64 reserved_10; /* rax already available at 0x01f8 */ + u8 reserved_8[20]; + u64 reserved_9; /* rax already available at 0x01f8 */ u64 rcx; u64 rdx; u64 rbx; - u64 reserved_11; /* rsp already available at 0x01d8 */ + u64 reserved_10; /* rsp already available at 0x01d8 */ u64 rbp; u64 rsi; u64 rdi; @@ -342,16 +358,34 @@ struct sev_es_save_area { u64 r13; u64 r14; u64 r15; - u8 reserved_12[16]; - u64 sw_exit_code; - u64 sw_exit_info_1; - u64 sw_exit_info_2; - u64 sw_scratch; + u8 reserved_11[16]; + u64 guest_exit_info_1; + u64 guest_exit_info_2; + u64 guest_exit_int_info; + u64 guest_nrip; u64 sev_features; - u8 reserved_13[48]; + u64 vintr_ctrl; + u64 guest_exit_code; + u64 virtual_tom; + u64 tlb_id; + u64 pcpu_id; + u64 event_inj; u64 xcr0; - u8 valid_bitmap[16]; - u64 x87_state_gpa; + u8 reserved_12[16]; + + /* Floating point area */ + u64 x87_dp; + u32 mxcsr; + u16 x87_ftw; + u16 x87_fsw; + u16 x87_fcw; + u16 x87_fop; + u16 x87_ds; + u16 x87_cs; + u64 x87_rip; + u8 fpreg_x87[80]; + u8 fpreg_xmm[256]; + u8 fpreg_ymm[256]; } __packed; struct ghcb_save_area { @@ -408,7 +442,7 @@ struct ghcb { #define EXPECTED_VMCB_SAVE_AREA_SIZE 740 #define EXPECTED_GHCB_SAVE_AREA_SIZE 1032 -#define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1032 +#define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1648 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024 #define EXPECTED_GHCB_SIZE PAGE_SIZE From patchwork Fri Oct 8 18:04:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC49BC433F5 for ; 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Fri, 8 Oct 2021 13:05:51 -0500 From: Brijesh Singh To: , , , , , , CC: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , "Vitaly Kuznetsov" , Jim Mattson , "Andy Lutomirski" , Dave Hansen , Sergio Lopez , Peter Gonda , "Peter Zijlstra" , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , "Dr . David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 24/42] x86/sev: Use SEV-SNP AP creation to start secondary CPUs Date: Fri, 8 Oct 2021 13:04:35 -0500 Message-ID: <20211008180453.462291-25-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d9a46dd4-8ef7-467f-09d2-08d98a864512 X-MS-TrafficTypeDiagnostic: SN1PR12MB2384: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: x3LAlDAQFgjq9DlyfOAWDA87h9i6DHAHNANrIXiSYHgbvH+DDfxXNyFfSLETpFsnU5kdoSWez6K63cYrjvHEvYK9aWsOGvMTx0NPNOTXAkPWdticA3hSznE/GFWdhwNFTgjuRSG5L4WGOYThIzBvxGc3zsXakChOwrCARPD2mjcsSZkPOwB82tMH02Zo5/aTXHlC/kAWWxxwCELcnaK3SG3khP9Hib1KhqjF+Q/kyUXcYPReUn00NSfyzKi+GhpZl+054OZuVu//mtErD7w7zdfbXcBUCbDZxvwYZ0WqyRc4BuAZK9mj9WRZAHSbXmSMyHSBCxhUKPkAc2fLUXHheybYCSLYFEO12vGVR7R5VGIEwjwLz2TgQ+NxSzBNiN/mlBUCENun0m5wvWaEpuX42GN6jkb9yiJNzbOhhXduq0N4zjXivko8M3WamALl6kSO6LVD1hT5e2vxWFg++64oSTcnygqOYWVXsUn6+qDzHuAWCJSB9fOtDsjB30soEdr2a4Aqd4I4dHZFLuUsBqXnLvFykX5cBAqptDCz2WGu/Iv536swJ7nH9Sc4/kU+AzKBzOKA3hhim5WEO/L64NH425xpAYjbP+UcqT6blWeayJSVoW5hTGGMVYlkppTTPi4Xa9XnEAzXkXGp9aIJYPoxdTL3mOkfzoQ5qH9BasiG3NQrJC5rgMBbk0n4nfqfFSuIGxFB/i2uU+aNHFugN2Lv9Mo5Q4EGvHHBFED/+WRvqCxxprIYB1mZbtQhU6b8uZ5x X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(83380400001)(186003)(6666004)(16526019)(336012)(426003)(7416002)(82310400003)(44832011)(7696005)(36756003)(2616005)(8676002)(7406005)(26005)(86362001)(54906003)(110136005)(36860700001)(356005)(508600001)(4326008)(70586007)(70206006)(81166007)(8936002)(316002)(2906002)(5660300002)(47076005)(1076003)(30864003)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:53.7067 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9a46dd4-8ef7-467f-09d2-08d98a864512 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR12MB2384 X-Rspamd-Server: rspam02 X-Rspamd-Queue-Id: 8EA8FB001BF3 X-Stat-Signature: 6a6479spt434xdzeeoeuo798jmiyair3 Authentication-Results: imf24.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=lfn0xZGU; spf=pass (imf24.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.237.87 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-HE-Tag: 1633716358-7617 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Tom Lendacky To provide a more secure way to start APs under SEV-SNP, use the SEV-SNP AP Creation NAE event. This allows for guest control over the AP register state rather than trusting the hypervisor with the SEV-ES Jump Table address. During native_smp_prepare_cpus(), invoke an SEV-SNP function that, if SEV-SNP is active, will set/override apic->wakeup_secondary_cpu. This will allow the SEV-SNP AP Creation NAE event method to be used to boot the APs. As a result of installing the override when SEV-SNP is active, this method of starting the APs becomes the required method. The override function will fail to start the AP if the hypervisor does not have support for AP creation. Signed-off-by: Tom Lendacky Signed-off-by: Brijesh Singh --- arch/x86/include/asm/sev-common.h | 1 + arch/x86/include/asm/sev.h | 4 + arch/x86/include/uapi/asm/svm.h | 5 + arch/x86/kernel/sev.c | 205 ++++++++++++++++++++++++++++++ arch/x86/kernel/smpboot.c | 3 + 5 files changed, 218 insertions(+) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index c2c5d60f0da0..c380aba9fc8d 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -104,6 +104,7 @@ enum psc_op { (((u64)(v) & GENMASK_ULL(63, 12)) >> 12) #define GHCB_HV_FT_SNP BIT_ULL(0) +#define GHCB_HV_FT_SNP_AP_CREATION (BIT_ULL(1) | GHCB_HV_FT_SNP) /* SNP Page State Change NAE event */ #define VMGEXIT_PSC_MAX_ENTRY 253 diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 005f230d0406..7f063127aa66 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -65,6 +65,8 @@ extern bool handle_vc_boot_ghcb(struct pt_regs *regs); /* RMP page size */ #define RMP_PG_SIZE_4K 0 +#define RMPADJUST_VMSA_PAGE_BIT BIT(16) + #ifdef CONFIG_AMD_MEM_ENCRYPT extern struct static_key_false sev_es_enable_key; extern void __sev_es_ist_enter(struct pt_regs *regs); @@ -111,6 +113,7 @@ void __init early_snp_set_memory_shared(unsigned long vaddr, unsigned long paddr void __init snp_prep_memory(unsigned long paddr, unsigned int sz, enum psc_op op); void snp_set_memory_shared(unsigned long vaddr, unsigned int npages); void snp_set_memory_private(unsigned long vaddr, unsigned int npages); +void snp_set_wakeup_secondary_cpu(void); #else static inline void sev_es_ist_enter(struct pt_regs *regs) { } static inline void sev_es_ist_exit(void) { } @@ -125,6 +128,7 @@ early_snp_set_memory_shared(unsigned long vaddr, unsigned long paddr, unsigned i static inline void __init snp_prep_memory(unsigned long paddr, unsigned int sz, enum psc_op op) { } static inline void snp_set_memory_shared(unsigned long vaddr, unsigned int npages) { } static inline void snp_set_memory_private(unsigned long vaddr, unsigned int npages) { } +static inline void snp_set_wakeup_secondary_cpu(void) { } #endif #endif diff --git a/arch/x86/include/uapi/asm/svm.h b/arch/x86/include/uapi/asm/svm.h index 0dcdb6e0c913..8b4c57baec52 100644 --- a/arch/x86/include/uapi/asm/svm.h +++ b/arch/x86/include/uapi/asm/svm.h @@ -109,6 +109,10 @@ #define SVM_VMGEXIT_SET_AP_JUMP_TABLE 0 #define SVM_VMGEXIT_GET_AP_JUMP_TABLE 1 #define SVM_VMGEXIT_PSC 0x80000010 +#define SVM_VMGEXIT_AP_CREATION 0x80000013 +#define SVM_VMGEXIT_AP_CREATE_ON_INIT 0 +#define SVM_VMGEXIT_AP_CREATE 1 +#define SVM_VMGEXIT_AP_DESTROY 2 #define SVM_VMGEXIT_HV_FEATURES 0x8000fffd #define SVM_VMGEXIT_UNSUPPORTED_EVENT 0x8000ffff @@ -221,6 +225,7 @@ { SVM_VMGEXIT_AP_HLT_LOOP, "vmgexit_ap_hlt_loop" }, \ { SVM_VMGEXIT_AP_JUMP_TABLE, "vmgexit_ap_jump_table" }, \ { SVM_VMGEXIT_PSC, "vmgexit_page_state_change" }, \ + { SVM_VMGEXIT_AP_CREATION, "vmgexit_ap_creation" }, \ { SVM_VMGEXIT_HV_FEATURES, "vmgexit_hypervisor_feature" }, \ { SVM_EXIT_ERR, "invalid_guest_state" } diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 80fdfd83770a..dfb5b2920933 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -31,6 +32,7 @@ #include #include #include +#include #define DR7_RESET_VALUE 0x400 @@ -94,6 +96,8 @@ struct ghcb_state { static DEFINE_PER_CPU(struct sev_es_runtime_data*, runtime_data); DEFINE_STATIC_KEY_FALSE(sev_es_enable_key); +static DEFINE_PER_CPU(struct sev_es_save_area *, snp_vmsa); + static __always_inline bool on_vc_stack(struct pt_regs *regs) { unsigned long sp = regs->sp; @@ -820,6 +824,207 @@ void snp_set_memory_private(unsigned long vaddr, unsigned int npages) pvalidate_pages(vaddr, npages, 1); } +static int rmpadjust(void *va, bool vmsa) +{ + u64 attrs; + int err; + + /* + * The RMPADJUST instruction is used to set or clear the VMSA bit for + * a page. A change to the VMSA bit is only performed when running + * at VMPL0 and is ignored at other VMPL levels. If too low of a target + * VMPL level is specified, the instruction can succeed without changing + * the VMSA bit should the kernel not be in VMPL0. Using a target VMPL + * level of 1 will return a FAIL_PERMISSION error if the kernel is not + * at VMPL0, thus ensuring that the VMSA bit has been properly set when + * no error is returned. + */ + attrs = 1; + if (vmsa) + attrs |= RMPADJUST_VMSA_PAGE_BIT; + + /* Instruction mnemonic supported in binutils versions v2.36 and later */ + asm volatile (".byte 0xf3,0x0f,0x01,0xfe\n\t" + : "=a" (err) + : "a" (va), "c" (RMP_PG_SIZE_4K), "d" (attrs) + : "memory", "cc"); + + return err; +} + +#define __ATTR_BASE (SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK) +#define INIT_CS_ATTRIBS (__ATTR_BASE | SVM_SELECTOR_READ_MASK | SVM_SELECTOR_CODE_MASK) +#define INIT_DS_ATTRIBS (__ATTR_BASE | SVM_SELECTOR_WRITE_MASK) + +#define INIT_LDTR_ATTRIBS (SVM_SELECTOR_P_MASK | 2) +#define INIT_TR_ATTRIBS (SVM_SELECTOR_P_MASK | 3) + +static int wakeup_cpu_via_vmgexit(int apic_id, unsigned long start_ip) +{ + struct sev_es_save_area *cur_vmsa, *vmsa; + struct ghcb_state state; + unsigned long flags; + struct ghcb *ghcb; + int cpu, err, ret; + u8 sipi_vector; + u64 cr4; + + if ((sev_hv_features & GHCB_HV_FT_SNP_AP_CREATION) != GHCB_HV_FT_SNP_AP_CREATION) + return -EOPNOTSUPP; + + /* + * Verify the desired start IP against the known trampoline start IP + * to catch any future new trampolines that may be introduced that + * would require a new protected guest entry point. + */ + if (WARN_ONCE(start_ip != real_mode_header->trampoline_start, + "Unsupported SEV-SNP start_ip: %lx\n", start_ip)) + return -EINVAL; + + /* Override start_ip with known protected guest start IP */ + start_ip = real_mode_header->sev_es_trampoline_start; + + /* Find the logical CPU for the APIC ID */ + for_each_present_cpu(cpu) { + if (arch_match_cpu_phys_id(cpu, apic_id)) + break; + } + if (cpu >= nr_cpu_ids) + return -EINVAL; + + cur_vmsa = per_cpu(snp_vmsa, cpu); + + /* + * A new VMSA is created each time because there is no guarantee that + * the current VMSA is the kernels or that the vCPU is not running. If + * an attempt was done to use the current VMSA with a running vCPU, a + * #VMEXIT of that vCPU would wipe out all of the settings being done + * here. + */ + vmsa = (struct sev_es_save_area *)get_zeroed_page(GFP_KERNEL); + if (!vmsa) + return -ENOMEM; + + /* CR4 should maintain the MCE value */ + cr4 = native_read_cr4() & X86_CR4_MCE; + + /* Set the CS value based on the start_ip converted to a SIPI vector */ + sipi_vector = (start_ip >> 12); + vmsa->cs.base = sipi_vector << 12; + vmsa->cs.limit = 0xffff; + vmsa->cs.attrib = INIT_CS_ATTRIBS; + vmsa->cs.selector = sipi_vector << 8; + + /* Set the RIP value based on start_ip */ + vmsa->rip = start_ip & 0xfff; + + /* Set VMSA entries to the INIT values as documented in the APM */ + vmsa->ds.limit = 0xffff; + vmsa->ds.attrib = INIT_DS_ATTRIBS; + vmsa->es = vmsa->ds; + vmsa->fs = vmsa->ds; + vmsa->gs = vmsa->ds; + vmsa->ss = vmsa->ds; + + vmsa->gdtr.limit = 0xffff; + vmsa->ldtr.limit = 0xffff; + vmsa->ldtr.attrib = INIT_LDTR_ATTRIBS; + vmsa->idtr.limit = 0xffff; + vmsa->tr.limit = 0xffff; + vmsa->tr.attrib = INIT_TR_ATTRIBS; + + vmsa->efer = 0x1000; /* Must set SVME bit */ + vmsa->cr4 = cr4; + vmsa->cr0 = 0x60000010; + vmsa->dr7 = 0x400; + vmsa->dr6 = 0xffff0ff0; + vmsa->rflags = 0x2; + vmsa->g_pat = 0x0007040600070406ULL; + vmsa->xcr0 = 0x1; + vmsa->mxcsr = 0x1f80; + vmsa->x87_ftw = 0x5555; + vmsa->x87_fcw = 0x0040; + + /* + * Set the SNP-specific fields for this VMSA: + * VMPL level + * SEV_FEATURES (matches the SEV STATUS MSR right shifted 2 bits) + */ + vmsa->vmpl = 0; + vmsa->sev_features = sev_status >> 2; + + /* Switch the page over to a VMSA page now that it is initialized */ + ret = rmpadjust(vmsa, true); + if (ret) { + pr_err("set VMSA page failed (%u)\n", ret); + free_page((unsigned long)vmsa); + + return -EINVAL; + } + + /* Issue VMGEXIT AP Creation NAE event */ + local_irq_save(flags); + + ghcb = __sev_get_ghcb(&state); + + vc_ghcb_invalidate(ghcb); + ghcb_set_rax(ghcb, vmsa->sev_features); + ghcb_set_sw_exit_code(ghcb, SVM_VMGEXIT_AP_CREATION); + ghcb_set_sw_exit_info_1(ghcb, ((u64)apic_id << 32) | SVM_VMGEXIT_AP_CREATE); + ghcb_set_sw_exit_info_2(ghcb, __pa(vmsa)); + + sev_es_wr_ghcb_msr(__pa(ghcb)); + VMGEXIT(); + + if (!ghcb_sw_exit_info_1_is_valid(ghcb) || + lower_32_bits(ghcb->save.sw_exit_info_1)) { + pr_alert("SNP AP Creation error\n"); + ret = -EINVAL; + } + + __sev_put_ghcb(&state); + + local_irq_restore(flags); + + /* Perform cleanup if there was an error */ + if (ret) { + err = rmpadjust(vmsa, false); + if (err) + pr_err("clear VMSA page failed (%u), leaking page\n", err); + else + free_page((unsigned long)vmsa); + + vmsa = NULL; + } + + /* Free up any previous VMSA page */ + if (cur_vmsa) { + err = rmpadjust(cur_vmsa, false); + if (err) + pr_err("clear VMSA page failed (%u), leaking page\n", err); + else + free_page((unsigned long)cur_vmsa); + } + + /* Record the current VMSA page */ + per_cpu(snp_vmsa, cpu) = vmsa; + + return ret; +} + +void snp_set_wakeup_secondary_cpu(void) +{ + if (!cc_platform_has(CC_ATTR_SEV_SNP)) + return; + + /* + * Always set this override if SEV-SNP is enabled. This makes it the + * required method to start APs under SEV-SNP. If the hypervisor does + * not support AP creation, then no APs will be started. + */ + apic->wakeup_secondary_cpu = wakeup_cpu_via_vmgexit; +} + int sev_es_setup_ap_jump_table(struct real_mode_header *rmh) { u16 startup_cs, startup_ip; diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index c453b825a57f..b04cf8ebcb37 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -82,6 +82,7 @@ #include #include #include +#include #ifdef CONFIG_ACPI_CPPC_LIB #include @@ -1380,6 +1381,8 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus) smp_quirk_init_udelay(); speculative_store_bypass_ht_init(); + + snp_set_wakeup_secondary_cpu(); } void arch_thaw_secondary_cpus_begin(void) From patchwork Fri Oct 8 18:04:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B579C4321E for ; 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Fri, 8 Oct 2021 13:05:53 -0500 From: Brijesh Singh To: , , , , , , CC: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , "Vitaly Kuznetsov" , Jim Mattson , "Andy Lutomirski" , Dave Hansen , Sergio Lopez , Peter Gonda , "Peter Zijlstra" , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , "Dr . David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 25/42] x86/head: re-enable stack protection for 32/64-bit builds Date: Fri, 8 Oct 2021 13:04:36 -0500 Message-ID: <20211008180453.462291-26-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 97eac712-136a-4258-f03a-08d98a864638 X-MS-TrafficTypeDiagnostic: MWHPR1201MB0029: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2yYNTAUPxEnf4Yfy58jvNAxFpltNZdb7yqdrLANEfd2FSbWSp+sf1YMT3adLm56ass/qjOKvojwcbRY3dSJ5dEHBT2YBZXuwMr/MHp1dCwtVDjmzS9EhLw/+awIU7KdF3ci1rvtL7rXDKYajksqrADDyIUE48c7/aO3idDJj9H89CNx6Kqq4grzaNBA6TymA2X8yrQoY8gbx62Id8Km0ji1tunZNft6e6wvNG255NEBq5Z2l0z9/XEYtQsgiACiqYqnC5zYlPjanBOj6lxGyHcHRczvX+wkNz65ZEzAfKzlewJ1ydiriOvlbNgbVQ934iRoLmTVXSeMXg0hD0Q834e8YOPWJMxSvbVVj/UR9FOZXfleRDRHGdSR9CFI8LE7wFSk4K3NG+ZdcLyjTJJHBIUxUP+/QeT9QEcNCZngrOreEwn3hlFGnvww1o/S2h/Ox1Zx6ol8fqUVKJW1/MFQO59ywOFNPe66trpzcr/4t+p8wxsvlPwpN+mbF842ojl4Z9AcEefLLqp+R+De0kIlW1PpJPRPUhikPC9DmupEcmeUhhiGgyyihR1LsRpkTJAM+t/dtRs3Zav9s4SrTwoOMKTimYELGeCEzm3DgH6jnRuX0WQ7XV9G5PEEzjNE3rgHdjwMP1OJKWSuR/uoiHYpGTNQrgcr8gGypxNtNhApWCmzqMrNBb0oaMg8L1HuQWBTphJVVRBFpdxO/+Zu4wRM39AbOVFBfNbCpKWuN/Tscj7whX77HtokGWsy68UApedxC X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(8936002)(70206006)(70586007)(16526019)(186003)(47076005)(6666004)(316002)(2906002)(4326008)(8676002)(26005)(82310400003)(54906003)(508600001)(7416002)(7406005)(36860700001)(5660300002)(83380400001)(44832011)(1076003)(426003)(7696005)(356005)(81166007)(110136005)(86362001)(36756003)(336012)(2616005)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:55.6484 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 97eac712-136a-4258-f03a-08d98a864638 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1201MB0029 X-Rspamd-Server: rspam01 X-Rspamd-Queue-Id: 511C4D00024D X-Stat-Signature: 4yki3ixbfq3o3w3tpjqbbdngq8e43tdx Authentication-Results: imf20.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=wbkkstah; dmarc=pass (policy=quarantine) header.from=amd.com; spf=pass (imf20.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.100.49 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com X-HE-Tag: 1633716362-228367 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Michael Roth As of commit 103a4908ad4d ("x86/head/64: Disable stack protection for head$(BITS).o") kernel/head64.c is compiled with -fno-stack-protector to allow a call to set_bringup_idt_handler(), which would otherwise have stack protection enabled with CONFIG_STACKPROTECTOR_STRONG. While sufficient for that case, there may still be issues with calls to any external functions that were compiled with stack protection enabled that in-turn make stack-protected calls, or if the exception handlers set up by set_bringup_idt_handler() make calls to stack-protected functions. As part of 103a4908ad4d, stack protection was also disabled for kernel/head32.c as a precaution. Subsequent patches for SEV-SNP CPUID validation support will introduce both such cases. Attempting to disable stack protection for everything in scope to address that is prohibitive since much of the code, like SEV-ES #VC handler, is shared code that remains in use after boot and could benefit from having stack protection enabled. Attempting to inline calls is brittle and can quickly balloon out to library/helper code where that's not really an option. Instead, re-enable stack protection for head32.c/head64.c and make the appropriate changes to ensure the segment used for the stack canary is initialized in advance of any stack-protected C calls. for head64.c: - The BSP will enter from startup_64 and call into C code (startup_64_setup_env) shortly after setting up the stack, which may result in calls to stack-protected code. Set up %gs early to allow for this safely. - APs will enter from secondary_startup_64*, and %gs will be set up soon after. There is one call to C code prior to this (__startup_secondary_64), but it is only to fetch sme_me_mask, and unlikely to be stack-protected, so leave things as they are, but add a note about this in case things change in the future. for head32.c: - BSPs/APs will set %fs to __BOOT_DS prior to any C calls. In recent kernels, the compiler is configured to access the stack canary at %fs:__stack_chk_guard, which overlaps with the initial per-cpu __stack_chk_guard variable in the initial/'master' .data..percpu area. This is sufficient to allow access to the canary for use during initial startup, so no changes are needed there. Suggested-by: Joerg Roedel #for 64-bit %gs set up Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- arch/x86/kernel/Makefile | 1 - arch/x86/kernel/head_64.S | 24 ++++++++++++++++++++++++ 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index 2ff3e600f426..4df8c8f7d2ac 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -48,7 +48,6 @@ endif # non-deterministic coverage. KCOV_INSTRUMENT := n -CFLAGS_head$(BITS).o += -fno-stack-protector CFLAGS_cc_platform.o += -fno-stack-protector CFLAGS_irq.o := -I $(srctree)/$(src)/../include/asm/trace diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index d8b3ebd2bb85..7074ebf2b47b 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -65,6 +65,22 @@ SYM_CODE_START_NOALIGN(startup_64) leaq (__end_init_task - FRAME_SIZE)(%rip), %rsp leaq _text(%rip), %rdi + + /* + * initial_gs points to initial fixed_per_cpu struct with storage for + * the stack protector canary. Global pointer fixups are needed at this + * stage, so apply them as is done in fixup_pointer(), and initialize %gs + * such that the canary can be accessed at %gs:40 for subsequent C calls. + */ + movl $MSR_GS_BASE, %ecx + movq initial_gs(%rip), %rax + movq $_text, %rdx + subq %rdx, %rax + addq %rdi, %rax + movq %rax, %rdx + shrq $32, %rdx + wrmsr + pushq %rsi call startup_64_setup_env popq %rsi @@ -133,6 +149,14 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) * added to the initial pgdir entry that will be programmed into CR3. */ pushq %rsi + /* + * NOTE: %gs at this point is a stale data segment left over from the + * real-mode trampoline, so the default stack protector canary location + * at %gs:40 does not yet coincide with the expected fixed_per_cpu struct + * that contains storage for the stack canary. So take care not to add + * anything to the C functions in this path that would result in stack + * protected C code being generated. + */ call __startup_secondary_64 popq %rsi From patchwork Fri Oct 8 18:04:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545943 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4642C4332F for ; Fri, 8 Oct 2021 18:06:29 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 7707361039 for ; Fri, 8 Oct 2021 18:06:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 7707361039 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=amd.com Authentication-Results: mail.kernel.org; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 26/42] x86/sev: move MSR-based VMGEXITs for CPUID to helper Date: Fri, 8 Oct 2021 13:04:37 -0500 Message-ID: <20211008180453.462291-27-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ff95202d-840a-4b6f-b792-08d98a864740 X-MS-TrafficTypeDiagnostic: BN6PR12MB1202: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4303; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sdFrzmvkmdQLsH+F+Wr0Kc6hAP2v6cCh7ErBWLGy6s4WRUd75eXjfEch7/P/6mquCe0ktSwDpO+zqBmv4ilJLD/eDN9KcO3aa2BKw67JKbkrToN0DvxmxGAOIMCdEUGp3m+gVGav5Ap8ODZF15AZKTGaJoTzHmFfunwf8xGATuiZfaDSSpCCQCCKeblR0u736DRh9jek/mVO5YgJGwM+OUWZur+7MIUc3Uitb8pl8448qCIN0qCmFx0Z2yONYVkgezxCqvDQEU6tBy23nJoRUOrXbxWOjOPT7uwnuIw+LnxWox+v1Y1W3m59c/IBcDD93TqCVITJtsQSuujvd3g501jdciIC6Al5T3V6YwBRB4FSEXiMEMgBdmMDke+hCmvVCR98N0OZxNSIVFjNal+VpiZHd8l/+og0WrETtDAzP1uwjorlXJeI9Vb6r+9C1k6GNySUN+YNbHJz3OgV5c6e+/GBN6yWoZlbVQhHKVXXtEkkhAgthhW5OajRL4z+fl4fE6LP/F8+P3/yVYmeGSW2Rfnc73w/8OkOeRCHR83i4HON3AXSph6VmZYS9HtrwOvCIRhO1cTG2Gx12CNiAASVcc2dBneRrkCRp/EWhtyvuCICjaD9aRaaB12Mp5gdaAF74LdtnnJoFo/LKJGjXvGEd7IdT94K8KbpmrrbBJERnzH8i19/C8dVDtrxljb/gUGJ4XmsOW9F28yO7ACxnHIg5YZfqeRJhvuggNdrqhAkmu+P/S5OgH/3gbPT30lJtFqb X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(5660300002)(83380400001)(7696005)(6666004)(2906002)(508600001)(8676002)(36756003)(7406005)(7416002)(4326008)(16526019)(186003)(1076003)(8936002)(81166007)(82310400003)(26005)(47076005)(110136005)(36860700001)(54906003)(44832011)(86362001)(70586007)(426003)(316002)(336012)(356005)(70206006)(2616005)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:57.3771 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff95202d-840a-4b6f-b792-08d98a864740 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1202 X-Rspamd-Server: rspam02 X-Rspamd-Queue-Id: 5456240039D4 X-Stat-Signature: 7zf35tp41ad1xduk43y5g5rszpm7z39o Authentication-Results: imf18.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=enYyUE+p; spf=pass (imf18.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.94.77 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-HE-Tag: 1633716367-535555 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Michael Roth This code will also be used later for SEV-SNP-validated CPUID code in some cases, so move it to a common helper. Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- arch/x86/kernel/sev-shared.c | 84 +++++++++++++++++++++++++----------- 1 file changed, 58 insertions(+), 26 deletions(-) diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index 2b53b622108f..402b19f1c75d 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -193,6 +193,58 @@ static enum es_result sev_es_ghcb_hv_call(struct ghcb *ghcb, return ret; } +static int sev_cpuid_hv(u32 func, u32 subfunc, u32 *eax, u32 *ebx, + u32 *ecx, u32 *edx) +{ + u64 val; + + if (eax) { + sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(func, GHCB_CPUID_REQ_EAX)); + VMGEXIT(); + val = sev_es_rd_ghcb_msr(); + + if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) + return -EIO; + + *eax = (val >> 32); + } + + if (ebx) { + sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(func, GHCB_CPUID_REQ_EBX)); + VMGEXIT(); + val = sev_es_rd_ghcb_msr(); + + if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) + return -EIO; + + *ebx = (val >> 32); + } + + if (ecx) { + sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(func, GHCB_CPUID_REQ_ECX)); + VMGEXIT(); + val = sev_es_rd_ghcb_msr(); + + if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) + return -EIO; + + *ecx = (val >> 32); + } + + if (edx) { + sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(func, GHCB_CPUID_REQ_EDX)); + VMGEXIT(); + val = sev_es_rd_ghcb_msr(); + + if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) + return -EIO; + + *edx = (val >> 32); + } + + return 0; +} + /* * Boot VC Handler - This is the first VC handler during boot, there is no GHCB * page yet, so it only supports the MSR based communication with the @@ -201,7 +253,7 @@ static enum es_result sev_es_ghcb_hv_call(struct ghcb *ghcb, void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code) { unsigned int fn = lower_bits(regs->ax, 32); - unsigned long val; + u32 eax, ebx, ecx, edx; /* Only CPUID is supported via MSR protocol */ if (exit_code != SVM_EXIT_CPUID) @@ -221,33 +273,13 @@ void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code) sev_status = (hi << 32) | lo; } - sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_EAX)); - VMGEXIT(); - val = sev_es_rd_ghcb_msr(); - if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) + if (sev_cpuid_hv(fn, 0, &eax, &ebx, &ecx, &edx)) goto fail; - regs->ax = val >> 32; - sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_EBX)); - VMGEXIT(); - val = sev_es_rd_ghcb_msr(); - if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) - goto fail; - regs->bx = val >> 32; - - sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_ECX)); - VMGEXIT(); - val = sev_es_rd_ghcb_msr(); - if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) - goto fail; - regs->cx = val >> 32; - - sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_EDX)); - VMGEXIT(); - val = sev_es_rd_ghcb_msr(); - if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) - goto fail; - regs->dx = val >> 32; + regs->ax = eax; + regs->bx = ebx; + regs->cx = ecx; + regs->dx = edx; /* * This is a VC handler and the #VC is only raised when SEV-ES is From patchwork Fri Oct 8 18:04:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27099C433EF for ; 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Fri, 8 Oct 2021 13:05:56 -0500 From: Brijesh Singh To: , , , , , , CC: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , "Vitaly Kuznetsov" , Jim Mattson , "Andy Lutomirski" , Dave Hansen , Sergio Lopez , Peter Gonda , "Peter Zijlstra" , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , "Dr . David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 27/42] KVM: x86: move lookup of indexed CPUID leafs to helper Date: Fri, 8 Oct 2021 13:04:38 -0500 Message-ID: <20211008180453.462291-28-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8f04729c-f7ab-46f4-383f-08d98a86487e X-MS-TrafficTypeDiagnostic: SJ0PR12MB5503: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2150; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mXbtoPs/G5gtLqi2Cfpebe5aZQiQGKfn2LqVDRRUKzly8u+0QCBkNikmhv1eSS0ul8RNxD+XcZdMtZmtQKWtZEdwJEbd8ml935ClppHG+cVJPfyuISZRY0/1Pp8t7EZ+E/QvpiN4t1dXNs2NKtIwFMYKoe3TM5r2Zu9135S2lnAMJHqfNPzGO1TROW781/aEF/oa1ENp+nIbsp2qx9Cqaeb+CgPP/ycoEK7Uuw9sWfUhQy1VrZnv2ROoDJ2jjoF58bWsvaHR7rEFDWU+A/M8cQxx/5MOy3a9BB/PWWX1sgEZ+hOZx3n1Wst0VyXbZCl275P5WiacxsssA7JFSfR2SzTBY9ijfAjKI/icOx7xZDtQLVFM6VaQA7+XPqz3R0ymT9HWCSaPCU1VN9kufLRPDdAzrg+5x3Ja/InXHt9xctd25Tn2bpErgJRFIdeNFbJLrvHWMSnbNZ7EcuUl/LBBXyJdh7ddW7hqfxx76/xZKLPzwY7ObkfTfE1N669cUY6AzudVj1ahgrbjGRju0zOrv/J2TlXjUfTqws9JGpD7bLjDuFDycD7lw/9HLrIO54gFQYauKwdJwgxRz+pmW6togA/18UcmYU1dFmHWk7T8vyXaS7DXE34lMqlPR8c+UWHZVCjXKVFqzCeGXHNtwF8IWQr7t0+0PlRAbM/nixFrgNvACvFnG5GNZoRJPeB5bgkwXxQgUn9OhwOUQBU/iSlH5l2GsTDb5hl8f9HxV/lnYNLLXcOQEf+kiNTY6SqYmJ5f X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(426003)(8676002)(26005)(54906003)(4326008)(5660300002)(8936002)(7696005)(2616005)(110136005)(6666004)(82310400003)(70206006)(508600001)(83380400001)(70586007)(336012)(47076005)(1076003)(36860700001)(316002)(36756003)(81166007)(2906002)(86362001)(186003)(356005)(7406005)(16526019)(7416002)(44832011)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:05:59.4578 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8f04729c-f7ab-46f4-383f-08d98a86487e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5503 X-Rspamd-Server: rspam01 X-Rspamd-Queue-Id: 7BB83B000E18 X-Stat-Signature: 8e36ys43xmzxj9mn1h1za83iufjau16b Authentication-Results: imf25.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=sdEvoq7n; dmarc=pass (policy=quarantine) header.from=amd.com; spf=pass (imf25.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.223.81 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com X-HE-Tag: 1633716363-980535 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Michael Roth Determining which CPUID leafs have significant ECX/index values is also needed by guest kernel code when doing SEV-SNP-validated CPUID lookups. Move this to common code to keep future updates in sync. Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- arch/x86/include/asm/cpuid.h | 26 ++++++++++++++++++++++++++ arch/x86/kvm/cpuid.c | 17 ++--------------- 2 files changed, 28 insertions(+), 15 deletions(-) create mode 100644 arch/x86/include/asm/cpuid.h diff --git a/arch/x86/include/asm/cpuid.h b/arch/x86/include/asm/cpuid.h new file mode 100644 index 000000000000..61426eb1f665 --- /dev/null +++ b/arch/x86/include/asm/cpuid.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_CPUID_H +#define _ASM_X86_CPUID_H + +static __always_inline bool cpuid_function_is_indexed(u32 function) +{ + switch (function) { + case 4: + case 7: + case 0xb: + case 0xd: + case 0xf: + case 0x10: + case 0x12: + case 0x14: + case 0x17: + case 0x18: + case 0x1f: + case 0x8000001d: + return true; + } + + return false; +} + +#endif /* _ASM_X86_CPUID_H */ diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 751aa85a3001..312b0382e541 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "cpuid.h" #include "lapic.h" #include "mmu.h" @@ -582,22 +583,8 @@ static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, cpuid_count(entry->function, entry->index, &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); - switch (function) { - case 4: - case 7: - case 0xb: - case 0xd: - case 0xf: - case 0x10: - case 0x12: - case 0x14: - case 0x17: - case 0x18: - case 0x1f: - case 0x8000001d: + if (cpuid_function_is_indexed(function)) entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; - break; - } return entry; } From patchwork Fri Oct 8 18:04:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545941 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26570C43217 for ; Fri, 8 Oct 2021 18:06:27 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id C833C6138B for ; Fri, 8 Oct 2021 18:06:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C833C6138B Authentication-Results: mail.kernel.org; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 28/42] x86/compressed/acpi: move EFI system table lookup to helper Date: Fri, 8 Oct 2021 13:04:39 -0500 Message-ID: <20211008180453.462291-29-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a3cfeeb2-7062-40de-3338-08d98a864903 X-MS-TrafficTypeDiagnostic: CH2PR12MB3656: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4125; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4eylEkm0Sm1yOWm7Iu3haZjwclq95UGdaMvu3AVqkipaBcLJxK3pc50KjoPOIFBWXMthiOYBPHRct6FXSDK8v51gGmbNL/B3OKAOy6sJVbSB5nzGyYuhBLObHNJAFLvb4uGRC0m5RhZqn2Xo7U8VJkRZYIxE0vkYYO4bt3/16aIbKjhbfZIyXge3oEjDKHCn8pnpsbxeldtXIfISvNg8kwfH0vpwbuSsoFU/4aw/Ta33wcttHQey9Bw7EngVxRcb4hmxugr6fniSIOBRsRBPCqiOmF9LN3J0RkU2rzkeYAxflnkXacUQyaLusMG75jb+XxQHoaYCtM/k4jXrbUh4uSyXbkRKJWcqKiovAV5FPE2K4ty7o4DDggLQufRlEO1a6mQpbmPFwVKR5zjFSsS6XYHUAVpCWbG33/4S12TLupOeGCV5u0dPY8cSv+yxi3fnxq3Ati6012aL9L4y3YF/Pd5wCnPOhYJSfmVm+Gv+wvS7WEbL9fqGrH7yFEpIp7XS2jF0HxWbGiNw1pn21D8XdDVEBrvBZjXFRjfhbY47GUEMXhrJj3zTik7jChzMzVbcFG4jDYlU4YlP1BpZgO0NaVBWW6sFTXJ3H+u/EMGBkPugU2l8VMahlZudhgpJztQ7/IgVGqKhyXgj4BmnJ10Q7cSA5gTqy+H/gvqhxJNKa79/AQu6r3M4nCUldfpJ+NpYv2khWyICSlJYjySFnXkhDEKbOs5ROX8HCQtf9l+wW0kZtCwMCwoazK3AvJyHtYj0 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(2906002)(81166007)(36860700001)(110136005)(70206006)(26005)(508600001)(16526019)(7406005)(316002)(47076005)(356005)(1076003)(86362001)(7416002)(426003)(44832011)(336012)(5660300002)(36756003)(83380400001)(8676002)(186003)(8936002)(54906003)(4326008)(2616005)(82310400003)(70586007)(6666004)(7696005)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:06:00.3303 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a3cfeeb2-7062-40de-3338-08d98a864903 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB3656 X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: 555F16004408 X-Stat-Signature: 6ej7dioyhnyda3bs9hedyr9u3usfcfq4 Authentication-Results: imf14.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b="ZVa96w6/"; dmarc=pass (policy=quarantine) header.from=amd.com; spf=pass (imf14.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.237.86 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com X-HE-Tag: 1633716365-356537 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Michael Roth Future patches for SEV-SNP-validated CPUID will also require early parsing of the EFI configuration. Incrementally move the related code into a set of helpers that can be re-used for that purpose. Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- arch/x86/boot/compressed/Makefile | 1 + arch/x86/boot/compressed/acpi.c | 18 ++++----- arch/x86/boot/compressed/efi.c | 64 +++++++++++++++++++++++++++++++ arch/x86/boot/compressed/misc.h | 14 +++++++ 4 files changed, 87 insertions(+), 10 deletions(-) create mode 100644 arch/x86/boot/compressed/efi.c diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile index 431bf7f846c3..d364192c2367 100644 --- a/arch/x86/boot/compressed/Makefile +++ b/arch/x86/boot/compressed/Makefile @@ -100,6 +100,7 @@ endif vmlinux-objs-$(CONFIG_ACPI) += $(obj)/acpi.o vmlinux-objs-$(CONFIG_EFI_MIXED) += $(obj)/efi_thunk_$(BITS).o +vmlinux-objs-$(CONFIG_EFI) += $(obj)/efi.o efi-obj-$(CONFIG_EFI_STUB) = $(objtree)/drivers/firmware/efi/libstub/lib.a $(obj)/vmlinux: $(vmlinux-objs-y) $(efi-obj-y) FORCE diff --git a/arch/x86/boot/compressed/acpi.c b/arch/x86/boot/compressed/acpi.c index 8bcbcee54aa1..255f6959c090 100644 --- a/arch/x86/boot/compressed/acpi.c +++ b/arch/x86/boot/compressed/acpi.c @@ -86,8 +86,8 @@ static acpi_physical_address kexec_get_rsdp_addr(void) { efi_system_table_64_t *systab; struct efi_setup_data *esd; - struct efi_info *ei; - char *sig; + bool efi_64; + int ret; esd = (struct efi_setup_data *)get_kexec_setup_data_addr(); if (!esd) @@ -98,18 +98,16 @@ static acpi_physical_address kexec_get_rsdp_addr(void) return 0; } - ei = &boot_params->efi_info; - sig = (char *)&ei->efi_loader_signature; - if (strncmp(sig, EFI64_LOADER_SIGNATURE, 4)) { + /* Get systab from boot params. */ + ret = efi_get_system_table(boot_params, (unsigned long *)&systab, &efi_64); + if (ret) + error("EFI system table not found in kexec boot_params."); + + if (!efi_64) { debug_putstr("Wrong kexec EFI loader signature.\n"); return 0; } - /* Get systab from boot params. */ - systab = (efi_system_table_64_t *) (ei->efi_systab | ((__u64)ei->efi_systab_hi << 32)); - if (!systab) - error("EFI system table not found in kexec boot_params."); - return __efi_get_rsdp_addr((unsigned long)esd->tables, systab->nr_tables, true); } #else diff --git a/arch/x86/boot/compressed/efi.c b/arch/x86/boot/compressed/efi.c new file mode 100644 index 000000000000..306b287b7368 --- /dev/null +++ b/arch/x86/boot/compressed/efi.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Helpers for early access to EFI configuration table + * + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Author: Michael Roth + */ + +#include "misc.h" +#include +#include + +/** + * Given boot_params, retrieve the physical address of EFI system table. + * + * @boot_params: pointer to boot_params + * @sys_tbl_pa: location to store physical address of system table + * @is_efi_64: location to store whether using 64-bit EFI or not + * + * Returns 0 on success. On error, return params are left unchanged. + */ +int efi_get_system_table(struct boot_params *boot_params, unsigned long *sys_tbl_pa, + bool *is_efi_64) +{ + unsigned long sys_tbl; + struct efi_info *ei; + bool efi_64; + char *sig; + + if (!sys_tbl_pa || !is_efi_64) + return -EINVAL; + + ei = &boot_params->efi_info; + sig = (char *)&ei->efi_loader_signature; + + if (!strncmp(sig, EFI64_LOADER_SIGNATURE, 4)) { + efi_64 = true; + } else if (!strncmp(sig, EFI32_LOADER_SIGNATURE, 4)) { + efi_64 = false; + } else { + debug_putstr("Wrong EFI loader signature.\n"); + return -ENOENT; + } + + /* Get systab from boot params. */ +#ifdef CONFIG_X86_64 + sys_tbl = ei->efi_systab | ((__u64)ei->efi_systab_hi << 32); +#else + if (ei->efi_systab_hi || ei->efi_memmap_hi) { + debug_putstr("Error: EFI system table located above 4GB.\n"); + return -EINVAL; + } + sys_tbl = ei->efi_systab; +#endif + if (!sys_tbl) { + debug_putstr("EFI system table not found."); + return -ENOENT; + } + + *sys_tbl_pa = sys_tbl; + *is_efi_64 = efi_64; + return 0; +} diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/misc.h index 822e0c254b9a..f86ff866fd7a 100644 --- a/arch/x86/boot/compressed/misc.h +++ b/arch/x86/boot/compressed/misc.h @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -174,4 +175,17 @@ void boot_stage2_vc(void); unsigned long sev_verify_cbit(unsigned long cr3); +#ifdef CONFIG_EFI +/* helpers for early EFI config table access */ +int efi_get_system_table(struct boot_params *boot_params, + unsigned long *sys_tbl_pa, bool *is_efi_64); +#else +static inline int +efi_get_system_table(struct boot_params *boot_params, + unsigned long *sys_tbl_pa, bool *is_efi_64) +{ + return -ENOENT; +} +#endif /* CONFIG_EFI */ + #endif /* BOOT_COMPRESSED_MISC_H */ From patchwork Fri Oct 8 18:04:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A623C433FE for ; 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Fri, 8 Oct 2021 13:05:59 -0500 From: Brijesh Singh To: , , , , , , CC: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , "Vitaly Kuznetsov" , Jim Mattson , "Andy Lutomirski" , Dave Hansen , Sergio Lopez , Peter Gonda , "Peter Zijlstra" , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , "Dr . David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 29/42] x86/compressed/acpi: move EFI config table lookup to helper Date: Fri, 8 Oct 2021 13:04:40 -0500 Message-ID: <20211008180453.462291-30-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 359fab6d-ea3a-4be5-a5ea-08d98a864d3d X-MS-TrafficTypeDiagnostic: BYAPR12MB2680: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3513; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ToWo+smgHThN0SqqsGJ3yU9nQdYGZr4tGgIxUI8DbCQBTywOzofV3toWxY8OEIIqh6/dsNy5VLn0SDaZiMSXHDxHdJSiWIbbH8tqfBtiZCRCfsvMIKOUzwt63uP7qiVpzSau89CSrs/9BkLzskrsSCtjgVuLjxuKxPJblqoEmBJIBdEIlpocojE+zablvTr99YqL2rtSkNuAlWjDbd6eUwd5HmtMWzRg/9dghRf5Z1aWmlXMQS/Ms6+hRXpcLLxCdRhZ5Yjxu9GkJqLP838PDlosUcGxECzB1ou1MdRuNCiIc93hKEHXCoH2Gk/u2fiRPnRoLBQihq+3OlVAtL/2w73TUQgc7SfsQlUR9naBR7X3eCMWDioJKAFeXYma0yyjFwrokMaOtePe45K1dLCO/KqPXZdNQz1XOeK2t6eXx3abIPCnMxrhkud1QbMpapxvDCOsRIGEePpWhRTbpqWl2eGS8b6nr9lxSHMyqGp3HuLnhLf2BxPqAlt6F59Yq1kVMgvODUg3wqXTyoLa4M2dKAY39NEYiLoA71Adg9m3t5yCUEyQRcQcSS8ASc27GvzjUT8s+3HfE5je1ht51P2YwwjzdPFKcuiv1/dGM/y3e2LLbhkoygPMYraxxUOajFjQrx2CBd+UQ+UuA4N8nXjfMWZY91GGhJmNGX98ZnR/JDQfZtqbOM4zSSJONdGa44ImicQdaUR7aE4YIb/1CH5ww0y1GqNmqThU5uVU6jZ6DKr17RjeiUIAofCQR+vGWS5p X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(54906003)(8676002)(110136005)(44832011)(82310400003)(83380400001)(336012)(7696005)(86362001)(8936002)(186003)(16526019)(1076003)(47076005)(426003)(5660300002)(36756003)(70586007)(2616005)(26005)(36860700001)(508600001)(7416002)(7406005)(356005)(70206006)(81166007)(6666004)(4326008)(2906002)(316002)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:06:07.4223 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 359fab6d-ea3a-4be5-a5ea-08d98a864d3d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2680 X-Rspamd-Server: rspam01 X-Rspamd-Queue-Id: 75E35D03E843 X-Stat-Signature: fs9po7de4jeiy7kiaisewd9re8qfeq8z Authentication-Results: imf21.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=1YkXkYdx; dmarc=pass (policy=quarantine) header.from=amd.com; spf=pass (imf21.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.92.60 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com X-HE-Tag: 1633716372-188876 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Michael Roth Future patches for SEV-SNP-validated CPUID will also require early parsing of the EFI configuration. Incrementally move the related code into a set of helpers that can be re-used for that purpose. Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- arch/x86/boot/compressed/acpi.c | 52 +++++---------------------------- arch/x86/boot/compressed/efi.c | 42 ++++++++++++++++++++++++++ arch/x86/boot/compressed/misc.h | 9 ++++++ 3 files changed, 58 insertions(+), 45 deletions(-) diff --git a/arch/x86/boot/compressed/acpi.c b/arch/x86/boot/compressed/acpi.c index 255f6959c090..d43ff3ff573b 100644 --- a/arch/x86/boot/compressed/acpi.c +++ b/arch/x86/boot/compressed/acpi.c @@ -117,54 +117,16 @@ static acpi_physical_address kexec_get_rsdp_addr(void) { return 0; } static acpi_physical_address efi_get_rsdp_addr(void) { #ifdef CONFIG_EFI - unsigned long systab, config_tables; - unsigned int nr_tables; - struct efi_info *ei; + unsigned long cfg_tbl_pa = 0; + unsigned int cfg_tbl_len; bool efi_64; - char *sig; - - ei = &boot_params->efi_info; - sig = (char *)&ei->efi_loader_signature; - - if (!strncmp(sig, EFI64_LOADER_SIGNATURE, 4)) { - efi_64 = true; - } else if (!strncmp(sig, EFI32_LOADER_SIGNATURE, 4)) { - efi_64 = false; - } else { - debug_putstr("Wrong EFI loader signature.\n"); - return 0; - } - - /* Get systab from boot params. */ -#ifdef CONFIG_X86_64 - systab = ei->efi_systab | ((__u64)ei->efi_systab_hi << 32); -#else - if (ei->efi_systab_hi || ei->efi_memmap_hi) { - debug_putstr("Error getting RSDP address: EFI system table located above 4GB.\n"); - return 0; - } - systab = ei->efi_systab; -#endif - if (!systab) - error("EFI system table not found."); - - /* Handle EFI bitness properly */ - if (efi_64) { - efi_system_table_64_t *stbl = (efi_system_table_64_t *)systab; - - config_tables = stbl->tables; - nr_tables = stbl->nr_tables; - } else { - efi_system_table_32_t *stbl = (efi_system_table_32_t *)systab; - - config_tables = stbl->tables; - nr_tables = stbl->nr_tables; - } + int ret; - if (!config_tables) - error("EFI config tables not found."); + ret = efi_get_conf_table(boot_params, &cfg_tbl_pa, &cfg_tbl_len, &efi_64); + if (ret || !cfg_tbl_pa) + error("EFI config table not found."); - return __efi_get_rsdp_addr(config_tables, nr_tables, efi_64); + return __efi_get_rsdp_addr(cfg_tbl_pa, cfg_tbl_len, efi_64); #else return 0; #endif diff --git a/arch/x86/boot/compressed/efi.c b/arch/x86/boot/compressed/efi.c index 306b287b7368..e5f39b3f5665 100644 --- a/arch/x86/boot/compressed/efi.c +++ b/arch/x86/boot/compressed/efi.c @@ -62,3 +62,45 @@ int efi_get_system_table(struct boot_params *boot_params, unsigned long *sys_tbl *is_efi_64 = efi_64; return 0; } + +/** + * Given boot_params, locate EFI system table from it and return the physical + * address EFI configuration table. + * + * @boot_params: pointer to boot_params + * @cfg_tbl_pa: location to store physical address of config table + * @cfg_tbl_len: location to store number of config table entries + * @is_efi_64: location to store whether using 64-bit EFI or not + * + * Returns 0 on success. On error, return params are left unchanged. + */ +int efi_get_conf_table(struct boot_params *boot_params, unsigned long *cfg_tbl_pa, + unsigned int *cfg_tbl_len, bool *is_efi_64) +{ + unsigned long sys_tbl_pa = 0; + int ret; + + if (!cfg_tbl_pa || !cfg_tbl_len || !is_efi_64) + return -EINVAL; + + ret = efi_get_system_table(boot_params, &sys_tbl_pa, is_efi_64); + if (ret) + return ret; + + /* Handle EFI bitness properly */ + if (*is_efi_64) { + efi_system_table_64_t *stbl = + (efi_system_table_64_t *)sys_tbl_pa; + + *cfg_tbl_pa = stbl->tables; + *cfg_tbl_len = stbl->nr_tables; + } else { + efi_system_table_32_t *stbl = + (efi_system_table_32_t *)sys_tbl_pa; + + *cfg_tbl_pa = stbl->tables; + *cfg_tbl_len = stbl->nr_tables; + } + + return 0; +} diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/misc.h index f86ff866fd7a..b72fd860362a 100644 --- a/arch/x86/boot/compressed/misc.h +++ b/arch/x86/boot/compressed/misc.h @@ -179,6 +179,8 @@ unsigned long sev_verify_cbit(unsigned long cr3); /* helpers for early EFI config table access */ int efi_get_system_table(struct boot_params *boot_params, unsigned long *sys_tbl_pa, bool *is_efi_64); +int efi_get_conf_table(struct boot_params *boot_params, unsigned long *cfg_tbl_pa, + unsigned int *cfg_tbl_len, bool *is_efi_64); #else static inline int efi_get_system_table(struct boot_params *boot_params, @@ -186,6 +188,13 @@ efi_get_system_table(struct boot_params *boot_params, { return -ENOENT; } + +static inline int +efi_get_conf_table(struct boot_params *boot_params, unsigned long *cfg_tbl_pa, + unsigned int *cfg_tbl_len, bool *is_efi_64) +{ + return -ENOENT; +} #endif /* CONFIG_EFI */ #endif /* BOOT_COMPRESSED_MISC_H */ From patchwork Fri Oct 8 18:04:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C9AEC433EF for ; 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Fri, 8 Oct 2021 13:06:01 -0500 From: Brijesh Singh To: , , , , , , CC: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , "Vitaly Kuznetsov" , Jim Mattson , "Andy Lutomirski" , Dave Hansen , Sergio Lopez , Peter Gonda , "Peter Zijlstra" , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , "Dr . David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 30/42] x86/compressed/acpi: move EFI vendor table lookup to helper Date: Fri, 8 Oct 2021 13:04:41 -0500 Message-ID: <20211008180453.462291-31-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5dd9cd5e-9af6-4bf7-07f2-08d98a864dd2 X-MS-TrafficTypeDiagnostic: SN1PR12MB2589: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1417; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AFtEfoa8m9q8xCzkqAhmGQ0RGG2KEjTV+iRuZZRd1wfdNYXUH+GLOu2HvyzuNPiTQOmmleyIwUbu2M2FQvVrcgCY01SgTJINzHHbpVuFhXTzcUS/OnwIExGDfB+QeUuG/0c2YVbYFBEQ5yFDkt0JPKFWXp5IVoj1yIpSVuX49CIfZtjrqjpC0SPpTQWbMalEN77RS9bJw23qLwl/PZX6rkI9A+1ZpbscjbASD54abjZZHJ8I2bUMxfzUjwvuyWnDu7Dwp0vd+iuOIpLd/mnhPQ59SOj4BjjV9BjORl5AfPuzR2hWaL/c58/cA8gchd7Cf0fNUAOIFMKeYncLLbCUGTMRDwpufLpvuE1PLUIGq+D+SriyaxL8ABnuAcPGvRGl1WnK7iozTsski6io7QQVDw6o+OTixfEmc1JASUZBzc8nqM3pdflUSZOyhbtlrFkLon5PRObRjefXJA1N4pfw4V04qJU8MM1om2Px4PcbvCAbghPsMduT6D9FFeHqXJlqUxwS63V7gHYe+V/1NKMNK14+jXfBa1GfdVD8MCKTbz9Kk+gEMEY5Hw0rB6fbNXjLTAhDUvNy0JG+IJB8MH9UqZ+mEIrf2EwJ+4eCKeQnMWZNJF865sP+jCcjhwR4M8setBXkuUJ/EftBigYjIq/WJ5zwxKoVjRQwQe60Xx0aVRpBlUtKVi9ZkXjQRSrBhxOr//+7FJtt57fxniW3aSiB1MONhVFWD88lF+lDdhmbvgS/C5jEIdcSeJX+IiPOZOnr X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(81166007)(82310400003)(426003)(2616005)(36860700001)(336012)(16526019)(186003)(6666004)(26005)(70586007)(4326008)(44832011)(508600001)(1076003)(36756003)(8676002)(83380400001)(356005)(7696005)(7406005)(316002)(2906002)(86362001)(70206006)(8936002)(47076005)(5660300002)(7416002)(110136005)(54906003)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:06:08.3947 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5dd9cd5e-9af6-4bf7-07f2-08d98a864dd2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR12MB2589 Authentication-Results: imf10.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=PdwgybrL; spf=pass (imf10.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.101.67 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 146D560037EF X-Stat-Signature: qjr1j1dxje6rrm6n89ga7amznny4tatb X-HE-Tag: 1633716373-739335 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Michael Roth Future patches for SEV-SNP-validated CPUID will also require early parsing of the EFI configuration. Incrementally move the related code into a set of helpers that can be re-used for that purpose. Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- arch/x86/boot/compressed/acpi.c | 50 ++++++++----------------- arch/x86/boot/compressed/efi.c | 65 +++++++++++++++++++++++++++++++++ arch/x86/boot/compressed/misc.h | 9 +++++ 3 files changed, 90 insertions(+), 34 deletions(-) diff --git a/arch/x86/boot/compressed/acpi.c b/arch/x86/boot/compressed/acpi.c index d43ff3ff573b..f2a6092738cd 100644 --- a/arch/x86/boot/compressed/acpi.c +++ b/arch/x86/boot/compressed/acpi.c @@ -20,46 +20,28 @@ */ struct mem_vector immovable_mem[MAX_NUMNODES*2]; -/* - * Search EFI system tables for RSDP. If both ACPI_20_TABLE_GUID and - * ACPI_TABLE_GUID are found, take the former, which has more features. - */ static acpi_physical_address -__efi_get_rsdp_addr(unsigned long config_tables, unsigned int nr_tables, - bool efi_64) +__efi_get_rsdp_addr(unsigned long cfg_tbl_pa, unsigned int cfg_tbl_len, bool efi_64) { acpi_physical_address rsdp_addr = 0; #ifdef CONFIG_EFI - int i; - - /* Get EFI tables from systab. */ - for (i = 0; i < nr_tables; i++) { - acpi_physical_address table; - efi_guid_t guid; - - if (efi_64) { - efi_config_table_64_t *tbl = (efi_config_table_64_t *)config_tables + i; - - guid = tbl->guid; - table = tbl->table; - - if (!IS_ENABLED(CONFIG_X86_64) && table >> 32) { - debug_putstr("Error getting RSDP address: EFI config table located above 4GB.\n"); - return 0; - } - } else { - efi_config_table_32_t *tbl = (efi_config_table_32_t *)config_tables + i; - - guid = tbl->guid; - table = tbl->table; - } + int ret; - if (!(efi_guidcmp(guid, ACPI_TABLE_GUID))) - rsdp_addr = table; - else if (!(efi_guidcmp(guid, ACPI_20_TABLE_GUID))) - return table; - } + /* + * Search EFI system tables for RSDP. Preferred is ACPI_20_TABLE_GUID to + * ACPI_TABLE_GUID because it has more features. + */ + ret = efi_find_vendor_table(cfg_tbl_pa, cfg_tbl_len, ACPI_20_TABLE_GUID, + efi_64, (unsigned long *)&rsdp_addr); + if (!ret) + return rsdp_addr; + + /* No ACPI_20_TABLE_GUID found, fallback to ACPI_TABLE_GUID. */ + ret = efi_find_vendor_table(cfg_tbl_pa, cfg_tbl_len, ACPI_TABLE_GUID, + efi_64, (unsigned long *)&rsdp_addr); + if (ret) + debug_putstr("Error getting RSDP address.\n"); #endif return rsdp_addr; } diff --git a/arch/x86/boot/compressed/efi.c b/arch/x86/boot/compressed/efi.c index e5f39b3f5665..9817e3020207 100644 --- a/arch/x86/boot/compressed/efi.c +++ b/arch/x86/boot/compressed/efi.c @@ -104,3 +104,68 @@ int efi_get_conf_table(struct boot_params *boot_params, unsigned long *cfg_tbl_p return 0; } + +/* Get vendor table address/guid from EFI config table at the given index */ +static int get_vendor_table(void *cfg_tbl, unsigned int idx, + unsigned long *vendor_tbl_pa, + efi_guid_t *vendor_tbl_guid, + bool efi_64) +{ + if (efi_64) { + efi_config_table_64_t *tbl_entry = + (efi_config_table_64_t *)cfg_tbl + idx; + + if (!IS_ENABLED(CONFIG_X86_64) && tbl_entry->table >> 32) { + debug_putstr("Error: EFI config table entry located above 4GB.\n"); + return -EINVAL; + } + + *vendor_tbl_pa = tbl_entry->table; + *vendor_tbl_guid = tbl_entry->guid; + + } else { + efi_config_table_32_t *tbl_entry = + (efi_config_table_32_t *)cfg_tbl + idx; + + *vendor_tbl_pa = tbl_entry->table; + *vendor_tbl_guid = tbl_entry->guid; + } + + return 0; +} + +/** + * Given EFI config table, search it for the physical address of the vendor + * table associated with GUID. + * + * @cfg_tbl_pa: pointer to EFI configuration table + * @cfg_tbl_len: number of entries in EFI configuration table + * @guid: GUID of vendor table + * @efi_64: true if using 64-bit EFI + * @vendor_tbl_pa: location to store physical address of vendor table + * + * Returns 0 on success. On error, return params are left unchanged. + */ +int efi_find_vendor_table(unsigned long cfg_tbl_pa, unsigned int cfg_tbl_len, + efi_guid_t guid, bool efi_64, unsigned long *vendor_tbl_pa) +{ + unsigned int i; + + for (i = 0; i < cfg_tbl_len; i++) { + unsigned long vendor_tbl_pa_tmp; + efi_guid_t vendor_tbl_guid; + int ret; + + if (get_vendor_table((void *)cfg_tbl_pa, i, + &vendor_tbl_pa_tmp, + &vendor_tbl_guid, efi_64)) + return -EINVAL; + + if (!efi_guidcmp(guid, vendor_tbl_guid)) { + *vendor_tbl_pa = vendor_tbl_pa_tmp; + return 0; + } + } + + return -ENOENT; +} diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/misc.h index b72fd860362a..d4a26f3d3580 100644 --- a/arch/x86/boot/compressed/misc.h +++ b/arch/x86/boot/compressed/misc.h @@ -181,6 +181,8 @@ int efi_get_system_table(struct boot_params *boot_params, unsigned long *sys_tbl_pa, bool *is_efi_64); int efi_get_conf_table(struct boot_params *boot_params, unsigned long *cfg_tbl_pa, unsigned int *cfg_tbl_len, bool *is_efi_64); +int efi_find_vendor_table(unsigned long cfg_tbl_pa, unsigned int cfg_tbl_len, + efi_guid_t guid, bool efi_64, unsigned long *vendor_tbl_pa); #else static inline int efi_get_system_table(struct boot_params *boot_params, @@ -195,6 +197,13 @@ efi_get_conf_table(struct boot_params *boot_params, unsigned long *cfg_tbl_pa, { return -ENOENT; } + +static inline int +efi_find_vendor_table(unsigned long cfg_tbl_pa, unsigned int cfg_tbl_len, + efi_guid_t guid, bool efi_64, unsigned long *vendor_tbl_pa) +{ + return -ENOENT; +} #endif /* CONFIG_EFI */ #endif /* BOOT_COMPRESSED_MISC_H */ From patchwork Fri Oct 8 18:04:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6BE9C433EF for ; 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Fri, 8 Oct 2021 13:06:03 -0500 From: Brijesh Singh To: , , , , , , CC: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , "Vitaly Kuznetsov" , Jim Mattson , "Andy Lutomirski" , Dave Hansen , Sergio Lopez , Peter Gonda , "Peter Zijlstra" , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , "Dr . David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 31/42] x86/boot: Add Confidential Computing type to setup_data Date: Fri, 8 Oct 2021 13:04:42 -0500 Message-ID: <20211008180453.462291-32-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ee19d9e3-5332-487d-1547-08d98a865079 X-MS-TrafficTypeDiagnostic: MN2PR12MB4437: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zSEhMNQdc4pmoE9yprLbyJhdczDZwhH8Wa4jCpsV9BK3zV6e9qG6WVKesfgK3GqBNiON940p1Fg3pD52hXG/S3TkOHDbSk8hjkxFD7oJlaIlZR9w2Ym9apnDPP4Rs0yitWmTEm/s3Kn8CgSMF2Mcz4JfrpYILsN+aTUVZJta2R1eorIpGb4m6S5Yb74ZxXmkxSoqo/UvHaSz9kEsp5U+bjRNWXgOQrppQ0r4TUDEff+E2fOQJ6Yg5aeiP49piSYSOSACy95vfkFCfhL5YNhe9QFg80PrcBbrzgNVfpJ+thxKACvco8OjKnJnDMZx6GGhDlFoQgRk6XGD7c4jWGtps2J70l/FtTY3aIjkVHDa7/vFxaRuZ1siAn8tcgKX5IAYDRm+deO5xDD/bd8Crb6WHcVCK3DKGDIkL3hTRNSFEWavK1O1Xew+Q/OBuHCJsHScSl9x6BqhOREpS5daBW9nvaLpbuAhiGBp2IOEm2RRY5UipaJ/FhYQptWx/FOhrbr7BtDhIfCOK7a0KztiaX276piKZtGPDuvDsSYCVgoZ8KHRsd8vq4yyyGtBK3bw3qnB501ZTUDMjAkvv9zRsVh7wyzsNAqqVkya/cjAyzTzBRAqlggjrhHEUFSPZB5hSSFlrmEx7Liq8gIEY4N/sXrKjDfdxWzysvEZ7uhEUubZ0dSDgi0Vfj6D8oJYIcOuDNLFGBsmc7VpDxpikNQQdkaRjvN/tGYXCO3D/Cq7Z7EwVeqXUPzaQ1lBLLQAksAYsJhA X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(336012)(110136005)(426003)(316002)(2906002)(7406005)(54906003)(4326008)(8676002)(7416002)(356005)(8936002)(26005)(16526019)(508600001)(1076003)(5660300002)(6666004)(70206006)(70586007)(44832011)(81166007)(7696005)(186003)(86362001)(82310400003)(36860700001)(36756003)(2616005)(47076005)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:06:12.8350 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ee19d9e3-5332-487d-1547-08d98a865079 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4437 X-Rspamd-Server: rspam03 X-Rspamd-Queue-Id: C846D5078477 X-Stat-Signature: igabxj8dk9soepkxsckruthxjekmdyr6 Authentication-Results: imf01.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=iHOQ9qIp; dmarc=pass (policy=quarantine) header.from=amd.com; spf=pass (imf01.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.212.53 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com X-HE-Tag: 1633716376-693949 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: While launching the encrypted guests, the hypervisor may need to provide some additional information during the guest boot. When booting under the EFI based BIOS, the EFI configuration table contains an entry for the confidential computing blob that contains the required information. To support booting encrypted guests on non-EFI VM, the hypervisor needs to pass this additional information to the kernel with a different method. For this purpose, introduce SETUP_CC_BLOB type in setup_data to hold the physical address of the confidential computing blob location. The boot loader or hypervisor may choose to use this method instead of EFI configuration table. The CC blob location scanning should give preference to setup_data data over the EFI configuration table. In AMD SEV-SNP, the CC blob contains the address of the secrets and CPUID pages. The secrets page includes information such as a VM to PSP communication key and CPUID page contains PSP filtered CPUID values. Define the AMD SEV confidential computing blob structure. While at it, define the EFI GUID for the confidential computing blob. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/sev.h | 12 ++++++++++++ arch/x86/include/uapi/asm/bootparam.h | 1 + include/linux/efi.h | 1 + 3 files changed, 14 insertions(+) diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 7f063127aa66..534fa1c4c881 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -44,6 +44,18 @@ struct es_em_ctxt { void do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code); +/* AMD SEV Confidential computing blob structure */ +#define CC_BLOB_SEV_HDR_MAGIC 0x45444d41 +struct cc_blob_sev_info { + u32 magic; + u16 version; + u16 reserved; + u64 secrets_phys; + u32 secrets_len; + u64 cpuid_phys; + u32 cpuid_len; +}; + static inline u64 lower_bits(u64 val, unsigned int bits) { u64 mask = (1ULL << bits) - 1; diff --git a/arch/x86/include/uapi/asm/bootparam.h b/arch/x86/include/uapi/asm/bootparam.h index b25d3f82c2f3..1ac5acca72ce 100644 --- a/arch/x86/include/uapi/asm/bootparam.h +++ b/arch/x86/include/uapi/asm/bootparam.h @@ -10,6 +10,7 @@ #define SETUP_EFI 4 #define SETUP_APPLE_PROPERTIES 5 #define SETUP_JAILHOUSE 6 +#define SETUP_CC_BLOB 7 #define SETUP_INDIRECT (1<<31) diff --git a/include/linux/efi.h b/include/linux/efi.h index 6b5d36babfcc..75aeb2a56888 100644 --- a/include/linux/efi.h +++ b/include/linux/efi.h @@ -344,6 +344,7 @@ void efi_native_runtime_setup(void); #define EFI_CERT_SHA256_GUID EFI_GUID(0xc1c41626, 0x504c, 0x4092, 0xac, 0xa9, 0x41, 0xf9, 0x36, 0x93, 0x43, 0x28) #define EFI_CERT_X509_GUID EFI_GUID(0xa5c059a1, 0x94e4, 0x4aa7, 0x87, 0xb5, 0xab, 0x15, 0x5c, 0x2b, 0xf0, 0x72) #define EFI_CERT_X509_SHA256_GUID EFI_GUID(0x3bd2a492, 0x96c0, 0x4079, 0xb4, 0x20, 0xfc, 0xf9, 0x8e, 0xf1, 0x03, 0xed) +#define EFI_CC_BLOB_GUID EFI_GUID(0x067b1f5f, 0xcf26, 0x44c5, 0x85, 0x54, 0x93, 0xd7, 0x77, 0x91, 0x2d, 0x42) /* * This GUID is used to pass to the kernel proper the struct screen_info From patchwork Fri Oct 8 18:04:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BD49C433F5 for ; Fri, 8 Oct 2021 18:06:46 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 0419961039 for ; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 32/42] x86/compressed/64: add support for SEV-SNP CPUID table in #VC handlers Date: Fri, 8 Oct 2021 13:04:43 -0500 Message-ID: <20211008180453.462291-33-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5c3e0f26-2e1d-4330-178e-08d98a865241 X-MS-TrafficTypeDiagnostic: BYAPR12MB2710: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3383; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: P/UencLad3+2XT9+pEq57ZTVwdYbAgAe1uJyL3IemOedUFL5iWbEQX0otOiSVAvMcLW569SlTrAPeQcXOg4aJh0nOxcemYVxP00U88u1W0Z+cukBuVRjE3/3XYoUzFKAwd6A83Glgf7tom8kFAHqcMkjX+jbz/sMFZxmFnVd1vMKOkCyVbrNRelk4+JOBT0ZsmApWQiYp8l/9gnn5tLKhyy7kIGyoTKfutjwCN7y6emcCXY0ZFtHJuW5jm42GFoWC+WjAGH/1mCdXFBb/wFHB+gaUlcPQpH3oRbWcrYSe+aKxXfd92A5m95OZMTOsjsSsW5Z+ouJfzBokWwCiE7Y0Dbx52Bq1x/QQhHs16FvczViPZdt2Uw1LmfrB8ROlF42XiACDkO4pm83+5EQcfZr51j2gqPkSyd12X7oeF+j53ysmUahZWtoTCFllqItGmSC0PvX5zsoKzSOnXsRrBSbQfKbUE2JYR7jE3ljVH0CuMuqJsgxdl7qqEpYC8iJIPLiAL34KJ80YuefBJcbqaMt6YdnR5ptnh/NyBt8zog2b63K4/uBn6k9Kobkwic56cJtQPJcGNQN858i1OCyTGgba7mdebMRn03cJrPSxXjECud7yYGQcRxkLQ1aQTksb7jNbsJQrqAiVLZ5c4XgB3jt40dwqMJLa+c9f92UimZOBIopelVeW7AlLFuxrfBz/wAfSu8bcbCCwdKZKUuVKsb0PTsfSn5F0mpJOKnknK4+bvfr+5qXF+4y5/XF4WMh8aSLeGzkoJWPBMUsqGux/E6rsA1lwIow0WY5oeXgi9lJV60= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(7406005)(7416002)(8936002)(30864003)(4326008)(83380400001)(70586007)(508600001)(70206006)(336012)(81166007)(36860700001)(356005)(2906002)(186003)(16526019)(8676002)(426003)(47076005)(5660300002)(26005)(1076003)(82310400003)(86362001)(7696005)(54906003)(36756003)(110136005)(316002)(6666004)(2616005)(44832011)(36900700001)(2101003)(309714004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:06:15.8355 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c3e0f26-2e1d-4330-178e-08d98a865241 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2710 X-Rspamd-Server: rspam03 X-Rspamd-Queue-Id: 61B15103B54D X-Stat-Signature: he5onupcwgh8g5d9uf34gppnd547bu5a Authentication-Results: imf13.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=zgCnVM0P; dmarc=pass (policy=quarantine) header.from=amd.com; spf=pass (imf13.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.96.47 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com X-HE-Tag: 1633716381-534905 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Michael Roth CPUID instructions generate a #VC exception for SEV-ES/SEV-SNP guests, for which early handlers are currently set up to handle. In the case of SEV-SNP, guests can use a configurable location in guest memory that has been pre-populated with a firmware-validated CPUID table to look up the relevant CPUID values rather than requesting them from hypervisor via a VMGEXIT. Add the various hooks in the #VC handlers to allow CPUID instructions to be handled via the table. The code to actually configure/enable the table will be added in a subsequent commit. Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- arch/x86/boot/compressed/sev.c | 1 + arch/x86/include/asm/sev-common.h | 2 + arch/x86/kernel/sev-shared.c | 308 ++++++++++++++++++++++++++++++ arch/x86/kernel/sev.c | 1 + 4 files changed, 312 insertions(+) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index e8308ada610d..11c459809d4c 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "error.h" diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index c380aba9fc8d..45c535eb75f1 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -152,6 +152,8 @@ struct snp_psc_desc { #define GHCB_TERM_PSC 1 /* Page State Change failure */ #define GHCB_TERM_PVALIDATE 2 /* Pvalidate failure */ #define GHCB_TERM_NOT_VMPL0 3 /* SNP guest is not running at VMPL-0 */ +#define GHCB_TERM_CPUID 4 /* CPUID-validation failure */ +#define GHCB_TERM_CPUID_HV 5 /* CPUID failure during hypervisor fallback */ #define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK) diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index 402b19f1c75d..193ca49a1689 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -14,6 +14,41 @@ #define has_cpuflag(f) boot_cpu_has(f) #endif +/* + * Individual entries of the SEV-SNP CPUID table, as defined by the SEV-SNP + * Firmware ABI, Revision 0.9, Section 7.1, Table 14. Note that the XCR0_IN + * and XSS_IN are denoted here as __unused/__unused2, since they are not + * needed for the current guest implementation, where the size of the buffers + * needed to store enabled XSAVE-saved features are calculated rather than + * encoded in the CPUID table for each possible combination of XCR0_IN/XSS_IN + * to save space. + */ +struct snp_cpuid_fn { + u32 eax_in; + u32 ecx_in; + u64 __unused; + u64 __unused2; + u32 eax; + u32 ebx; + u32 ecx; + u32 edx; + u64 __reserved; +} __packed; + +/* + * SEV-SNP CPUID table header, as defined by the SEV-SNP Firmware ABI, + * Revision 0.9, Section 8.14.2.6. Also noted there is the SEV-SNP + * firmware-enforced limit of 64 entries per CPUID table. + */ +#define SNP_CPUID_COUNT_MAX 64 + +struct snp_cpuid_info { + u32 count; + u32 __reserved1; + u64 __reserved2; + struct snp_cpuid_fn fn[SNP_CPUID_COUNT_MAX]; +} __packed; + /* * Since feature negotiation related variables are set early in the boot * process they must reside in the .data section so as not to be zeroed @@ -26,6 +61,28 @@ static u16 __ro_after_init ghcb_version; /* Bitmap of SEV features supported by the hypervisor */ static u64 __ro_after_init sev_hv_features; +/* + * These are stored in .data section to avoid the need to re-parse boot_params + * and regenerate the CPUID table/pointer when .bss is cleared. + */ + +/* + * The CPUID info can't always be referenced directly due to the need for + * pointer fixups during initial startup phase of kernel proper, so access must + * be done through this pointer, which will be fixed up as-needed during boot. + */ +static const struct snp_cpuid_info *cpuid_info __ro_after_init; + +/* + * These will be initialized based on CPUID table so that non-present + * all-zero leaves (for sparse tables) can be differentiated from + * invalid/out-of-range leaves. This is needed since all-zero leaves + * still need to be post-processed. + */ +u32 cpuid_std_range_max __ro_after_init; +u32 cpuid_hyp_range_max __ro_after_init; +u32 cpuid_ext_range_max __ro_after_init; + static bool __init sev_es_check_cpu_features(void) { if (!has_cpuflag(X86_FEATURE_RDRAND)) { @@ -245,6 +302,224 @@ static int sev_cpuid_hv(u32 func, u32 subfunc, u32 *eax, u32 *ebx, return 0; } +static inline bool snp_cpuid_active(void) +{ + return !!cpuid_info; +} + +static int snp_cpuid_calc_xsave_size(u64 xfeatures_en, u32 base_size, + u32 *xsave_size, bool compacted) +{ + u32 xsave_size_total = base_size; + u64 xfeatures_found = 0; + int i; + + for (i = 0; i < cpuid_info->count; i++) { + const struct snp_cpuid_fn *fn = &cpuid_info->fn[i]; + + if (!(fn->eax_in == 0xD && fn->ecx_in > 1 && fn->ecx_in < 64)) + continue; + if (!(xfeatures_en & (BIT_ULL(fn->ecx_in)))) + continue; + if (xfeatures_found & (BIT_ULL(fn->ecx_in))) + continue; + + xfeatures_found |= (BIT_ULL(fn->ecx_in)); + + if (compacted) + xsave_size_total += fn->eax; + else + xsave_size_total = max(xsave_size_total, + fn->eax + fn->ebx); + } + + /* + * Either the guest set unsupported XCR0/XSS bits, or the corresponding + * entries in the CPUID table were not present. This is not a valid + * state to be in. + */ + if (xfeatures_found != (xfeatures_en & GENMASK_ULL(63, 2))) + return -EINVAL; + + *xsave_size = xsave_size_total; + + return 0; +} + +static void snp_cpuid_hv(u32 func, u32 subfunc, u32 *eax, u32 *ebx, u32 *ecx, + u32 *edx) +{ + /* + * MSR protocol does not support fetching indexed subfunction, but is + * sufficient to handle current fallback cases. Should that change, + * make sure to terminate rather than ignoring the index and grabbing + * random values. If this issue arises in the future, handling can be + * added here to use GHCB-page protocol for cases that occur late + * enough in boot that GHCB page is available. + */ + if (cpuid_function_is_indexed(func) && subfunc) + sev_es_terminate(1, GHCB_TERM_CPUID_HV); + + if (sev_cpuid_hv(func, 0, eax, ebx, ecx, edx)) + sev_es_terminate(1, GHCB_TERM_CPUID_HV); +} + +static bool +snp_cpuid_find_validated_func(u32 func, u32 subfunc, u32 *eax, u32 *ebx, + u32 *ecx, u32 *edx) +{ + int i; + + for (i = 0; i < cpuid_info->count; i++) { + const struct snp_cpuid_fn *fn = &cpuid_info->fn[i]; + + if (fn->eax_in != func) + continue; + + if (cpuid_function_is_indexed(func) && fn->ecx_in != subfunc) + continue; + + *eax = fn->eax; + *ebx = fn->ebx; + *ecx = fn->ecx; + *edx = fn->edx; + + return true; + } + + return false; +} + +static bool snp_cpuid_check_range(u32 func) +{ + if (func <= cpuid_std_range_max || + (func >= 0x40000000 && func <= cpuid_hyp_range_max) || + (func >= 0x80000000 && func <= cpuid_ext_range_max)) + return true; + + return false; +} + +static int snp_cpuid_postprocess(u32 func, u32 subfunc, u32 *eax, u32 *ebx, + u32 *ecx, u32 *edx) +{ + u32 ebx2, ecx2, edx2; + + switch (func) { + case 0x1: + snp_cpuid_hv(func, subfunc, NULL, &ebx2, NULL, &edx2); + + /* initial APIC ID */ + *ebx = (ebx2 & GENMASK(31, 24)) | (*ebx & GENMASK(23, 0)); + /* APIC enabled bit */ + *edx = (edx2 & BIT(9)) | (*edx & ~BIT(9)); + + /* OSXSAVE enabled bit */ + if (native_read_cr4() & X86_CR4_OSXSAVE) + *ecx |= BIT(27); + break; + case 0x7: + /* OSPKE enabled bit */ + *ecx &= ~BIT(4); + if (native_read_cr4() & X86_CR4_PKE) + *ecx |= BIT(4); + break; + case 0xB: + /* extended APIC ID */ + snp_cpuid_hv(func, 0, NULL, NULL, NULL, edx); + break; + case 0xD: { + bool compacted = false; + u64 xcr0 = 1, xss = 0; + u32 xsave_size; + + if (subfunc != 0 && subfunc != 1) + return 0; + + if (native_read_cr4() & X86_CR4_OSXSAVE) + xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); + if (subfunc == 1) { + /* Get XSS value if XSAVES is enabled. */ + if (*eax & BIT(3)) { + unsigned long lo, hi; + + asm volatile("rdmsr" : "=a" (lo), "=d" (hi) + : "c" (MSR_IA32_XSS)); + xss = (hi << 32) | lo; + } + + /* + * The PPR and APM aren't clear on what size should be + * encoded in 0xD:0x1:EBX when compaction is not enabled + * by either XSAVEC (feature bit 1) or XSAVES (feature + * bit 3) since SNP-capable hardware has these feature + * bits fixed as 1. KVM sets it to 0 in this case, but + * to avoid this becoming an issue it's safer to simply + * treat this as unsupported for SEV-SNP guests. + */ + if (!(*eax & (BIT(1) | BIT(3)))) + return -EINVAL; + + compacted = true; + } + + if (snp_cpuid_calc_xsave_size(xcr0 | xss, *ebx, &xsave_size, + compacted)) + return -EINVAL; + + *ebx = xsave_size; + } + break; + case 0x8000001E: + /* extended APIC ID */ + snp_cpuid_hv(func, subfunc, eax, &ebx2, &ecx2, NULL); + /* compute ID */ + *ebx = (*ebx & GENMASK(31, 8)) | (ebx2 & GENMASK(7, 0)); + /* node ID */ + *ecx = (*ecx & GENMASK(31, 8)) | (ecx2 & GENMASK(7, 0)); + break; + default: + /* No fix-ups needed, use values as-is. */ + break; + } + + return 0; +} + +/* + * Returns -EOPNOTSUPP if feature not enabled. Any other return value should be + * treated as fatal by caller. + */ +static int snp_cpuid(u32 func, u32 subfunc, u32 *eax, u32 *ebx, u32 *ecx, + u32 *edx) +{ + if (!snp_cpuid_active()) + return -EOPNOTSUPP; + + if (!snp_cpuid_find_validated_func(func, subfunc, eax, ebx, ecx, edx)) { + /* + * Some hypervisors will avoid keeping track of CPUID entries + * where all values are zero, since they can be handled the + * same as out-of-range values (all-zero). This is useful here + * as well as it allows virtually all guest configurations to + * work using a single SEV-SNP CPUID table. + * + * To allow for this, there is a need to distinguish between + * out-of-range entries and in-range zero entries, since the + * CPUID table entries are only a template that may need to be + * augmented with additional values for things like + * CPU-specific information during post-processing. So if it's + * not in the table, but is still in the valid range, proceed + * with the post-processing. Otherwise, just return zeros. + */ + *eax = *ebx = *ecx = *edx = 0; + if (!snp_cpuid_check_range(func)) + return 0; + } + + return snp_cpuid_postprocess(func, subfunc, eax, ebx, ecx, edx); +} + /* * Boot VC Handler - This is the first VC handler during boot, there is no GHCB * page yet, so it only supports the MSR based communication with the @@ -252,8 +527,10 @@ static int sev_cpuid_hv(u32 func, u32 subfunc, u32 *eax, u32 *ebx, */ void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code) { + unsigned int subfn = lower_bits(regs->cx, 32); unsigned int fn = lower_bits(regs->ax, 32); u32 eax, ebx, ecx, edx; + int ret; /* Only CPUID is supported via MSR protocol */ if (exit_code != SVM_EXIT_CPUID) @@ -273,9 +550,17 @@ void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code) sev_status = (hi << 32) | lo; } + ret = snp_cpuid(fn, subfn, &eax, &ebx, &ecx, &edx); + if (ret == 0) + goto cpuid_done; + + if (ret != -EOPNOTSUPP) + goto fail; + if (sev_cpuid_hv(fn, 0, &eax, &ebx, &ecx, &edx)) goto fail; +cpuid_done: regs->ax = eax; regs->bx = ebx; regs->cx = ecx; @@ -569,12 +854,35 @@ static enum es_result vc_handle_ioio(struct ghcb *ghcb, struct es_em_ctxt *ctxt) return ret; } +static int vc_handle_cpuid_snp(struct pt_regs *regs) +{ + u32 eax, ebx, ecx, edx; + int ret; + + ret = snp_cpuid(regs->ax, regs->cx, &eax, &ebx, &ecx, &edx); + if (ret == 0) { + regs->ax = eax; + regs->bx = ebx; + regs->cx = ecx; + regs->dx = edx; + } + + return ret; +} + static enum es_result vc_handle_cpuid(struct ghcb *ghcb, struct es_em_ctxt *ctxt) { struct pt_regs *regs = ctxt->regs; u32 cr4 = native_read_cr4(); enum es_result ret; + int snp_cpuid_ret; + + snp_cpuid_ret = vc_handle_cpuid_snp(regs); + if (snp_cpuid_ret == 0) + return ES_OK; + if (snp_cpuid_ret != -EOPNOTSUPP) + return ES_VMM_ERROR; ghcb_set_rax(ghcb, regs->ax); ghcb_set_rcx(ghcb, regs->cx); diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index dfb5b2920933..d348ad027df8 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -33,6 +33,7 @@ #include #include #include +#include #define DR7_RESET_VALUE 0x400 From patchwork Fri Oct 8 18:04:44 2021 Content-Type: text/plain; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 33/42] boot/compressed/64: use firmware-validated CPUID for SEV-SNP guests Date: Fri, 8 Oct 2021 13:04:44 -0500 Message-ID: <20211008180453.462291-34-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6e95bd3e-3ef1-498f-a0a2-08d98a8652d5 X-MS-TrafficTypeDiagnostic: DM8PR12MB5447: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: cdAAfaHqKuoLGTdzC+dO8XYhyApSRuP0AA3Nl2Va10WEV9ldlGITTXr3p3IQb00llD8cZgfr7IocOP84bSbdc36MszoVRlRw9bn5pYmH05/cZsV7z+bDjN9Oy4jTn732WWdOzatgvv3K9L/bvu6g4iA8XQOUA2j40SasFLRahkH88rHoTyxh+mcAJDJDLZc9SA3pwpDfp5822b7/jluG7JyFDRvAkigoeXP4TD4Mcj3dXAP8wtDbPk/1lIwC70NysZXf8ajG0rjAdoGIzGQmhnZR9WYSgjntuzzhTAETeIgJ/Z753GcBXYRtoFS16BHWPW8qBeA0EScQuJQ2+sUPWXK7Dy+PvxOcj+AsRvr3bkJKzlWrgEr3IsXSfwkS+4qqirKKHaRXhsn6cgtskFWhDQK6UEHYFgNeBqmIsutleyRemYwM9xlX18VCMt+hRriayX2Y8CmtCLuXEiq8C9SffgMJ8TTXEcxg2miTXqwritMFCLjTsmbfe4YyuoF+1h0ciMGi5lXQAU1PBOy63kJBtla9dTLtoq5KsujOEAHzi3oMVOR4u3idbXV4csBnhl6f7IYVnJGzOcaiQl5TqNVwqy0VzDrYszOglPwaBS5qUEtOwzBFXpCfDZyMAXgNOlL8NPJAVL68/1PGhZtKkh5ToKqKACIb0fx298PNDGY9zrJZ4SdddusZKS8N/cL+T3QQYfoZx2GIDqzDsdIIMowcidy9FQ0FPkJOtBEyeiJBVZ1RwandFR4f8IX4xSDvqA/+ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(8936002)(110136005)(7416002)(30864003)(47076005)(15650500001)(7406005)(2616005)(36860700001)(6666004)(54906003)(5660300002)(26005)(8676002)(508600001)(86362001)(336012)(316002)(16526019)(70586007)(82310400003)(4326008)(70206006)(44832011)(186003)(83380400001)(81166007)(1076003)(7696005)(36756003)(426003)(2906002)(356005)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:06:16.8089 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6e95bd3e-3ef1-498f-a0a2-08d98a8652d5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5447 X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: 7BF37F0013A9 X-Stat-Signature: s38z5k7pj7zudi8he1n1hn3tf8zj7oe4 Authentication-Results: imf16.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=xB5Adnbv; dmarc=pass (policy=quarantine) header.from=amd.com; spf=pass (imf16.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.101.69 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com X-HE-Tag: 1633716380-298090 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Michael Roth SEV-SNP guests will be provided the location of special 'secrets' and 'CPUID' pages via the Confidential Computing blob. This blob is provided to the boot kernel either through an EFI config table entry, or via a setup_data structure as defined by the Linux Boot Protocol. Locate the Confidential Computing from these sources and, if found, use the provided CPUID page/table address to create a copy that the boot kernel will use when servicing cpuid instructions via a #VC handler. Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- arch/x86/boot/compressed/head_64.S | 1 + arch/x86/boot/compressed/idt_64.c | 5 +- arch/x86/boot/compressed/misc.h | 2 + arch/x86/boot/compressed/sev.c | 79 ++++++++++++++++++++++++++++++ arch/x86/include/asm/sev.h | 14 ++++++ arch/x86/kernel/sev-shared.c | 78 +++++++++++++++++++++++++++++ 6 files changed, 178 insertions(+), 1 deletion(-) diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S index 572c535cf45b..c9252f0b0e81 100644 --- a/arch/x86/boot/compressed/head_64.S +++ b/arch/x86/boot/compressed/head_64.S @@ -444,6 +444,7 @@ SYM_CODE_START(startup_64) .Lon_kernel_cs: pushq %rsi + movq %rsi, %rdi /* real mode address */ call load_stage1_idt popq %rsi diff --git a/arch/x86/boot/compressed/idt_64.c b/arch/x86/boot/compressed/idt_64.c index 9b93567d663a..3c0f7c8d9152 100644 --- a/arch/x86/boot/compressed/idt_64.c +++ b/arch/x86/boot/compressed/idt_64.c @@ -28,7 +28,7 @@ static void load_boot_idt(const struct desc_ptr *dtr) } /* Setup IDT before kernel jumping to .Lrelocated */ -void load_stage1_idt(void) +void load_stage1_idt(void *rmode) { boot_idt_desc.address = (unsigned long)boot_idt; @@ -37,6 +37,9 @@ void load_stage1_idt(void) set_idt_entry(X86_TRAP_VC, boot_stage1_vc); load_boot_idt(&boot_idt_desc); + + if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) + snp_cpuid_init_boot(rmode); } /* Setup IDT after kernel jumping to .Lrelocated */ diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/misc.h index d4a26f3d3580..9b66a8bf336e 100644 --- a/arch/x86/boot/compressed/misc.h +++ b/arch/x86/boot/compressed/misc.h @@ -124,6 +124,7 @@ void sev_es_shutdown_ghcb(void); extern bool sev_es_check_ghcb_fault(unsigned long address); void snp_set_page_private(unsigned long paddr); void snp_set_page_shared(unsigned long paddr); +void snp_cpuid_init_boot(struct boot_params *bp); #else static inline void sev_es_shutdown_ghcb(void) { } @@ -133,6 +134,7 @@ static inline bool sev_es_check_ghcb_fault(unsigned long address) } static inline void snp_set_page_private(unsigned long paddr) { } static inline void snp_set_page_shared(unsigned long paddr) { } +static inline void snp_cpuid_init_boot(struct boot_params *bp) { } #endif diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index 11c459809d4c..60885d80bf5f 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -297,3 +297,82 @@ void do_boot_stage2_vc(struct pt_regs *regs, unsigned long exit_code) else if (result != ES_RETRY) sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ); } + +/* Search for Confidential Computing blob in the EFI config table. */ +static struct cc_blob_sev_info *snp_find_cc_blob_efi(struct boot_params *bp) +{ + struct cc_blob_sev_info *cc_info; + unsigned long conf_table_pa; + unsigned int conf_table_len; + bool efi_64; + int ret; + + ret = efi_get_conf_table(bp, &conf_table_pa, &conf_table_len, &efi_64); + if (ret) + return NULL; + + ret = efi_find_vendor_table(conf_table_pa, conf_table_len, + EFI_CC_BLOB_GUID, efi_64, + (unsigned long *)&cc_info); + if (ret) + return NULL; + + return cc_info; +} + +/* + * Initial set up of SEV-SNP CPUID table relies on information provided + * by the Confidential Computing blob, which can be passed to the boot kernel + * by firmware/bootloader in the following ways: + * + * - via an entry in the EFI config table + * - via a setup_data structure, as defined by the Linux Boot Protocol + * + * Scan for the blob in that order. + */ +struct cc_blob_sev_info *snp_find_cc_blob(struct boot_params *bp) +{ + struct cc_blob_sev_info *cc_info; + + cc_info = snp_find_cc_blob_efi(bp); + if (cc_info) + goto found_cc_info; + + cc_info = snp_find_cc_blob_setup_data(bp); + if (!cc_info) + return NULL; + +found_cc_info: + if (cc_info->magic != CC_BLOB_SEV_HDR_MAGIC) + sev_es_terminate(0, GHCB_SNP_UNSUPPORTED); + + return cc_info; +} + +void snp_cpuid_init_boot(struct boot_params *bp) +{ + struct cc_blob_sev_info *cc_info; + u32 eax; + + if (!bp) + return; + + cc_info = snp_find_cc_blob(bp); + if (!cc_info) + return; + + snp_cpuid_info_create(cc_info); + + /* SEV-SNP CPUID table is set up now. Do some sanity checks. */ + if (!snp_cpuid_active()) + sev_es_terminate(1, GHCB_TERM_CPUID); + + /* CPUID bits for SEV (bit 1) and SEV-SNP (bit 4) should be enabled. */ + eax = native_cpuid_eax(0x8000001f); + if (!(eax & (BIT(4) | BIT(1)))) + sev_es_terminate(1, GHCB_TERM_CPUID); + + /* It should be safe to read SEV MSR and check features now. */ + if (!sev_snp_enabled()) + sev_es_terminate(1, GHCB_TERM_CPUID); +} diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 534fa1c4c881..7c88762cdb23 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -11,6 +11,7 @@ #include #include #include +#include #define GHCB_PROTOCOL_MIN 1ULL #define GHCB_PROTOCOL_MAX 2ULL @@ -126,6 +127,17 @@ void __init snp_prep_memory(unsigned long paddr, unsigned int sz, enum psc_op op void snp_set_memory_shared(unsigned long vaddr, unsigned int npages); void snp_set_memory_private(unsigned long vaddr, unsigned int npages); void snp_set_wakeup_secondary_cpu(void); +/* + * TODO: These are exported only temporarily while boot/compressed/sev.c is + * the only user. This is to avoid unused function warnings for kernel/sev.c + * during the build of kernel proper. + * + * Once the code is added to consume these in kernel proper these functions + * can be moved back to being statically-scoped to units that pull in + * sev-shared.c via #include and these declarations can be dropped. + */ +void __init snp_cpuid_info_create(const struct cc_blob_sev_info *cc_info); +struct cc_blob_sev_info *snp_find_cc_blob_setup_data(struct boot_params *bp); #else static inline void sev_es_ist_enter(struct pt_regs *regs) { } static inline void sev_es_ist_exit(void) { } @@ -141,6 +153,8 @@ static inline void __init snp_prep_memory(unsigned long paddr, unsigned int sz, static inline void snp_set_memory_shared(unsigned long vaddr, unsigned int npages) { } static inline void snp_set_memory_private(unsigned long vaddr, unsigned int npages) { } static inline void snp_set_wakeup_secondary_cpu(void) { } +void snp_cpuid_info_create(const struct cc_blob_sev_info *cc_info) { } +struct cc_blob_sev_info *snp_find_cc_blob_setup_data(struct boot_params *bp) { } #endif #endif diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index 193ca49a1689..b321c1b7d07c 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -66,6 +66,9 @@ static u64 __ro_after_init sev_hv_features; * and regenerate the CPUID table/pointer when .bss is cleared. */ +/* Copy of the SNP firmware's CPUID page. */ +static struct snp_cpuid_info cpuid_info_copy __ro_after_init; + /* * The CPUID info can't always be referenced directly due to the need for * pointer fixups during initial startup phase of kernel proper, so access must @@ -390,6 +393,22 @@ snp_cpuid_find_validated_func(u32 func, u32 subfunc, u32 *eax, u32 *ebx, return false; } +static void __init snp_cpuid_set_ranges(void) +{ + int i; + + for (i = 0; i < cpuid_info->count; i++) { + const struct snp_cpuid_fn *fn = &cpuid_info->fn[i]; + + if (fn->eax_in == 0x0) + cpuid_std_range_max = fn->eax; + else if (fn->eax_in == 0x40000000) + cpuid_hyp_range_max = fn->eax; + else if (fn->eax_in == 0x80000000) + cpuid_ext_range_max = fn->eax; + } +} + static bool snp_cpuid_check_range(u32 func) { if (func <= cpuid_std_range_max || @@ -934,3 +953,62 @@ static enum es_result vc_handle_rdtsc(struct ghcb *ghcb, return ES_OK; } + +struct cc_setup_data { + struct setup_data header; + u32 cc_blob_address; +}; + +static struct cc_setup_data *get_cc_setup_data(struct boot_params *bp) +{ + struct setup_data *hdr = (struct setup_data *)bp->hdr.setup_data; + + while (hdr) { + if (hdr->type == SETUP_CC_BLOB) + return (struct cc_setup_data *)hdr; + hdr = (struct setup_data *)hdr->next; + } + + return NULL; +} + +/* + * Search for a Confidential Computing blob passed in as a setup_data entry + * via the Linux Boot Protocol. + */ +struct cc_blob_sev_info * +snp_find_cc_blob_setup_data(struct boot_params *bp) +{ + struct cc_setup_data *sd; + + sd = get_cc_setup_data(bp); + if (!sd) + return NULL; + + return (struct cc_blob_sev_info *)(unsigned long)sd->cc_blob_address; +} + +/* + * Initialize the kernel's copy of the SEV-SNP CPUID table, and set up the + * pointer that will be used to access it. + * + * Maintaining a direct mapping of the SEV-SNP CPUID table used by firmware + * would be possible as an alternative, but the approach is brittle since the + * mapping needs to be updated in sync with all the changes to virtual memory + * layout and related mapping facilities throughout the boot process. + */ +void __init snp_cpuid_info_create(const struct cc_blob_sev_info *cc_info) +{ + const struct snp_cpuid_info *cpuid_info_fw; + + if (!cc_info || !cc_info->cpuid_phys || cc_info->cpuid_len < PAGE_SIZE) + sev_es_terminate(1, GHCB_TERM_CPUID); + + cpuid_info_fw = (const struct snp_cpuid_info *)cc_info->cpuid_phys; + if (!cpuid_info_fw->count || cpuid_info_fw->count > SNP_CPUID_COUNT_MAX) + sev_es_terminate(1, GHCB_TERM_CPUID); + + cpuid_info = &cpuid_info_copy; + memcpy((void *)cpuid_info, cpuid_info_fw, sizeof(*cpuid_info)); + snp_cpuid_set_ranges(); +} From patchwork Fri Oct 8 18:04:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD848C433EF for ; Fri, 8 Oct 2021 18:06:40 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 5A07D60F6D for ; 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Fri, 8 Oct 2021 13:06:08 -0500 From: Brijesh Singh To: , , , , , , CC: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , "Vitaly Kuznetsov" , Jim Mattson , "Andy Lutomirski" , Dave Hansen , Sergio Lopez , Peter Gonda , "Peter Zijlstra" , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , "Dr . David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 34/42] x86/boot: add a pointer to Confidential Computing blob in bootparams Date: Fri, 8 Oct 2021 13:04:45 -0500 Message-ID: <20211008180453.462291-35-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 914c8814-9c8c-47f7-8d81-08d98a86532c X-MS-TrafficTypeDiagnostic: DM8PR12MB5430: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ssHDQhHk67gXk7OVD4/x+tH18SmGKfY4BMx9pZWvthOa9gMkxm59YfGtU07pCwpF0Ck52sKjNMtonR7jqo6p5JYvBTgxawFk5K1bgOvA29DmskVxXli0otIJq23RG7btJLQDL/jmQd714DfGfzdKCSTKaCui1mfMj3O3L+uZD0BG2IKZneF9IQJtqNaSryoqCfiz2EAXZgfPPkX+KdLRl6GYR68rcae8NN7JQltcWtR2nJZY3vGw09sjJ3iQJ0qUnVgqKMJZXaPO9lZjmssShMULtdR3/T9HwmKjEO1O8z1hEPUklQv2WCTqnpaAsas4K8UGLDV80sRo92UyIyd9lK1znM1SxCVIlpU19P3wLLThdyMjaVDpqsEPhYnS42sMj6ikoSlTiBHN/H4neu56OisN82hkwpr45uoWCsRFx7SHqB84JE9xA0VKuUnJmuLP3fj7H1X8UTqxpYCWvGalMxattoh7cF1fhQOEUN0IxCXq9zXx9oKqV/nzC4RzTR9GKdd9l4BEeAUZK+7mg3SP1WnUKoPmsdIiB2nMMTIuCzx9X3pQMK1pKit8QqfjfJrrVRTS3HGg0ZWFHGgNq2jpW9/qrpfhcn9Znwk1G6RVGfEMY0YbfjDuUCKg7n+y1ZEHmGUoUAjvv2ww6+J0M1DJZmM02oE80dPYK0pfmXNbKUxnRj0dvkS+6jsKyWxS4ByNvnyFUHYKWu3JOGeU7mGbwTUPearwIGQsQAF/aix+OIQnInKAHC4Kg0RtWJBcYUGs X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(316002)(7696005)(70586007)(2906002)(70206006)(44832011)(36860700001)(47076005)(110136005)(86362001)(54906003)(36756003)(6666004)(508600001)(186003)(16526019)(26005)(7416002)(7406005)(8936002)(8676002)(336012)(4326008)(426003)(356005)(2616005)(1076003)(83380400001)(5660300002)(81166007)(82310400003)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:06:17.3786 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 914c8814-9c8c-47f7-8d81-08d98a86532c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5430 Authentication-Results: imf26.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=wDFwnxf4; spf=pass (imf26.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.93.49 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 7F14E200FC82 X-Stat-Signature: qe4n9cs5s3qfx9rbnzah9hpwexh8x4am X-HE-Tag: 1633716380-641157 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Michael Roth The previously defined Confidential Computing blob is provided to the kernel via a setup_data structure or EFI config table entry. Currently these are both checked for by boot/compressed kernel to access the CPUID table address within it for use with SEV-SNP CPUID enforcement. To also enable SEV-SNP CPUID enforcement for the run-time kernel, similar early access to the CPUID table is needed early on while it's still using the identity-mapped page table set up by boot/compressed, where global pointers need to be accessed via fixup_pointer(). This isn't much of an issue for accessing setup_data, and the EFI config table helper code currently used in boot/compressed *could* be used in this case as well since they both rely on identity-mapping. However, it has some reliance on EFI helpers/string constants that would need to be accessed via fixup_pointer(), and fixing it up while making it shareable between boot/compressed and run-time kernel is fragile and introduces a good bit of uglyness. Instead, add a boot_params->cc_blob_address pointer that the boot/compressed kernel can initialize so that the run-time kernel can access the CC blob from there instead of re-scanning the EFI config table. Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- arch/x86/include/asm/bootparam_utils.h | 1 + arch/x86/include/uapi/asm/bootparam.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/bootparam_utils.h b/arch/x86/include/asm/bootparam_utils.h index 981fe923a59f..53e9b0620d96 100644 --- a/arch/x86/include/asm/bootparam_utils.h +++ b/arch/x86/include/asm/bootparam_utils.h @@ -74,6 +74,7 @@ static void sanitize_boot_params(struct boot_params *boot_params) BOOT_PARAM_PRESERVE(hdr), BOOT_PARAM_PRESERVE(e820_table), BOOT_PARAM_PRESERVE(eddbuf), + BOOT_PARAM_PRESERVE(cc_blob_address), }; memset(&scratch, 0, sizeof(scratch)); diff --git a/arch/x86/include/uapi/asm/bootparam.h b/arch/x86/include/uapi/asm/bootparam.h index 1ac5acca72ce..bea5cdcdf532 100644 --- a/arch/x86/include/uapi/asm/bootparam.h +++ b/arch/x86/include/uapi/asm/bootparam.h @@ -188,7 +188,8 @@ struct boot_params { __u32 ext_ramdisk_image; /* 0x0c0 */ __u32 ext_ramdisk_size; /* 0x0c4 */ __u32 ext_cmd_line_ptr; /* 0x0c8 */ - __u8 _pad4[116]; /* 0x0cc */ + __u8 _pad4[112]; /* 0x0cc */ + __u32 cc_blob_address; /* 0x13c */ struct edid_info edid_info; /* 0x140 */ struct efi_info efi_info; /* 0x1c0 */ __u32 alt_mem_k; /* 0x1e0 */ From patchwork Fri Oct 8 18:04:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E498C433F5 for ; Fri, 8 Oct 2021 18:06:52 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id BC7A5610E7 for ; Fri, 8 Oct 2021 18:06:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org BC7A5610E7 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=amd.com Authentication-Results: mail.kernel.org; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 35/42] x86/compressed/64: store Confidential Computing blob address in bootparams Date: Fri, 8 Oct 2021 13:04:46 -0500 Message-ID: <20211008180453.462291-36-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bdd76ffe-05ca-4a58-b2e5-08d98a865377 X-MS-TrafficTypeDiagnostic: BY5PR12MB3748: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: c6BKZn3UQZwmRcrJGY9Rd4DpWSVtcD2rGfkCEQgEduVws27Hq47qNCurak9ecGcgPKf0FpLGVXJw1YkNyv2K+0TeVVtADoPUddCSo6MOPqmgq9x0n/VQM2ScAaSWoV6GY8cGx2qjhD4hcnTQxqkYVDgrXjNXkxVWYZ1966OA2RQEeSPz1jYJEs8bucIy3djYYETKPIRBurnCLTDuz7ZLaQzCj2RBfEgHbT55VgIX3mZogTcJ1vh96Fp9K1DfYlPmWAd9SM5bnDQ/Ai4u3QjLEQlg5FSgNY/j4I5XsRc2AjPIzirTzzeoz9bxglbb8F2Dp2A2oRwQ7s+5XtcX0El/otXucwjOuMWux2E8O5GneEkZJxYNpYwosOGKBCHijxNPfV6j3UDAiIDJb2EdOgJiMAWs8lxh6YqgjmBgQ0pRjyxWTW7ZWHnrwelgPUm5vP+92Mk6FoHRZPRRV3HZ5iatfknpjeUlDqSd7dfRBJv2G+zPFFPTtsrBY08CYPp6RsxUFKgOrOZuyv1KgCDwfgZyA9bOLFIvL3RZLWvRKQN0zeK8hygNQFaDMeI51C6AYuqNsMLZjOf2NfssRIxPfcDI/fGJqGlNhD31NRfFHYp0gXujkyUBS8WSH41vsCz7WzqfKfe0WsMPmP+hu3CDqkCWzqEfA7zrMf2ItSMChdBU4RcWq6mfrWAslbOCGijITwySGsTTWxLMmhXrTeEYAR5nGz/G4NQMxcMiR9HpEZTolYTpnxs6PBtPsalqCXhyYaK2 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(7696005)(44832011)(36860700001)(6666004)(508600001)(8676002)(54906003)(110136005)(316002)(4326008)(2906002)(26005)(86362001)(36756003)(186003)(16526019)(1076003)(70586007)(82310400003)(5660300002)(8936002)(336012)(7416002)(426003)(47076005)(7406005)(70206006)(356005)(2616005)(81166007)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:06:17.8631 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bdd76ffe-05ca-4a58-b2e5-08d98a865377 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3748 X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: 46BEA801B38F X-Stat-Signature: fzkz9euh6m8ez67ofqc5a67cz8pmgpfp Authentication-Results: imf06.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=NM+385ow; dmarc=pass (policy=quarantine) header.from=amd.com; spf=pass (imf06.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.243.45 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com X-HE-Tag: 1633716382-500712 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Michael Roth When the Confidential Computing blob is located by the boot/compressed kernel, store a pointer to it in bootparams->cc_blob_address to avoid the need for the run-time kernel to rescan the EFI config table to find it again. Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- arch/x86/boot/compressed/sev.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index 60885d80bf5f..9d6a2ecb609f 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -375,4 +375,11 @@ void snp_cpuid_init_boot(struct boot_params *bp) /* It should be safe to read SEV MSR and check features now. */ if (!sev_snp_enabled()) sev_es_terminate(1, GHCB_TERM_CPUID); + + /* + * Pass run-time kernel a pointer to CC info via boot_params so EFI + * config table doesn't need to be searched again during early startup + * phase. + */ + bp->cc_blob_address = (u32)(unsigned long)cc_info; } From patchwork Fri Oct 8 18:04:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B083C433EF for ; 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Fri, 8 Oct 2021 13:06:11 -0500 From: Brijesh Singh To: , , , , , , CC: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , "Vitaly Kuznetsov" , Jim Mattson , "Andy Lutomirski" , Dave Hansen , Sergio Lopez , Peter Gonda , "Peter Zijlstra" , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , "Dr . David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 36/42] x86/compressed/64: add identity mapping for Confidential Computing blob Date: Fri, 8 Oct 2021 13:04:47 -0500 Message-ID: <20211008180453.462291-37-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 142dfe3a-96fe-4fa4-feea-08d98a86540c X-MS-TrafficTypeDiagnostic: DM4PR12MB5280: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: N96+EH+SlT4ldGYGcydQ9QvNKmJt2GvB2ubc7L6dN93C2zjsF1uBawi5cVX9vrVd7MPQg/ovlaZDLnQGc874vIorpj8giKA/Qw1Rz6r2zPWi25tXNHo+PU93alVsYnlP7cyq8GmKNh2bVdT+o1FWaEmiupfY/c5HVK4q+Q5mxD8w8Kz6t1UNObdr49dfmjCyrLWPyvFaBlVcf+1lJ+9FjBnBoDGgDzG6Hf5gGVFbCA9cCJZBz4bku4EUQt7fUgbVLcNMHObwC73S1s1Y/udzso5xnv4eKnZ7NRs46dAa0UUV5PsBO563mvxAmOwDuvWW8iPSI3h2fLFMMxiKIGA+Fa74xgmVX7qvn9hDMS1IjD5S3xFGlxE7deilf36/0DK2SQKidkFyersmRew1Q3AN06xghQYD2NX9U4xQ2/ep28N6rpdHUqEqM1Lk7WaSFma/hN3ZBkXe7bdwvHpq006H90RZ/lCS01a+Unc4v3kJRbvL2LNhTB9xjyOv8FytdVxmCKeglYnugwHxGtL546CGiQM0YRS2XP1zD1TkDOlnlFhsvqAsXwQAwSRRUOaU8+ToFXAG6/U1NMywZvoDYj9SZzdXm5tBTrdi0i1wlJj5OzEAIhiSP8lDnQkGMbgC93dnJVjkxrcXuprCU6PGSVXmhVUJ7AqvL7dxpVzb6PHZ0S+DENrNyJF4G9FzZ+VsckCDv/kKLwpMD8+jRY/AQ90vTov0gTeFj3flVPynSo9/QT0LiCeYyoQHWCG44fLCU+sp X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(47076005)(316002)(336012)(508600001)(8676002)(7696005)(83380400001)(2616005)(4326008)(44832011)(1076003)(426003)(6666004)(82310400003)(186003)(26005)(356005)(36860700001)(54906003)(16526019)(7416002)(5660300002)(81166007)(70206006)(8936002)(70586007)(36756003)(2906002)(7406005)(86362001)(110136005)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:06:18.8375 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 142dfe3a-96fe-4fa4-feea-08d98a86540c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5280 X-Rspamd-Queue-Id: 34F7C801AB3F X-Stat-Signature: oxzqhu89esbo9qz8z5xginskzmjgsrij Authentication-Results: imf06.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=P6BbvzvN; spf=pass (imf06.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.237.80 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam06 X-HE-Tag: 1633716382-768252 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Michael Roth The run-time kernel will need to access the Confidential Computing blob very early in boot to access the CPUID table it points to. At that stage of boot it will be relying on the identity-mapped page table set up by boot/compressed kernel, so make sure the blob and the CPUID table it points to are mapped in advance. Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- arch/x86/boot/compressed/ident_map_64.c | 26 ++++++++++++++++++++++++- arch/x86/boot/compressed/misc.h | 2 ++ arch/x86/boot/compressed/sev.c | 2 +- 3 files changed, 28 insertions(+), 2 deletions(-) diff --git a/arch/x86/boot/compressed/ident_map_64.c b/arch/x86/boot/compressed/ident_map_64.c index 3cf7a7575f5c..10ecbc53f8bc 100644 --- a/arch/x86/boot/compressed/ident_map_64.c +++ b/arch/x86/boot/compressed/ident_map_64.c @@ -37,6 +37,8 @@ #include /* For COMMAND_LINE_SIZE */ #undef _SETUP +#include /* For ConfidentialComputing blob */ + extern unsigned long get_cmd_line_ptr(void); /* Used by PAGE_KERN* macros: */ @@ -106,6 +108,27 @@ static void add_identity_map(unsigned long start, unsigned long end) error("Error: kernel_ident_mapping_init() failed\n"); } +void sev_prep_identity_maps(void) +{ + /* + * The ConfidentialComputing blob is used very early in uncompressed + * kernel to find the in-memory cpuid table to handle cpuid + * instructions. Make sure an identity-mapping exists so it can be + * accessed after switchover. + */ + if (sev_snp_enabled()) { + struct cc_blob_sev_info *cc_info = + (void *)(unsigned long)boot_params->cc_blob_address; + + add_identity_map((unsigned long)cc_info, + (unsigned long)cc_info + sizeof(*cc_info)); + add_identity_map((unsigned long)cc_info->cpuid_phys, + (unsigned long)cc_info->cpuid_phys + cc_info->cpuid_len); + } + + sev_verify_cbit(top_level_pgt); +} + /* Locates and clears a region for a new top level page table. */ void initialize_identity_maps(void *rmode) { @@ -163,8 +186,9 @@ void initialize_identity_maps(void *rmode) cmdline = get_cmd_line_ptr(); add_identity_map(cmdline, cmdline + COMMAND_LINE_SIZE); + sev_prep_identity_maps(); + /* Load the new page-table. */ - sev_verify_cbit(top_level_pgt); write_cr3(top_level_pgt); } diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/misc.h index 9b66a8bf336e..ce1a884e8322 100644 --- a/arch/x86/boot/compressed/misc.h +++ b/arch/x86/boot/compressed/misc.h @@ -125,6 +125,7 @@ extern bool sev_es_check_ghcb_fault(unsigned long address); void snp_set_page_private(unsigned long paddr); void snp_set_page_shared(unsigned long paddr); void snp_cpuid_init_boot(struct boot_params *bp); +bool sev_snp_enabled(void); #else static inline void sev_es_shutdown_ghcb(void) { } @@ -135,6 +136,7 @@ static inline bool sev_es_check_ghcb_fault(unsigned long address) static inline void snp_set_page_private(unsigned long paddr) { } static inline void snp_set_page_shared(unsigned long paddr) { } static inline void snp_cpuid_init_boot(struct boot_params *bp) { } +static inline bool sev_snp_enabled(void) { return false; } #endif diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index 9d6a2ecb609f..1b77b819ddb4 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -120,7 +120,7 @@ static enum es_result vc_read_mem(struct es_em_ctxt *ctxt, /* Include code for early handlers */ #include "../../kernel/sev-shared.c" -static inline bool sev_snp_enabled(void) +bool sev_snp_enabled(void) { return sev_status & MSR_AMD64_SEV_SNP_ENABLED; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 37/42] x86/sev: use firmware-validated CPUID for SEV-SNP guests Date: Fri, 8 Oct 2021 13:04:48 -0500 Message-ID: <20211008180453.462291-38-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0efd54d0-3fb2-4213-fb90-08d98a8654f0 X-MS-TrafficTypeDiagnostic: BL0PR12MB4914: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rhiziY8LFSJbr2zgFjnq3zlNyCuazMg/6zFq35SK7gT6QCrLUuoARuNOyit6lb/M2LHN2mvJGlsvkoLxYSSPpG21pz/9Prbu+Pyf+IBfzoNm8oWCg05ES0XYzHyv61P81YnivdIhN9iO9YszTCiNI9Uk0MJfrlYjNCsTq4R6MZNUiuLygLHpHkBoGUnaHhmkTMD56Sm2yWt7wygu0mwUW5Wg4Obp5dv4nQLJO2f7di6HJwx+Ghpoq6NjcqOC93MbA89DvbZsUVkskAELC5kyfuihFY2TLjUOa9Z/ObMC5vZzE5xqK4RKUjmA1c2LIxz/fF3n1ieGrpZvt0YdG1KWx1WmYkvwRoeGvwqIMPKEW4uA764+aav5vVinTqh7QrEZZJWXstZFYYeRq6ej0NPAxE7NcCXAyd5mycsrDNOCh6Ujrw3D/nljcdr/2ACnkaFat4teyk+zuJBKsl9oOw8rkUME+iFAZ26Ay8dV0tfc4uIQk0pCTOgpKJYA/DFSTOTq65+h/QsWcOOKF3blB9mFvWGGGiNbT9AjT9raUcqKa6UV7HFF4ukEg3rkNwQD2yPJiDCruns7KHzdfnLeGS4fq+NUd+ojfwL4S0j+zlZ+lk2bINF8hWxxUjunJkHDjq4Gez/mhDo6znLE5fHsx9bmbu5MMlPyvUwntdDCXQdyp0Vzg/jrMWU7OOZELx1ZslMzxGoOPYjF94QkxTI6NWysyEMn9MPN4qffrmBNGA8P141zIsYnOcAxywYlOSxwCuZV X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(2906002)(8676002)(7416002)(7406005)(4326008)(8936002)(83380400001)(82310400003)(47076005)(36860700001)(6666004)(36756003)(508600001)(336012)(81166007)(5660300002)(186003)(70206006)(16526019)(70586007)(26005)(1076003)(110136005)(426003)(86362001)(15650500001)(44832011)(54906003)(30864003)(316002)(7696005)(2616005)(356005)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:06:20.3356 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0efd54d0-3fb2-4213-fb90-08d98a8654f0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4914 X-Rspamd-Server: rspam02 X-Rspamd-Queue-Id: 5292EB00245A X-Stat-Signature: fg8c9y31niu3oiwm1tn6ja37obwzxyqd Authentication-Results: imf19.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=HSXtCzoA; spf=pass (imf19.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.223.68 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-HE-Tag: 1633716384-823176 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Michael Roth SEV-SNP guests will be provided the location of special 'secrets' and 'CPUID' pages via the Confidential Computing blob. This blob is provided to the run-time kernel either through bootparams field that was initialized by the boot/compressed kernel, or via a setup_data structure as defined by the Linux Boot Protocol. Locate the Confidential Computing from these sources and, if found, use the provided CPUID page/table address to create a copy that the run-time kernel will use when servicing cpuid instructions via a #VC handler. This must be set up during early startup before any cpuid instructions are issued. As result, some pointer fixups are needed early on that must be adjusted later in boot, which is why there are 2 init routines. Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- arch/x86/boot/compressed/sev.c | 2 +- arch/x86/include/asm/setup.h | 2 +- arch/x86/include/asm/sev.h | 17 +---- arch/x86/kernel/head64.c | 12 ++- arch/x86/kernel/sev-shared.c | 23 +++++- arch/x86/kernel/sev.c | 135 +++++++++++++++++++++++++++++++++ 6 files changed, 170 insertions(+), 21 deletions(-) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index 1b77b819ddb4..2f31f69715d0 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -361,7 +361,7 @@ void snp_cpuid_init_boot(struct boot_params *bp) if (!cc_info) return; - snp_cpuid_info_create(cc_info); + snp_cpuid_info_create(cc_info, 0); /* SEV-SNP CPUID table is set up now. Do some sanity checks. */ if (!snp_cpuid_active()) diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h index a12458a7a8d4..cee1e816fdcd 100644 --- a/arch/x86/include/asm/setup.h +++ b/arch/x86/include/asm/setup.h @@ -50,7 +50,7 @@ extern void reserve_standard_io_resources(void); extern void i386_reserve_resources(void); extern unsigned long __startup_64(unsigned long physaddr, struct boot_params *bp); extern unsigned long __startup_secondary_64(void); -extern void startup_64_setup_env(unsigned long physbase); +extern void startup_64_setup_env(unsigned long physbase, struct boot_params *bp); extern void early_setup_idt(void); extern void __init do_early_exception(struct pt_regs *regs, int trapnr); diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 7c88762cdb23..1c58060b48b7 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -127,17 +127,8 @@ void __init snp_prep_memory(unsigned long paddr, unsigned int sz, enum psc_op op void snp_set_memory_shared(unsigned long vaddr, unsigned int npages); void snp_set_memory_private(unsigned long vaddr, unsigned int npages); void snp_set_wakeup_secondary_cpu(void); -/* - * TODO: These are exported only temporarily while boot/compressed/sev.c is - * the only user. This is to avoid unused function warnings for kernel/sev.c - * during the build of kernel proper. - * - * Once the code is added to consume these in kernel proper these functions - * can be moved back to being statically-scoped to units that pull in - * sev-shared.c via #include and these declarations can be dropped. - */ -void __init snp_cpuid_info_create(const struct cc_blob_sev_info *cc_info); -struct cc_blob_sev_info *snp_find_cc_blob_setup_data(struct boot_params *bp); +void snp_cpuid_init_startup(struct boot_params *bp, unsigned long physaddr); +void snp_cpuid_init(void); #else static inline void sev_es_ist_enter(struct pt_regs *regs) { } static inline void sev_es_ist_exit(void) { } @@ -153,8 +144,8 @@ static inline void __init snp_prep_memory(unsigned long paddr, unsigned int sz, static inline void snp_set_memory_shared(unsigned long vaddr, unsigned int npages) { } static inline void snp_set_memory_private(unsigned long vaddr, unsigned int npages) { } static inline void snp_set_wakeup_secondary_cpu(void) { } -void snp_cpuid_info_create(const struct cc_blob_sev_info *cc_info) { } -struct cc_blob_sev_info *snp_find_cc_blob_setup_data(struct boot_params *bp) { } +static inline void snp_cpuid_startup(struct boot_params *bp, unsigned long physbase) { } +static inline void snp_cpuid_init(void) { } #endif #endif diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c index 3c0bfed3b58e..ef5efa484efa 100644 --- a/arch/x86/kernel/head64.c +++ b/arch/x86/kernel/head64.c @@ -571,7 +571,7 @@ static void set_bringup_idt_handler(gate_desc *idt, int n, void *handler) } /* This runs while still in the direct mapping */ -static void startup_64_load_idt(unsigned long physbase) +static void startup_64_load_idt(unsigned long physbase, struct boot_params *bp) { struct desc_ptr *desc = fixup_pointer(&bringup_idt_descr, physbase); gate_desc *idt = fixup_pointer(bringup_idt_table, physbase); @@ -587,6 +587,9 @@ static void startup_64_load_idt(unsigned long physbase) desc->address = (unsigned long)idt; native_load_idt(desc); + + if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) + snp_cpuid_init_startup(bp, physbase); } /* This is used when running on kernel addresses */ @@ -598,12 +601,15 @@ void early_setup_idt(void) bringup_idt_descr.address = (unsigned long)bringup_idt_table; native_load_idt(&bringup_idt_descr); + + if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) + snp_cpuid_init(); } /* * Setup boot CPU state needed before kernel switches to virtual addresses. */ -void __head startup_64_setup_env(unsigned long physbase) +void __head startup_64_setup_env(unsigned long physbase, struct boot_params *bp) { /* Load GDT */ startup_gdt_descr.address = (unsigned long)fixup_pointer(startup_gdt, physbase); @@ -614,5 +620,5 @@ void __head startup_64_setup_env(unsigned long physbase) "movl %%eax, %%ss\n" "movl %%eax, %%es\n" : : "a"(__KERNEL_DS) : "memory"); - startup_64_load_idt(physbase); + startup_64_load_idt(physbase, bp); } diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index b321c1b7d07c..341ea8800b9f 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -976,7 +976,7 @@ static struct cc_setup_data *get_cc_setup_data(struct boot_params *bp) * Search for a Confidential Computing blob passed in as a setup_data entry * via the Linux Boot Protocol. */ -struct cc_blob_sev_info * +static struct cc_blob_sev_info * snp_find_cc_blob_setup_data(struct boot_params *bp) { struct cc_setup_data *sd; @@ -988,6 +988,22 @@ snp_find_cc_blob_setup_data(struct boot_params *bp) return (struct cc_blob_sev_info *)(unsigned long)sd->cc_blob_address; } +static const struct snp_cpuid_info * +snp_cpuid_info_get_ptr(unsigned long physbase) +{ + void *ptr = &cpuid_info_copy; + + /* physbase is only 0 when the caller doesn't need adjustments */ + if (!physbase) + return ptr; + + /* + * Handle relocation adjustments for global pointers, as done by + * fixup_pointer() in __startup64(). + */ + return ptr - (void *)_text + (void *)physbase; +} + /* * Initialize the kernel's copy of the SEV-SNP CPUID table, and set up the * pointer that will be used to access it. @@ -997,7 +1013,8 @@ snp_find_cc_blob_setup_data(struct boot_params *bp) * mapping needs to be updated in sync with all the changes to virtual memory * layout and related mapping facilities throughout the boot process. */ -void __init snp_cpuid_info_create(const struct cc_blob_sev_info *cc_info) +static void __init snp_cpuid_info_create(const struct cc_blob_sev_info *cc_info, + unsigned long physbase) { const struct snp_cpuid_info *cpuid_info_fw; @@ -1008,7 +1025,7 @@ void __init snp_cpuid_info_create(const struct cc_blob_sev_info *cc_info) if (!cpuid_info_fw->count || cpuid_info_fw->count > SNP_CPUID_COUNT_MAX) sev_es_terminate(1, GHCB_TERM_CPUID); - cpuid_info = &cpuid_info_copy; + cpuid_info = snp_cpuid_info_get_ptr(physbase); memcpy((void *)cpuid_info, cpuid_info_fw, sizeof(*cpuid_info)); snp_cpuid_set_ranges(); } diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index d348ad027df8..1e6152fe27ba 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -1986,3 +1986,138 @@ bool __init handle_vc_boot_ghcb(struct pt_regs *regs) while (true) halt(); } + +/* + * Initial set up of SEV-SNP CPUID table relies on information provided + * by the Confidential Computing blob, which can be passed to the kernel + * in the following ways, depending on how it is booted: + * + * - when booted via the boot/decompress kernel: + * - via boot_params + * + * - when booted directly by firmware/bootloader (e.g. CONFIG_PVH): + * - via a setup_data entry, as defined by the Linux Boot Protocol + * + * Scan for the blob in that order. + */ +struct cc_blob_sev_info *snp_find_cc_blob(struct boot_params *bp) +{ + struct cc_blob_sev_info *cc_info; + + /* Boot kernel would have passed the CC blob via boot_params. */ + if (bp->cc_blob_address) { + cc_info = (struct cc_blob_sev_info *) + (unsigned long)bp->cc_blob_address; + goto found_cc_info; + } + + /* + * If kernel was booted directly, without the use of the + * boot/decompression kernel, the CC blob may have been passed via + * setup_data instead. + */ + cc_info = snp_find_cc_blob_setup_data(bp); + if (!cc_info) + return NULL; + +found_cc_info: + if (cc_info->magic != CC_BLOB_SEV_HDR_MAGIC) + sev_es_terminate(1, GHCB_SNP_UNSUPPORTED); + + return cc_info; +} + +/* + * Initial set up of SEV-SNP CPUID table during early startup when still + * using identity-mapped addresses. + * + * Since this is during early startup, physbase is needed to generate the + * correct pointer to the initialized CPUID table. This pointer will be + * adjusted again later via snp_cpuid_init() after the kernel switches over + * to virtual addresses and pointer fixups are no longer needed. + */ +void __init snp_cpuid_init_startup(struct boot_params *bp, + unsigned long physbase) +{ + struct cc_blob_sev_info *cc_info; + u32 eax; + + if (!bp) + return; + + cc_info = snp_find_cc_blob(bp); + if (!cc_info) + return; + + snp_cpuid_info_create(cc_info, physbase); + + /* SEV-SNP CPUID table is set up now. Do some sanity checks. */ + if (!snp_cpuid_active()) + sev_es_terminate(1, GHCB_TERM_CPUID); + + /* SEV (bit 1) and SEV-SNP (bit 4) should be enabled in CPUID. */ + eax = native_cpuid_eax(0x8000001f); + if (!(eax & (BIT(4) | BIT(1)))) + sev_es_terminate(1, GHCB_TERM_CPUID); + + /* #VC generated by CPUID above will set sev_status based on SEV MSR. */ + if (!(sev_status & MSR_AMD64_SEV_SNP_ENABLED)) + sev_es_terminate(1, GHCB_TERM_CPUID); + + /* + * The CC blob will be used later to access the secrets page. Cache + * it here like the boot kernel does. + */ + bp->cc_blob_address = (u32)(unsigned long)cc_info; +} + +/* + * This is called after the kernel switches over to virtual addresses. Fixup + * offsets are no longer needed at this point, so update the CPUID table + * pointer accordingly. + */ +void snp_cpuid_init(void) +{ + if (!cc_platform_has(CC_ATTR_SEV_SNP)) { + /* Firmware should not have advertised the feature. */ + if (snp_cpuid_active()) + panic("Invalid use of SEV-SNP CPUID table."); + return; + } + + /* CPUID table should always be available when SEV-SNP is enabled. */ + if (!snp_cpuid_active()) + sev_es_terminate(1, GHCB_TERM_CPUID); + + /* Remove the fixup offset from the cpuid_info pointer. */ + cpuid_info = snp_cpuid_info_get_ptr(0); +} + +/* + * It is useful from an auditing/testing perspective to provide an easy way + * for the guest owner to know that the CPUID table has been initialized as + * expected, but that initialization happens too early in boot to print any + * sort of indicator, and there's not really any other good place to do it. So + * do it here, and while at it, go ahead and re-verify that nothing strange has + * happened between early boot and now. + */ +static int __init snp_cpuid_check_status(void) +{ + if (!cc_platform_has(CC_ATTR_SEV_SNP)) { + /* Firmware should not have advertised the feature. */ + if (snp_cpuid_active()) + panic("Invalid use of SEV-SNP CPUID table."); + return 0; + } + + /* CPUID table should always be available when SEV-SNP is enabled. */ + if (!snp_cpuid_active()) + sev_es_terminate(1, GHCB_TERM_CPUID); + + pr_info("Using SEV-SNP CPUID table, %d entries present.\n", + cpuid_info->count); + + return 0; +} + +arch_initcall(snp_cpuid_check_status); From patchwork Fri Oct 8 18:04:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545963 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE1DFC433EF for ; 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Fri, 8 Oct 2021 13:06:15 -0500 From: Brijesh Singh To: , , , , , , CC: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , "Vitaly Kuznetsov" , Jim Mattson , "Andy Lutomirski" , Dave Hansen , Sergio Lopez , Peter Gonda , "Peter Zijlstra" , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , "Dr . David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 38/42] x86/sev: Provide support for SNP guest request NAEs Date: Fri, 8 Oct 2021 13:04:49 -0500 Message-ID: <20211008180453.462291-39-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 172569e1-1cff-4b0e-ce06-08d98a865587 X-MS-TrafficTypeDiagnostic: BY5PR12MB4950: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 1DUiwlXxKFSDSep/x9qP3UyGZzHr1PO4gOzDgefoMPsUDBucTR+OZre3K3p5Qb7ZyN4hDGzfm/paywao+3GxLQC03VdMx6CwgvwpruEFZlGc2YjAR109JsP/Jf6XVimkFBKdK52cAoxBS1SaCL+5S/4xpHyYrEMgagahkBxkuhP+VrtRQ3Pj2aeOQ7BuaKxZg2V0xvYaDUuF9TZBQcKaGRPHO9RaWcFH+BG2pvHivqBgoks0nUdMnxWJR/XelLFY8+j2TehGOD7+sDDC9akHi9QjAb81jBq6n7HG7/T53FlNPCFiVIJUQSvQFTSEs/hPv2xbIA/2v/ctGWGQk7dOR71yvbVJRyjt7ylSwp692NPMJZj9wv9VDw7GwQCAsapb7pbLGh7d6ABWQFUfqUIO4/fgazJl/Z8H/90WJMipD4S9ZvlnfBkRhSrOuOVFS1cgRRHcpHBAUqnTjPuGj4DE0TLByGb3FE0knwULjw9z8+FL+02qDX6yUnUAMZszwZPV9G+PoTBXWtb9nxZxo/LQ8sNAzc+bUpyK5LM4fGpw8zW+6WNWzU6oCTQOyeqKRu0N6ybH7K5kltU69Znw3OKQUXrmZmPIVDxRD4489XSjbUea9fnS5EkmU/BZ0jfRWUH/oHYEygllOy/e5lPeXs/TzfaOYbcy6+0xI/5774QrxBmjeEbKtXrjsSlYsYV8Ll3HGXdhIJqQ44vxJ2mIICUUHGhk0nka79DNTUHRIOxDmaZKm6j0yX8J6yZCOahVdAG+ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(70206006)(54906003)(316002)(8936002)(7696005)(82310400003)(2906002)(7416002)(7406005)(36860700001)(110136005)(83380400001)(47076005)(2616005)(16526019)(186003)(70586007)(26005)(6666004)(356005)(4326008)(86362001)(336012)(5660300002)(36756003)(8676002)(44832011)(426003)(508600001)(1076003)(81166007)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:06:21.3230 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 172569e1-1cff-4b0e-ce06-08d98a865587 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4950 Authentication-Results: imf10.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=TnRfDhD1; spf=pass (imf10.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.244.48 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: BA10E600441B X-Stat-Signature: ow57zyow1r6pu6krhnfixi4u7j6gfij6 X-HE-Tag: 1633716385-40090 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Version 2 of GHCB specification provides SNP_GUEST_REQUEST and SNP_EXT_GUEST_REQUEST NAE that can be used by the SNP guest to communicate with the PSP. While at it, add a snp_issue_guest_request() helper that can be used by driver or other subsystem to issue the request to PSP. See SEV-SNP and GHCB spec for more details. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/sev-common.h | 3 ++ arch/x86/include/asm/sev.h | 13 ++++++++ arch/x86/include/uapi/asm/svm.h | 4 +++ arch/x86/kernel/sev.c | 50 +++++++++++++++++++++++++++++++ 4 files changed, 70 insertions(+) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 45c535eb75f1..cf66600b1c68 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -128,6 +128,9 @@ struct snp_psc_desc { struct psc_entry entries[VMGEXIT_PSC_MAX_ENTRY]; } __packed; +/* Guest message request error code */ +#define SNP_GUEST_REQ_INVALID_LEN BIT_ULL(32) + #define GHCB_MSR_TERM_REQ 0x100 #define GHCB_MSR_TERM_REASON_SET_POS 12 #define GHCB_MSR_TERM_REASON_SET_MASK 0xf diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 1c58060b48b7..4ea8e2f73d37 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -80,6 +80,14 @@ extern bool handle_vc_boot_ghcb(struct pt_regs *regs); #define RMPADJUST_VMSA_PAGE_BIT BIT(16) +/* SNP Guest message request */ +struct snp_req_data { + unsigned long req_gpa; + unsigned long resp_gpa; + unsigned long data_gpa; + unsigned int data_npages; +}; + #ifdef CONFIG_AMD_MEM_ENCRYPT extern struct static_key_false sev_es_enable_key; extern void __sev_es_ist_enter(struct pt_regs *regs); @@ -129,6 +137,7 @@ void snp_set_memory_private(unsigned long vaddr, unsigned int npages); void snp_set_wakeup_secondary_cpu(void); void snp_cpuid_init_startup(struct boot_params *bp, unsigned long physaddr); void snp_cpuid_init(void); +int snp_issue_guest_request(u64 exit_code, struct snp_req_data *input, unsigned long *fw_err); #else static inline void sev_es_ist_enter(struct pt_regs *regs) { } static inline void sev_es_ist_exit(void) { } @@ -146,6 +155,10 @@ static inline void snp_set_memory_private(unsigned long vaddr, unsigned int npag static inline void snp_set_wakeup_secondary_cpu(void) { } static inline void snp_cpuid_startup(struct boot_params *bp, unsigned long physbase) { } static inline void snp_cpuid_init(void) { } +static int snp_issue_guest_request(u64 exit_code, struct snp_req_data *input, unsigned long *fw_err) +{ + return -ENOTTY; +} #endif #endif diff --git a/arch/x86/include/uapi/asm/svm.h b/arch/x86/include/uapi/asm/svm.h index 8b4c57baec52..5b8bc2b65a5e 100644 --- a/arch/x86/include/uapi/asm/svm.h +++ b/arch/x86/include/uapi/asm/svm.h @@ -109,6 +109,8 @@ #define SVM_VMGEXIT_SET_AP_JUMP_TABLE 0 #define SVM_VMGEXIT_GET_AP_JUMP_TABLE 1 #define SVM_VMGEXIT_PSC 0x80000010 +#define SVM_VMGEXIT_GUEST_REQUEST 0x80000011 +#define SVM_VMGEXIT_EXT_GUEST_REQUEST 0x80000012 #define SVM_VMGEXIT_AP_CREATION 0x80000013 #define SVM_VMGEXIT_AP_CREATE_ON_INIT 0 #define SVM_VMGEXIT_AP_CREATE 1 @@ -225,6 +227,8 @@ { SVM_VMGEXIT_AP_HLT_LOOP, "vmgexit_ap_hlt_loop" }, \ { SVM_VMGEXIT_AP_JUMP_TABLE, "vmgexit_ap_jump_table" }, \ { SVM_VMGEXIT_PSC, "vmgexit_page_state_change" }, \ + { SVM_VMGEXIT_GUEST_REQUEST, "vmgexit_guest_request" }, \ + { SVM_VMGEXIT_EXT_GUEST_REQUEST, "vmgexit_ext_guest_request" }, \ { SVM_VMGEXIT_AP_CREATION, "vmgexit_ap_creation" }, \ { SVM_VMGEXIT_HV_FEATURES, "vmgexit_hypervisor_feature" }, \ { SVM_EXIT_ERR, "invalid_guest_state" } diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 1e6152fe27ba..c29a78f868ed 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -2121,3 +2121,53 @@ static int __init snp_cpuid_check_status(void) } arch_initcall(snp_cpuid_check_status); + +int snp_issue_guest_request(u64 exit_code, struct snp_req_data *input, unsigned long *fw_err) +{ + struct ghcb_state state; + unsigned long flags; + struct ghcb *ghcb; + int ret; + + if (!cc_platform_has(CC_ATTR_SEV_SNP)) + return -ENODEV; + + local_irq_save(flags); + + ghcb = __sev_get_ghcb(&state); + if (!ghcb) { + ret = -EIO; + goto e_restore_irq; + } + + vc_ghcb_invalidate(ghcb); + + if (exit_code == SVM_VMGEXIT_EXT_GUEST_REQUEST) { + ghcb_set_rax(ghcb, input->data_gpa); + ghcb_set_rbx(ghcb, input->data_npages); + } + + ret = sev_es_ghcb_hv_call(ghcb, NULL, exit_code, input->req_gpa, input->resp_gpa); + if (ret) + goto e_put; + + if (ghcb->save.sw_exit_info_2) { + /* Number of expected pages are returned in RBX */ + if (exit_code == SVM_VMGEXIT_EXT_GUEST_REQUEST && + ghcb->save.sw_exit_info_2 == SNP_GUEST_REQ_INVALID_LEN) + input->data_npages = ghcb_get_rbx(ghcb); + + if (fw_err) + *fw_err = ghcb->save.sw_exit_info_2; + + ret = -EIO; + } + +e_put: + __sev_put_ghcb(&state); +e_restore_irq: + local_irq_restore(flags); + + return ret; +} +EXPORT_SYMBOL_GPL(snp_issue_guest_request); From patchwork Fri Oct 8 18:04:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545969 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E1C9C433FE for ; Fri, 8 Oct 2021 18:07:06 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 4000B61177 for ; Fri, 8 Oct 2021 18:07:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4000B61177 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=amd.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvack.org Received: by kanga.kvack.org (Postfix) id 7871994002A; Fri, 8 Oct 2021 14:06:28 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 737306B0073; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 39/42] x86/sev: Register SNP guest request platform device Date: Fri, 8 Oct 2021 13:04:50 -0500 Message-ID: <20211008180453.462291-40-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: db846a49-5ba8-4732-a59c-08d98a865613 X-MS-TrafficTypeDiagnostic: MWHPR12MB1197: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: pfjGfrwAlHyF1nWivcSu2kQKpsUzFvMaqbffjiBjfe6lVWbg+EyrWCYWSgFtxNc5ZJdgVI8AWS2IF2oBJtb4CmMu4Vc/XWUrXB6GweZ8dL+0r0pEenP5Qmw7t2cpwQtY6J8Sfhd1obJv8FgACOzoPm2EgE7Bo+yVS10UviVvzCSc6J2K7OA/b+32h2N5AWs2iawpr7I98QEyJ5zQLEpVzhJS0SEQ4WKnlrH6qPcaSYWjrXkjie+FQp7Fb6xluprwwgFpCN48nzFWd5MYgtl8zDHg0Hp1VPP1j5iNdpvy1xWvfJjxXuDTf8LKHxFfTlwaGXeGjmm8c3qjf2aaEJAUhWOAfP2rD3vTUZmIcsO5+IG3izXCGHtGnoduh06glOlFmuGuxiH0k6iUk5I2elUlqdZlcqMMy8xuKPO7n75JrHhTS1/M6KLrHbsCRgZ8r65+j/hUaZkGbOaaOqhYNqyziMp9r3bN1bC+N7wFSbHn2Zs86WN+P4uWIT4jYzuxRsLeqjinF/qFwj1nseQ1FlIyEh0gDvBaggac2txJJ17w2cCkLKlpuZY939f8SQ8qKlu+iI7Kq7IGRrtcZRpDJiLFYuGTvZPgQYbOE4PWjD56RFfLgGvi2Vtwj2lndTrFHLnxrZRS/pYH8suimsX2raNwKTQT5NI+QTdGp6xh5zv0JL39s8W3aa22RPFTSoz6Woywlv3BwhUxfjItUAlbIe4/Dhu10OdQhZF9zgGLbL7BX6kGLZC1e7EHtMNrcC7SnRma X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(81166007)(7406005)(7416002)(356005)(36756003)(44832011)(8676002)(2616005)(47076005)(83380400001)(36860700001)(4326008)(16526019)(26005)(82310400003)(7696005)(2906002)(70586007)(508600001)(5660300002)(316002)(70206006)(54906003)(336012)(426003)(1076003)(86362001)(6666004)(8936002)(186003)(110136005)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:06:22.2405 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: db846a49-5ba8-4732-a59c-08d98a865613 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1197 Authentication-Results: imf01.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=P0JpXPLQ; spf=pass (imf01.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.237.89 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 6C5CE5079242 X-Stat-Signature: rm7ryjpkcq519dc4sgnu4w93g58jrzep X-HE-Tag: 1633716387-879948 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Version 2 of GHCB specification provides Non Automatic Exit (NAE) that can be used by the SNP guest to communicate with the PSP without risk from a malicious hypervisor who wishes to read, alter, drop or replay the messages sent. SNP_LAUNCH_UPDATE can insert two special pages into the guest’s memory: the secrets page and the CPUID page. The PSP firmware populate the contents of the secrets page. The secrets page contains encryption keys used by the guest to interact with the firmware. Because the secrets page is encrypted with the guest’s memory encryption key, the hypervisor cannot read the keys. See SNP FW ABI spec for further details about the secrets page. Create a platform device that the SNP guest driver can bind to get the platform resources such as encryption key and message id to use to communicate with the PSP. The SNP guest driver provides a userspace interface to get the attestation report, key derivation, extended attestation report etc. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/sev.h | 4 +++ arch/x86/kernel/sev.c | 61 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 4ea8e2f73d37..2a9e6ea11242 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -88,6 +88,10 @@ struct snp_req_data { unsigned int data_npages; }; +struct snp_guest_platform_data { + u64 secrets_gpa; +}; + #ifdef CONFIG_AMD_MEM_ENCRYPT extern struct static_key_false sev_es_enable_key; extern void __sev_es_ist_enter(struct pt_regs *regs); diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index c29a78f868ed..01505ac9c7b2 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -19,6 +19,9 @@ #include #include #include +#include +#include +#include #include #include @@ -34,6 +37,7 @@ #include #include #include +#include #define DR7_RESET_VALUE 0x400 @@ -2171,3 +2175,60 @@ int snp_issue_guest_request(u64 exit_code, struct snp_req_data *input, unsigned return ret; } EXPORT_SYMBOL_GPL(snp_issue_guest_request); + +static struct platform_device guest_req_device = { + .name = "snp-guest", + .id = -1, +}; + +static u64 get_secrets_page(void) +{ + u64 pa_data = boot_params.cc_blob_address; + struct cc_blob_sev_info info; + void *map; + + /* + * The CC blob contains the address of the secrets page, check if the + * blob is present. + */ + if (!pa_data) + return 0; + + map = early_memremap(pa_data, sizeof(info)); + memcpy(&info, map, sizeof(info)); + early_memunmap(map, sizeof(info)); + + /* smoke-test the secrets page passed */ + if (!info.secrets_phys || info.secrets_len != PAGE_SIZE) + return 0; + + return info.secrets_phys; +} + +static int __init init_snp_platform_device(void) +{ + struct snp_guest_platform_data data; + u64 gpa; + + if (!cc_platform_has(CC_ATTR_SEV_SNP)) + return -ENODEV; + + gpa = get_secrets_page(); + if (!gpa) + return -ENODEV; + + data.secrets_gpa = gpa; + if (platform_device_add_data(&guest_req_device, &data, sizeof(data))) + goto e_fail; + + if (platform_device_register(&guest_req_device)) + goto e_fail; + + pr_info("SNP guest platform device initialized.\n"); + return 0; + +e_fail: + pr_err("Failed to initialize SNP guest device\n"); + return -ENODEV; +} +device_initcall(init_snp_platform_device); From patchwork Fri Oct 8 18:04:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C411CC433EF for ; Fri, 8 Oct 2021 18:07:00 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 587A6610E7 for ; Fri, 8 Oct 2021 18:07:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 587A6610E7 Authentication-Results: mail.kernel.org; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 40/42] virt: Add SEV-SNP guest driver Date: Fri, 8 Oct 2021 13:04:51 -0500 Message-ID: <20211008180453.462291-41-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b0273da8-d985-4171-a29e-08d98a865619 X-MS-TrafficTypeDiagnostic: DM6PR12MB4401: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3631; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gC2S6z9l3zxhkg29j2BZcS5ALwXFnc8BTKGs3RrLqN/rQBlAGexdua6McHebu2WdwnHP9AvKl4Bxb+T5r1o/wUR8DQPnjtlyROdcMlqf/zu21Tj8dndrLNEoGOGkP9AQ1doE0HQ0f1y2SlqeWvh2S66fVgk+vZsBQzaO0Ng/ETB237lD1DzZAFIeTtSWydP/F/aJfBw7KoVzQgPGVeRgGq/UPLEajSQdm5rVWPryxt+PHn63nEq/2tBfHNaRbjEOdMYtuM17HWLrlFkpYosa0so6JjZX6/I4785shmi6/7X2MOmLNzJNZ1vBFDCUXoqSbqzvXPIY9iheGLF6FIo8D7HSdNLIYKQHRbsAfNRxlZjD8ow36nZI9wPCyOsoQAvOeaPvxkxCbG6ZoQd6V9fOKuFhRUIm6rRehNuMQ2e3A4pt/T4CT1AouSE7IWcSkahOqnO76OitUhXKIBOm9wy0LD8UzloWOAi/9nnbjFyFnbinRZFGVmYcVcd6yC7ipZDUa+W3YbeyrRqrms0agAKUv4p4vVVNVC2wMV2p3WrvSdWiq0LpjdENafHmhnoVf/cBOZ9iALbaDnRQlWmTQch5/t4oXtLtRn3bqf6Y66/j0/IZ67sHhUjiYaqwiVsnD0KhUUmqQ5ST6W/w0+Dfc84y+KJllHgN5HCpa61JacwN9eLqn84paITqQi2fcWauVSP+yprA5G4cKYqE6QcmreyMz7OZoJ15YCaQcVJ4ly99gesUbF42Zj8tBd2U9IhB/W71dBmZEKsi2Q9iLviiD79UFIkO8YlppUNzwiRNJSFC25MBsg4zJBPuY9SRcpXrvF48fiTBQ8N+u5lilcKuBy0wiA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(30864003)(70206006)(70586007)(82310400003)(36860700001)(1076003)(86362001)(47076005)(81166007)(36756003)(356005)(44832011)(966005)(426003)(5660300002)(2616005)(186003)(16526019)(508600001)(4326008)(336012)(6666004)(316002)(54906003)(110136005)(2906002)(83380400001)(8676002)(7406005)(7416002)(26005)(7696005)(8936002)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:06:22.2878 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b0273da8-d985-4171-a29e-08d98a865619 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4401 X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: 2D358D0005CF X-Stat-Signature: nsenax6b4gc35iu574afw1ce6mi93buw Authentication-Results: imf15.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=PjJjmrJB; dmarc=pass (policy=quarantine) header.from=amd.com; spf=pass (imf15.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.243.83 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com X-HE-Tag: 1633716386-549155 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: SEV-SNP specification provides the guest a mechanisum to communicate with the PSP without risk from a malicious hypervisor who wishes to read, alter, drop or replay the messages sent. The driver uses snp_issue_guest_request() to issue GHCB SNP_GUEST_REQUEST or SNP_EXT_GUEST_REQUEST NAE events to submit the request to PSP. The PSP requires that all communication should be encrypted using key specified through the platform_data. The userspace can use SNP_GET_REPORT ioctl() to query the guest attestation report. See SEV-SNP spec section Guest Messages for more details. Signed-off-by: Brijesh Singh --- Documentation/virt/coco/sevguest.rst | 77 ++++ drivers/virt/Kconfig | 3 + drivers/virt/Makefile | 1 + drivers/virt/coco/sevguest/Kconfig | 9 + drivers/virt/coco/sevguest/Makefile | 2 + drivers/virt/coco/sevguest/sevguest.c | 561 ++++++++++++++++++++++++++ drivers/virt/coco/sevguest/sevguest.h | 98 +++++ include/uapi/linux/sev-guest.h | 44 ++ 8 files changed, 795 insertions(+) create mode 100644 Documentation/virt/coco/sevguest.rst create mode 100644 drivers/virt/coco/sevguest/Kconfig create mode 100644 drivers/virt/coco/sevguest/Makefile create mode 100644 drivers/virt/coco/sevguest/sevguest.c create mode 100644 drivers/virt/coco/sevguest/sevguest.h create mode 100644 include/uapi/linux/sev-guest.h diff --git a/Documentation/virt/coco/sevguest.rst b/Documentation/virt/coco/sevguest.rst new file mode 100644 index 000000000000..002c90946b8a --- /dev/null +++ b/Documentation/virt/coco/sevguest.rst @@ -0,0 +1,77 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=================================================================== +The Definitive SEV Guest API Documentation +=================================================================== + +1. General description +====================== + +The SEV API is a set of ioctls that are used by the guest or hypervisor +to get or set certain aspect of the SEV virtual machine. The ioctls belong +to the following classes: + + - Hypervisor ioctls: These query and set global attributes which affect the + whole SEV firmware. These ioctl are used by platform provision tools. + + - Guest ioctls: These query and set attributes of the SEV virtual machine. + +2. API description +================== + +This section describes ioctls that can be used to query or set SEV guests. +For each ioctl, the following information is provided along with a +description: + + Technology: + which SEV techology provides this ioctl. sev, sev-es, sev-snp or all. + + Type: + hypervisor or guest. The ioctl can be used inside the guest or the + hypervisor. + + Parameters: + what parameters are accepted by the ioctl. + + Returns: + the return value. General error numbers (ENOMEM, EINVAL) + are not detailed, but errors with specific meanings are. + +The guest ioctl should be issued on a file descriptor of the /dev/sev-guest device. +The ioctl accepts struct snp_user_guest_request. The input and output structure is +specified through the req_data and resp_data field respectively. If the ioctl fails +to execute due to a firmware error, then fw_err code will be set. + +:: + struct snp_guest_request_ioctl { + /* Request and response structure address */ + __u64 req_data; + __u64 resp_data; + + /* firmware error code on failure (see psp-sev.h) */ + __u64 fw_err; + }; + +2.1 SNP_GET_REPORT +------------------ + +:Technology: sev-snp +:Type: guest ioctl +:Parameters (in): struct snp_report_req +:Returns (out): struct snp_report_resp on success, -negative on error + +The SNP_GET_REPORT ioctl can be used to query the attestation report from the +SEV-SNP firmware. The ioctl uses the SNP_GUEST_REQUEST (MSG_REPORT_REQ) command +provided by the SEV-SNP firmware to query the attestation report. + +On success, the snp_report_resp.data will contains the report. The report +will contain the format described in the SEV-SNP specification. See the SEV-SNP +specification for further details. + + +Reference +--------- + +SEV-SNP and GHCB specification: developer.amd.com/sev + +The driver is based on SEV-SNP firmware spec 0.9 and GHCB spec version 2.0. diff --git a/drivers/virt/Kconfig b/drivers/virt/Kconfig index 8061e8ef449f..e457e47610d3 100644 --- a/drivers/virt/Kconfig +++ b/drivers/virt/Kconfig @@ -36,4 +36,7 @@ source "drivers/virt/vboxguest/Kconfig" source "drivers/virt/nitro_enclaves/Kconfig" source "drivers/virt/acrn/Kconfig" + +source "drivers/virt/coco/sevguest/Kconfig" + endif diff --git a/drivers/virt/Makefile b/drivers/virt/Makefile index 3e272ea60cd9..9c704a6fdcda 100644 --- a/drivers/virt/Makefile +++ b/drivers/virt/Makefile @@ -8,3 +8,4 @@ obj-y += vboxguest/ obj-$(CONFIG_NITRO_ENCLAVES) += nitro_enclaves/ obj-$(CONFIG_ACRN_HSM) += acrn/ +obj-$(CONFIG_SEV_GUEST) += coco/sevguest/ diff --git a/drivers/virt/coco/sevguest/Kconfig b/drivers/virt/coco/sevguest/Kconfig new file mode 100644 index 000000000000..96190919cca8 --- /dev/null +++ b/drivers/virt/coco/sevguest/Kconfig @@ -0,0 +1,9 @@ +config SEV_GUEST + tristate "AMD SEV Guest driver" + default y + depends on AMD_MEM_ENCRYPT && CRYPTO_AEAD2 + help + The driver can be used by the SEV-SNP guest to communicate with the PSP to + request the attestation report and more. + + If you choose 'M' here, this module will be called sevguest. diff --git a/drivers/virt/coco/sevguest/Makefile b/drivers/virt/coco/sevguest/Makefile new file mode 100644 index 000000000000..b1ffb2b4177b --- /dev/null +++ b/drivers/virt/coco/sevguest/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_SEV_GUEST) += sevguest.o diff --git a/drivers/virt/coco/sevguest/sevguest.c b/drivers/virt/coco/sevguest/sevguest.c new file mode 100644 index 000000000000..2d313fb2ffae --- /dev/null +++ b/drivers/virt/coco/sevguest/sevguest.c @@ -0,0 +1,561 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AMD Secure Encrypted Virtualization Nested Paging (SEV-SNP) guest request interface + * + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Author: Brijesh Singh + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "sevguest.h" + +#define DEVICE_NAME "sev-guest" +#define AAD_LEN 48 +#define MSG_HDR_VER 1 + +struct snp_guest_crypto { + struct crypto_aead *tfm; + u8 *iv, *authtag; + int iv_len, a_len; +}; + +struct snp_guest_dev { + struct device *dev; + struct miscdevice misc; + + struct snp_guest_crypto *crypto; + struct snp_guest_msg *request, *response; + struct snp_secrets_page_layout *layout; + struct snp_req_data input; + u32 *os_area_msg_seqno; +}; + +static u32 vmpck_id; +module_param(vmpck_id, uint, 0444); +MODULE_PARM_DESC(vmpck_id, "The VMPCK ID to use when communicating with the PSP."); + +static DEFINE_MUTEX(snp_cmd_mutex); + +static inline u64 __snp_get_msg_seqno(struct snp_guest_dev *snp_dev) +{ + u64 count; + + /* Read the current message sequence counter from secrets pages */ + count = *snp_dev->os_area_msg_seqno; + + return count + 1; +} + +/* Return a non-zero on success */ +static u64 snp_get_msg_seqno(struct snp_guest_dev *snp_dev) +{ + u64 count = __snp_get_msg_seqno(snp_dev); + + /* + * The message sequence counter for the SNP guest request is a 64-bit + * value but the version 2 of GHCB specification defines a 32-bit storage + * for the it. If the counter exceeds the 32-bit value then return zero. + * The caller should check the return value, but if the caller happen to + * not check the value and use it, then the firmware treats zero as an + * invalid number and will fail the message request. + */ + if (count >= UINT_MAX) { + pr_err_ratelimited("SNP guest request message sequence counter overflow\n"); + return 0; + } + + return count; +} + +static void snp_inc_msg_seqno(struct snp_guest_dev *snp_dev) +{ + /* + * The counter is also incremented by the PSP, so increment it by 2 + * and save in secrets page. + */ + *snp_dev->os_area_msg_seqno += 2; +} + +static inline struct snp_guest_dev *to_snp_dev(struct file *file) +{ + struct miscdevice *dev = file->private_data; + + return container_of(dev, struct snp_guest_dev, misc); +} + +static struct snp_guest_crypto *init_crypto(struct snp_guest_dev *snp_dev, u8 *key, size_t keylen) +{ + struct snp_guest_crypto *crypto; + + crypto = kzalloc(sizeof(*crypto), GFP_KERNEL_ACCOUNT); + if (!crypto) + return NULL; + + crypto->tfm = crypto_alloc_aead("gcm(aes)", 0, 0); + if (IS_ERR(crypto->tfm)) + goto e_free; + + if (crypto_aead_setkey(crypto->tfm, key, keylen)) + goto e_free_crypto; + + crypto->iv_len = crypto_aead_ivsize(crypto->tfm); + if (crypto->iv_len < 12) { + dev_err(snp_dev->dev, "IV length is less than 12.\n"); + goto e_free_crypto; + } + + crypto->iv = kmalloc(crypto->iv_len, GFP_KERNEL_ACCOUNT); + if (!crypto->iv) + goto e_free_crypto; + + if (crypto_aead_authsize(crypto->tfm) > MAX_AUTHTAG_LEN) { + if (crypto_aead_setauthsize(crypto->tfm, MAX_AUTHTAG_LEN)) { + dev_err(snp_dev->dev, "failed to set authsize to %d\n", MAX_AUTHTAG_LEN); + goto e_free_crypto; + } + } + + crypto->a_len = crypto_aead_authsize(crypto->tfm); + crypto->authtag = kmalloc(crypto->a_len, GFP_KERNEL_ACCOUNT); + if (!crypto->authtag) + goto e_free_crypto; + + return crypto; + +e_free_crypto: + crypto_free_aead(crypto->tfm); +e_free: + kfree(crypto->iv); + kfree(crypto->authtag); + kfree(crypto); + + return NULL; +} + +static void deinit_crypto(struct snp_guest_crypto *crypto) +{ + crypto_free_aead(crypto->tfm); + kfree(crypto->iv); + kfree(crypto->authtag); + kfree(crypto); +} + +static int enc_dec_message(struct snp_guest_crypto *crypto, struct snp_guest_msg *msg, + u8 *src_buf, u8 *dst_buf, size_t len, bool enc) +{ + struct snp_guest_msg_hdr *hdr = &msg->hdr; + struct scatterlist src[3], dst[3]; + DECLARE_CRYPTO_WAIT(wait); + struct aead_request *req; + int ret; + + req = aead_request_alloc(crypto->tfm, GFP_KERNEL); + if (!req) + return -ENOMEM; + + /* + * AEAD memory operations: + * +------ AAD -------+------- DATA -----+---- AUTHTAG----+ + * | msg header | plaintext | hdr->authtag | + * | bytes 30h - 5Fh | or | | + * | | cipher | | + * +------------------+------------------+----------------+ + */ + sg_init_table(src, 3); + sg_set_buf(&src[0], &hdr->algo, AAD_LEN); + sg_set_buf(&src[1], src_buf, hdr->msg_sz); + sg_set_buf(&src[2], hdr->authtag, crypto->a_len); + + sg_init_table(dst, 3); + sg_set_buf(&dst[0], &hdr->algo, AAD_LEN); + sg_set_buf(&dst[1], dst_buf, hdr->msg_sz); + sg_set_buf(&dst[2], hdr->authtag, crypto->a_len); + + aead_request_set_ad(req, AAD_LEN); + aead_request_set_tfm(req, crypto->tfm); + aead_request_set_callback(req, 0, crypto_req_done, &wait); + + aead_request_set_crypt(req, src, dst, len, crypto->iv); + ret = crypto_wait_req(enc ? crypto_aead_encrypt(req) : crypto_aead_decrypt(req), &wait); + + aead_request_free(req); + return ret; +} + +static int __enc_payload(struct snp_guest_dev *snp_dev, struct snp_guest_msg *msg, + void *plaintext, size_t len) +{ + struct snp_guest_crypto *crypto = snp_dev->crypto; + struct snp_guest_msg_hdr *hdr = &msg->hdr; + + memset(crypto->iv, 0, crypto->iv_len); + memcpy(crypto->iv, &hdr->msg_seqno, sizeof(hdr->msg_seqno)); + + return enc_dec_message(crypto, msg, plaintext, msg->payload, len, true); +} + +static int dec_payload(struct snp_guest_dev *snp_dev, struct snp_guest_msg *msg, + void *plaintext, size_t len) +{ + struct snp_guest_crypto *crypto = snp_dev->crypto; + struct snp_guest_msg_hdr *hdr = &msg->hdr; + + /* Build IV with response buffer sequence number */ + memset(crypto->iv, 0, crypto->iv_len); + memcpy(crypto->iv, &hdr->msg_seqno, sizeof(hdr->msg_seqno)); + + return enc_dec_message(crypto, msg, msg->payload, plaintext, len, false); +} + +static int verify_and_dec_payload(struct snp_guest_dev *snp_dev, void *payload, u32 sz) +{ + struct snp_guest_crypto *crypto = snp_dev->crypto; + struct snp_guest_msg *resp = snp_dev->response; + struct snp_guest_msg *req = snp_dev->request; + struct snp_guest_msg_hdr *req_hdr = &req->hdr; + struct snp_guest_msg_hdr *resp_hdr = &resp->hdr; + + dev_dbg(snp_dev->dev, "response [seqno %lld type %d version %d sz %d]\n", + resp_hdr->msg_seqno, resp_hdr->msg_type, resp_hdr->msg_version, resp_hdr->msg_sz); + + /* Verify that the sequence counter is incremented by 1 */ + if (unlikely(resp_hdr->msg_seqno != (req_hdr->msg_seqno + 1))) + return -EBADMSG; + + /* Verify response message type and version number. */ + if (resp_hdr->msg_type != (req_hdr->msg_type + 1) || + resp_hdr->msg_version != req_hdr->msg_version) + return -EBADMSG; + + /* + * If the message size is greater than our buffer length then return + * an error. + */ + if (unlikely((resp_hdr->msg_sz + crypto->a_len) > sz)) + return -EBADMSG; + + return dec_payload(snp_dev, resp, payload, resp_hdr->msg_sz + crypto->a_len); +} + +static bool enc_payload(struct snp_guest_dev *snp_dev, u64 seqno, int version, u8 type, + void *payload, size_t sz) +{ + struct snp_guest_msg *req = snp_dev->request; + struct snp_guest_msg_hdr *hdr = &req->hdr; + + memset(req, 0, sizeof(*req)); + + hdr->algo = SNP_AEAD_AES_256_GCM; + hdr->hdr_version = MSG_HDR_VER; + hdr->hdr_sz = sizeof(*hdr); + hdr->msg_type = type; + hdr->msg_version = version; + hdr->msg_seqno = seqno; + hdr->msg_vmpck = vmpck_id; + hdr->msg_sz = sz; + + /* Verify the sequence number is non-zero */ + if (!hdr->msg_seqno) + return -ENOSR; + + dev_dbg(snp_dev->dev, "request [seqno %lld type %d version %d sz %d]\n", + hdr->msg_seqno, hdr->msg_type, hdr->msg_version, hdr->msg_sz); + + return __enc_payload(snp_dev, req, payload, sz); +} + +static int handle_guest_request(struct snp_guest_dev *snp_dev, u64 exit_code, int msg_ver, + u8 type, void *req_buf, size_t req_sz, void *resp_buf, + u32 resp_sz, __u64 *fw_err) +{ + unsigned long err; + u64 seqno; + int rc; + + /* Get message sequence and verify that its a non-zero */ + seqno = snp_get_msg_seqno(snp_dev); + if (!seqno) + return -EIO; + + memset(snp_dev->response, 0, sizeof(*snp_dev->response)); + + /* Encrypt the userspace provided payload */ + rc = enc_payload(snp_dev, seqno, msg_ver, type, req_buf, req_sz); + if (rc) + return rc; + + /* Call firmware to process the request */ + rc = snp_issue_guest_request(exit_code, &snp_dev->input, &err); + if (fw_err) + *fw_err = err; + + if (rc) + return rc; + + rc = verify_and_dec_payload(snp_dev, resp_buf, resp_sz); + if (rc) + return rc; + + /* Increment to new message sequence after the command is successful. */ + snp_inc_msg_seqno(snp_dev); + + return 0; +} + +static int get_report(struct snp_guest_dev *snp_dev, struct snp_guest_request_ioctl *arg) +{ + struct snp_guest_crypto *crypto = snp_dev->crypto; + struct snp_report_resp *resp; + struct snp_report_req req; + int rc, resp_len; + + if (!arg->req_data || !arg->resp_data) + return -EINVAL; + + /* Copy the request payload from userspace */ + if (copy_from_user(&req, (void __user *)arg->req_data, sizeof(req))) + return -EFAULT; + + /* Message version must be non-zero */ + if (!req.msg_version) + return -EINVAL; + + /* + * The intermediate response buffer is used while decrypting the + * response payload. Make sure that it has enough space to cover the + * authtag. + */ + resp_len = sizeof(resp->data) + crypto->a_len; + resp = kzalloc(resp_len, GFP_KERNEL_ACCOUNT); + if (!resp) + return -ENOMEM; + + /* Issue the command to get the attestation report */ + rc = handle_guest_request(snp_dev, SVM_VMGEXIT_GUEST_REQUEST, req.msg_version, + SNP_MSG_REPORT_REQ, &req.user_data, sizeof(req.user_data), + resp->data, resp_len, &arg->fw_err); + if (rc) + goto e_free; + + /* Copy the response payload to userspace */ + if (copy_to_user((void __user *)arg->resp_data, resp, sizeof(*resp))) + rc = -EFAULT; + +e_free: + kfree(resp); + return rc; +} + +static long snp_guest_ioctl(struct file *file, unsigned int ioctl, unsigned long arg) +{ + struct snp_guest_dev *snp_dev = to_snp_dev(file); + void __user *argp = (void __user *)arg; + struct snp_guest_request_ioctl input; + int ret = -ENOTTY; + + if (copy_from_user(&input, argp, sizeof(input))) + return -EFAULT; + + input.fw_err = 0; + + mutex_lock(&snp_cmd_mutex); + + switch (ioctl) { + case SNP_GET_REPORT: + ret = get_report(snp_dev, &input); + break; + default: + break; + } + + mutex_unlock(&snp_cmd_mutex); + + if (input.fw_err && copy_to_user(argp, &input, sizeof(input))) + return -EFAULT; + + return ret; +} + +static void free_shared_pages(void *buf, size_t sz) +{ + unsigned int npages = PAGE_ALIGN(sz) >> PAGE_SHIFT; + + if (!buf) + return; + + /* If fail to restore the encryption mask then leak it. */ + if (WARN_ONCE(set_memory_encrypted((unsigned long)buf, npages), + "Failed to restore encryption mask (leak it)\n")) + return; + + __free_pages(virt_to_page(buf), get_order(sz)); +} + +static void *alloc_shared_pages(size_t sz) +{ + unsigned int npages = PAGE_ALIGN(sz) >> PAGE_SHIFT; + struct page *page; + int ret; + + page = alloc_pages(GFP_KERNEL_ACCOUNT, get_order(sz)); + if (IS_ERR(page)) + return NULL; + + ret = set_memory_decrypted((unsigned long)page_address(page), npages); + if (ret) { + pr_err("SEV-SNP: failed to mark page shared, ret=%d\n", ret); + __free_pages(page, get_order(sz)); + return NULL; + } + + return page_address(page); +} + +static const struct file_operations snp_guest_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = snp_guest_ioctl, +}; + +static u8 *get_vmpck(int id, struct snp_secrets_page_layout *layout, u32 **seqno) +{ + u8 *key = NULL; + + switch (id) { + case 0: + *seqno = &layout->os_area.msg_seqno_0; + key = layout->vmpck0; + break; + case 1: + *seqno = &layout->os_area.msg_seqno_1; + key = layout->vmpck1; + break; + case 2: + *seqno = &layout->os_area.msg_seqno_2; + key = layout->vmpck2; + break; + case 3: + *seqno = &layout->os_area.msg_seqno_3; + key = layout->vmpck3; + break; + default: + break; + } + + return NULL; +} + +static int __init snp_guest_probe(struct platform_device *pdev) +{ + struct snp_secrets_page_layout *layout; + struct snp_guest_platform_data *data; + struct device *dev = &pdev->dev; + struct snp_guest_dev *snp_dev; + struct miscdevice *misc; + u8 *vmpck; + int ret; + + if (!dev->platform_data) + return -ENODEV; + + data = (struct snp_guest_platform_data *)dev->platform_data; + layout = (__force void *)ioremap_encrypted(data->secrets_gpa, PAGE_SIZE); + if (!layout) + return -ENODEV; + + ret = -ENOMEM; + snp_dev = devm_kzalloc(&pdev->dev, sizeof(struct snp_guest_dev), GFP_KERNEL); + if (!snp_dev) + goto e_fail; + + ret = -EINVAL; + vmpck = get_vmpck(vmpck_id, layout, &snp_dev->os_area_msg_seqno); + if (!vmpck) { + dev_err(dev, "invalid vmpck id %d\n", vmpck_id); + goto e_fail; + } + + platform_set_drvdata(pdev, snp_dev); + snp_dev->dev = dev; + snp_dev->layout = layout; + + /* Allocate the shared page used for the request and response message. */ + snp_dev->request = alloc_shared_pages(sizeof(struct snp_guest_msg)); + if (!snp_dev->request) + goto e_fail; + + snp_dev->response = alloc_shared_pages(sizeof(struct snp_guest_msg)); + if (!snp_dev->response) + goto e_fail; + + ret = -EIO; + snp_dev->crypto = init_crypto(snp_dev, vmpck, VMPCK_KEY_LEN); + if (!snp_dev->crypto) + goto e_fail; + + misc = &snp_dev->misc; + misc->minor = MISC_DYNAMIC_MINOR; + misc->name = DEVICE_NAME; + misc->fops = &snp_guest_fops; + + /* initial the input address for guest request */ + snp_dev->input.req_gpa = __pa(snp_dev->request); + snp_dev->input.resp_gpa = __pa(snp_dev->response); + + ret = misc_register(misc); + if (ret) + goto e_fail; + + dev_dbg(dev, "Initialized SNP guest driver (using vmpck_id %d)\n", vmpck_id); + return 0; + +e_fail: + iounmap(layout); + free_shared_pages(snp_dev->request, sizeof(struct snp_guest_msg)); + free_shared_pages(snp_dev->response, sizeof(struct snp_guest_msg)); + + return ret; +} + +static int __exit snp_guest_remove(struct platform_device *pdev) +{ + struct snp_guest_dev *snp_dev = platform_get_drvdata(pdev); + + free_shared_pages(snp_dev->request, sizeof(struct snp_guest_msg)); + free_shared_pages(snp_dev->response, sizeof(struct snp_guest_msg)); + deinit_crypto(snp_dev->crypto); + misc_deregister(&snp_dev->misc); + + return 0; +} + +static struct platform_driver snp_guest_driver = { + .remove = __exit_p(snp_guest_remove), + .driver = { + .name = "snp-guest", + }, +}; + +module_platform_driver_probe(snp_guest_driver, snp_guest_probe); + +MODULE_AUTHOR("Brijesh Singh "); +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0.0"); +MODULE_DESCRIPTION("AMD SNP Guest Driver"); diff --git a/drivers/virt/coco/sevguest/sevguest.h b/drivers/virt/coco/sevguest/sevguest.h new file mode 100644 index 000000000000..cfa76cf8a21a --- /dev/null +++ b/drivers/virt/coco/sevguest/sevguest.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Author: Brijesh Singh + * + * SEV-SNP API spec is available at https://developer.amd.com/sev + */ + +#ifndef __LINUX_SEVGUEST_H_ +#define __LINUX_SEVGUEST_H_ + +#include + +#define MAX_AUTHTAG_LEN 32 + +/* See SNP spec SNP_GUEST_REQUEST section for the structure */ +enum msg_type { + SNP_MSG_TYPE_INVALID = 0, + SNP_MSG_CPUID_REQ, + SNP_MSG_CPUID_RSP, + SNP_MSG_KEY_REQ, + SNP_MSG_KEY_RSP, + SNP_MSG_REPORT_REQ, + SNP_MSG_REPORT_RSP, + SNP_MSG_EXPORT_REQ, + SNP_MSG_EXPORT_RSP, + SNP_MSG_IMPORT_REQ, + SNP_MSG_IMPORT_RSP, + SNP_MSG_ABSORB_REQ, + SNP_MSG_ABSORB_RSP, + SNP_MSG_VMRK_REQ, + SNP_MSG_VMRK_RSP, + + SNP_MSG_TYPE_MAX +}; + +enum aead_algo { + SNP_AEAD_INVALID, + SNP_AEAD_AES_256_GCM, +}; + +struct snp_guest_msg_hdr { + u8 authtag[MAX_AUTHTAG_LEN]; + u64 msg_seqno; + u8 rsvd1[8]; + u8 algo; + u8 hdr_version; + u16 hdr_sz; + u8 msg_type; + u8 msg_version; + u16 msg_sz; + u32 rsvd2; + u8 msg_vmpck; + u8 rsvd3[35]; +} __packed; + +struct snp_guest_msg { + struct snp_guest_msg_hdr hdr; + u8 payload[4000]; +} __packed; + +/* + * The secrets page contains 96-bytes of reserved field that can be used by + * the guest OS. The guest OS uses the area to save the message sequence + * number for each VMPCK. + * + * See the GHCB spec section Secret page layout for the format for this area. + */ +struct secrets_os_area { + u32 msg_seqno_0; + u32 msg_seqno_1; + u32 msg_seqno_2; + u32 msg_seqno_3; + u64 ap_jump_table_pa; + u8 rsvd[40]; + u8 guest_usage[32]; +} __packed; + +#define VMPCK_KEY_LEN 32 + +/* See the SNP spec version 0.9 for secrets page format */ +struct snp_secrets_page_layout { + u32 version; + u32 imien : 1, + rsvd1 : 31; + u32 fms; + u32 rsvd2; + u8 gosvw[16]; + u8 vmpck0[VMPCK_KEY_LEN]; + u8 vmpck1[VMPCK_KEY_LEN]; + u8 vmpck2[VMPCK_KEY_LEN]; + u8 vmpck3[VMPCK_KEY_LEN]; + struct secrets_os_area os_area; + u8 rsvd3[3840]; +} __packed; + +#endif /* __LINUX_SNP_GUEST_H__ */ diff --git a/include/uapi/linux/sev-guest.h b/include/uapi/linux/sev-guest.h new file mode 100644 index 000000000000..eda7edcffda8 --- /dev/null +++ b/include/uapi/linux/sev-guest.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Userspace interface for AMD SEV and SEV-SNP guest driver. + * + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Author: Brijesh Singh + * + * SEV API specification is available at: https://developer.amd.com/sev/ + */ + +#ifndef __UAPI_LINUX_SEV_GUEST_H_ +#define __UAPI_LINUX_SEV_GUEST_H_ + +#include + +struct snp_report_req { + /* message version number (must be non-zero) */ + __u8 msg_version; + + /* user data that should be included in the report */ + __u8 user_data[64]; +}; + +struct snp_report_resp { + /* response data, see SEV-SNP spec for the format */ + __u8 data[4000]; +}; + +struct snp_guest_request_ioctl { + /* Request and response structure address */ + __u64 req_data; + __u64 resp_data; + + /* firmware error code on failure (see psp-sev.h) */ + __u64 fw_err; +}; + +#define SNP_GUEST_REQ_IOC_TYPE 'S' + +/* Get SNP attestation report */ +#define SNP_GET_REPORT _IOWR(SNP_GUEST_REQ_IOC_TYPE, 0x0, struct snp_guest_request_ioctl) + +#endif /* __UAPI_LINUX_SEV_GUEST_H_ */ From patchwork Fri Oct 8 18:04:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12545967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2B4CC433F5 for ; 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Fri, 8 Oct 2021 13:06:20 -0500 From: Brijesh Singh To: , , , , , , CC: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , "Vitaly Kuznetsov" , Jim Mattson , "Andy Lutomirski" , Dave Hansen , Sergio Lopez , Peter Gonda , "Peter Zijlstra" , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , "Dr . David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 41/42] virt: sevguest: Add support to derive key Date: Fri, 8 Oct 2021 13:04:52 -0500 Message-ID: <20211008180453.462291-42-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5c329cc3-113b-4fff-5ee0-08d98a86567d X-MS-TrafficTypeDiagnostic: MN2PR12MB4472: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2582; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZqxCwVyuXtfdMLiSleUhxX90w0agzCZjqgrBsNyQ8g/Rh5jGpB8z6ukGxG1mvREAPEMZXgA9lxfWxNes09VjyPC1v8ZA8ag+QACusXkFhT0lioDlwDu+TMWl+SNFAiIfh+KAUA12mqSaclb5wEwe9Dn9kl5p/MZpn3AAB5b8Evk/4MLsdpOytocfVzRUg02M7PvOBzks1AUFUe/9QspeaGcZis44vU/SlkXDnVd6PwJj21kHcZYAdiX7/UGzeNuKq5oW1MGRNzFLMkRgLrwl1n2J73ELVLBKTqZVM+WvH9pXo9rpJ8K8yRfOXREABo5Xx/hkfm3RLsHYBt6wduokXmXVvgz6y+puCTzgUpHg40/tRuckTMweOT4L0Hg7z9NEeY2OTgu0sYFpJ5LEVuo+uq7B+4EGhQO6PZAvnNcLTzVtqKTJ8CQ+BY3I+cQ8YNRgj1aQspfBR4k9cm98qu5aVYhQDvH5Ak6HvQ6jqA3RprlJ6kplJpNkK1GMMANAvQd4W82W+9trndeb4ifl320Gakug7+B6rfK1VI4KURhEdxo12pDL5iobrTN5BcfKsDZR7znOAQgaY+MRY4/21dmK3Dsj86oz+l90wkZP0tYvvf9YXMB+dUcezjhiqSwVHgPJc/8+ideVF1iCz3OsFQMyP/7D/HEm4U1P3ScXrRa+MTmLwivnKUjxKrVYzC/bhiS0ZpAtH0EDbUUMi/VukqHorCtasI7fq2JBcXFB4F3B8AYsRUURuCKaXeWnClZ5tNsm X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(2906002)(36860700001)(186003)(5660300002)(70586007)(70206006)(86362001)(26005)(8676002)(4326008)(47076005)(7696005)(36756003)(83380400001)(16526019)(2616005)(7416002)(8936002)(81166007)(426003)(316002)(508600001)(1076003)(7406005)(356005)(336012)(110136005)(54906003)(6666004)(82310400003)(44832011)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:06:22.9394 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c329cc3-113b-4fff-5ee0-08d98a86567d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4472 Authentication-Results: imf11.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=bjtPN5q5; spf=pass (imf11.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.237.79 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 23A80F002856 X-Stat-Signature: 59jrkkph6jk8tq6ao5ne6rsinwu31yma X-HE-Tag: 1633716387-267024 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: The SNP_GET_DERIVED_KEY ioctl interface can be used by the SNP guest to ask the firmware to provide a key derived from a root key. The derived key may be used by the guest for any purposes it choose, such as a sealing key or communicating with the external entities. See SEV-SNP firmware spec for more information. Signed-off-by: Brijesh Singh --- Documentation/virt/coco/sevguest.rst | 19 ++++++++++- drivers/virt/coco/sevguest/sevguest.c | 49 +++++++++++++++++++++++++++ include/uapi/linux/sev-guest.h | 24 +++++++++++++ 3 files changed, 91 insertions(+), 1 deletion(-) diff --git a/Documentation/virt/coco/sevguest.rst b/Documentation/virt/coco/sevguest.rst index 002c90946b8a..4b524d1de37c 100644 --- a/Documentation/virt/coco/sevguest.rst +++ b/Documentation/virt/coco/sevguest.rst @@ -64,10 +64,27 @@ The SNP_GET_REPORT ioctl can be used to query the attestation report from the SEV-SNP firmware. The ioctl uses the SNP_GUEST_REQUEST (MSG_REPORT_REQ) command provided by the SEV-SNP firmware to query the attestation report. -On success, the snp_report_resp.data will contains the report. The report +On success, the snp_report_resp.data will contain the report. The report will contain the format described in the SEV-SNP specification. See the SEV-SNP specification for further details. +2.2 SNP_GET_DERIVED_KEY +----------------------- +:Technology: sev-snp +:Type: guest ioctl +:Parameters (in): struct snp_derived_key_req +:Returns (out): struct snp_derived_key_req on success, -negative on error + +The SNP_GET_DERIVED_KEY ioctl can be used to get a key derive from a root key. +The derived key can be used by the guest for any purpose, such as sealing keys +or communicating with external entities. + +The ioctl uses the SNP_GUEST_REQUEST (MSG_KEY_REQ) command provided by the +SEV-SNP firmware to derive the key. See SEV-SNP specification for further details +on the various fileds passed in the key derivation request. + +On success, the snp_derived_key_resp.data will contains the derived key value. See +the SEV-SNP specification for further details. Reference --------- diff --git a/drivers/virt/coco/sevguest/sevguest.c b/drivers/virt/coco/sevguest/sevguest.c index 2d313fb2ffae..c6ca7d861a3a 100644 --- a/drivers/virt/coco/sevguest/sevguest.c +++ b/drivers/virt/coco/sevguest/sevguest.c @@ -364,6 +364,52 @@ static int get_report(struct snp_guest_dev *snp_dev, struct snp_guest_request_io return rc; } +static int get_derived_key(struct snp_guest_dev *snp_dev, struct snp_guest_request_ioctl *arg) +{ + struct snp_guest_crypto *crypto = snp_dev->crypto; + struct snp_derived_key_resp resp = {0}; + struct snp_derived_key_req req; + int rc, resp_len; + u8 buf[89]; + + if (!arg->req_data || !arg->resp_data) + return -EINVAL; + + /* Copy the request payload from userspace */ + if (copy_from_user(&req, (void __user *)arg->req_data, sizeof(req))) + return -EFAULT; + + /* Message version must be non-zero */ + if (!req.msg_version) + return -EINVAL; + + /* + * The intermediate response buffer is used while decrypting the + * response payload. Make sure that it has enough space to cover the + * authtag. + */ + resp_len = sizeof(resp.data) + crypto->a_len; + if (sizeof(buf) < resp_len) + return -ENOMEM; + + /* Issue the command to get the attestation report */ + rc = handle_guest_request(snp_dev, SVM_VMGEXIT_GUEST_REQUEST, req.msg_version, + SNP_MSG_KEY_REQ, &req.data, sizeof(req.data), buf, resp_len, + &arg->fw_err); + if (rc) + goto e_free; + + /* Copy the response payload to userspace */ + memcpy(resp.data, buf, sizeof(resp.data)); + if (copy_to_user((void __user *)arg->resp_data, &resp, sizeof(resp))) + rc = -EFAULT; + +e_free: + memzero_explicit(buf, sizeof(buf)); + memzero_explicit(&resp, sizeof(resp)); + return rc; +} + static long snp_guest_ioctl(struct file *file, unsigned int ioctl, unsigned long arg) { struct snp_guest_dev *snp_dev = to_snp_dev(file); @@ -382,6 +428,9 @@ static long snp_guest_ioctl(struct file *file, unsigned int ioctl, unsigned long case SNP_GET_REPORT: ret = get_report(snp_dev, &input); break; + case SNP_GET_DERIVED_KEY: + ret = get_derived_key(snp_dev, &input); + break; default: break; } diff --git a/include/uapi/linux/sev-guest.h b/include/uapi/linux/sev-guest.h index eda7edcffda8..f6d9c136ff4d 100644 --- a/include/uapi/linux/sev-guest.h +++ b/include/uapi/linux/sev-guest.h @@ -36,9 +36,33 @@ struct snp_guest_request_ioctl { __u64 fw_err; }; +struct __snp_derived_key_req { + __u32 root_key_select; + __u32 rsvd; + __u64 guest_field_select; + __u32 vmpl; + __u32 guest_svn; + __u64 tcb_version; +}; + +struct snp_derived_key_req { + /* message version number (must be non-zero) */ + __u8 msg_version; + + struct __snp_derived_key_req data; +}; + +struct snp_derived_key_resp { + /* response data, see SEV-SNP spec for the format */ + __u8 data[64]; +}; + #define SNP_GUEST_REQ_IOC_TYPE 'S' /* Get SNP attestation report */ #define SNP_GET_REPORT _IOWR(SNP_GUEST_REQ_IOC_TYPE, 0x0, struct snp_guest_request_ioctl) +/* Get a derived key from the root */ +#define SNP_GET_DERIVED_KEY _IOWR(SNP_GUEST_REQ_IOC_TYPE, 0x1, struct snp_guest_request_ioctl) + #endif /* __UAPI_LINUX_SEV_GUEST_H_ */ From patchwork Fri Oct 8 18:04:53 2021 Content-Type: text/plain; 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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v6 42/42] virt: sevguest: Add support to get extended report Date: Fri, 8 Oct 2021 13:04:53 -0500 Message-ID: <20211008180453.462291-43-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008180453.462291-1-brijesh.singh@amd.com> References: <20211008180453.462291-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f0bb5298-a280-40fd-36b8-08d98a865746 X-MS-TrafficTypeDiagnostic: CH0PR12MB5059: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2331; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nvt8AuGpGE65e1BaT2QFsw3SPTk34u/31pfN4z6coBXEDOQDHWYVuo6Dh1wRlsscUEnF6jUKOsi5Mh5/NEdU3snFw9GQ6TIQ1YpNcj/ugAhkOMjBCP7WKNTw6OL0/g6tROktfauAFf7lNKALPGQJl+7JRpvbM5MfAPWUFPE/HFUydNKlTjU20WQfgi+lEnIP+FxsOJqdNdfgsJjz65Iza4kkez9E6jEKr5ox5L9PWP2pCanFZYhD6+a1pfA/l46q3nCYqMnSYGKbgpm4ux1IqgLuDMfb55Jnw+k7Le2cdj5SqyJjHzua/ESg6YCfQHwYhrgYWMIgvWpEgGCtpkyk6dae1gPCR4ZOAsEFTCjiH19W/8UCFJc3bNzYv1kzPvz45mPYBDRjf5I6s1hpvIxz1VlAuUjG5DdRuhgn/gF0BgVlQpeWwlBOMYewGh5eZ1EVh+H+AmkIn0ctSh3HbiQCe8h2KZkXJv0Z3F6LG4faKYSVpPQFjfYXz7i9WM+pslrjsui5Dbo/E5Ft2KzeSsJW2Rte5Tw4K4rj4+JhhpQn2prZu1m3zq5syDm29HLWLPdJCEE0NpsPFtWT09ARo1ZQwl1QrHxJPFpHfBAW2DoN+hWjQbjZD47FqOWDZ4WsF/GUsHtk1xE2EpFZ9IzqiNXg++tqW/HbrjPbsh62Irr5waAy+QUaAK2IwHwnNrWYVBMQjgqNBlDuTPoH8EzYjmU2yTRgSkjul+Oqj0ChMs2BvtPUt89Lw/YTysw0ZkyVoPyj X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(2906002)(86362001)(2616005)(8676002)(82310400003)(36860700001)(7416002)(8936002)(1076003)(7406005)(316002)(54906003)(426003)(81166007)(44832011)(356005)(5660300002)(47076005)(110136005)(26005)(16526019)(4326008)(83380400001)(186003)(6666004)(508600001)(336012)(7696005)(70586007)(70206006)(36756003)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 18:06:24.2566 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f0bb5298-a280-40fd-36b8-08d98a865746 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5059 Authentication-Results: imf18.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=LaJySJyS; spf=pass (imf18.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.236.81 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 8D716400281B X-Stat-Signature: pyigbpbpa3s1pxd6j3ztgk5xo9s858r3 X-HE-Tag: 1633716388-155412 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Version 2 of GHCB specification defines Non-Automatic-Exit(NAE) to get the extended guest report. It is similar to the SNP_GET_REPORT ioctl. The main difference is related to the additional data that will be returned. The additional data returned is a certificate blob that can be used by the SNP guest user. The certificate blob layout is defined in the GHCB specification. The driver simply treats the blob as a opaque data and copies it to userspace. Signed-off-by: Brijesh Singh --- Documentation/virt/coco/sevguest.rst | 23 +++++++ drivers/virt/coco/sevguest/sevguest.c | 97 ++++++++++++++++++++++++++- include/uapi/linux/sev-guest.h | 13 ++++ 3 files changed, 131 insertions(+), 2 deletions(-) diff --git a/Documentation/virt/coco/sevguest.rst b/Documentation/virt/coco/sevguest.rst index 4b524d1de37c..071dc93aad6c 100644 --- a/Documentation/virt/coco/sevguest.rst +++ b/Documentation/virt/coco/sevguest.rst @@ -86,6 +86,29 @@ on the various fileds passed in the key derivation request. On success, the snp_derived_key_resp.data will contains the derived key value. See the SEV-SNP specification for further details. + +2.3 SNP_GET_EXT_REPORT +---------------------- +:Technology: sev-snp +:Type: guest ioctl +:Parameters (in/out): struct snp_ext_report_req +:Returns (out): struct snp_report_resp on success, -negative on error + +The SNP_GET_EXT_REPORT ioctl is similar to the SNP_GET_REPORT. The difference is +related to the additional certificate data that is returned with the report. +The certificate data returned is being provided by the hypervisor through the +SNP_SET_EXT_CONFIG. + +The ioctl uses the SNP_GUEST_REQUEST (MSG_REPORT_REQ) command provided by the SEV-SNP +firmware to get the attestation report. + +On success, the snp_ext_report_resp.data will contain the attestation report +and snp_ext_report_req.certs_address will contain the certificate blob. If the +length of the blob is smaller than expected then snp_ext_report_req.certs_len will +be updated with the expected value. + +See GHCB specification for further detail on how to parse the certificate blob. + Reference --------- diff --git a/drivers/virt/coco/sevguest/sevguest.c b/drivers/virt/coco/sevguest/sevguest.c index c6ca7d861a3a..f7115adc4378 100644 --- a/drivers/virt/coco/sevguest/sevguest.c +++ b/drivers/virt/coco/sevguest/sevguest.c @@ -41,6 +41,7 @@ struct snp_guest_dev { struct device *dev; struct miscdevice misc; + void *certs_data; struct snp_guest_crypto *crypto; struct snp_guest_msg *request, *response; struct snp_secrets_page_layout *layout; @@ -410,6 +411,88 @@ static int get_derived_key(struct snp_guest_dev *snp_dev, struct snp_guest_reque return rc; } +static int get_ext_report(struct snp_guest_dev *snp_dev, struct snp_guest_request_ioctl *arg) +{ + struct snp_guest_crypto *crypto = snp_dev->crypto; + struct snp_ext_report_req req; + struct snp_report_resp *resp; + int ret, npages = 0, resp_len; + + if (!arg->req_data || !arg->resp_data) + return -EINVAL; + + /* Copy the request payload from userspace */ + if (copy_from_user(&req, (void __user *)arg->req_data, sizeof(req))) + return -EFAULT; + + /* Message version must be non-zero */ + if (!req.data.msg_version) + return -EINVAL; + + if (req.certs_len) { + if (req.certs_len > SEV_FW_BLOB_MAX_SIZE || + !IS_ALIGNED(req.certs_len, PAGE_SIZE)) + return -EINVAL; + } + + if (req.certs_address && req.certs_len) { + if (!access_ok(req.certs_address, req.certs_len)) + return -EFAULT; + + /* + * Initialize the intermediate buffer with all zero's. This buffer + * is used in the guest request message to get the certs blob from + * the host. If host does not supply any certs in it, then copy + * zeros to indicate that certificate data was not provided. + */ + memset(snp_dev->certs_data, 0, req.certs_len); + + npages = req.certs_len >> PAGE_SHIFT; + } + + /* + * The intermediate response buffer is used while decrypting the + * response payload. Make sure that it has enough space to cover the + * authtag. + */ + resp_len = sizeof(resp->data) + crypto->a_len; + resp = kzalloc(resp_len, GFP_KERNEL_ACCOUNT); + if (!resp) + return -ENOMEM; + + snp_dev->input.data_npages = npages; + ret = handle_guest_request(snp_dev, SVM_VMGEXIT_EXT_GUEST_REQUEST, req.data.msg_version, + SNP_MSG_REPORT_REQ, &req.data.user_data, + sizeof(req.data.user_data), resp->data, resp_len, &arg->fw_err); + + /* If certs length is invalid then copy the returned length */ + if (arg->fw_err == SNP_GUEST_REQ_INVALID_LEN) { + req.certs_len = snp_dev->input.data_npages << PAGE_SHIFT; + + if (copy_to_user((void __user *)arg->req_data, &req, sizeof(req))) + ret = -EFAULT; + } + + if (ret) + goto e_free; + + /* Copy the certificate data blob to userspace */ + if (req.certs_address && req.certs_len && + copy_to_user((void __user *)req.certs_address, snp_dev->certs_data, + req.certs_len)) { + ret = -EFAULT; + goto e_free; + } + + /* Copy the response payload to userspace */ + if (copy_to_user((void __user *)arg->resp_data, resp, sizeof(*resp))) + ret = -EFAULT; + +e_free: + kfree(resp); + return ret; +} + static long snp_guest_ioctl(struct file *file, unsigned int ioctl, unsigned long arg) { struct snp_guest_dev *snp_dev = to_snp_dev(file); @@ -431,6 +514,9 @@ static long snp_guest_ioctl(struct file *file, unsigned int ioctl, unsigned long case SNP_GET_DERIVED_KEY: ret = get_derived_key(snp_dev, &input); break; + case SNP_GET_EXT_REPORT: + ret = get_ext_report(snp_dev, &input); + break; default: break; } @@ -508,7 +594,7 @@ static u8 *get_vmpck(int id, struct snp_secrets_page_layout *layout, u32 **seqno break; } - return NULL; + return key; } static int __init snp_guest_probe(struct platform_device *pdev) @@ -554,6 +640,10 @@ static int __init snp_guest_probe(struct platform_device *pdev) if (!snp_dev->response) goto e_fail; + snp_dev->certs_data = alloc_shared_pages(SEV_FW_BLOB_MAX_SIZE); + if (!snp_dev->certs_data) + goto e_fail; + ret = -EIO; snp_dev->crypto = init_crypto(snp_dev, vmpck, VMPCK_KEY_LEN); if (!snp_dev->crypto) @@ -567,16 +657,18 @@ static int __init snp_guest_probe(struct platform_device *pdev) /* initial the input address for guest request */ snp_dev->input.req_gpa = __pa(snp_dev->request); snp_dev->input.resp_gpa = __pa(snp_dev->response); + snp_dev->input.data_gpa = __pa(snp_dev->certs_data); ret = misc_register(misc); if (ret) goto e_fail; - dev_dbg(dev, "Initialized SNP guest driver (using vmpck_id %d)\n", vmpck_id); + dev_info(dev, "Initialized SNP guest driver (using vmpck_id %d)\n", vmpck_id); return 0; e_fail: iounmap(layout); + free_shared_pages(snp_dev->certs_data, SEV_FW_BLOB_MAX_SIZE); free_shared_pages(snp_dev->request, sizeof(struct snp_guest_msg)); free_shared_pages(snp_dev->response, sizeof(struct snp_guest_msg)); @@ -589,6 +681,7 @@ static int __exit snp_guest_remove(struct platform_device *pdev) free_shared_pages(snp_dev->request, sizeof(struct snp_guest_msg)); free_shared_pages(snp_dev->response, sizeof(struct snp_guest_msg)); + free_shared_pages(snp_dev->certs_data, SEV_FW_BLOB_MAX_SIZE); deinit_crypto(snp_dev->crypto); misc_deregister(&snp_dev->misc); diff --git a/include/uapi/linux/sev-guest.h b/include/uapi/linux/sev-guest.h index f6d9c136ff4d..3f6a9d694a47 100644 --- a/include/uapi/linux/sev-guest.h +++ b/include/uapi/linux/sev-guest.h @@ -57,6 +57,16 @@ struct snp_derived_key_resp { __u8 data[64]; }; +struct snp_ext_report_req { + struct snp_report_req data; + + /* where to copy the certificate blob */ + __u64 certs_address; + + /* length of the certificate blob */ + __u32 certs_len; +}; + #define SNP_GUEST_REQ_IOC_TYPE 'S' /* Get SNP attestation report */ @@ -65,4 +75,7 @@ struct snp_derived_key_resp { /* Get a derived key from the root */ #define SNP_GET_DERIVED_KEY _IOWR(SNP_GUEST_REQ_IOC_TYPE, 0x1, struct snp_guest_request_ioctl) +/* Get SNP extended report as defined in the GHCB specification version 2. */ +#define SNP_GET_EXT_REPORT _IOWR(SNP_GUEST_REQ_IOC_TYPE, 0x2, struct snp_guest_request_ioctl) + #endif /* __UAPI_LINUX_SEV_GUEST_H_ */