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[2603:6080:6a07:6dd1:a8f2:a380:3d8d:1528]) by smtp.gmail.com with ESMTPSA id 9sm403010qkn.84.2021.10.08.13.56.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Oct 2021 13:56:39 -0700 (PDT) From: hasheddan To: Cc: georgedanielmangum@gmail.com, Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Peter Zijlstra , Kefeng Wang , Will Deacon , Thomas Gleixner , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] riscv: cacheinfo: fix typo of homogenous Date: Fri, 8 Oct 2021 16:56:25 -0400 Message-Id: <20211008205628.3073014-1-georgedanielmangum@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211008_135642_116376_7FBEFF70 X-CRM114-Status: GOOD ( 11.87 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Updates 'homonogenous' to 'homogenous' in comment. Signed-off-by: hasheddan --- arch/riscv/kernel/cacheinfo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c index 90deabfe63ea..ff98546b1152 100644 --- a/arch/riscv/kernel/cacheinfo.c +++ b/arch/riscv/kernel/cacheinfo.c @@ -29,7 +29,7 @@ static struct cacheinfo *get_cacheinfo(u32 level, enum cache_type type) /* * Using raw_smp_processor_id() elides a preemptability check, but this * is really indicative of a larger problem: the cacheinfo UABI assumes - * that cores have a homonogenous view of the cache hierarchy. That + * that cores have a homogenous view of the cache hierarchy. That * happens to be the case for the current set of RISC-V systems, but * likely won't be true in general. Since there's no way to provide * correct information for these systems via the current UABI we're