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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id x11sm1877253edj.62.2021.10.09.18.56.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Oct 2021 18:56:09 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v3 01/13] net: dsa: qca8k: add mac_power_sel support Date: Sun, 10 Oct 2021 03:55:51 +0200 Message-Id: <20211010015603.24483-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211010015603.24483-1-ansuelsmth@gmail.com> References: <20211010015603.24483-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add missing mac power sel support needed for ipq8064/5 SoC that require 1.8v for the internal regulator port instead of the default 1.5v. If other device needs this, consider adding a dedicated binding to support this. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 31 +++++++++++++++++++++++++++++++ drivers/net/dsa/qca8k.h | 5 +++++ 2 files changed, 36 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index bda5a9bf4f52..a892b897cd0d 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -950,6 +950,33 @@ qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv) return 0; } +static int +qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv) +{ + u32 mask = 0; + int ret = 0; + + /* SoC specific settings for ipq8064. + * If more device require this consider adding + * a dedicated binding. + */ + if (of_machine_is_compatible("qcom,ipq8064")) + mask |= QCA8K_MAC_PWR_RGMII0_1_8V; + + /* SoC specific settings for ipq8065 */ + if (of_machine_is_compatible("qcom,ipq8065")) + mask |= QCA8K_MAC_PWR_RGMII1_1_8V; + + if (mask) { + ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL, + QCA8K_MAC_PWR_RGMII0_1_8V | + QCA8K_MAC_PWR_RGMII1_1_8V, + mask); + } + + return ret; +} + static int qca8k_setup(struct dsa_switch *ds) { @@ -979,6 +1006,10 @@ qca8k_setup(struct dsa_switch *ds) if (ret) return ret; + ret = qca8k_setup_mac_pwr_sel(priv); + if (ret) + return ret; + /* Enable CPU Port */ ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index ed3b05ad6745..fc7db94cc0c9 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -100,6 +100,11 @@ #define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22) #define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22) +/* MAC_PWR_SEL registers */ +#define QCA8K_REG_MAC_PWR_SEL 0x0e4 +#define QCA8K_MAC_PWR_RGMII1_1_8V BIT(18) +#define QCA8K_MAC_PWR_RGMII0_1_8V BIT(19) + /* EEE control registers */ #define QCA8K_REG_EEE_CTRL 0x100 #define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2) From patchwork Sun Oct 10 01:55:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12548203 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A59A6C4332F for ; Sun, 10 Oct 2021 01:56:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8CD7F60F5A for ; Sun, 10 Oct 2021 01:56:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230318AbhJJB6P (ORCPT ); Sat, 9 Oct 2021 21:58:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229549AbhJJB6L (ORCPT ); Sat, 9 Oct 2021 21:58:11 -0400 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B370C061570; Sat, 9 Oct 2021 18:56:13 -0700 (PDT) Received: by mail-ed1-x533.google.com with SMTP id g8so52054909edt.7; Sat, 09 Oct 2021 18:56:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/uV0tNjeCdvzIjAHo5SSrbhvyG9Yb/Fo0F1BEFXhIe8=; b=hYRJldA60Z40LlHSKe7vV3YhxHs2ZkAUyzJoNZx9l7ev0rbFBgDFGvUkVmf89w5rcC 7FuPXLUDRXDJ4GpaRpjhiYeKNlU0/fTM4I3y0mldxJKyuHNL681QW+ahOauZTQyh8XRo 1eHwVTHNnuJsXGrG9CpcASEjQ1jgmSMenFN41lGBVX9evnCuAotLBJ6H261OHFLiUZAT 4+ClFb1iszDheRRHwO/agTVdrLj2pvGvIi3VbkjP75QbMOLx14n3ZiBVBmO/vQdi1Eyt 3j2uPe5BUpom9si4yPgrvp/EiM/Q9UjLa3Js83os6WriQgWR7gQVOZTZevwhjHa5YrAl ja7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/uV0tNjeCdvzIjAHo5SSrbhvyG9Yb/Fo0F1BEFXhIe8=; b=s8LL2z+4By6C62Iy3A3h7/EUoLKIwBgbGGkH6ftoNICfRTcp7k+LOx7ArrfvSG7fTg UI4e3dEUX5acM5n5VpWShJVXrsvojBGcbPDx4Nge19uEbfmEFrb5Mw29acO6OASrgX9T K+fw12tmSTTeL3bNv3KW2rsxYOi6CGG4x29SWuAFcprSATOcjYvrRqBToUHhFVgnMlc5 ZjGVkKSrwbjfYfDuR0hkv3/zecwufulHRe9h1yqnlqk2m1v+MF+re79M2qYPt9sxDOhS 7gVDl5RkmMlr2B0rp/DGgtjheCla4XhLHzcWz/Q2w+OEvmium4NN1oop0QReaiEYvwXZ i5SA== X-Gm-Message-State: AOAM530NwMQUXvKgJWuJ/ptHklm9yPkX7VAJd7wteUl5JCMeiDsgvmSp 6CLbFxU+QjeAMDOV+5pq0nM= X-Google-Smtp-Source: ABdhPJwpGC28wq6F9uOuizgw2lH4IKyiLUVCza8Z6NlSflVNXJ1rQBFDSCaZDa29jAmJVGzkHt1Blw== X-Received: by 2002:a50:cfc1:: with SMTP id i1mr28543657edk.251.1633830971647; Sat, 09 Oct 2021 18:56:11 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id x11sm1877253edj.62.2021.10.09.18.56.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Oct 2021 18:56:11 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ansuel Smith , Matthew Hagan Subject: [net-next PATCH v3 02/13] net: dsa: qca8k: add support for sgmii falling edge Date: Sun, 10 Oct 2021 03:55:52 +0200 Message-Id: <20211010015603.24483-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211010015603.24483-1-ansuelsmth@gmail.com> References: <20211010015603.24483-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add support for this in the qca8k driver. Also add support for SGMII rx/tx clock falling edge. This is only present for pad0, pad5 and pad6 have these bit reserved from Documentation. Add a comment that this is hardcoded to PAD0 as qca8327/28/34/37 have an unique sgmii line and setting falling in port0 applies to both configuration with sgmii used for port0 or port6. Signed-off-by: Matthew Hagan Signed-off-by: Ansuel Smith Reported-by: kernel test robot --- drivers/net/dsa/qca8k.c | 25 +++++++++++++++++++++++++ drivers/net/dsa/qca8k.h | 3 +++ 2 files changed, 28 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index a892b897cd0d..863eeac6eace 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1172,6 +1172,7 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, const struct phylink_link_state *state) { struct qca8k_priv *priv = ds->priv; + struct dsa_port *dp; u32 reg, val; int ret; @@ -1240,6 +1241,8 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, break; case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_1000BASEX: + dp = dsa_to_port(ds, port); + /* Enable SGMII on the port */ qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN); @@ -1274,6 +1277,28 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, } qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val); + + /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and + * falling edge is set writing in the PORT0 PAD reg + */ + if (priv->switch_id == PHY_ID_QCA8327 || + priv->switch_id == PHY_ID_QCA8337) + reg = QCA8K_REG_PORT0_PAD_CTRL; + + val = 0; + + /* SGMII Clock phase configuration */ + if (of_property_read_bool(dp->dn, "qca,sgmii-rxclk-falling-edge")) + val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE; + + if (of_property_read_bool(dp->dn, "qca,sgmii-txclk-falling-edge")) + val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE; + + if (val) + ret = qca8k_rmw(priv, reg, + QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE | + QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE, + val); break; default: dev_err(ds->dev, "xMII mode %s not supported for port %d\n", diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index fc7db94cc0c9..3fded69a6839 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -35,6 +35,9 @@ #define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8) #define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8) #define QCA8K_REG_PORT0_PAD_CTRL 0x004 +#define QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG BIT(31) +#define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE BIT(19) +#define QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE BIT(18) #define QCA8K_REG_PORT5_PAD_CTRL 0x008 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c #define QCA8K_PORT_PAD_RGMII_EN BIT(26) From patchwork Sun Oct 10 01:55:53 2021 Content-Type: text/plain; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id x11sm1877253edj.62.2021.10.09.18.56.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Oct 2021 18:56:12 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ansuel Smith , Matthew Hagan Subject: [net-next PATCH v3 03/13] dt-bindings: net: dsa: qca8k: Add MAC swap and clock phase properties Date: Sun, 10 Oct 2021 03:55:53 +0200 Message-Id: <20211010015603.24483-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211010015603.24483-1-ansuelsmth@gmail.com> References: <20211010015603.24483-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add names and descriptions of additional PORT0_PAD_CTRL properties. qca,sgmii-(rx|tx)clk-falling-edge are for setting the respective clock phase to failling edge. Signed-off-by: Matthew Hagan Signed-off-by: Ansuel Smith --- Documentation/devicetree/bindings/net/dsa/qca8k.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index 8c73f67c43ca..cc214e655442 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -37,6 +37,10 @@ A CPU port node has the following optional node: managed entity. See Documentation/devicetree/bindings/net/fixed-link.txt for details. +- qca,sgmii-rxclk-falling-edge: Set the receive clock phase to falling edge. + Mostly used in qca8327 with CPU port 0 set to + sgmii. +- qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge. For QCA8K the 'fixed-link' sub-node supports only the following properties: From patchwork Sun Oct 10 01:55:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12548205 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1453FC433EF for ; Sun, 10 Oct 2021 01:56:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ED85C60F5A for ; Sun, 10 Oct 2021 01:56:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230448AbhJJB6R (ORCPT ); Sat, 9 Oct 2021 21:58:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230215AbhJJB6N (ORCPT ); Sat, 9 Oct 2021 21:58:13 -0400 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75F80C061570; Sat, 9 Oct 2021 18:56:15 -0700 (PDT) Received: by mail-ed1-x535.google.com with SMTP id t16so30046192eds.9; Sat, 09 Oct 2021 18:56:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AciBJHMxPSxj5ixrhgamlXUQnrChehe6osViae8/6fM=; b=IX7HVU6TmY/A/vH86L1VMP3KP8RG1ku2vfHBEXYuOM3RapUwhgkZw3rZvjcVwX/65U pEE/6X4lZ76lhiDMDKmKubLFOsKnTARWe6Zig0mcIy0QJBG2X/ZNpB7fHmOPJNYMbMtB L/6NlaYwgRR/OYJOhO3sEwg0Jj9OPOP6N8Zy49dPZgB/NLcztafTF0H7rxBQa+Bg1VR6 pzte2oDMCo/rWtu2CWuviOVgPttwYnTSMOIDPtA6tWU2NUL9eOlJCXYeWHO0AIqlpOsT J4p1sybWRkR8JOZrpUYoi6b4maT8u0sSbW/7wvhrc8mMoEWL/WBq1QuOE+V0p8kSIiGY 5V4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AciBJHMxPSxj5ixrhgamlXUQnrChehe6osViae8/6fM=; b=gWnnXxnWG+cRWkimk2Fdq54U61eoo8Ktl2yrPp1aknMEaBaz//hQKMOETFK4aMoBE2 X8aXg9WFp0/QhnIuhkWDeFfBBTsb+mb9VPutSKI5WMeG8/lB7FQFW7+CmiD4QW6A0lj2 cYJOeNCvaCv7g+iEiUlb83eQDBB7MhYcjH+auEkOny7YCMq6NCxzUJW+CfGDgfSfI4ep 74D1jKMWQ6RkEI/cTSGBiujR7kNKfv1PZbWrho7pYx/aWa3JgVKVM+X/vme2Na+rLL2d qsxUCuP8aoamTHdjRk5LSCJm5nSm27NvzntIFSWKNPs9B482qjzRMdA/D8kl7zsXHo5p PjPQ== X-Gm-Message-State: AOAM533E9Etyh9wr1+4TV7zxLyU0/ZJ5Ff1KhF/89qaIVk4/7aeOgwE1 Sv6HhxBufUe9MXmsoSLCg8A= X-Google-Smtp-Source: ABdhPJz2LeTPz8SzGM7AA26+/Q3t7R4bFeMIAoLpaXt0VQcHX9607I9tnc6KmGKJdOgIiopG5GGLxA== X-Received: by 2002:a50:a2a5:: with SMTP id 34mr28154145edm.150.1633830973894; Sat, 09 Oct 2021 18:56:13 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id x11sm1877253edj.62.2021.10.09.18.56.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Oct 2021 18:56:13 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v3 04/13] drivers: net: dsa: qca8k: add support for cpu port 6 Date: Sun, 10 Oct 2021 03:55:54 +0200 Message-Id: <20211010015603.24483-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211010015603.24483-1-ansuelsmth@gmail.com> References: <20211010015603.24483-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Currently CPU port is always hardcoded to port 0. This switch have 2 CPU port. The original intention of this driver seems to be use the mac06_exchange bit to swap MAC0 with MAC6 in the strange configuration where device have connected only the CPU port 6. To skip the introduction of a new binding, rework the driver to address the secondary CPU port as primary and drop any reference of hardcoded port. With configuration of mac06 exchange, just skip the definition of port0 and define the CPU port as a secondary. The driver will autoconfigure the switch to use that as the primary CPU port. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 50 +++++++++++++++++++++++++++++------------ drivers/net/dsa/qca8k.h | 2 -- 2 files changed, 36 insertions(+), 16 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 863eeac6eace..91334fa23183 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -977,17 +977,34 @@ qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv) return ret; } +static int qca8k_find_cpu_port(struct dsa_switch *ds) +{ + struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; + + /* Find the connected cpu port. Valid port are 0 or 6 */ + if (dsa_is_cpu_port(ds, 0)) + return 0; + + dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6"); + + if (dsa_is_cpu_port(ds, 6)) + return 6; + + return -EINVAL; +} + static int qca8k_setup(struct dsa_switch *ds) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; + u8 cpu_port; int ret, i; u32 mask; - /* Make sure that port 0 is the cpu port */ - if (!dsa_is_cpu_port(ds, 0)) { - dev_err(priv->dev, "port 0 is not the CPU port"); - return -EINVAL; + cpu_port = qca8k_find_cpu_port(ds); + if (cpu_port < 0) { + dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6"); + return cpu_port; } mutex_init(&priv->reg_mutex); @@ -1024,7 +1041,7 @@ qca8k_setup(struct dsa_switch *ds) dev_warn(priv->dev, "mib init failed"); /* Enable QCA header mode on the cpu port */ - ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT), + ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(cpu_port), QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S | QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S); if (ret) { @@ -1046,10 +1063,10 @@ qca8k_setup(struct dsa_switch *ds) /* Forward all unknown frames to CPU port for Linux processing */ ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1, - BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S | - BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S | - BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S | - BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S); + BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S | + BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S | + BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S | + BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S); if (ret) return ret; @@ -1057,7 +1074,7 @@ qca8k_setup(struct dsa_switch *ds) for (i = 0; i < QCA8K_NUM_PORTS; i++) { /* CPU port gets connected to all user ports of the switch */ if (dsa_is_cpu_port(ds, i)) { - ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT), + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(cpu_port), QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds)); if (ret) return ret; @@ -1069,7 +1086,7 @@ qca8k_setup(struct dsa_switch *ds) ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), QCA8K_PORT_LOOKUP_MEMBER, - BIT(QCA8K_CPU_PORT)); + BIT(cpu_port)); if (ret) return ret; @@ -1578,9 +1595,12 @@ static int qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - int port_mask = BIT(QCA8K_CPU_PORT); + int port_mask, cpu_port; int i, ret; + cpu_port = dsa_to_port(ds, port)->cpu_dp->index; + port_mask = BIT(cpu_port); + for (i = 1; i < QCA8K_NUM_PORTS; i++) { if (dsa_to_port(ds, i)->bridge_dev != br) continue; @@ -1607,7 +1627,9 @@ static void qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - int i; + int cpu_port, i; + + cpu_port = dsa_to_port(ds, port)->cpu_dp->index; for (i = 1; i < QCA8K_NUM_PORTS; i++) { if (dsa_to_port(ds, i)->bridge_dev != br) @@ -1624,7 +1646,7 @@ qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br) * this port */ qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT)); + QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port)); } static int diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 3fded69a6839..5df0f0ef6526 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -24,8 +24,6 @@ #define QCA8K_NUM_FDB_RECORDS 2048 -#define QCA8K_CPU_PORT 0 - #define QCA8K_PORT_VID_DEF 1 /* Global control registers */ From patchwork Sun Oct 10 01:55:55 2021 Content-Type: text/plain; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id x11sm1877253edj.62.2021.10.09.18.56.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Oct 2021 18:56:14 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v3 05/13] dt-bindings: net: dsa: qca8k: Document support for CPU port 6 Date: Sun, 10 Oct 2021 03:55:55 +0200 Message-Id: <20211010015603.24483-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211010015603.24483-1-ansuelsmth@gmail.com> References: <20211010015603.24483-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The switch now support CPU port to be set 6 instead of be hardcoded to 0. Document support for it and describe logic selection. Signed-off-by: Ansuel Smith --- Documentation/devicetree/bindings/net/dsa/qca8k.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index cc214e655442..aeb206556f54 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -29,7 +29,11 @@ the mdio MASTER is used as communication. Don't use mixed external and internal mdio-bus configurations, as this is not supported by the hardware. -The CPU port of this switch is always port 0. +This switch support 2 CPU port. Normally and advised configuration is with +CPU port set to port 0. It is also possible to set the CPU port to port 6 +if the device requires it. The driver will configure the switch to the defined +port. With both CPU port declared the first CPU port is selected as primary +and the secondary CPU ignored. A CPU port node has the following optional node: From patchwork Sun Oct 10 01:55:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12548211 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD1BFC433FE for ; Sun, 10 Oct 2021 01:56:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9892D60EE7 for ; Sun, 10 Oct 2021 01:56:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230353AbhJJB6d (ORCPT ); Sat, 9 Oct 2021 21:58:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230342AbhJJB6P (ORCPT ); Sat, 9 Oct 2021 21:58:15 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6AD27C061570; Sat, 9 Oct 2021 18:56:17 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id y12so38931962eda.4; Sat, 09 Oct 2021 18:56:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=76EGozKysDsid4PBsA7POrevwp5ilwSPedQ5ZoavCE4=; b=NfyqQlmlYKAHsmhWBrE4TUctt4Hnw0dlxcXuaUnVDKDTR645g2zYIE5EeGhGdZCULR bUwMcM6GE3gJr1SCE/0qo8jvmcDxiPKP11Fbndik98v+LDzUg1WkARNXMk5oFTExK5LM nCak8koxsOscWeYDnjAVBoQC8ZzPHHj3J1ihCivnIkulh4WVh9QRS15vB9oEvEUZZpq7 K3aUgCrhyKwwG3C0/Jeayr+Xn6HpU5D7dxKIlNEz9lk1HX5is/D2NWEkZN4WbXV1ogdi le5rBNc3ztAnZhLkQTR95NPyMAQH0p7A0TD9DD7LJRbvA/GkrCVaCeALaGgn9fcupEg/ aaxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=76EGozKysDsid4PBsA7POrevwp5ilwSPedQ5ZoavCE4=; b=GstViEiqOMGhABhve8KJ3+bGy9cUMny0y8ggSis0/1sy+v76Icewhe+TL/hUmP1q1v r0oLTvN8sNqq5SWaULNrRulkPH7d9+33mkdwLz2uxD7/rgqVeI2g0BcqSvZlvCX7Azj2 rDZpGT6QgsVvhSc9V8K4MtyXpLDJe4seVm2iihREpWn6koOCf3LwIzkBBsMWntiwBFQ5 mFInmOmUv7lBK/PKPvx5jh3i49FmJ7o+rQrHVvP9UVjH4ua3/nqNO5GA6M2O1acwUUy7 mAIoeRcGK3C2hgcfZQc4dJkqJJ4xvgb9te3G28ItR96KFqBZ5EvYiFOt/lCyBGVSlp5i G8Aw== X-Gm-Message-State: AOAM531DfGMPhEQk2c56N5pDeQ+Ri4qeEChdXVzCc54nt5aSzBOkekhJ P1vGetvor213XVRDeOxuX3I= X-Google-Smtp-Source: ABdhPJwkwjro4Sis0idfoYxWj2fuT6dWySRIGbFkw5V3oonMlaFSAWxvn008aZrjRN8dD6o6fUSwcQ== X-Received: by 2002:a50:d84e:: with SMTP id v14mr28332781edj.85.1633830975869; Sat, 09 Oct 2021 18:56:15 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id x11sm1877253edj.62.2021.10.09.18.56.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Oct 2021 18:56:15 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v3 06/13] net: dsa: qca8k: move rgmii delay detection to phylink mac_config Date: Sun, 10 Oct 2021 03:55:56 +0200 Message-Id: <20211010015603.24483-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211010015603.24483-1-ansuelsmth@gmail.com> References: <20211010015603.24483-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Future proof commit. This switch have 2 CPU port and one valid configuration is first CPU port set to sgmii and second CPU port set to regmii-id. The current implementation detects delay only for CPU port zero set to rgmii and doesn't count any delay set in a secondary CPU port. Drop the current delay scan function and move it to the phylink mac_config to generilize and implicitly add support for secondary CPU port set to rgmii-id. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 121 +++++++++++++++------------------------- drivers/net/dsa/qca8k.h | 2 - 2 files changed, 44 insertions(+), 79 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 91334fa23183..043980a5db7f 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -888,68 +888,6 @@ qca8k_setup_mdio_bus(struct qca8k_priv *priv) return 0; } -static int -qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv) -{ - struct device_node *port_dn; - phy_interface_t mode; - struct dsa_port *dp; - u32 val; - - /* CPU port is already checked */ - dp = dsa_to_port(priv->ds, 0); - - port_dn = dp->dn; - - /* Check if port 0 is set to the correct type */ - of_get_phy_mode(port_dn, &mode); - if (mode != PHY_INTERFACE_MODE_RGMII_ID && - mode != PHY_INTERFACE_MODE_RGMII_RXID && - mode != PHY_INTERFACE_MODE_RGMII_TXID) { - return 0; - } - - switch (mode) { - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - if (of_property_read_u32(port_dn, "rx-internal-delay-ps", &val)) - val = 2; - else - /* Switch regs accept value in ns, convert ps to ns */ - val = val / 1000; - - if (val > QCA8K_MAX_DELAY) { - dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value"); - val = 3; - } - - priv->rgmii_rx_delay = val; - /* Stop here if we need to check only for rx delay */ - if (mode != PHY_INTERFACE_MODE_RGMII_ID) - break; - - fallthrough; - case PHY_INTERFACE_MODE_RGMII_TXID: - if (of_property_read_u32(port_dn, "tx-internal-delay-ps", &val)) - val = 1; - else - /* Switch regs accept value in ns, convert ps to ns */ - val = val / 1000; - - if (val > QCA8K_MAX_DELAY) { - dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value"); - val = 3; - } - - priv->rgmii_tx_delay = val; - break; - default: - return 0; - } - - return 0; -} - static int qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv) { @@ -1019,10 +957,6 @@ qca8k_setup(struct dsa_switch *ds) if (ret) return ret; - ret = qca8k_setup_of_rgmii_delay(priv); - if (ret) - return ret; - ret = qca8k_setup_mac_pwr_sel(priv); if (ret) return ret; @@ -1190,7 +1124,7 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, { struct qca8k_priv *priv = ds->priv; struct dsa_port *dp; - u32 reg, val; + u32 reg, val, delay; int ret; switch (port) { @@ -1241,17 +1175,50 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_TXID: case PHY_INTERFACE_MODE_RGMII_RXID: - /* RGMII_ID needs internal delay. This is enabled through - * PORT5_PAD_CTRL for all ports, rather than individual port - * registers + dp = dsa_to_port(ds, port); + val = QCA8K_PORT_PAD_RGMII_EN; + + if (state->interface == PHY_INTERFACE_MODE_RGMII_ID || + state->interface == PHY_INTERFACE_MODE_RGMII_TXID) { + if (of_property_read_u32(dp->dn, "tx-internal-delay-ps", &delay)) + delay = 1; + else + /* Switch regs accept value in ns, convert ps to ns */ + delay = delay / 1000; + + if (delay > QCA8K_MAX_DELAY) { + dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value"); + delay = 3; + } + + val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) | + QCA8K_PORT_PAD_RGMII_TX_DELAY_EN; + } + + if (state->interface == PHY_INTERFACE_MODE_RGMII_ID || + state->interface == PHY_INTERFACE_MODE_RGMII_RXID) { + if (of_property_read_u32(dp->dn, "rx-internal-delay-ps", &delay)) + delay = 2; + else + /* Switch regs accept value in ns, convert ps to ns */ + delay = delay / 1000; + + if (delay > QCA8K_MAX_DELAY) { + dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value"); + delay = 3; + } + + val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) | + QCA8K_PORT_PAD_RGMII_RX_DELAY_EN; + } + + /* Set RGMII delay based on the selected values */ + qca8k_write(priv, reg, val); + + /* QCA8337 requires to set rgmii rx delay for all ports. + * This is enabled through PORT5_PAD_CTRL for all ports, + * rather than individual port registers. */ - qca8k_write(priv, reg, - QCA8K_PORT_PAD_RGMII_EN | - QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) | - QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) | - QCA8K_PORT_PAD_RGMII_TX_DELAY_EN | - QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); - /* QCA8337 requires to set rgmii rx delay */ if (priv->switch_id == QCA8K_ID_QCA8337) qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 5df0f0ef6526..a790b27bc310 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -259,8 +259,6 @@ struct qca8k_match_data { struct qca8k_priv { u8 switch_id; u8 switch_revision; - u8 rgmii_tx_delay; - u8 rgmii_rx_delay; bool legacy_phy_port_mapping; struct regmap *regmap; struct mii_bus *bus; From patchwork Sun Oct 10 01:55:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12548223 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06882C4332F for ; Sun, 10 Oct 2021 01:57:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E4E6960F6B for ; Sun, 10 Oct 2021 01:57:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232259AbhJJB7I (ORCPT ); Sat, 9 Oct 2021 21:59:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230405AbhJJB6Q (ORCPT ); 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id x11sm1877253edj.62.2021.10.09.18.56.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Oct 2021 18:56:16 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v3 07/13] net: dsa: qca8k: add explicit SGMII PLL enable Date: Sun, 10 Oct 2021 03:55:57 +0200 Message-Id: <20211010015603.24483-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211010015603.24483-1-ansuelsmth@gmail.com> References: <20211010015603.24483-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Support enabling PLL on the SGMII CPU port. Some device require this special configuration or no traffic is transmitted and the switch doesn't work at all. A dedicated binding is added to the CPU node port to apply the correct reg on mac config. Fail to correctly configure sgmii with qca8327 switch and warn if pll is used on qca8337 with a revision greater than 1. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 043980a5db7f..b73b92ebd72e 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1245,8 +1245,20 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, if (ret) return; - val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX | - QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD; + val |= QCA8K_SGMII_EN_SD; + + if (of_property_read_bool(dp->dn, "qca,sgmii-enable-pll")) { + if (priv->switch_id == QCA8K_ID_QCA8327) { + dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling"); + return; + } + + if (priv->switch_revision < 2) + dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more."); + + val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX | + QCA8K_SGMII_EN_TX; + } if (dsa_is_cpu_port(ds, port)) { /* CPU port, we're talking to the CPU MAC, be a PHY */ From patchwork Sun Oct 10 01:55:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12548213 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF3B5C433EF for ; Sun, 10 Oct 2021 01:56:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 96C0460EE7 for ; Sun, 10 Oct 2021 01:56:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231869AbhJJB6k (ORCPT ); Sat, 9 Oct 2021 21:58:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230520AbhJJB6S (ORCPT ); Sat, 9 Oct 2021 21:58:18 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 868E7C061765; Sat, 9 Oct 2021 18:56:19 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id i20so35698846edj.10; Sat, 09 Oct 2021 18:56:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PVZTOX5p5oDFXWjsRtvrNcBi7SCHD7eFTAWryiBFY1g=; b=qCx/uTgRBDKUc+YCgMwCz/hQsMcDWBTldgUIFLknShciQEA0rNSqXbuhIJKifbtavR T2xwLO/RaMKbIB609TMUgwD/p+aA1NVqdvkKSxMT/1w1SXuQQ+XYJSK9MKO46vectBIU HQw7NmxASSPCGkJhXxRmR0+o5diYjcXuSwWGNOZi+BF8k8h8VrZxjUblrOaH6A1y3al4 xaiuVvWpEnKmkzP3qN9ExRR9ofXWCkfzjOcxQO+eYqmbeRNSTYbh23FwCZbiyE4AjIK4 1emhsEiNTFNrLUHLI6AtpwKqjo5C2PSdTxwqnoqd4winDU84oDz/x7TQ2nQRK5svvC3k EPGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PVZTOX5p5oDFXWjsRtvrNcBi7SCHD7eFTAWryiBFY1g=; b=DnhmspqgBXGJT+EXMpsJdTUqjGbWatO68BNugQERNDxTX6QkiG+fv9Y5a3TAnyr497 U6kA4VKIlTVWzzXKWpAJ6IoT44KIHuYf3D4UA2xV2fYnGoCeYwoZGlk6FZmKKx2UgTiV hvzj4t20RpRAMGi6x8eeapa/DsQsPf1XX3KefAKPsWIQ5o1WqJFs8fNlI7VTC4eOsIaw /XGpT2Iw+qVKkoeEP0RIP+Ie9a2GZfuusI1nBXWLeAdSl64mGHa8Ur8f6FVHqNmeH6ow 4SUAWjRsZDBwMlvosGrkHo4vUIhEK2NV2583qf6fyVGTpgfVh4F9bVTdkJdhDhKk1J3M ExCQ== X-Gm-Message-State: AOAM533kHYUsr6RByqKSnWsYrlU6SHIpjS78eRdK1BATwnr/mWmcqXum eH9SxlL2cqom/v6bIE1F0W0= X-Google-Smtp-Source: ABdhPJxU8v1dL0i8aZ6grRLupdYVYYMYy2m4qYNdOOzYslQEoOHYq3MZJ90mz64+auXnD8ZiFArJpw== X-Received: by 2002:a17:906:7a1e:: with SMTP id d30mr15195880ejo.517.1633830978040; Sat, 09 Oct 2021 18:56:18 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id x11sm1877253edj.62.2021.10.09.18.56.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Oct 2021 18:56:17 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v3 08/13] dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll Date: Sun, 10 Oct 2021 03:55:58 +0200 Message-Id: <20211010015603.24483-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211010015603.24483-1-ansuelsmth@gmail.com> References: <20211010015603.24483-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Document qca,sgmii-enable-pll binding used in the CPU nodes to enable SGMII PLL on MAC config. Signed-off-by: Ansuel Smith --- Documentation/devicetree/bindings/net/dsa/qca8k.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index aeb206556f54..05a8ddfb5483 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -45,6 +45,16 @@ A CPU port node has the following optional node: Mostly used in qca8327 with CPU port 0 set to sgmii. - qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge. +- qca,sgmii-enable-pll : For SGMII CPU port, explicitly enable PLL, TX and RX + chain along with Signal Detection. + This should NOT be enabled for qca8327. If enabled with + qca8327 the sgmii port won't correctly init and an err + is printed. + This can be required for qca8337 switch with revision 2. + A warning is displayed when used with revision greater + 2. + With CPU port set to sgmii and qca8337 it is advised + to set this unless a communication problem is observed. For QCA8K the 'fixed-link' sub-node supports only the following properties: From patchwork Sun Oct 10 01:55:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12548217 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73E6DC433EF for ; Sun, 10 Oct 2021 01:56:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5BEA360F5A for ; Sun, 10 Oct 2021 01:56:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232056AbhJJB6z (ORCPT ); Sat, 9 Oct 2021 21:58:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231179AbhJJB6T (ORCPT ); Sat, 9 Oct 2021 21:58:19 -0400 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A29FEC061769; Sat, 9 Oct 2021 18:56:20 -0700 (PDT) Received: by mail-ed1-x52a.google.com with SMTP id b8so51927976edk.2; Sat, 09 Oct 2021 18:56:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RquP4AmniefGHe5H1mUC7SsdZ/7Asb+THzH67+x1DGQ=; b=qQdCvxUZJHDxfiMXK7y78OyynKQZxFDrDF9dC9rYpxc1PlCvoSZdh+4wXjMmIM+lRQ N0biY717aistGMz1hqjobz/2uAX03Vnal9noGNreG7LRJYTV5ob3EhlS4sj/yFwCeDC9 O4SmcOizRrLBKD5yz5fC3R4miw6ty3lusGG5yMVzfN5nolhCSuHq1t9jew7SC1XOurKI +2rBAiFwXUYiFIruHP+VDK7csdVIYZQRISyUpEsd9BXuC31V0aaiBykdIkRbMu2C2RMJ 5TdtyggZzFGstO4d9CYv0kF93sFwTxXJG3O0kN9R3KTuPhEQfPwYd2HtOk28UN03oVTM RBoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RquP4AmniefGHe5H1mUC7SsdZ/7Asb+THzH67+x1DGQ=; b=rArIULOtVEV6VLbViLu3gpM8rjUyZnNlJT9vek5wRspWOnBgD0jlNfgDdDG277V3f0 i6dnvaLb9KeHod7k24uJktQnUXvEfD3Min3J7DM7qaSC34iKm8ITSQUz96PavbdhIrNg KLWxj5s1umdXl0jjdGB0JNhvBOLT/KJQLW67hqNdQgXKog3F9iEENxocN/WaMJgrf4LE Zc7ugLh3RRiSacjyL+huEd/lf8/f0BjKIjIb3UmWSGWO1/7AScHsmZl+B8degA4b4iW9 20zwQEGp7KwFQkYQ7ZkQBVlLEkDTyQ2CXX6fy7Jx/clNFfw152kJBhWJ/Lej5O5g3xRh 1ICA== X-Gm-Message-State: AOAM530LNGMRvVM/OHd4LQzYTKglgquHwgBw/bRL9pSnIQt3KBwvCrkv dELcsECnAagR4RruuneoDAII6yYo/Vo= X-Google-Smtp-Source: ABdhPJwiNDRjGWVkRgOUd0iSfYQK4cwLpmLF0fFVWgJ8wRyDc+bWSL738ye+I/lMfHfS3pMLNY0sbA== X-Received: by 2002:a17:907:2bc2:: with SMTP id gv2mr15025822ejc.433.1633830979130; Sat, 09 Oct 2021 18:56:19 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id x11sm1877253edj.62.2021.10.09.18.56.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Oct 2021 18:56:18 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v3 09/13] drivers: net: dsa: qca8k: add support for pws config reg Date: Sun, 10 Oct 2021 03:55:59 +0200 Message-Id: <20211010015603.24483-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211010015603.24483-1-ansuelsmth@gmail.com> References: <20211010015603.24483-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Some qca8327 switch require to force the ignore of power on sel strapping. Some switch require to set the led open drain mode in regs instead of using strapping. While most of the device implements this using the correct way using pin strapping, there are still some broken device that require to be set using sw regs. Introduce a new binding and support these special configuration. As led open drain require to ignore pin strapping to work, the probe fails with EINVAL error with incorrect configuration. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 39 +++++++++++++++++++++++++++++++++++++++ drivers/net/dsa/qca8k.h | 6 ++++++ 2 files changed, 45 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index b73b92ebd72e..3e2274cb82cd 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -931,6 +931,41 @@ static int qca8k_find_cpu_port(struct dsa_switch *ds) return -EINVAL; } +static int +qca8k_setup_of_pws_reg(struct qca8k_priv *priv) +{ + struct device_node *node = priv->dev->of_node; + u32 val = 0; + int ret; + + /* QCA8327 require to set to the correct mode. + * His bigger brother QCA8328 have the 172 pin layout. + * Should be applied by default but we set this just to make sure. + */ + if (priv->switch_id == QCA8K_ID_QCA8327) { + ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN, + QCA8327_PWS_PACKAGE148_EN); + if (ret) + return ret; + } + + if (of_property_read_bool(node, "qca,ignore-power-on-sel")) + val |= QCA8K_PWS_POWER_ON_SEL; + + if (of_property_read_bool(node, "qca,led-open-drain")) { + if (!(val & QCA8K_PWS_POWER_ON_SEL)) { + dev_err(priv->dev, "qca,led-open-drain require qca,ignore-power-on-sel to be set."); + return -EINVAL; + } + + val |= QCA8K_PWS_LED_OPEN_EN_CSR; + } + + return qca8k_rmw(priv, QCA8K_REG_PWS, + QCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL, + val); +} + static int qca8k_setup(struct dsa_switch *ds) { @@ -957,6 +992,10 @@ qca8k_setup(struct dsa_switch *ds) if (ret) return ret; + ret = qca8k_setup_of_pws_reg(priv); + if (ret) + return ret; + ret = qca8k_setup_mac_pwr_sel(priv); if (ret) return ret; diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index a790b27bc310..535a4515e7b9 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -46,6 +46,12 @@ #define QCA8K_MAX_DELAY 3 #define QCA8K_PORT_PAD_SGMII_EN BIT(7) #define QCA8K_REG_PWS 0x010 +#define QCA8K_PWS_POWER_ON_SEL BIT(31) +/* This reg is only valid for QCA832x and toggle the package + * type from 176 pin (by default) to 148 pin used on QCA8327 + */ +#define QCA8327_PWS_PACKAGE148_EN BIT(30) +#define QCA8K_PWS_LED_OPEN_EN_CSR BIT(24) #define QCA8K_PWS_SERDES_AEN_DIS BIT(7) #define QCA8K_REG_MODULE_EN 0x030 #define QCA8K_MODULE_EN_MIB BIT(0) From patchwork Sun Oct 10 01:56:00 2021 Content-Type: text/plain; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id x11sm1877253edj.62.2021.10.09.18.56.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Oct 2021 18:56:19 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v3 10/13] dt-bindings: net: dsa: qca8k: document open drain binding Date: Sun, 10 Oct 2021 03:56:00 +0200 Message-Id: <20211010015603.24483-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211010015603.24483-1-ansuelsmth@gmail.com> References: <20211010015603.24483-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Document new binding qca,power_on_sel used to enable Power-on-strapping select reg and qca,led_open_drain to set led to open drain mode. Signed-off-by: Ansuel Smith --- Documentation/devicetree/bindings/net/dsa/qca8k.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index 05a8ddfb5483..71cd45818430 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -13,6 +13,17 @@ Required properties: Optional properties: - reset-gpios: GPIO to be used to reset the whole device +- qca,ignore-power-on-sel: Ignore power on pin strapping to configure led open + drain or eeprom presence. This is needed for broken + device that have wrong configuration or when the oem + decided to not use pin strapping and fallback to sw + regs. +- qca,led-open-drain: Set leds to open-drain mode. This require the + qca,ignore-power-on-sel to be set or the driver will fail + to probe. This is needed if the oem doesn't use pin + strapping to set this mode and prefer to set it using sw + regs. The pin strapping related to led open drain mode is + the pin B68 for QCA832x and B49 for QCA833x Subnodes: From patchwork Sun Oct 10 01:56:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12548219 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2645BC433F5 for ; Sun, 10 Oct 2021 01:57:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0D4E960F5A for ; Sun, 10 Oct 2021 01:57:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231395AbhJJB7B (ORCPT ); Sat, 9 Oct 2021 21:59:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231244AbhJJB6W (ORCPT ); Sat, 9 Oct 2021 21:58:22 -0400 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E813C06176D; Sat, 9 Oct 2021 18:56:22 -0700 (PDT) Received: by mail-ed1-x531.google.com with SMTP id d3so24498511edp.3; Sat, 09 Oct 2021 18:56:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eZKKTWkNvu/0F33tX/g7gmdT/XzT4msMSsmAHd15+ag=; b=evrfuX50MFm+n4AMfXOT4lAzI6KQ7WUKnotf6MSaoQtXWZTKMK+arpo5+xwgtjeArO BvtPWq+F5b/P6Kbksef6UmmNKNWNHvpeV+eJ976I6FbFVkGqFd9Wkvu51JTjSxEVizk6 uIVhEXQ+XAVu25Nc8Kj3Q1XabAFOR73attndwNGbCof0H0Ow4lXLyAnw+YDiqYOV/Pmq ALLwt8dVDyepsr4UmLohYQK96uyvpCMxTlVWFcDgWuv7eC7aybAGf1YH9k9ocDy1qV5z XLwvtEO+GjJL9vvaYaNnkFeXzwX2uKPnVT8MVxs3oZZ4RcIQi68TAa5UPxNuAAUhYeKF Hb/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eZKKTWkNvu/0F33tX/g7gmdT/XzT4msMSsmAHd15+ag=; b=Vgled5GGRp4PmnuGgFt3xoXOoFlYD2B8c+OjFp30ArPnMR+awgUtoWOMIfZ39vvAdi y37kEARAcvtoDbfPQnKNDTwV6JgocrTG/VI8OoQCs1mq6RkCNrw9PgzByY3+rdMiVVn8 hvVTlItBuEoMGFy2sPdmXbBQN1mdmGIe8VgAhP6yLzloHoXWZRkZVZNkrB6k6Yzos1HK rNPTd6wfr8tNV/ufJUb3GV74Xl7iBDrojOnt5lA2BT5ORMSuK3BSnNlojIkteUOryUm8 TxczgFd7D7A+NG9eW/mGLMpbAE+HBDWxI/wjkPszOAR5TtGoiGalvZ28ATRbYpumRxgn fGrQ== X-Gm-Message-State: AOAM532CC+X1SL/nM9d+6WFTOmRyX6yuAeqo06YHKm2q0HALPjte/eei BVo4OJgLpodcY+pfTnmP4RY= X-Google-Smtp-Source: ABdhPJwjJk3C5hz2Kck1y7WQ4E/uA5brDN1qBQ12C6fTyc99BFQxReg6DTWLWv1PV/5H2qIzkJ4GXA== X-Received: by 2002:a17:906:c0d7:: with SMTP id bn23mr16050987ejb.426.1633830981095; Sat, 09 Oct 2021 18:56:21 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id x11sm1877253edj.62.2021.10.09.18.56.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Oct 2021 18:56:20 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v3 11/13] drivers: net: dsa: qca8k: add support for QCA8328 Date: Sun, 10 Oct 2021 03:56:01 +0200 Message-Id: <20211010015603.24483-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211010015603.24483-1-ansuelsmth@gmail.com> References: <20211010015603.24483-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org QCA8328 switch is the bigger brother of the qca8327. Same regs different chip. Change the function to set the correct pin layout and introduce a new match_data to differentiate the 2 switch as they have the same ID and their internal PHY have the same ID. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 19 ++++++++++++++++--- drivers/net/dsa/qca8k.h | 1 + 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 3e2274cb82cd..7c68c272ce3a 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -935,6 +935,7 @@ static int qca8k_setup_of_pws_reg(struct qca8k_priv *priv) { struct device_node *node = priv->dev->of_node; + const struct qca8k_match_data *data; u32 val = 0; int ret; @@ -943,8 +944,14 @@ qca8k_setup_of_pws_reg(struct qca8k_priv *priv) * Should be applied by default but we set this just to make sure. */ if (priv->switch_id == QCA8K_ID_QCA8327) { + data = of_device_get_match_data(priv->dev); + + /* Set the correct package of 148 pin for QCA8327 */ + if (data->reduced_package) + val |= QCA8327_PWS_PACKAGE148_EN; + ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN, - QCA8327_PWS_PACKAGE148_EN); + val); if (ret) return ret; } @@ -2018,7 +2025,12 @@ static int qca8k_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(qca8k_pm_ops, qca8k_suspend, qca8k_resume); -static const struct qca8k_match_data qca832x = { +static const struct qca8k_match_data qca8327 = { + .id = QCA8K_ID_QCA8327, + .reduced_package = true, +}; + +static const struct qca8k_match_data qca8328 = { .id = QCA8K_ID_QCA8327, }; @@ -2027,7 +2039,8 @@ static const struct qca8k_match_data qca833x = { }; static const struct of_device_id qca8k_of_match[] = { - { .compatible = "qca,qca8327", .data = &qca832x }, + { .compatible = "qca,qca8327", .data = &qca8327 }, + { .compatible = "qca,qca8328", .data = &qca8328 }, { .compatible = "qca,qca8334", .data = &qca833x }, { .compatible = "qca,qca8337", .data = &qca833x }, { /* sentinel */ }, diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 535a4515e7b9..c032db5e0d41 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -260,6 +260,7 @@ struct ar8xxx_port_status { struct qca8k_match_data { u8 id; + bool reduced_package; }; struct qca8k_priv { From patchwork Sun Oct 10 01:56:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12548221 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35F6CC433FE for ; Sun, 10 Oct 2021 01:57:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 21B4D60F6B for ; Sun, 10 Oct 2021 01:57:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230490AbhJJB7F (ORCPT ); Sat, 9 Oct 2021 21:59:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231371AbhJJB6Y (ORCPT ); Sat, 9 Oct 2021 21:58:24 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C209C061777; Sat, 9 Oct 2021 18:56:23 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id g8so52055801edt.7; Sat, 09 Oct 2021 18:56:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0aDD0ZRLezKNP93hdNBNXpgtETt+h6AkeOIcfTrSqio=; b=koCaojpHgAJfjGz2i2z2pt67cD+gREhciubz6P962AB1GeBz3YJDcpgLfME4Flr07Z k5c9JUxULPg+uQbKAsnh7uTcmfF2Lqa7v8j/EmLA4BJn4SKuZzYJa2/Kou1pecs4+sKA HqhhVvK0FEftIcTJSApKPOmzfJTeUqM50j/rt3BJcoK0SrtJ2MZipdrwtrMfD8O5sdLX 8Zv8dvZcMBJeTfrruj43Q2xbXpsfdIW1e7P7DJXaBqB35XjtJ9IXKDLxzeNs5LjpCbRA qAWdJYBMWzjX7JOTt/Ln3QKiwaQNUvCYGDzQ/HYxjwlPOg8lnQc3ONA/H+8RIimP54UJ Yq7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0aDD0ZRLezKNP93hdNBNXpgtETt+h6AkeOIcfTrSqio=; b=3VyTqGbqZ8YbkJ7tHDPFG5LHdOiJLjEysGtge1RadcbtnnTvaTg0rMzCLlTdm165QG ZLn086scgLqbUgqMPFunQX5+BJKvxm8qyoEU2WqG1GDrg0rJeBFMDZopQmB8nFRGthPq rbxiXiJG4qecGY0DLbtZiKSOaqCWyValpJZ1Xcc16LHklaOJU8IJWsiCvKkWX7/Vf+h6 ReYkXCMbpk5iWoFLBQMQuvqe1EuytguutE8BcMyAFohIF3o9meEX4mzw7DksWxAgJ3qW 7d1h2Vf5mwWzzyN78qF8N24OF6eovIj3V33QLCAksdCYOhKCK+EvOOCHyo7mZQ9c4pfA nhwg== X-Gm-Message-State: AOAM532aCFTaTD/XPQiZKt8oGGkPR9vi8p6NV+YQ+j3TVQ1/Q2u+ISYY NQNILZp5iZQXx3BQcfcWq1DJg21yKSg= X-Google-Smtp-Source: ABdhPJzVDnuJv33Qmd9lsrqBsM7r+eAKHsD8JIxGOpfzqxs7cLmY95k/nYriTc6QtG2UTzYlR8HsjA== X-Received: by 2002:a17:906:a044:: with SMTP id bg4mr15019090ejb.312.1633830982264; Sat, 09 Oct 2021 18:56:22 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id x11sm1877253edj.62.2021.10.09.18.56.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Oct 2021 18:56:21 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v3 12/13] dt-bindings: net: dsa: qca8k: document support for qca8328 Date: Sun, 10 Oct 2021 03:56:02 +0200 Message-Id: <20211010015603.24483-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211010015603.24483-1-ansuelsmth@gmail.com> References: <20211010015603.24483-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org QCA8328 is the bigger brother of qca8327. Document the new compatible binding and add some information to understand the various switch compatible. Signed-off-by: Ansuel Smith --- Documentation/devicetree/bindings/net/dsa/qca8k.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index 71cd45818430..e6b580d815c2 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -3,9 +3,10 @@ Required properties: - compatible: should be one of: - "qca,qca8327" - "qca,qca8334" - "qca,qca8337" + "qca,qca8328": referenced as AR8328(N)-AK1(A/B) QFN 176 pin package + "qca,qca8327": referenced as AR8327(N)-AL1A DR-QFN 148 pin package + "qca,qca8334": referenced as QCA8334-AL3C QFN 88 pin package + "qca,qca8337": referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package - #size-cells: must be 0 - #address-cells: must be 1 From patchwork Sun Oct 10 01:56:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12548225 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 679CAC433EF for ; Sun, 10 Oct 2021 01:57:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4D44860F5C for ; Sun, 10 Oct 2021 01:57:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230353AbhJJB7M (ORCPT ); Sat, 9 Oct 2021 21:59:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230254AbhJJB6Z (ORCPT ); Sat, 9 Oct 2021 21:58:25 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB62BC06177B; Sat, 9 Oct 2021 18:56:24 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id a25so36067227edx.8; Sat, 09 Oct 2021 18:56:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=65S6lCh47tZ5HxQyo6DocfizCuDWrcJIBiYIGFhvY1k=; b=mJWQtEL0O+3B0eLbY62Rh4f1pwQ7EXajJNKfLKm+Qo0CjYjQzRvwMYFEBmbCX4VccU PtxrHPANjnZF8Ybbs3SrpC/4iAoZZjl5xQ9fgxE32YHjWaOIl83rL0UOBC0OJgV8SBIf 7ChvswFvD4mGjV85RPTl7vUDPX/dqzPLk98zzkhlwNFI5F67QvP9WRhkfFYlnj+LifAR dHXV6U4su96n/9v3hUAErwokU7SB/h0sfm4Es7L2UPkxqnPGx/XUKKXDD0535Vzlm8IW 8/Qjqes1gIZERVtH7koafHvPbbfCYCLKOJoRehekKwaldLlOzmaq598PDcSM81dGp/jd nGFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=65S6lCh47tZ5HxQyo6DocfizCuDWrcJIBiYIGFhvY1k=; b=PZ1m8wp5MnzKo8CjTxZbZ31CN6i6jPAzLtveH437GYJ/USCEdT62HRI6v06wszcAX8 obvop6spYbIJheWQJSudimKCTYaE57PRzrgfP+RMlgHPARKqnNuIP8eX0zfDPkD3m+Hm r+FaqkLbG4OiwSf9tak+CnVycKcOvI/ONNpQchckfknT4fD1z0lTz0sdjlhyWuBgPfUn hhlANdrcj+7Yc3zucFfnT53wzxIngS2SFYfWVJ/k/gSQPd1x+DFB5gylbMnBKGknphMz liCBrEE4mnVZfU92Ogny0WDy0XYIcghPhNd0THjqq4uU7ZWC3hZU+duPUzRMbEYwS8ov AvRA== X-Gm-Message-State: AOAM532qPTr9aV0orpOobxvWIUDLfreL8y9zXvTQbXWXPcKjH32/9uh0 g6g5M8W4vrqnXUPzKepUBCY= X-Google-Smtp-Source: ABdhPJxMIt7F4ILICHqyAP5I4Py4EGQsUUf5FxCti1SBd22xO3sSAhGimgGMvv4FQEqyiIH61oXTiw== X-Received: by 2002:a50:cf4d:: with SMTP id d13mr28232129edk.50.1633830983188; Sat, 09 Oct 2021 18:56:23 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id x11sm1877253edj.62.2021.10.09.18.56.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Oct 2021 18:56:22 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v3 13/13] drivers: net: dsa: qca8k: set internal delay also for sgmii Date: Sun, 10 Oct 2021 03:56:03 +0200 Message-Id: <20211010015603.24483-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211010015603.24483-1-ansuelsmth@gmail.com> References: <20211010015603.24483-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org QCA original code report port instability and sa that SGMII also require to set internal delay. Generalize the rgmii delay function and apply the advised value if they are not defined in DT. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 102 +++++++++++++++++++++++++--------------- drivers/net/dsa/qca8k.h | 2 + 2 files changed, 67 insertions(+), 37 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 7c68c272ce3a..21776826bf2e 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1164,13 +1164,67 @@ qca8k_setup(struct dsa_switch *ds) return 0; } +static void +qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, struct dsa_port *dp, + u32 reg, const struct phylink_link_state *state) +{ + u32 delay, val = 0; + int ret; + + if (state->interface == PHY_INTERFACE_MODE_RGMII_ID || + state->interface == PHY_INTERFACE_MODE_RGMII_TXID || + state->interface == PHY_INTERFACE_MODE_SGMII) { + if (of_property_read_u32(dp->dn, "tx-internal-delay-ps", &delay)) + delay = 1; + else + /* Switch regs accept value in ns, convert ps to ns */ + delay = delay / 1000; + + if (delay > QCA8K_MAX_DELAY) { + dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value"); + delay = 3; + } + + val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) | + QCA8K_PORT_PAD_RGMII_TX_DELAY_EN; + } + + if (state->interface == PHY_INTERFACE_MODE_RGMII_ID || + state->interface == PHY_INTERFACE_MODE_RGMII_RXID || + state->interface == PHY_INTERFACE_MODE_SGMII) { + if (of_property_read_u32(dp->dn, "rx-internal-delay-ps", &delay)) + delay = 2; + else + /* Switch regs accept value in ns, convert ps to ns */ + delay = delay / 1000; + + if (delay > QCA8K_MAX_DELAY) { + dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value"); + delay = 3; + } + + val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) | + QCA8K_PORT_PAD_RGMII_RX_DELAY_EN; + } + + /* Set RGMII delay based on the selected values */ + ret = qca8k_rmw(priv, reg, + QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK | + QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK | + QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK | + QCA8K_PORT_PAD_RGMII_RX_DELAY_EN, + val); + if (ret) + dev_err(priv->dev, "Failed to set internal delay for CPU port %d", dp->index); +} + static void qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, const struct phylink_link_state *state) { struct qca8k_priv *priv = ds->priv; struct dsa_port *dp; - u32 reg, val, delay; + u32 reg, val; int ret; switch (port) { @@ -1222,44 +1276,11 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, case PHY_INTERFACE_MODE_RGMII_TXID: case PHY_INTERFACE_MODE_RGMII_RXID: dp = dsa_to_port(ds, port); - val = QCA8K_PORT_PAD_RGMII_EN; - - if (state->interface == PHY_INTERFACE_MODE_RGMII_ID || - state->interface == PHY_INTERFACE_MODE_RGMII_TXID) { - if (of_property_read_u32(dp->dn, "tx-internal-delay-ps", &delay)) - delay = 1; - else - /* Switch regs accept value in ns, convert ps to ns */ - delay = delay / 1000; - - if (delay > QCA8K_MAX_DELAY) { - dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value"); - delay = 3; - } - - val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) | - QCA8K_PORT_PAD_RGMII_TX_DELAY_EN; - } - if (state->interface == PHY_INTERFACE_MODE_RGMII_ID || - state->interface == PHY_INTERFACE_MODE_RGMII_RXID) { - if (of_property_read_u32(dp->dn, "rx-internal-delay-ps", &delay)) - delay = 2; - else - /* Switch regs accept value in ns, convert ps to ns */ - delay = delay / 1000; - - if (delay > QCA8K_MAX_DELAY) { - dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value"); - delay = 3; - } - - val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) | - QCA8K_PORT_PAD_RGMII_RX_DELAY_EN; - } + qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN); - /* Set RGMII delay based on the selected values */ - qca8k_write(priv, reg, val); + /* Configure rgmii delay from dp or taking advised values */ + qca8k_mac_config_setup_internal_delay(priv, dp, reg, state); /* QCA8337 requires to set rgmii rx delay for all ports. * This is enabled through PORT5_PAD_CTRL for all ports, @@ -1341,6 +1362,13 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE | QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE, val); + + /* From original code is reported port instability as SGMII also + * require delay set. Apply advised values here or take them from DT. + */ + if (state->interface == PHY_INTERFACE_MODE_SGMII) + qca8k_mac_config_setup_internal_delay(priv, dp, reg, state); + break; default: dev_err(ds->dev, "xMII mode %s not supported for port %d\n", diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index c032db5e0d41..92867001cc34 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -39,7 +39,9 @@ #define QCA8K_REG_PORT5_PAD_CTRL 0x008 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c #define QCA8K_PORT_PAD_RGMII_EN BIT(26) +#define QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK GENMASK(23, 22) #define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) ((x) << 22) +#define QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK GENMASK(21, 20) #define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) ((x) << 20) #define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25) #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)