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Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel Subject: [PATCH v8 1/8] RISC-V: Enable CPU_IDLE drivers Date: Mon, 11 Oct 2021 13:48:13 +0530 Message-Id: <20211011081820.1135261-2-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011081820.1135261-1-anup.patel@wdc.com> References: <20211011081820.1135261-1-anup.patel@wdc.com> X-ClientProxiedBy: MA1PR01CA0159.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::29) To CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) MIME-Version: 1.0 Received: from wdc.com (122.171.184.84) by MA1PR01CA0159.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4587.18 via Frontend Transport; Mon, 11 Oct 2021 08:18:48 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 43dbe2d9-f419-4a92-2662-08d98c8fc323 X-MS-TrafficTypeDiagnostic: CO6PR04MB8331: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:3044; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: s4eJ45iqp2rbX1rDRZFmYkbuN94Rj/tG4GB3rRJYCV3sHcOo7/zxC3ntr8dQnLSsGCHPfGf1Y9Y29gYHf3EJRH6bTW33Syt6chJbmctUQDt7Ak5gC2Af87MhSWDgaZDKQU/PbDOBM+mz9w1vr1bkeVFw7KSUb086qOHH6hKUCVgt5lkDrXDqqyksTdZOXUzycWGE6bFnEffVWB64HIMf+zEJzPedxU6Z+OttrMkUVgDe2/rRIPA/1T8tn3Tn39Ln6fHTPuFwuX7k9uYVwGuhtkNKxtOGPNxFpIFMDI4E/ufpMt9aKplJiCZu1CWFLKDmKAKe01mdsV1N1ig5KMyB36hYb/W4HqS6fTaiY+s+8Y7qgSGN8H3XpLYAw4C2SJ40SdrYR9cbyr1orQ51evs3DDzu8vqDXJaKZOF/39Kcz7bhXVHVv5KF5gi01xF5vzLIddT+48Z99FME537HoqV9V1jmwQf8rqlPTrRoBPd8qAQhYrf2HXn24TWaosNJgm8+R8ONzeprOzOzayleFSntqdhe0c2/OtTvITm6C1d0hnaaiG2z+jEtU0RDKqz3gHEij4lVZaENn8jI58N0JyxX5WrPyJdbD+rs+ZyXOnOax539LFsVffSzsspxWcA3CWa1T1JTL/zixNmrW5uy3FhuX1NX5b6DjMae5Cd48qSKCGbmG87ivMsgYUrHhNOlYrBz8XX7hyopdUcik4PEfI/SBA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CO6PR04MB7812.namprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(366004)(956004)(110136005)(2616005)(2906002)(55016002)(44832011)(316002)(6666004)(54906003)(5660300002)(83380400001)(38350700002)(38100700002)(8676002)(26005)(86362001)(7416002)(1076003)(36756003)(508600001)(66946007)(8886007)(66556008)(4326008)(66476007)(8936002)(186003)(52116002)(7696005);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Nu70Uc2njrs3T84P4T+0bm3kdd1HwXpWtUSapdKcOknEyok+UOEasCBi4xJ8sgZ6iph4SgWv3dzmkGgocS0I7oevC6535z9ebIx47Rnbg/hC9sLceQhh7Lkp3+LJwF7BbvQm+LF+mX2ORkiNgDgm3gSVNtoDalg8B/ciP9bSS3/fCz/lNuGB/pL2b06/v0m9bYFJajpINijUiBG2z4GlstnXw4QRlpLxsYHl+UdqVX+Oj6zpOLp+xc1s5Pya62KHJ0cFvksyUC7+P7ohP6mcM9e5BF9gPv01Lrpftc4xsXLVu1XO7GPA0TzToRXvE6g2fpK8vuzNaaRX+OKNQSorEcWsTdQPnIGy0CYDXCV1kyIjMZuFjwwiXictVR+gxnpq2aueifA7ozw4DGyj6QFExpMPdPztgngiDx8a4asezGF56AzlUIVBv4JvFQZzf42rEwTaVUCXxytibC7PQzLJu2sRqaPgquAKFRNIThSwwnUSoz2PFV7pIy4YrMx0CvO49seEKuWQ8GuRCNGbOMR/mtPkBZwOc9C76mWeXn+bgcUHG9k1JvhG2UO9Ld3NNrYXP2vmUd7LAjetdCOEgZ/DFhXYsNfj4IGp/inVx4ZASIlU4NVwy1N6hgkdTFmItkfbvw/IHZmn7yZzZDCZ9f+r7WI85mWgJWpWi7K7S7zsxpd3DutodUadxLkXCf4ETZrjXCZTS6LgXrm09M0a/un+VCDsU9pIsAYc46+8grt/dd91rpwYOUQ8QR/aB45ziYDxwSPPGii+mj+1moe6n24NJZbrJkDcz/A0KnFJCzZbmmJtCgrgHNQDMx7rwQOnvMWBTUtlUMcYmhr9bmMAp/axrNnA5iqQfBgm62dUwGdEBysKBUkhLa74AuloP7pBzJ0p1+tMSENDW9rWGtxDU1TjAifms/RihprwSY/i4aaYGHtQDL9cNHKICPagAPUhKGjrYBgZUG9nNZKDGxg+T8pRlJID9LnVkHtcphhZXxSIMsV35T1Jawn9/KCTIXWzkE1oTW4PDHq7Si20AE6JsZHfgr/8Z3QDFRK0jw2xWUODYDSrhDqefgE/QWdxCHvPPnbDjKqghUrol01vei13/xc+Vo5K0t1WOAsKlkjKie4aWNVqN0tMS/oEuPGFIQO1WD8Tq0Hp2wVmoMj2gpouCI1tLIcwUT3mTDMnsf6ndLxFcWSV650FK5LesUvbivzw8LfRCrBVIAVR61uvLzO28KrN3pOHhdq4dDXtmG0C/iiC4Z6FVia30WLSq9cw86cSypWGhVd1elEY2F0q2qbrrT8eHk7wzpFKbzGmx46rpY1yrC5mxfXlfbvrkOqSnQ3QFlyC X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 43dbe2d9-f419-4a92-2662-08d98c8fc323 X-MS-Exchange-CrossTenant-AuthSource: CO6PR04MB7812.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Oct 2021 08:18:53.4844 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: rSa1TPvwJK4uDhBRDJE8wrL0D0VIzy/5zEovFMQM9BSn6JhCCoRjr2HqQSKEGGPjjVSblGyEwLP+20FkhRSiWw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR04MB8331 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org We force select CPU_PM and provide asm/cpuidle.h so that we can use CPU IDLE drivers for Linux RISC-V kernel. Signed-off-by: Anup Patel --- arch/riscv/Kconfig | 7 +++++++ arch/riscv/configs/defconfig | 1 + arch/riscv/configs/rv32_defconfig | 1 + arch/riscv/include/asm/cpuidle.h | 24 ++++++++++++++++++++++++ arch/riscv/kernel/process.c | 3 ++- 5 files changed, 35 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/cpuidle.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 8de2afb460f7..d02f1f5a2431 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -46,6 +46,7 @@ config RISCV select CLONE_BACKWARDS select CLINT_TIMER if !MMU select COMMON_CLK + select CPU_PM if CPU_IDLE select EDAC_SUPPORT select GENERIC_ARCH_TOPOLOGY if SMP select GENERIC_ATOMIC64 if !64BIT @@ -564,5 +565,11 @@ source "kernel/power/Kconfig" endmenu +menu "CPU Power Management" + +source "drivers/cpuidle/Kconfig" + +endmenu + source "arch/riscv/kvm/Kconfig" source "drivers/firmware/Kconfig" diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index be21f54e9b91..39b4c32e7997 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -20,6 +20,7 @@ CONFIG_SOC_SIFIVE=y CONFIG_SOC_VIRT=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y +CONFIG_CPU_IDLE=y CONFIG_VIRTUALIZATION=y CONFIG_KVM=y CONFIG_JUMP_LABEL=y diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig index ad01f50c98f1..fed827c82a9e 100644 --- a/arch/riscv/configs/rv32_defconfig +++ b/arch/riscv/configs/rv32_defconfig @@ -20,6 +20,7 @@ CONFIG_SOC_VIRT=y CONFIG_ARCH_RV32I=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y +CONFIG_CPU_IDLE=y CONFIG_VIRTUALIZATION=y CONFIG_KVM=y CONFIG_JUMP_LABEL=y diff --git a/arch/riscv/include/asm/cpuidle.h b/arch/riscv/include/asm/cpuidle.h new file mode 100644 index 000000000000..71fdc607d4bc --- /dev/null +++ b/arch/riscv/include/asm/cpuidle.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Allwinner Ltd + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + */ + +#ifndef _ASM_RISCV_CPUIDLE_H +#define _ASM_RISCV_CPUIDLE_H + +#include +#include + +static inline void cpu_do_idle(void) +{ + /* + * Add mb() here to ensure that all + * IO/MEM accesses are completed prior + * to entering WFI. + */ + mb(); + wait_for_interrupt(); +} + +#endif diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 03ac3aa611f5..504b496787aa 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -23,6 +23,7 @@ #include #include #include +#include register unsigned long gp_in_global __asm__("gp"); @@ -37,7 +38,7 @@ extern asmlinkage void ret_from_kernel_thread(void); void arch_cpu_idle(void) { - wait_for_interrupt(); + cpu_do_idle(); raw_local_irq_enable(); } From patchwork Mon Oct 11 08:18:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12549353 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BC51C433F5 for ; Mon, 11 Oct 2021 08:19:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5389D60EB1 for ; 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Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel Subject: [PATCH v8 2/8] RISC-V: Rename relocate() and make it global Date: Mon, 11 Oct 2021 13:48:14 +0530 Message-Id: <20211011081820.1135261-3-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011081820.1135261-1-anup.patel@wdc.com> References: <20211011081820.1135261-1-anup.patel@wdc.com> X-ClientProxiedBy: MA1PR01CA0159.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::29) To CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) MIME-Version: 1.0 Received: from wdc.com (122.171.184.84) by MA1PR01CA0159.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4587.18 via Frontend Transport; Mon, 11 Oct 2021 08:18:53 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8a50a941-8b21-4f09-fb76-08d98c8fc644 X-MS-TrafficTypeDiagnostic: CO6PR04MB8345: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:3276; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eHTejd1yQGiNE/Aix+1jdRXaDyoGZlA6fmDZeABL6A1uAwDUPc/BsNY3e+hRsTo8hTWbCehkoStHNkA10H4rQIPPRXbMqk9zNDaj2+TLoa3rUjkebvnJ5t95bSSuMbF2Psj3hmie7zlFb+ru+/oGryGDaqZRUyva+CwRqhcmfAirGjsk+7FlB79xWWigG/DwPon5jv8nU7oP4y8hcPDxI0MKcXs6+4+93WIIhM0gtejt++OePeA0gHlY8N+VJqhDu0Wm3eJkTJllidf7h3fOD+WTvaImTsxdHkM1+nq1qLuZa9VKcrkiEa5axDOu8y10V3w1xTK7hAofFxoS2MpJR9N70pqmGlpkwFKhCaRqiwopAYO5PCwIuW3QBvUP63Dnngc0+z2k3lnbcAYmn0cI5cmEINdiTvbTjWwC5w46GxLfg3SP9JkagKYAB5busQPO6alUeanZjtSzTyFfT3Z8heHshqh5dJ+SbBOIFiL1leAYc+N61qSzFJ4wPiDOR2IDY2kWmAzmUITxGjHQGlHov7mAs+Mb/Yi3gnPSA2aTNiQMnqOkIg/qPL9JqKGUvPVLNA6xmLKZZ4ORvWYD3ylC6HDoY3n6syUU0Fk7hYUWVdK+xLuUp71FN6drr4UzAVoUBVxkpZ9F37WnBzvlgFCM8tUvAfhjoejhyk2+PJUnEzb6ZqbXCR8Qpj0/K7vhWqfhal7RUDQxiX3YS/RaOAH6Gw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CO6PR04MB7812.namprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(366004)(186003)(54906003)(2616005)(956004)(5660300002)(2906002)(26005)(6666004)(8886007)(38350700002)(38100700002)(110136005)(4326008)(8676002)(508600001)(7416002)(44832011)(316002)(8936002)(7696005)(52116002)(1076003)(55016002)(66946007)(36756003)(86362001)(83380400001)(66476007)(66556008);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: g6TWzDHI6Zjme1uemLT6FW0XsOUGXSmk1uZO5aUyLRFDF+bJPYzUT3UGC6+7Gh5fma1woayCTswtJmf2bVssiwxT3bQf58H6eBRwfjmSmsg78d5FZ4pHUIqhQf7+ExjShYq9u6O7+lProl7tvwtDq6/rboS47L8OvXa/AvVNHHFnkoNimxmEx24/ozc13suBDW2WDTmcbCD20mZTG6f2QuudGKbXpYI6+ozXgYOlAO+YkpoaCWHPdeqUQL6cwRsxJXDRpJNiNUw1p7vBuAL+6WtUwjp0T96BMiDkdVLKrQM6BuHKMP5kyK3pr5oyZu9nenznilJ1lsjhS1DRrhl59ecVlsesZ1FOETg0VAhrm++RYoQSi/TDr+Hu3efh54HwfB6M16UsVkHqZ845e7v3QEFlmdHGKObIGXq1XaXsL3r5MRlTPNr7ywgsr5GOGO6SbxH+TaBTId8L/jUKxwtMK5qXvX7rJvXrOgC9t6NEEHlEM7l9JxwVWTYpXNAFgDCU5EBdJvPZDc950Sb8+ASn4p8zfuFqsjXz+oh9KUyxWNEtGUi+Cq0W3/mhGpRtzQmEd67amShqeZdMjsi2LzzCYQldBWsmXd1oZ4a8sFe0tuLak3termWrQYOW+t3t1reykavuXjk64nPqNegzMD1XesSknTRweaZSSrErlNuzRUy50A/hyMOYJuLvuPB+VryoPUz0WGrK85Aeb0DfLeOwxZctbpU7+TB7azHcb3svyEfNYIJ6Dcvye7mPRh7a2nPcoaRPLFyizCFQq5g1waKEy6kd/oJy7l5RoMY7Z0pELlmeafR99uB+1hvZguuxfjGDxSPGUZQJNB9rJSlwUKyBc/VLkKVSPcdEV9e2SRbPys8cfXpL0KxKVDuTf8/MHbbAu1HMtNWC8hI/5Tg2xGQgr8fIPvTWy6v6NE2obDVPc7MBm1ywOU2bMaFPKN1UdFFqHkLhYijC3akQ7F9qwAR6uVhb/fcfOMRIKOlx3sCqeSLijHGsuMZZglKBYlR89OEzreXKalqgCgdf1JGW11dyD+23E1SmS7XgiaKrelJdh7cOP3JQo+whwdLEadiVIa4T7Qnnnt/jsQpI0dThSp/pzRIdm2YW/sj409Rx8dDaZXk1/pIutJBQQx9ijpApyRSotx04vykacvHOS0rcIMop5Asua48kAe3cOqwuQSAUV7ASRuDj3rMJMXXpDXm1BbyenvSy54dtPFhPIFjq1s+STP++Ahz/2dI28++mF8i/gHn3HNuQgvPgdnCBhrWiGn3qqe5nXC9Lg6S4YOOFQ8Z68x9J5RYSGn/TT5fLzalha50pD6RnUhsj4nfLRgsYz0lm X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8a50a941-8b21-4f09-fb76-08d98c8fc644 X-MS-Exchange-CrossTenant-AuthSource: CO6PR04MB7812.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Oct 2021 08:18:58.7811 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: dyINJ2BRgajV59UeAhmdjbnBRSeGeH4BQMovSvqKEUKCWFj0foirnZ5nyayBETceJrCz7+Uy6sltYIy8fG6bvw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR04MB8345 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The low-level relocate() function enables mmu and relocates execution to link-time addresses. We rename relocate() function to relocate_enable_mmu() function which is more informative. Also, the relocate_enable_mmu() function will be used in the resume path when a CPU wakes-up from a non-retentive suspend so we make it global symbol. Signed-off-by: Anup Patel --- arch/riscv/kernel/head.S | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index fce5184b22c3..8ff8412db99f 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -79,7 +79,8 @@ pe_head_start: .align 2 #ifdef CONFIG_MMU -relocate: + .global relocate_enable_mmu +relocate_enable_mmu: /* Relocate return address */ la a1, kernel_map XIP_FIXUP_OFFSET a1 @@ -174,7 +175,7 @@ secondary_start_common: /* Enable virtual memory and relocate to virtual address */ la a0, swapper_pg_dir XIP_FIXUP_OFFSET a0 - call relocate + call relocate_enable_mmu #endif call setup_trap_vector tail smp_callin @@ -311,7 +312,7 @@ clear_bss_done: #ifdef CONFIG_MMU la a0, early_pg_dir XIP_FIXUP_OFFSET a0 - call relocate + call relocate_enable_mmu #endif /* CONFIG_MMU */ call setup_trap_vector From patchwork Mon Oct 11 08:18:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12549355 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75EBAC433FE for ; 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dmarc=none action=none header.from=wdc.com; Received: from CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) by CO6PR04MB8345.namprd04.prod.outlook.com (2603:10b6:303:134::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4587.25; Mon, 11 Oct 2021 08:19:04 +0000 Received: from CO6PR04MB7812.namprd04.prod.outlook.com ([fe80::8100:4308:5b21:8d97]) by CO6PR04MB7812.namprd04.prod.outlook.com ([fe80::8100:4308:5b21:8d97%9]) with mapi id 15.20.4587.026; Mon, 11 Oct 2021 08:19:04 +0000 From: Anup Patel To: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Ulf Hansson , "Rafael J . Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel Subject: [PATCH v8 3/8] RISC-V: Add arch functions for non-retentive suspend entry/exit Date: Mon, 11 Oct 2021 13:48:15 +0530 Message-Id: <20211011081820.1135261-4-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011081820.1135261-1-anup.patel@wdc.com> References: <20211011081820.1135261-1-anup.patel@wdc.com> X-ClientProxiedBy: MA1PR01CA0159.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::29) To CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) MIME-Version: 1.0 Received: from wdc.com (122.171.184.84) by MA1PR01CA0159.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4587.18 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: zWm6OWkz9sp7agulNKccjKnAPny/sZye+pMHFNHahLPVGMiMGaFAzwlHos6W/8nX+HvCVpJvD1qLYfMcB/OhP45KZjipfHdLpyLpOdSfVoVgtDrsAC2NECyQJW6UbqYXrg3Bay9z75CKH0P79+MsuOszV3iVLaVr9tH/kHYaMMNHTg94yKGa0cEZBBIZkwOV9j3zOswTAkV+oW22MxlkkfOWKAfnogycBum4WckjB48pIpWSPYsNxat9j+fwToO0EMYt/wK2A8BIz4TMTHCZ70AwZVC9hZSBh14/5n2rg8YOE+Wdb59cZM6jSxnw6EqUjo/spqOKQRQP2+h6gNVp22kquMNUc/TIACJO79aMHqjWknwxC46AJsm8h0+N8hEHCxNP09xQNLgcMiwDaRu2qKf4sMnbfCKJoZD2TQN5izTevQYdSdRHVboemsETBm1dSglmopsrAV7VzTc6dWps1lQzVsR3us0NQ/fp3AqVtaYiL3KgMIOfioZrfms0FKB/rAXG5KQyWes3PMxokdQx6dc6cl2yqdYT+SwxxQv5ROR/c8zqI1DfcDMS+qLoFOi69UTSCfMHwuPv2UjBL61JYswhbgiOeXClMsHNdgSyIbX1qknqM/L82qbcFIYcd+fLn9XfeXfoIzbMjGHj3axBe1KPJTB5AJFRcsjMYE9BjGlPCGzclxCmjGn8vtG3FsDegxkfu5N+C3tUYTMK4HoMXo6XFVNe8wqnpzzSrNMtgOQIF8RF9kocyxPVu1pWJGBYHc10FtiuhZqwmiuUwzjxRG+Qr0l+YObhiCEen6exFO+FQ6cSTl+8iL6AzViSnV+S4+dmXtNyeEmcK6KJGeJq+KcDkl4kyFbNVBK3B7riUXbX4fqrJYbv25BodSKyWmXJqQ1eFVOGzO5mQdc3Jf4r3ooOfY9R8kj+9KD1R5t54VojP+bH/VsSrAkp3nhtzK2sN4frL3hAqzkjpXYu7s/yGkC2sGoQ8twxtCSi0ItWdIpZD3n7m2KPoBmRZgZWzEBfEifCfHIqU+dLEilJPtBFOmXHKYEanEh1P92kFLOENuRUDZmezRtTNnhbECPkf0lbeFGrQXvpb9R5K5fgvvTtEdx1cnW6s/NWB09gr4UUxOKd4ydAZibqHl6KrKGBb0XOFqFLGzOS0uBOFOjli04hYGVmwZt1iFFKMcdR0QAdIzntsDn/0Yi2vdCqalTJlzV5Nb9RvCyUwoZaI6LUJ0aFgNjAbtlYWA177rs5DTw/jRRDgKLoXbJlgtDlTfiAY0sSa7fqV+MdXfmvoBABR14zGjo6NJPXy/PT0sbyHfNj5u+q/JNuQlmJxJjWIRUQdk7g X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 95435e7a-3202-42da-6f90-08d98c8fc96c X-MS-Exchange-CrossTenant-AuthSource: CO6PR04MB7812.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Oct 2021 08:19:03.8588 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: IsVconLBuwsXTMUVKTRMWCD8GckgWv1XMMf3koQAdg6Q08uevOVIWGvjzH0AD0DKiyu8T6Lkvvy2ulJS7Z85lA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR04MB8345 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The hart registers and CSRs are not preserved in non-retentative suspend state so we provide arch specific helper functions which will save/restore hart context upon entry/exit to non-retentive suspend state. These helper functions can be used by cpuidle drivers for non-retentive suspend entry/exit. Signed-off-by: Anup Patel --- arch/riscv/include/asm/asm.h | 17 +++++ arch/riscv/include/asm/suspend.h | 35 +++++++++ arch/riscv/kernel/Makefile | 2 + arch/riscv/kernel/asm-offsets.c | 3 + arch/riscv/kernel/head.S | 11 --- arch/riscv/kernel/suspend.c | 86 +++++++++++++++++++++ arch/riscv/kernel/suspend_entry.S | 123 ++++++++++++++++++++++++++++++ 7 files changed, 266 insertions(+), 11 deletions(-) create mode 100644 arch/riscv/include/asm/suspend.h create mode 100644 arch/riscv/kernel/suspend.c create mode 100644 arch/riscv/kernel/suspend_entry.S diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h index 618d7c5af1a2..6c93f2806eb7 100644 --- a/arch/riscv/include/asm/asm.h +++ b/arch/riscv/include/asm/asm.h @@ -67,4 +67,21 @@ #error "Unexpected __SIZEOF_SHORT__" #endif +#ifdef __ASSEMBLY__ + +/* Common assembly source macros */ + +#ifdef CONFIG_XIP_KERNEL +.macro XIP_FIXUP_OFFSET reg + REG_L t0, _xip_fixup + add \reg, \reg, t0 +.endm +_xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET +#else +.macro XIP_FIXUP_OFFSET reg +.endm +#endif /* CONFIG_XIP_KERNEL */ + +#endif + #endif /* _ASM_RISCV_ASM_H */ diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h new file mode 100644 index 000000000000..63e9f434fb89 --- /dev/null +++ b/arch/riscv/include/asm/suspend.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + */ + +#ifndef _ASM_RISCV_SUSPEND_H +#define _ASM_RISCV_SUSPEND_H + +#include + +struct suspend_context { + /* Saved and restored by low-level functions */ + struct pt_regs regs; + /* Saved and restored by high-level functions */ + unsigned long scratch; + unsigned long tvec; + unsigned long ie; +#ifdef CONFIG_MMU + unsigned long satp; +#endif +}; + +/* Low-level CPU suspend entry function */ +int __cpu_suspend_enter(struct suspend_context *context); + +/* High-level CPU suspend which will save context and call finish() */ +int cpu_suspend(unsigned long arg, + int (*finish)(unsigned long arg, + unsigned long entry, + unsigned long context)); + +/* Low-level CPU resume entry function */ +int __cpu_resume_enter(unsigned long hartid, unsigned long context); + +#endif diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 38b555edb2ee..65bcd8e344b6 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -47,6 +47,8 @@ obj-$(CONFIG_SMP) += cpu_ops_spinwait.o obj-$(CONFIG_MODULES) += module.o obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o +obj-$(CONFIG_CPU_PM) += suspend_entry.o suspend.o + obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c index 24d3827e4837..47563a191951 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -12,6 +12,7 @@ #include #include #include +#include void asm_offsets(void); @@ -113,6 +114,8 @@ void asm_offsets(void) OFFSET(PT_BADADDR, pt_regs, badaddr); OFFSET(PT_CAUSE, pt_regs, cause); + OFFSET(SUSPEND_CONTEXT_REGS, suspend_context, regs); + OFFSET(KVM_ARCH_GUEST_ZERO, kvm_vcpu_arch, guest_context.zero); OFFSET(KVM_ARCH_GUEST_RA, kvm_vcpu_arch, guest_context.ra); OFFSET(KVM_ARCH_GUEST_SP, kvm_vcpu_arch, guest_context.sp); diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 8ff8412db99f..6cb6f6eec575 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -15,17 +15,6 @@ #include #include "efi-header.S" -#ifdef CONFIG_XIP_KERNEL -.macro XIP_FIXUP_OFFSET reg - REG_L t0, _xip_fixup - add \reg, \reg, t0 -.endm -_xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET -#else -.macro XIP_FIXUP_OFFSET reg -.endm -#endif /* CONFIG_XIP_KERNEL */ - __HEAD ENTRY(_start) /* diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c new file mode 100644 index 000000000000..49dddec30e99 --- /dev/null +++ b/arch/riscv/kernel/suspend.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + */ + +#include +#include +#include + +static void suspend_save_csrs(struct suspend_context *context) +{ + context->scratch = csr_read(CSR_SCRATCH); + context->tvec = csr_read(CSR_TVEC); + context->ie = csr_read(CSR_IE); + + /* + * No need to save/restore IP CSR (i.e. MIP or SIP) because: + * + * 1. For no-MMU (M-mode) kernel, the bits in MIP are set by + * external devices (such as interrupt controller, timer, etc). + * 2. For MMU (S-mode) kernel, the bits in SIP are set by + * M-mode firmware and external devices (such as interrupt + * controller, etc). + */ + +#ifdef CONFIG_MMU + context->satp = csr_read(CSR_SATP); +#endif +} + +static void suspend_restore_csrs(struct suspend_context *context) +{ + csr_write(CSR_SCRATCH, context->scratch); + csr_write(CSR_TVEC, context->tvec); + csr_write(CSR_IE, context->ie); + +#ifdef CONFIG_MMU + csr_write(CSR_SATP, context->satp); +#endif +} + +int cpu_suspend(unsigned long arg, + int (*finish)(unsigned long arg, + unsigned long entry, + unsigned long context)) +{ + int rc = 0; + struct suspend_context context = { 0 }; + + /* Finisher should be non-NULL */ + if (!finish) + return -EINVAL; + + /* Save additional CSRs*/ + suspend_save_csrs(&context); + + /* + * Function graph tracer state gets incosistent when the kernel + * calls functions that never return (aka finishers) hence disable + * graph tracing during their execution. + */ + pause_graph_tracing(); + + /* Save context on stack */ + if (__cpu_suspend_enter(&context)) { + /* Call the finisher */ + rc = finish(arg, __pa_symbol(__cpu_resume_enter), + (ulong)&context); + + /* + * Should never reach here, unless the suspend finisher + * fails. Successful cpu_suspend() should return from + * __cpu_resume_entry() + */ + if (!rc) + rc = -EOPNOTSUPP; + } + + /* Enable function graph tracer */ + unpause_graph_tracing(); + + /* Restore additional CSRs */ + suspend_restore_csrs(&context); + + return rc; +} diff --git a/arch/riscv/kernel/suspend_entry.S b/arch/riscv/kernel/suspend_entry.S new file mode 100644 index 000000000000..b8d20decfc28 --- /dev/null +++ b/arch/riscv/kernel/suspend_entry.S @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + */ + +#include +#include +#include +#include + + .text + .altmacro + .option norelax + +ENTRY(__cpu_suspend_enter) + /* Save registers (except A0 and T0-T6) */ + REG_S ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0) + REG_S sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0) + REG_S gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0) + REG_S tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0) + REG_S s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0) + REG_S s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0) + REG_S a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0) + REG_S a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0) + REG_S a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0) + REG_S a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0) + REG_S a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0) + REG_S a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0) + REG_S a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0) + REG_S s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0) + REG_S s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0) + REG_S s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0) + REG_S s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0) + REG_S s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0) + REG_S s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0) + REG_S s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0) + REG_S s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0) + REG_S s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0) + REG_S s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0) + + /* Save CSRs */ + csrr t0, CSR_EPC + REG_S t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0) + csrr t0, CSR_STATUS + REG_S t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0) + csrr t0, CSR_TVAL + REG_S t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0) + csrr t0, CSR_CAUSE + REG_S t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0) + + /* Return non-zero value */ + li a0, 1 + + /* Return to C code */ + ret +END(__cpu_suspend_enter) + +ENTRY(__cpu_resume_enter) + /* Load the global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + .option pop + +#ifdef CONFIG_MMU + /* Save A0 and A1 */ + add t0, a0, zero + add t1, a1, zero + + /* Enable MMU */ + la a0, swapper_pg_dir + XIP_FIXUP_OFFSET a0 + call relocate_enable_mmu + + /* Restore A0 and A1 */ + add a0, t0, zero + add a1, t1, zero +#endif + + /* Make A0 point to suspend context */ + add a0, a1, zero + + /* Restore CSRs */ + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0) + csrw CSR_EPC, t0 + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0) + csrw CSR_STATUS, t0 + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0) + csrw CSR_TVAL, t0 + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0) + csrw CSR_CAUSE, t0 + + /* Restore registers (except A0 and T0-T6) */ + REG_L ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0) + REG_L sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0) + REG_L gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0) + REG_L tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0) + REG_L s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0) + REG_L s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0) + REG_L a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0) + REG_L a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0) + REG_L a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0) + REG_L a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0) + REG_L a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0) + REG_L a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0) + REG_L a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0) + REG_L s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0) + REG_L s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0) + REG_L s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0) + REG_L s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0) + REG_L s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0) + REG_L s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0) + REG_L s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0) + REG_L s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0) + REG_L s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0) + REG_L s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0) + + /* Return zero value */ + add a0, zero, zero + + /* Return to C code */ + ret +END(__cpu_resume_enter) From patchwork Mon Oct 11 08:18:16 2021 Content-Type: text/plain; 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Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel Subject: [PATCH v8 4/8] RISC-V: Add SBI HSM suspend related defines Date: Mon, 11 Oct 2021 13:48:16 +0530 Message-Id: <20211011081820.1135261-5-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011081820.1135261-1-anup.patel@wdc.com> References: <20211011081820.1135261-1-anup.patel@wdc.com> X-ClientProxiedBy: MA1PR01CA0159.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::29) To CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) MIME-Version: 1.0 Received: from wdc.com (122.171.184.84) by MA1PR01CA0159.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4587.18 via Frontend Transport; Mon, 11 Oct 2021 08:19:04 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 69d3e582-d97e-48d3-09ab-08d98c8fcc7c X-MS-TrafficTypeDiagnostic: CO6PR04MB7874: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:220; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TORyZgBYYEiEGwwMwzkYxyDDEFRFAL9BNLAex8GSS97Cv00H6v/nFaHDYW+FuvQax6+P4mnc9s2QgHWtHStsUG08mIevqjP5PkxukiCGW6yezCy+HGqxQlx/lgBxHicNPYrJCj62XZ1T8vO5UNzh1CHlEOK8HdSDaIFkVQeiybX6Zj8ljih/GJoBgg2XmjCay2pQ03RvtdeNDkg5Y0TNSzO7nE4cGByLcpo/KUPqlStB45XXo62o03cgKAnUnQeMtJpqg2krT3QJngdJ0IdgWCCTQ68rbNsjXC76wPOKDqvAdQsXeJEfKDH1S7VIQOXFOk/Kc1vtXiZdjP5nkpVnmZ6JwLOg9FQu0dyZMiTjzUlcFFRBgxpKJHrYaBoRExz+1VmjqpaaM9EGldh3jR31JWknqoXD89/oL7aK3+uRA2w/O2AE6lJxhzuWngVj9x/4f5grWl2+6+RFBnRyj4y7XuHWkTHDtnKJPsH2ACchUourdEh5ouIzdV/UOWzcvNlh6TVPWNp0BqvnullvJ+9YJMzfxvTVXDeYSay/3WXh6FCxDDjE2MJk9ju3tf6zLDzaB3iTrKZXUGa80INSsQGnVMfNhBwWOEJ9OZBImnLIGHk/VctDGjjyY61UwnKI6olA7e41ZhhgjsmMf8p7dgb08IlOgZ5jR4vLdzorZW8Rej1XSVV0dO5Q2cX4s9YFvjbxkEEiGdyvNYDAVU2+It0YIw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CO6PR04MB7812.namprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(366004)(8886007)(26005)(83380400001)(186003)(86362001)(15650500001)(44832011)(508600001)(2906002)(956004)(4326008)(7416002)(2616005)(52116002)(38350700002)(66946007)(66556008)(316002)(54906003)(110136005)(6666004)(8676002)(5660300002)(1076003)(66476007)(38100700002)(7696005)(8936002)(36756003)(55016002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: lBAshW2gxms3Th0VvYlcQ9Hub3z1toMOeb/y6Ot6EGoliEwrFQtfLlvtdLdKWcgsr7D0TQox8bY1YDI6RvAC3fxocA+1sK7iFXks5/bErJK7V6on6oKDc/WuNO8ak2JUIo+ptzEUaSrQamXQ0PCNocJFx9U0VDAUCoFUjvy3HBwD679ORWdsQGuhW0LJoyvQ7qfycdtRsCltutK/nHvkmtm5YNyMxHWhHnhn3qM956n1pHScrqyXI0IaWwxM+8VCaZWYYk5In+/Fjid5vKVTdL9gDn0VESPoBKfhRnDg/hJVugX9l5b1hnVwLn7ZZPcjFm/WrzdlRua7XrLYRb8ayo8EAW3+H7EmLv7ioxm8QLe9nZ/G9p+Dv8Ju6CeuTVkVEkwnadED6dmBVdxOPW+dwlDPiFql7JFwN3CA7N5e3kyTaXuoao5mhmm1AeNoeRekH8z42f6c6zcipZVACtK1mv4D66Dx8W79DZrUApNB6ymv9KeG9jBNwp/rkDAzsv3dMfxhTYJ5d33uVB5I+XK4VRbT1bgslYZczTds6U9kte7/NWkWvIQvsmaMwC0klQy4GKiqZ1ZMgfI4NLJtAVSxdjkEOARLQpGOVL009NWBYiX3fHqD6xf1l/2uy7nRtedGwXxEg+1aa46lv+pTuTPY4a5/ekhXJAhd0OaVqNbBn5JlmoMqMaeJ1AvA8Cp/inXj3fNuX0rVgeQYwzvkmeUH3SmufknlDLExDsO6ZW1vRAaV+GF1fa0lJZCyRvwHIdnCGxCjd9maKbF7fjcv+z6YVepLvePBwSI9ApR6iVwHwCFDav2Sl+BWkSfJulkKix1EW3rjg7G7H+VzDgdzV+genq6BK0xOKLFY7hUgKL1o1+reJE5Iquvfh5CJeGvtj+PJZ4SaylKPSFtO+GkY8Ii1nUMKF4XtIYr+4/6bz/BIFhK4Uz3/vHxvhW/xZS67nlhf7Q0EbNwcmNyh9oNA9lJFvhscOFmVwNpy9dhDkN0aBSamyR1HC6wAq7D+qC08XMTelKU25Pw7iEHoONYKWqfivQrymse3LtUWV+1wpUmkts0bequulmHiERT2hSGIqI1VXf2aCitQUsdC4vxvHlwwyzTF8TkbDLnld3rRwm8+/ETYg2AvYZf50X/l0hJdMA5qLBATkH56rknM3yGYwFjexMvA8h5NuJ7kLuVLpYfK1wlQzl/bv/XruwcUo/l4obG57/DEE/B4yrtGlrZjJQXy/4yl7EKHczi1R9tRkjF3hFziDLtDT3AmYIQhdKBZz01C6x5k6qTaQl+3j/HJ+EX+bKgvzYmaBqi1gTyJmLQWFj/JcGmLw8+KX8uP5cDvNdzw X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 69d3e582-d97e-48d3-09ab-08d98c8fcc7c X-MS-Exchange-CrossTenant-AuthSource: CO6PR04MB7812.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Oct 2021 08:19:08.9793 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: GrwWmC4oGvEbE7BV+R8yYz/G3FNNUS7Bjnq5oMxtv5wSuL1duhuxzu8saPqyINEXZQGGMdKu8Uzb7lqKq2O8fg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR04MB7874 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org We add defines related to SBI HSM suspend call and also update HSM states naming as-per latest SBI specification. Signed-off-by: Anup Patel --- arch/riscv/include/asm/sbi.h | 27 ++++++++++++++++++++++----- arch/riscv/kernel/cpu_ops_sbi.c | 2 +- 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index a992faeded7e..ff5cecd13bda 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -62,15 +62,32 @@ enum sbi_ext_hsm_fid { SBI_EXT_HSM_HART_START = 0, SBI_EXT_HSM_HART_STOP, SBI_EXT_HSM_HART_STATUS, + SBI_EXT_HSM_HART_SUSPEND, }; -enum sbi_hsm_hart_status { - SBI_HSM_HART_STATUS_STARTED = 0, - SBI_HSM_HART_STATUS_STOPPED, - SBI_HSM_HART_STATUS_START_PENDING, - SBI_HSM_HART_STATUS_STOP_PENDING, +enum sbi_hsm_hart_state { + SBI_HSM_STATE_STARTED = 0, + SBI_HSM_STATE_STOPPED, + SBI_HSM_STATE_START_PENDING, + SBI_HSM_STATE_STOP_PENDING, + SBI_HSM_STATE_SUSPENDED, + SBI_HSM_STATE_SUSPEND_PENDING, + SBI_HSM_STATE_RESUME_PENDING, }; +#define SBI_HSM_SUSP_BASE_MASK 0x7fffffff +#define SBI_HSM_SUSP_NON_RET_BIT 0x80000000 +#define SBI_HSM_SUSP_PLAT_BASE 0x10000000 + +#define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000 +#define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE +#define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK +#define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT +#define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \ + SBI_HSM_SUSP_PLAT_BASE) +#define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \ + SBI_HSM_SUSP_BASE_MASK) + enum sbi_ext_srst_fid { SBI_EXT_SRST_RESET = 0, }; diff --git a/arch/riscv/kernel/cpu_ops_sbi.c b/arch/riscv/kernel/cpu_ops_sbi.c index 685fae72b7f5..5fd90f03a3e9 100644 --- a/arch/riscv/kernel/cpu_ops_sbi.c +++ b/arch/riscv/kernel/cpu_ops_sbi.c @@ -97,7 +97,7 @@ static int sbi_cpu_is_stopped(unsigned int cpuid) rc = sbi_hsm_hart_get_status(hartid); - if (rc == SBI_HSM_HART_STATUS_STOPPED) + if (rc == SBI_HSM_STATE_STOPPED) return 0; return rc; } From patchwork Mon Oct 11 08:18:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12549361 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF9C2C433EF for ; Mon, 11 Oct 2021 08:21:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BAB3E60ED4 for ; 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Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel Subject: [PATCH v8 5/8] cpuidle: Factor-out power domain related code from PSCI domain driver Date: Mon, 11 Oct 2021 13:48:17 +0530 Message-Id: <20211011081820.1135261-6-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011081820.1135261-1-anup.patel@wdc.com> References: <20211011081820.1135261-1-anup.patel@wdc.com> X-ClientProxiedBy: MA1PR01CA0159.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::29) To CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) MIME-Version: 1.0 Received: from wdc.com (122.171.184.84) by MA1PR01CA0159.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4587.18 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ZWkiN8/3e8M9Z44LUeOWg3DUyv8lLrQcAAMedLah5IgZkjKstwAzAUgjswms8L2gMSWJysHKhqBJ4EgcWIOTy6ZM9bsBDSlbNTgBBNNRC5VSryrdYD2IEp3YMgFhHc2mC4ztd6BjcsWNlSqbT4Ct90YPzih39iA3ZaytaGT0R4yKxhaumo9TeRZq+7JQ6XvbGxFi/jI+s2SZ6by0LMaLbuNhqcr/y654cQ9GfpBPX6sR+xQLQf7nym4bgDjamLBLBp8tIpJtyd6U92C+fpfLgNCmIxXMKFVb3DjeCQ+F0D+mkwohJYA4pCumo95wGvSGRDYgkRpx0H4cRoxezpmWfmvFsPBA1lFxuQxS2F4Z72IFpafoebPmfDDTy07giFB5d8a3gLIif0rEN2zBBrKZW81w2vjIS7En9AwrhUf2JdsoxbqFuMYNFgl9N9cfYGa5zdGcBKvL/iTWz10UDw7x2oUKdQzWidMosg2IAMRZxOgWgemrPKhK3vhOGP6uotxuziX74XKu3/heYAOyAmt/J3Aeq5gs/UWMaURpQW9QRj5OCnWGq8HH0429yTuYSuTfQQ6EHPFm1N4bX7/WkiaiNEX4UmtkpA/C67whRHQZEywLg2AzQh/9SipTAF6NtKGjI4b7f4elCozrG0sEUt5ymERW1+Kro5iC/X0IP2vCM7s0p8G7Pb+Qx01bD5oJjBvANZQb+04b7D3n0xFffnbTti5T/riO4PPEDlRhUmzNr1dOXEABLjhsKsvhW+nIjMnf3Aj4T8aN8RHhP2CEK/Pdzh3/lrdQ5CGr/e+kXrDAUgPtAFF5VmC1U1xnTQMFJnCIer5Uu3Z1R7cjSaaMY+1MuYzIQRyqpbaKu9vFEeY86AyYuiR6/deGa7VghRt0Hip8gCf1jon7Knz7PZMO8hcoIbUppCgpT2BlV7O2dOhKVY4rDi1A7+13Tg1I9j8s7IhJp0MeGHjVEG94vT3d0fvLP8sUs1KFeLIyV0uLT1T4Lf8DdUqg1zHHXnr/8ryUSta/cCMUblLVfC5GQVKNFi3xDOgB03+8ELuBSgEUYQj26iYxfyC0JJFjWkOe+oGIJgzMt5cj9xuogPvC1xqgCwlZxzAAIckdjY65Iw/EYOSltSaNv966PbEBOFI36rijYypIHep5sxiTlEzjY0bjboLkB7IO5+K0GtP+rJ8bWX+3RX0gC5188mKYQ3tZ8gSlKonYW2B2ntisYZo/RTp8Q9JaoIxhuhRAWsEV8eskJbTNGoE4Vj+z6GMOi042ZXVJ3z5mOfua+/DJeeSkTQZolNPo3dVmAr+h4QqJleXsCIcIsSuNhWnS6pYU3y6IXvKXLMds X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 09e310f5-4993-4459-6faa-08d98c8fcf83 X-MS-Exchange-CrossTenant-AuthSource: CO6PR04MB7812.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Oct 2021 08:19:14.1137 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: yIfZMF0PBh4XXG7a+oUx9K+/xOW94yhk+7nhlqPiWN/BSnHG3nqB/6pMX1GGLxr3yp2mC9bMEbujaPVZHmwHMg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR04MB8236 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The generic power domain related code in PSCI domain driver is largely independent of PSCI and can be shared with RISC-V SBI domain driver hence we factor-out this code into dt_idle_genpd.c and dt_idle_genpd.h. Signed-off-by: Anup Patel Reviewed-by: Ulf Hansson --- MAINTAINERS | 7 + drivers/cpuidle/Kconfig | 4 + drivers/cpuidle/Kconfig.arm | 1 + drivers/cpuidle/Makefile | 1 + drivers/cpuidle/cpuidle-psci-domain.c | 138 +------------------- drivers/cpuidle/cpuidle-psci.h | 15 ++- drivers/cpuidle/dt_idle_genpd.c | 177 ++++++++++++++++++++++++++ drivers/cpuidle/dt_idle_genpd.h | 50 ++++++++ 8 files changed, 258 insertions(+), 135 deletions(-) create mode 100644 drivers/cpuidle/dt_idle_genpd.c create mode 100644 drivers/cpuidle/dt_idle_genpd.h diff --git a/MAINTAINERS b/MAINTAINERS index 4ccf3bce5c23..e42c17f9a316 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4904,6 +4904,13 @@ S: Supported F: drivers/cpuidle/cpuidle-psci.h F: drivers/cpuidle/cpuidle-psci-domain.c +CPUIDLE DRIVER - DT IDLE PM DOMAIN +M: Ulf Hansson +L: linux-pm@vger.kernel.org +S: Supported +F: drivers/cpuidle/dt_idle_genpd.c +F: drivers/cpuidle/dt_idle_genpd.h + CRAMFS FILESYSTEM M: Nicolas Pitre S: Maintained diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig index c0aeedd66f02..f1afe7ab6b54 100644 --- a/drivers/cpuidle/Kconfig +++ b/drivers/cpuidle/Kconfig @@ -47,6 +47,10 @@ config CPU_IDLE_GOV_HALTPOLL config DT_IDLE_STATES bool +config DT_IDLE_GENPD + depends on PM_GENERIC_DOMAINS_OF + bool + menu "ARM CPU Idle Drivers" depends on ARM || ARM64 source "drivers/cpuidle/Kconfig.arm" diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm index 334f83e56120..be12a9ca78f0 100644 --- a/drivers/cpuidle/Kconfig.arm +++ b/drivers/cpuidle/Kconfig.arm @@ -27,6 +27,7 @@ config ARM_PSCI_CPUIDLE_DOMAIN bool "PSCI CPU idle Domain" depends on ARM_PSCI_CPUIDLE depends on PM_GENERIC_DOMAINS_OF + select DT_IDLE_GENPD default y help Select this to enable the PSCI based CPUidle driver to use PM domains, diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile index 26bbc5e74123..11a26cef279f 100644 --- a/drivers/cpuidle/Makefile +++ b/drivers/cpuidle/Makefile @@ -6,6 +6,7 @@ obj-y += cpuidle.o driver.o governor.o sysfs.o governors/ obj-$(CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED) += coupled.o obj-$(CONFIG_DT_IDLE_STATES) += dt_idle_states.o +obj-$(CONFIG_DT_IDLE_GENPD) += dt_idle_genpd.o obj-$(CONFIG_ARCH_HAS_CPU_RELAX) += poll_state.o obj-$(CONFIG_HALTPOLL_CPUIDLE) += cpuidle-haltpoll.o diff --git a/drivers/cpuidle/cpuidle-psci-domain.c b/drivers/cpuidle/cpuidle-psci-domain.c index ff2c3f8e4668..755bbdfc5b82 100644 --- a/drivers/cpuidle/cpuidle-psci-domain.c +++ b/drivers/cpuidle/cpuidle-psci-domain.c @@ -47,73 +47,14 @@ static int psci_pd_power_off(struct generic_pm_domain *pd) return 0; } -static int psci_pd_parse_state_nodes(struct genpd_power_state *states, - int state_count) -{ - int i, ret; - u32 psci_state, *psci_state_buf; - - for (i = 0; i < state_count; i++) { - ret = psci_dt_parse_state_node(to_of_node(states[i].fwnode), - &psci_state); - if (ret) - goto free_state; - - psci_state_buf = kmalloc(sizeof(u32), GFP_KERNEL); - if (!psci_state_buf) { - ret = -ENOMEM; - goto free_state; - } - *psci_state_buf = psci_state; - states[i].data = psci_state_buf; - } - - return 0; - -free_state: - i--; - for (; i >= 0; i--) - kfree(states[i].data); - return ret; -} - -static int psci_pd_parse_states(struct device_node *np, - struct genpd_power_state **states, int *state_count) -{ - int ret; - - /* Parse the domain idle states. */ - ret = of_genpd_parse_idle_states(np, states, state_count); - if (ret) - return ret; - - /* Fill out the PSCI specifics for each found state. */ - ret = psci_pd_parse_state_nodes(*states, *state_count); - if (ret) - kfree(*states); - - return ret; -} - -static void psci_pd_free_states(struct genpd_power_state *states, - unsigned int state_count) -{ - int i; - - for (i = 0; i < state_count; i++) - kfree(states[i].data); - kfree(states); -} - static int psci_pd_init(struct device_node *np, bool use_osi) { struct generic_pm_domain *pd; struct psci_pd_provider *pd_provider; struct dev_power_governor *pd_gov; - struct genpd_power_state *states = NULL; int ret = -ENOMEM, state_count = 0; - pd = kzalloc(sizeof(*pd), GFP_KERNEL); + pd = dt_idle_pd_alloc(np, psci_dt_parse_state_node); if (!pd) goto out; @@ -121,22 +62,6 @@ static int psci_pd_init(struct device_node *np, bool use_osi) if (!pd_provider) goto free_pd; - pd->name = kasprintf(GFP_KERNEL, "%pOF", np); - if (!pd->name) - goto free_pd_prov; - - /* - * Parse the domain idle states and let genpd manage the state selection - * for those being compatible with "domain-idle-state". - */ - ret = psci_pd_parse_states(np, &states, &state_count); - if (ret) - goto free_name; - - pd->free_states = psci_pd_free_states; - pd->name = kbasename(pd->name); - pd->states = states; - pd->state_count = state_count; pd->flags |= GENPD_FLAG_IRQ_SAFE | GENPD_FLAG_CPU_DOMAIN; /* Allow power off when OSI has been successfully enabled. */ @@ -149,10 +74,8 @@ static int psci_pd_init(struct device_node *np, bool use_osi) pd_gov = state_count > 0 ? &pm_domain_cpu_gov : NULL; ret = pm_genpd_init(pd, pd_gov, false); - if (ret) { - psci_pd_free_states(states, state_count); - goto free_name; - } + if (ret) + goto free_pd_prov; ret = of_genpd_add_provider_simple(np, pd); if (ret) @@ -166,12 +89,10 @@ static int psci_pd_init(struct device_node *np, bool use_osi) remove_pd: pm_genpd_remove(pd); -free_name: - kfree(pd->name); free_pd_prov: kfree(pd_provider); free_pd: - kfree(pd); + dt_idle_pd_free(pd); out: pr_err("failed to init PM domain ret=%d %pOF\n", ret, np); return ret; @@ -195,30 +116,6 @@ static void psci_pd_remove(void) } } -static int psci_pd_init_topology(struct device_node *np) -{ - struct device_node *node; - struct of_phandle_args child, parent; - int ret; - - for_each_child_of_node(np, node) { - if (of_parse_phandle_with_args(node, "power-domains", - "#power-domain-cells", 0, &parent)) - continue; - - child.np = node; - child.args_count = 0; - ret = of_genpd_add_subdomain(&parent, &child); - of_node_put(parent.np); - if (ret) { - of_node_put(node); - return ret; - } - } - - return 0; -} - static bool psci_pd_try_set_osi_mode(void) { int ret; @@ -282,7 +179,7 @@ static int psci_cpuidle_domain_probe(struct platform_device *pdev) goto no_pd; /* Link genpd masters/subdomains to model the CPU topology. */ - ret = psci_pd_init_topology(np); + ret = dt_idle_pd_init_topology(np); if (ret) goto remove_pd; @@ -314,28 +211,3 @@ static int __init psci_idle_init_domains(void) return platform_driver_register(&psci_cpuidle_domain_driver); } subsys_initcall(psci_idle_init_domains); - -struct device *psci_dt_attach_cpu(int cpu) -{ - struct device *dev; - - dev = dev_pm_domain_attach_by_name(get_cpu_device(cpu), "psci"); - if (IS_ERR_OR_NULL(dev)) - return dev; - - pm_runtime_irq_safe(dev); - if (cpu_online(cpu)) - pm_runtime_get_sync(dev); - - dev_pm_syscore_device(dev, true); - - return dev; -} - -void psci_dt_detach_cpu(struct device *dev) -{ - if (IS_ERR_OR_NULL(dev)) - return; - - dev_pm_domain_detach(dev, false); -} diff --git a/drivers/cpuidle/cpuidle-psci.h b/drivers/cpuidle/cpuidle-psci.h index d8e925e84c27..4e132640ed64 100644 --- a/drivers/cpuidle/cpuidle-psci.h +++ b/drivers/cpuidle/cpuidle-psci.h @@ -10,8 +10,19 @@ void psci_set_domain_state(u32 state); int psci_dt_parse_state_node(struct device_node *np, u32 *state); #ifdef CONFIG_ARM_PSCI_CPUIDLE_DOMAIN -struct device *psci_dt_attach_cpu(int cpu); -void psci_dt_detach_cpu(struct device *dev); + +#include "dt_idle_genpd.h" + +static inline struct device *psci_dt_attach_cpu(int cpu) +{ + return dt_idle_attach_cpu(cpu, "psci"); +} + +static inline void psci_dt_detach_cpu(struct device *dev) +{ + dt_idle_detach_cpu(dev); +} + #else static inline struct device *psci_dt_attach_cpu(int cpu) { return NULL; } static inline void psci_dt_detach_cpu(struct device *dev) { } diff --git a/drivers/cpuidle/dt_idle_genpd.c b/drivers/cpuidle/dt_idle_genpd.c new file mode 100644 index 000000000000..db385fd2507e --- /dev/null +++ b/drivers/cpuidle/dt_idle_genpd.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PM domains for CPUs via genpd. + * + * Copyright (C) 2019 Linaro Ltd. + * Author: Ulf Hansson + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + */ + +#define pr_fmt(fmt) "dt-idle-genpd: " fmt + +#include +#include +#include +#include +#include +#include +#include + +#include "dt_idle_genpd.h" + +static int pd_parse_state_nodes( + int (*parse_state)(struct device_node *, u32 *), + struct genpd_power_state *states, int state_count) +{ + int i, ret; + u32 state, *state_buf; + + for (i = 0; i < state_count; i++) { + ret = parse_state(to_of_node(states[i].fwnode), &state); + if (ret) + goto free_state; + + state_buf = kmalloc(sizeof(u32), GFP_KERNEL); + if (!state_buf) { + ret = -ENOMEM; + goto free_state; + } + *state_buf = state; + states[i].data = state_buf; + } + + return 0; + +free_state: + i--; + for (; i >= 0; i--) + kfree(states[i].data); + return ret; +} + +static int pd_parse_states(struct device_node *np, + int (*parse_state)(struct device_node *, u32 *), + struct genpd_power_state **states, + int *state_count) +{ + int ret; + + /* Parse the domain idle states. */ + ret = of_genpd_parse_idle_states(np, states, state_count); + if (ret) + return ret; + + /* Fill out the dt specifics for each found state. */ + ret = pd_parse_state_nodes(parse_state, *states, *state_count); + if (ret) + kfree(*states); + + return ret; +} + +static void pd_free_states(struct genpd_power_state *states, + unsigned int state_count) +{ + int i; + + for (i = 0; i < state_count; i++) + kfree(states[i].data); + kfree(states); +} + +void dt_idle_pd_free(struct generic_pm_domain *pd) +{ + pd_free_states(pd->states, pd->state_count); + kfree(pd->name); + kfree(pd); +} + +struct generic_pm_domain *dt_idle_pd_alloc(struct device_node *np, + int (*parse_state)(struct device_node *, u32 *)) +{ + struct generic_pm_domain *pd; + struct genpd_power_state *states = NULL; + int ret, state_count = 0; + + pd = kzalloc(sizeof(*pd), GFP_KERNEL); + if (!pd) + goto out; + + pd->name = kasprintf(GFP_KERNEL, "%pOF", np); + if (!pd->name) + goto free_pd; + + /* + * Parse the domain idle states and let genpd manage the state selection + * for those being compatible with "domain-idle-state". + */ + ret = pd_parse_states(np, parse_state, &states, &state_count); + if (ret) + goto free_name; + + pd->free_states = pd_free_states; + pd->name = kbasename(pd->name); + pd->states = states; + pd->state_count = state_count; + + pr_debug("alloc PM domain %s\n", pd->name); + return pd; + +free_name: + kfree(pd->name); +free_pd: + kfree(pd); +out: + pr_err("failed to alloc PM domain %pOF\n", np); + return NULL; +} + +int dt_idle_pd_init_topology(struct device_node *np) +{ + struct device_node *node; + struct of_phandle_args child, parent; + int ret; + + for_each_child_of_node(np, node) { + if (of_parse_phandle_with_args(node, "power-domains", + "#power-domain-cells", 0, &parent)) + continue; + + child.np = node; + child.args_count = 0; + ret = of_genpd_add_subdomain(&parent, &child); + of_node_put(parent.np); + if (ret) { + of_node_put(node); + return ret; + } + } + + return 0; +} + +struct device *dt_idle_attach_cpu(int cpu, const char *name) +{ + struct device *dev; + + dev = dev_pm_domain_attach_by_name(get_cpu_device(cpu), name); + if (IS_ERR_OR_NULL(dev)) + return dev; + + pm_runtime_irq_safe(dev); + if (cpu_online(cpu)) + pm_runtime_get_sync(dev); + + dev_pm_syscore_device(dev, true); + + return dev; +} + +void dt_idle_detach_cpu(struct device *dev) +{ + if (IS_ERR_OR_NULL(dev)) + return; + + dev_pm_domain_detach(dev, false); +} diff --git a/drivers/cpuidle/dt_idle_genpd.h b/drivers/cpuidle/dt_idle_genpd.h new file mode 100644 index 000000000000..a95483d08a02 --- /dev/null +++ b/drivers/cpuidle/dt_idle_genpd.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_IDLE_GENPD +#define __DT_IDLE_GENPD + +struct device_node; +struct generic_pm_domain; + +#ifdef CONFIG_DT_IDLE_GENPD + +void dt_idle_pd_free(struct generic_pm_domain *pd); + +struct generic_pm_domain *dt_idle_pd_alloc(struct device_node *np, + int (*parse_state)(struct device_node *, u32 *)); + +int dt_idle_pd_init_topology(struct device_node *np); + +struct device *dt_idle_attach_cpu(int cpu, const char *name); + +void dt_idle_detach_cpu(struct device *dev); + +#else + +static inline void dt_idle_pd_free(struct generic_pm_domain *pd) +{ +} + +static inline struct generic_pm_domain *dt_idle_pd_alloc( + struct device_node *np, + int (*parse_state)(struct device_node *, u32 *)) +{ + return NULL; +} + +static inline int dt_idle_pd_init_topology(struct device_node *np) +{ + return 0; +} + +static inline struct device *dt_idle_attach_cpu(int cpu, const char *name) +{ + return NULL; +} + +static inline void dt_idle_detach_cpu(struct device *dev) +{ +} + +#endif + +#endif From patchwork Mon Oct 11 08:18:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12549365 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06CBCC43219 for ; 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dmarc=none action=none header.from=wdc.com; Received: from CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) by CO6PR04MB7874.namprd04.prod.outlook.com (2603:10b6:5:35c::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4587.18; Mon, 11 Oct 2021 08:19:19 +0000 Received: from CO6PR04MB7812.namprd04.prod.outlook.com ([fe80::8100:4308:5b21:8d97]) by CO6PR04MB7812.namprd04.prod.outlook.com ([fe80::8100:4308:5b21:8d97%9]) with mapi id 15.20.4587.026; Mon, 11 Oct 2021 08:19:19 +0000 From: Anup Patel To: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Ulf Hansson , "Rafael J . Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel Subject: [PATCH v8 6/8] cpuidle: Add RISC-V SBI CPU idle driver Date: Mon, 11 Oct 2021 13:48:18 +0530 Message-Id: <20211011081820.1135261-7-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011081820.1135261-1-anup.patel@wdc.com> References: <20211011081820.1135261-1-anup.patel@wdc.com> X-ClientProxiedBy: MA1PR01CA0159.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::29) To CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) MIME-Version: 1.0 Received: from wdc.com (122.171.184.84) by MA1PR01CA0159.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4587.18 via Frontend Transport; Mon, 11 Oct 2021 08:19:14 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 17b0d34b-7fe6-4060-5dff-08d98c8fd291 X-MS-TrafficTypeDiagnostic: CO6PR04MB7874: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Xd8BnPrL7gm8/kgFMQ5wlbSgfyOCvTGyj9utvclMah9jn8/N/3pGGF3bOW+8y0km++8UVTrA1q9c2mH0B8ZXNZywAQvfQyjL0PX5C8/lp0L2Pf3f7IACW/2lXeySgc+hnPEsAho07OSqm2Oc5n1nsBU8qMTvlNskz3X6Orti87nRni1h1g+3avPJoNuWy2xOmDjJjX/PS/SRJ0SDVB4uH+1zpzmVCP2y477OmjeS4cV4ePVYvw7PxdMM5a8ueBtLdYAdJBl59ibw0t9BtW6Z/B3rjCLmIEg7Q8npgmP53snXubnHMtIAn2d2gMtucQwV0ysDJCUHRnSv9YUgdrkvL+1i5567pgu8jTOLxyu2Cd0+xsrHPT/3ABDkyNishGbNhAtJJljv0iCWI29FRyf1oEOhEWUAq+D/AyQWiAAG2raGNKiaH3OvUwv7IhIElQX1w2z6RilJJmvE7DTSrlZCbbFmyF9/YED7CRMO41U2n02Qa6YXdZJtzA21B0icnUBsHW/brra3uBlsiFqob1N6kUBgD1mvwuE3yfrCynNoLSweUE58UHxgxPY6lpYhcl/ql9QIPUJVAvMvdk2KeZbbbDrnIYVnKdmmGFL0rF2V9ZHMA2ffDkPmvaEVebQI69phF2zRVUyDHwAFlkqHa/q0PM/1pX1CSZH6N761Hi+8pRUdpftgFuM88kHyw24XVBQwwJrTH+n3qeQzzSFOLPAlJA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CO6PR04MB7812.namprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(366004)(8886007)(26005)(83380400001)(186003)(86362001)(44832011)(508600001)(2906002)(956004)(4326008)(7416002)(2616005)(52116002)(30864003)(38350700002)(66946007)(66556008)(316002)(54906003)(110136005)(8676002)(5660300002)(1076003)(66476007)(38100700002)(7696005)(8936002)(36756003)(55016002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: EEbYo4aMf1jUTK+lrLYBGlcJpB0wutq6ykm+tzQf2hiipeXLfoV62XvIBInmATe3KNyl7FPOOKK+IkRLH9PQt63F4+eqYmJNdaq0WPyEfh4cX20po+wpAfh7FYRzXsCiWt/vsst1xL+xzytycYwNelAFRslmln0mZMTuZcwm2/bqAZk+8Ts/fNrY+MwTnARJbj09Olu4lpetGJ2j0XSlT+uJj0D3ocKGwnK4m+e44ET0XNZLtXZM8oDqHlI80SHqqUq6Zmon9kvHIUIXd/DJg0RTS20OEa6FZ88Nf30vXHe5bFt4t+PAFeOMh8DjtA2Lw6JfWBnl3/uYZFT9b4NL/8I6jIDdi5lyRH2HTakL8N0uc0PtVX5Yo3u58QcwTOzoO/m7oFwBdQoiY9h4tsZe1b43x/wk9DRXzTcHvvfCZVGEo1C3PHgax9+yaiGdsPXgdb7dVObgzyxvU8g2n7XgKqg5WYdTS2XtYYS2yt4QbgpJGYRL3lar8fm1Nlaxj4LAIDges11F4w5q7poNf9VmHX/6qrjawrmzSIW/kMaiRSDljHIDVFMTD/ixZWlNg/NrwoGmR6q0PIX6xDeuIds6IDRTGICsJPFvHQHBCUb4IfYCgIpG9M58S36X4raltWzuYtQk6DNc6C1lK48AFESkgqISAY+vHSf3/Z75R+n+cO/G4xkmTSoVYPlXMvi5OEZmRhWVGylFidt4yHH5M4T8P4kkh7bMLmCOK5ivEdeFAblvWcEWSA3Once8YI+1LBwebjUuLeT2DVyUCENNezuEJtRN/wLnxtQqqJ3vDe5vhYVEW+xcCXyk0DIR7CnZRbEfwoN4+A/NCw8v992RqbVacsTu8SHag1eLu3RkMtM48yAC9Jf42Bmg9O34XA0WGMxEVqAMPbOJ088D+IaJt59s3TVNepO6eHmzggJx+WYApehZTOdt7g25+wx92g29lcsosXPVr9moYJ4jmDw2fhpBmC5LRVQmxuSQgJsfpUNsa/AfKBP+aZU4VlGd/WiVV77zqiX/lT/qUe/UZHHxUJ525cmTOa0hbFnG2yRsf8EoV0vO2x5R0qkiT74/iaBvkb9CAZU2xTxDTOcMmSXSZ9sESelvGdy7DIfZPh0mxCcf08WMO8rZyFaKF/tXDxuRgI3NZSOeb8+Hx6NU+0SnBsX1m4GMwyO52L3yIBK7m2pwfk8FFZd5azzaU3CwfI3Lj2AHVzTPw8AvwZmtsq2B9knLV5SdhncgrNZII5ZfXoApJ/PH1Y+ERN55W/v7oaRnIRbhl3bKvnV396BvaprY+D+cHI5Y378hNf8Z5qjNOMI8LC6rF4kokVlGMyoW/KicbC4B X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 17b0d34b-7fe6-4060-5dff-08d98c8fd291 X-MS-Exchange-CrossTenant-AuthSource: CO6PR04MB7812.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Oct 2021 08:19:19.4891 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: dZEU7NerURM4wAzwkiYsy/fBLmra+6fqKNXYMYf5cUNrhguSo7CobTBrQXkKp754HsoYJrmH7ecrNq2Ot7LcyA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR04MB7874 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The RISC-V SBI HSM extension provides HSM suspend call which can be used by Linux RISC-V to enter platform specific low-power state. This patch adds a CPU idle driver based on RISC-V SBI calls which will populate idle states from device tree and use SBI calls to entry these idle states. Signed-off-by: Anup Patel --- MAINTAINERS | 7 + drivers/cpuidle/Kconfig | 5 + drivers/cpuidle/Kconfig.riscv | 15 + drivers/cpuidle/Makefile | 4 + drivers/cpuidle/cpuidle-riscv-sbi.c | 626 ++++++++++++++++++++++++++++ 5 files changed, 657 insertions(+) create mode 100644 drivers/cpuidle/Kconfig.riscv create mode 100644 drivers/cpuidle/cpuidle-riscv-sbi.c diff --git a/MAINTAINERS b/MAINTAINERS index e42c17f9a316..becbb4e273e0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4911,6 +4911,13 @@ S: Supported F: drivers/cpuidle/dt_idle_genpd.c F: drivers/cpuidle/dt_idle_genpd.h +CPUIDLE DRIVER - RISC-V SBI +M: Anup Patel +L: linux-pm@vger.kernel.org +L: linux-riscv@lists.infradead.org +S: Maintained +F: drivers/cpuidle/cpuidle-riscv-sbi.c + CRAMFS FILESYSTEM M: Nicolas Pitre S: Maintained diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig index f1afe7ab6b54..ff71dd662880 100644 --- a/drivers/cpuidle/Kconfig +++ b/drivers/cpuidle/Kconfig @@ -66,6 +66,11 @@ depends on PPC source "drivers/cpuidle/Kconfig.powerpc" endmenu +menu "RISC-V CPU Idle Drivers" +depends on RISCV +source "drivers/cpuidle/Kconfig.riscv" +endmenu + config HALTPOLL_CPUIDLE tristate "Halt poll cpuidle driver" depends on X86 && KVM_GUEST diff --git a/drivers/cpuidle/Kconfig.riscv b/drivers/cpuidle/Kconfig.riscv new file mode 100644 index 000000000000..78518c26af74 --- /dev/null +++ b/drivers/cpuidle/Kconfig.riscv @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# RISC-V CPU Idle drivers +# + +config RISCV_SBI_CPUIDLE + bool "RISC-V SBI CPU idle Driver" + depends on RISCV_SBI + select DT_IDLE_STATES + select CPU_IDLE_MULTIPLE_DRIVERS + select DT_IDLE_GENPD if PM_GENERIC_DOMAINS_OF + help + Select this option to enable RISC-V SBI firmware based CPU idle + driver for RISC-V systems. This drivers also supports hierarchical + DT based layout of the idle state. diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile index 11a26cef279f..d103342b7cfc 100644 --- a/drivers/cpuidle/Makefile +++ b/drivers/cpuidle/Makefile @@ -35,3 +35,7 @@ obj-$(CONFIG_MIPS_CPS_CPUIDLE) += cpuidle-cps.o # POWERPC drivers obj-$(CONFIG_PSERIES_CPUIDLE) += cpuidle-pseries.o obj-$(CONFIG_POWERNV_CPUIDLE) += cpuidle-powernv.o + +############################################################################### +# RISC-V drivers +obj-$(CONFIG_RISCV_SBI_CPUIDLE) += cpuidle-riscv-sbi.o diff --git a/drivers/cpuidle/cpuidle-riscv-sbi.c b/drivers/cpuidle/cpuidle-riscv-sbi.c new file mode 100644 index 000000000000..1f80e27c5cfb --- /dev/null +++ b/drivers/cpuidle/cpuidle-riscv-sbi.c @@ -0,0 +1,626 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RISC-V SBI CPU idle driver. + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + */ + +#define pr_fmt(fmt) "cpuidle-riscv-sbi: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dt_idle_states.h" +#include "dt_idle_genpd.h" + +struct sbi_cpuidle_data { + u32 *states; + struct device *dev; +}; + +struct sbi_domain_state { + bool available; + u32 state; +}; + +static DEFINE_PER_CPU_READ_MOSTLY(struct sbi_cpuidle_data, sbi_cpuidle_data); +static DEFINE_PER_CPU(struct sbi_domain_state, domain_state); +static bool sbi_cpuidle_use_osi; +static bool sbi_cpuidle_use_cpuhp; +static bool sbi_cpuidle_pd_allow_domain_state; + +static inline void sbi_set_domain_state(u32 state) +{ + struct sbi_domain_state *data = this_cpu_ptr(&domain_state); + + data->available = true; + data->state = state; +} + +static inline u32 sbi_get_domain_state(void) +{ + struct sbi_domain_state *data = this_cpu_ptr(&domain_state); + + return data->state; +} + +static inline void sbi_clear_domain_state(void) +{ + struct sbi_domain_state *data = this_cpu_ptr(&domain_state); + + data->available = false; +} + +static inline bool sbi_is_domain_state_available(void) +{ + struct sbi_domain_state *data = this_cpu_ptr(&domain_state); + + return data->available; +} + +static int sbi_suspend_finisher(unsigned long suspend_type, + unsigned long resume_addr, + unsigned long opaque) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_SUSPEND, + suspend_type, resume_addr, opaque, 0, 0, 0); + + return (ret.error) ? sbi_err_map_linux_errno(ret.error) : 0; +} + +static int sbi_suspend(u32 state) +{ + if (state & SBI_HSM_SUSP_NON_RET_BIT) + return cpu_suspend(state, sbi_suspend_finisher); + else + return sbi_suspend_finisher(state, 0, 0); +} + +static int sbi_cpuidle_enter_state(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int idx) +{ + u32 *states = __this_cpu_read(sbi_cpuidle_data.states); + + return CPU_PM_CPU_IDLE_ENTER_PARAM(sbi_suspend, idx, states[idx]); +} + +static int __sbi_enter_domain_idle_state(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int idx, + bool s2idle) +{ + struct sbi_cpuidle_data *data = this_cpu_ptr(&sbi_cpuidle_data); + u32 *states = data->states; + struct device *pd_dev = data->dev; + u32 state; + int ret; + + ret = cpu_pm_enter(); + if (ret) + return -1; + + /* Do runtime PM to manage a hierarchical CPU toplogy. */ + rcu_irq_enter_irqson(); + if (s2idle) + dev_pm_genpd_suspend(pd_dev); + else + pm_runtime_put_sync_suspend(pd_dev); + rcu_irq_exit_irqson(); + + if (sbi_is_domain_state_available()) + state = sbi_get_domain_state(); + else + state = states[idx]; + + ret = sbi_suspend(state) ? -1 : idx; + + rcu_irq_enter_irqson(); + if (s2idle) + dev_pm_genpd_resume(pd_dev); + else + pm_runtime_get_sync(pd_dev); + rcu_irq_exit_irqson(); + + cpu_pm_exit(); + + /* Clear the domain state to start fresh when back from idle. */ + sbi_clear_domain_state(); + return ret; +} + +static int sbi_enter_domain_idle_state(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int idx) +{ + return __sbi_enter_domain_idle_state(dev, drv, idx, false); +} + +static int sbi_enter_s2idle_domain_idle_state(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int idx) +{ + return __sbi_enter_domain_idle_state(dev, drv, idx, true); +} + +static int sbi_cpuidle_cpuhp_up(unsigned int cpu) +{ + struct device *pd_dev = __this_cpu_read(sbi_cpuidle_data.dev); + + if (pd_dev) + pm_runtime_get_sync(pd_dev); + + return 0; +} + +static int sbi_cpuidle_cpuhp_down(unsigned int cpu) +{ + struct device *pd_dev = __this_cpu_read(sbi_cpuidle_data.dev); + + if (pd_dev) { + pm_runtime_put_sync(pd_dev); + /* Clear domain state to start fresh at next online. */ + sbi_clear_domain_state(); + } + + return 0; +} + +static void sbi_idle_init_cpuhp(void) +{ + int err; + + if (!sbi_cpuidle_use_cpuhp) + return; + + err = cpuhp_setup_state_nocalls(CPUHP_AP_CPU_PM_STARTING, + "cpuidle/sbi:online", + sbi_cpuidle_cpuhp_up, + sbi_cpuidle_cpuhp_down); + if (err) + pr_warn("Failed %d while setup cpuhp state\n", err); +} + +static const struct of_device_id sbi_cpuidle_state_match[] = { + { .compatible = "riscv,idle-state", + .data = sbi_cpuidle_enter_state }, + { }, +}; + +static bool sbi_suspend_state_is_valid(u32 state) +{ + if (state > SBI_HSM_SUSPEND_RET_DEFAULT && + state < SBI_HSM_SUSPEND_RET_PLATFORM) + return false; + if (state > SBI_HSM_SUSPEND_NON_RET_DEFAULT && + state < SBI_HSM_SUSPEND_NON_RET_PLATFORM) + return false; + return true; +} + +static int sbi_dt_parse_state_node(struct device_node *np, u32 *state) +{ + int err = of_property_read_u32(np, "riscv,sbi-suspend-param", state); + + if (err) { + pr_warn("%pOF missing riscv,sbi-suspend-param property\n", np); + return err; + } + + if (!sbi_suspend_state_is_valid(*state)) { + pr_warn("Invalid SBI suspend state %#x\n", *state); + return -EINVAL; + } + + return 0; +} + +static int sbi_dt_cpu_init_topology(struct cpuidle_driver *drv, + struct sbi_cpuidle_data *data, + unsigned int state_count, int cpu) +{ + /* Currently limit the hierarchical topology to be used in OSI mode. */ + if (!sbi_cpuidle_use_osi) + return 0; + + data->dev = dt_idle_attach_cpu(cpu, "sbi"); + if (IS_ERR_OR_NULL(data->dev)) + return PTR_ERR_OR_ZERO(data->dev); + + /* + * Using the deepest state for the CPU to trigger a potential selection + * of a shared state for the domain, assumes the domain states are all + * deeper states. + */ + drv->states[state_count - 1].enter = sbi_enter_domain_idle_state; + drv->states[state_count - 1].enter_s2idle = + sbi_enter_s2idle_domain_idle_state; + sbi_cpuidle_use_cpuhp = true; + + return 0; +} + +static int sbi_cpuidle_dt_init_states(struct device *dev, + struct cpuidle_driver *drv, + unsigned int cpu, + unsigned int state_count) +{ + struct sbi_cpuidle_data *data = per_cpu_ptr(&sbi_cpuidle_data, cpu); + struct device_node *state_node; + struct device_node *cpu_node; + u32 *states; + int i, ret; + + cpu_node = of_cpu_device_node_get(cpu); + if (!cpu_node) + return -ENODEV; + + states = devm_kcalloc(dev, state_count, sizeof(*states), GFP_KERNEL); + if (!states) { + ret = -ENOMEM; + goto fail; + } + + /* Parse SBI specific details from state DT nodes */ + for (i = 1; i < state_count; i++) { + state_node = of_get_cpu_state_node(cpu_node, i - 1); + if (!state_node) + break; + + ret = sbi_dt_parse_state_node(state_node, &states[i]); + of_node_put(state_node); + + if (ret) + return ret; + + pr_debug("sbi-state %#x index %d\n", states[i], i); + } + if (i != state_count) { + ret = -ENODEV; + goto fail; + } + + /* Initialize optional data, used for the hierarchical topology. */ + ret = sbi_dt_cpu_init_topology(drv, data, state_count, cpu); + if (ret < 0) + return ret; + + /* Store states in the per-cpu struct. */ + data->states = states; + +fail: + of_node_put(cpu_node); + + return ret; +} + +static void sbi_cpuidle_deinit_cpu(int cpu) +{ + struct sbi_cpuidle_data *data = per_cpu_ptr(&sbi_cpuidle_data, cpu); + + dt_idle_detach_cpu(data->dev); + sbi_cpuidle_use_cpuhp = false; +} + +static int sbi_cpuidle_init_cpu(struct device *dev, int cpu) +{ + struct cpuidle_driver *drv; + unsigned int state_count = 0; + int ret = 0; + + drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL); + if (!drv) + return -ENOMEM; + + drv->name = "sbi_cpuidle"; + drv->owner = THIS_MODULE; + drv->cpumask = (struct cpumask *)cpumask_of(cpu); + + /* RISC-V architectural WFI to be represented as state index 0. */ + drv->states[0].enter = sbi_cpuidle_enter_state; + drv->states[0].exit_latency = 1; + drv->states[0].target_residency = 1; + drv->states[0].power_usage = UINT_MAX; + strcpy(drv->states[0].name, "WFI"); + strcpy(drv->states[0].desc, "RISC-V WFI"); + + /* + * If no DT idle states are detected (ret == 0) let the driver + * initialization fail accordingly since there is no reason to + * initialize the idle driver if only wfi is supported, the + * default archictectural back-end already executes wfi + * on idle entry. + */ + ret = dt_init_idle_driver(drv, sbi_cpuidle_state_match, 1); + if (ret <= 0) { + pr_debug("HART%ld: failed to parse DT idle states\n", + cpuid_to_hartid_map(cpu)); + return ret ? : -ENODEV; + } + state_count = ret + 1; /* Include WFI state as well */ + + /* Initialize idle states from DT. */ + ret = sbi_cpuidle_dt_init_states(dev, drv, cpu, state_count); + if (ret) { + pr_err("HART%ld: failed to init idle states\n", + cpuid_to_hartid_map(cpu)); + return ret; + } + + ret = cpuidle_register(drv, NULL); + if (ret) + goto deinit; + + cpuidle_cooling_register(drv); + + return 0; +deinit: + sbi_cpuidle_deinit_cpu(cpu); + return ret; +} + +static void sbi_cpuidle_domain_sync_state(struct device *dev) +{ + /* + * All devices have now been attached/probed to the PM domain + * topology, hence it's fine to allow domain states to be picked. + */ + sbi_cpuidle_pd_allow_domain_state = true; +} + +#ifdef CONFIG_DT_IDLE_GENPD + +static int sbi_cpuidle_pd_power_off(struct generic_pm_domain *pd) +{ + struct genpd_power_state *state = &pd->states[pd->state_idx]; + u32 *pd_state; + + if (!state->data) + return 0; + + if (!sbi_cpuidle_pd_allow_domain_state) + return -EBUSY; + + /* OSI mode is enabled, set the corresponding domain state. */ + pd_state = state->data; + sbi_set_domain_state(*pd_state); + + return 0; +} + +struct sbi_pd_provider { + struct list_head link; + struct device_node *node; +}; + +static LIST_HEAD(sbi_pd_providers); + +static int sbi_pd_init(struct device_node *np) +{ + struct generic_pm_domain *pd; + struct sbi_pd_provider *pd_provider; + struct dev_power_governor *pd_gov; + int ret = -ENOMEM, state_count = 0; + + pd = dt_idle_pd_alloc(np, sbi_dt_parse_state_node); + if (!pd) + goto out; + + pd_provider = kzalloc(sizeof(*pd_provider), GFP_KERNEL); + if (!pd_provider) + goto free_pd; + + pd->flags |= GENPD_FLAG_IRQ_SAFE | GENPD_FLAG_CPU_DOMAIN; + + /* Allow power off when OSI is available. */ + if (sbi_cpuidle_use_osi) + pd->power_off = sbi_cpuidle_pd_power_off; + else + pd->flags |= GENPD_FLAG_ALWAYS_ON; + + /* Use governor for CPU PM domains if it has some states to manage. */ + pd_gov = state_count > 0 ? &pm_domain_cpu_gov : NULL; + + ret = pm_genpd_init(pd, pd_gov, false); + if (ret) + goto free_pd_prov; + + ret = of_genpd_add_provider_simple(np, pd); + if (ret) + goto remove_pd; + + pd_provider->node = of_node_get(np); + list_add(&pd_provider->link, &sbi_pd_providers); + + pr_debug("init PM domain %s\n", pd->name); + return 0; + +remove_pd: + pm_genpd_remove(pd); +free_pd_prov: + kfree(pd_provider); +free_pd: + dt_idle_pd_free(pd); +out: + pr_err("failed to init PM domain ret=%d %pOF\n", ret, np); + return ret; +} + +static void sbi_pd_remove(void) +{ + struct sbi_pd_provider *pd_provider, *it; + struct generic_pm_domain *genpd; + + list_for_each_entry_safe(pd_provider, it, &sbi_pd_providers, link) { + of_genpd_del_provider(pd_provider->node); + + genpd = of_genpd_remove_last(pd_provider->node); + if (!IS_ERR(genpd)) + kfree(genpd); + + of_node_put(pd_provider->node); + list_del(&pd_provider->link); + kfree(pd_provider); + } +} + +static int sbi_genpd_probe(struct device_node *np) +{ + struct device_node *node; + int ret = 0, pd_count = 0; + + if (!np) + return -ENODEV; + + /* + * Parse child nodes for the "#power-domain-cells" property and + * initialize a genpd/genpd-of-provider pair when it's found. + */ + for_each_child_of_node(np, node) { + if (!of_find_property(node, "#power-domain-cells", NULL)) + continue; + + ret = sbi_pd_init(node); + if (ret) + goto put_node; + + pd_count++; + } + + /* Bail out if not using the hierarchical CPU topology. */ + if (!pd_count) + goto no_pd; + + /* Link genpd masters/subdomains to model the CPU topology. */ + ret = dt_idle_pd_init_topology(np); + if (ret) + goto remove_pd; + + return 0; + +put_node: + of_node_put(node); +remove_pd: + sbi_pd_remove(); + pr_err("failed to create CPU PM domains ret=%d\n", ret); +no_pd: + return ret; +} + +#else + +static inline int sbi_genpd_probe(struct device_node *np) +{ + return 0; +} + +#endif + +static int sbi_cpuidle_probe(struct platform_device *pdev) +{ + int cpu, ret; + struct cpuidle_driver *drv; + struct cpuidle_device *dev; + struct device_node *np, *pds_node; + + /* Detect OSI support based on CPU DT nodes */ + sbi_cpuidle_use_osi = true; + for_each_possible_cpu(cpu) { + np = of_cpu_device_node_get(cpu); + if (np && + of_find_property(np, "power-domains", NULL) && + of_find_property(np, "power-domain-names", NULL)) { + continue; + } else { + sbi_cpuidle_use_osi = false; + break; + } + } + + /* Populate generic power domains from DT nodes */ + pds_node = of_find_node_by_path("/cpus/power-domains"); + if (pds_node) { + ret = sbi_genpd_probe(pds_node); + of_node_put(pds_node); + if (ret) + return ret; + } + + /* Initialize CPU idle driver for each CPU */ + for_each_possible_cpu(cpu) { + ret = sbi_cpuidle_init_cpu(&pdev->dev, cpu); + if (ret) { + pr_debug("HART%ld: idle driver init failed\n", + cpuid_to_hartid_map(cpu)); + goto out_fail; + } + } + + /* Setup CPU hotplut notifiers */ + sbi_idle_init_cpuhp(); + + pr_info("idle driver registered for all CPUs\n"); + + return 0; + +out_fail: + while (--cpu >= 0) { + dev = per_cpu(cpuidle_devices, cpu); + drv = cpuidle_get_cpu_driver(dev); + cpuidle_unregister(drv); + sbi_cpuidle_deinit_cpu(cpu); + } + + return ret; +} + +static struct platform_driver sbi_cpuidle_driver = { + .probe = sbi_cpuidle_probe, + .driver = { + .name = "sbi-cpuidle", + .sync_state = sbi_cpuidle_domain_sync_state, + }, +}; + +static int __init sbi_cpuidle_init(void) +{ + int ret; + struct platform_device *pdev; + + /* + * The SBI HSM suspend function is only available when: + * 1) SBI version is 0.3 or higher + * 2) SBI HSM extension is available + */ + if ((sbi_spec_version < sbi_mk_version(0, 3)) || + sbi_probe_extension(SBI_EXT_HSM) <= 0) { + pr_info("HSM suspend not available\n"); + return 0; + } + + ret = platform_driver_register(&sbi_cpuidle_driver); + if (ret) + return ret; + + pdev = platform_device_register_simple("sbi-cpuidle", + -1, NULL, 0); + if (IS_ERR(pdev)) { + platform_driver_unregister(&sbi_cpuidle_driver); + return PTR_ERR(pdev); + } + + return 0; +} +device_initcall(sbi_cpuidle_init); From patchwork Mon Oct 11 08:18:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12549363 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3AD1C4167D for ; Mon, 11 Oct 2021 08:21:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D2D4E60EFE for ; Mon, 11 Oct 2021 08:21:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234991AbhJKIXP (ORCPT ); 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Mon, 11 Oct 2021 08:19:25 +0000 From: Anup Patel To: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Ulf Hansson , "Rafael J . Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel , Rob Herring Subject: [PATCH v8 7/8] dt-bindings: Add common bindings for ARM and RISC-V idle states Date: Mon, 11 Oct 2021 13:48:19 +0530 Message-Id: <20211011081820.1135261-8-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011081820.1135261-1-anup.patel@wdc.com> References: <20211011081820.1135261-1-anup.patel@wdc.com> X-ClientProxiedBy: MA1PR01CA0159.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::29) To CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) MIME-Version: 1.0 Received: from wdc.com (122.171.184.84) by MA1PR01CA0159.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4587.18 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: hI2IqGHLuciE90MhYxKgAtTh8OUkBYjMstGJ60fFWO9TI4QNeM/+CRb1VNyO/Kdt44sgKWCHwpJFmVNJFQjrOHcjKtjkOXfEDvYFQbcolSl4gUOaG/D5O+43CX3+glY7Em5vXo3w9cLt0UXmSJX5M+uE/WMcd2YPWLImK5Wp05tbA4xV7W2ABjj5ajU52we/qWcizrspLxvMaxx/b6WdcimKprnRE+B/EIqwooOBHD2YkAaaR5ZbaqQimiJIf52kp3nXbAUD/DnCnbDA+2bGjOhxzmHXzgRHERei2cKzL4dMl0cjxDt0jc3kN8XSK+sd6bCsPMohSc/6ub7nioHChZ9srtSXPUwYKriOY/9wM2nqhz09aK3b8jKWz8B0q55hrjmOlj6kaPGXTv0qd3mInYVtSMVYUUlpzYdD4gVV26bKsltChjtCnb9R8RM+mrkVpUSP/HzuY3ucof1LL3b8T9b8SdhbFT8IqpYLQ1Fj1ZdgRw+uFNpKxVYeim4e3o1luti+oaFvJZpwwZ4X0oNsCxUXt3glt/QKEHh3VIFWUgMqqz+CYovOXOt4l0jyGfpgUvjF9Y/KDaVWnLFMih3Ulft3XJ2ll4BZ7L4gYu80dpb5lwFR2+jsAHTt5y3w9aH7Q2vQZ3letjqX9/g8UDGFhcg5X6feyV/6IHmhUlv9B3cGABsYSC/nkdBKqJtFsT2yYpYEMitSXmLoPYo+mzNNduMtfHfUsEkBml/BcG/CEXdL0Wkd6faqG8jcpo42btbQYZe/+TaT+D61ruPVc89rM3QGEkF9hgpzGvi9n+ZOG9JFVFfjq4+aO+0znMofnwLeuwsrPsGsha6kVvT23gbySht7+z7tN6mgMfiCfqx6nJ28RGSr7OVSB+xcAC9QeutDHAu+bFVUCwef0Ew7lsMrEv9B/y9CvRH2R+c397mzwLko2nm9PB68jumarWGp47yQIHlMOxDvhoDgDJ2jp/tb2LVcAPWSySsG2tywAnAYY2o9qyJTxWPYATG5AFHcDVzGWWVltmBARIf4BXl+nNJRd87vtfnBFzhHstEVSp82NAvIcIG5/8r47b5bRWJt04v1Hx6aCuOzzMNTtiujcC2BIa5j2pQHjy10qNw8ibkvLHsa8K9IGawASJWNT0zuizIre0F/JytQtULej1DXvO4a0smrMjl89RFVeNZBdRxVMpILM+RnhEW0whUvazosCckOjh4UHoWrei6bJA2+4MAywdRfr+H0oi+NmCVoBLIBZhOxPMR3qVGaDj8IzTCN+MKn2MzsT9Rnbf5tRvvaWYxuvy/quVWwr6A99qdoUL+CHfW1e+7kXa3W0nKAOTL+0L7z X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 97c8d3ee-055a-48c1-5bb1-08d98c8fd5e3 X-MS-Exchange-CrossTenant-AuthSource: CO6PR04MB7812.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Oct 2021 08:19:24.9461 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: WlSd0r89ZVkiyiOrwkLJtD8cqTMeZdK0Y0nADlmUaBbgTAlvV1+78WQbAQNPcHLOo7+JmQZCxqot5/5Z9QPdig== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR04MB7874 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The RISC-V CPU idle states will be described in under the /cpus/idle-states DT node in the same way as ARM CPU idle states. This patch adds common bindings documentation for both ARM and RISC-V idle states. Signed-off-by: Anup Patel Reviewed-by: Rob Herring --- .../bindings/arm/msm/qcom,idle-state.txt | 2 +- .../devicetree/bindings/arm/psci.yaml | 2 +- .../bindings/{arm => cpu}/idle-states.yaml | 228 ++++++++++++++++-- .../devicetree/bindings/riscv/cpus.yaml | 6 + 4 files changed, 219 insertions(+), 19 deletions(-) rename Documentation/devicetree/bindings/{arm => cpu}/idle-states.yaml (74%) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt index 6ce0b212ec6d..606b4b1b709d 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt +++ b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt @@ -81,4 +81,4 @@ Example: }; }; -[1]. Documentation/devicetree/bindings/arm/idle-states.yaml +[1]. Documentation/devicetree/bindings/cpu/idle-states.yaml diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml index 8b77cf83a095..dd83ef278af0 100644 --- a/Documentation/devicetree/bindings/arm/psci.yaml +++ b/Documentation/devicetree/bindings/arm/psci.yaml @@ -101,7 +101,7 @@ properties: bindings in [1]) must specify this property. [1] Kernel documentation - ARM idle states bindings - Documentation/devicetree/bindings/arm/idle-states.yaml + Documentation/devicetree/bindings/cpu/idle-states.yaml patternProperties: "^power-domain-": diff --git a/Documentation/devicetree/bindings/arm/idle-states.yaml b/Documentation/devicetree/bindings/cpu/idle-states.yaml similarity index 74% rename from Documentation/devicetree/bindings/arm/idle-states.yaml rename to Documentation/devicetree/bindings/cpu/idle-states.yaml index 52bce5dbb11f..74466f160cb2 100644 --- a/Documentation/devicetree/bindings/arm/idle-states.yaml +++ b/Documentation/devicetree/bindings/cpu/idle-states.yaml @@ -1,25 +1,30 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/idle-states.yaml# +$id: http://devicetree.org/schemas/cpu/idle-states.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ARM idle states binding description +title: Idle states binding description maintainers: - Lorenzo Pieralisi + - Anup Patel description: |+ ========================================== 1 - Introduction ========================================== - ARM systems contain HW capable of managing power consumption dynamically, - where cores can be put in different low-power states (ranging from simple wfi - to power gating) according to OS PM policies. The CPU states representing the - range of dynamic idle states that a processor can enter at run-time, can be - specified through device tree bindings representing the parameters required to - enter/exit specific idle states on a given processor. + ARM and RISC-V systems contain HW capable of managing power consumption + dynamically, where cores can be put in different low-power states (ranging + from simple wfi to power gating) according to OS PM policies. The CPU states + representing the range of dynamic idle states that a processor can enter at + run-time, can be specified through device tree bindings representing the + parameters required to enter/exit specific idle states on a given processor. + + ========================================== + 2 - ARM idle states + ========================================== According to the Server Base System Architecture document (SBSA, [3]), the power states an ARM CPU can be put into are identified by the following list: @@ -43,8 +48,23 @@ description: |+ The device tree binding definition for ARM idle states is the subject of this document. + ========================================== + 3 - RISC-V idle states + ========================================== + + On RISC-V systems, the HARTs (or CPUs) [6] can be put in platform specific + suspend (or idle) states (ranging from simple WFI, power gating, etc). The + RISC-V SBI v0.3 (or higher) [7] hart state management extension provides a + standard mechanism for OS to request HART state transitions. + + The platform specific suspend (or idle) states of a hart can be either + retentive or non-rententive in nature. A retentive suspend state will + preserve HART registers and CSR values for all privilege modes whereas + a non-retentive suspend state will not preserve HART registers and CSR + values. + =========================================== - 2 - idle-states definitions + 4 - idle-states definitions =========================================== Idle states are characterized for a specific system through a set of @@ -211,10 +231,10 @@ description: |+ properties specification that is the subject of the following sections. =========================================== - 3 - idle-states node + 5 - idle-states node =========================================== - ARM processor idle states are defined within the idle-states node, which is + The processor idle states are defined within the idle-states node, which is a direct child of the cpus node [1] and provides a container where the processor idle states, defined as device tree nodes, are listed. @@ -223,7 +243,7 @@ description: |+ just supports idle_standby, an idle-states node is not required. =========================================== - 4 - References + 6 - References =========================================== [1] ARM Linux Kernel documentation - CPUs bindings @@ -238,9 +258,15 @@ description: |+ [4] ARM Architecture Reference Manuals http://infocenter.arm.com/help/index.jsp - [6] ARM Linux Kernel documentation - Booting AArch64 Linux + [5] ARM Linux Kernel documentation - Booting AArch64 Linux Documentation/arm64/booting.rst + [6] RISC-V Linux Kernel documentation - CPUs bindings + Documentation/devicetree/bindings/riscv/cpus.yaml + + [7] RISC-V Supervisor Binary Interface (SBI) + http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc + properties: $nodename: const: idle-states @@ -253,7 +279,7 @@ properties: On ARM 32-bit systems this property is optional This assumes that the "enable-method" property is set to "psci" in the cpu - node[6] that is responsible for setting up CPU idle management in the OS + node[5] that is responsible for setting up CPU idle management in the OS implementation. const: psci @@ -265,8 +291,8 @@ patternProperties: as follows. The idle state entered by executing the wfi instruction (idle_standby - SBSA,[3][4]) is considered standard on all ARM platforms and therefore - must not be listed. + SBSA,[3][4]) is considered standard on all ARM and RISC-V platforms and + therefore must not be listed. In addition to the properties listed above, a state node may require additional properties specific to the entry-method defined in the @@ -275,7 +301,27 @@ patternProperties: properties: compatible: - const: arm,idle-state + oneOf: + - const: arm,idle-state + - const: riscv,idle-state + + arm,psci-suspend-param: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + power_state parameter to pass to the ARM PSCI suspend call. + + Device tree nodes that require usage of PSCI CPU_SUSPEND function + (i.e. idle states node with entry-method property is set to "psci") + must specify this property. + + riscv,sbi-suspend-param: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + suspend_type parameter to pass to the RISC-V SBI HSM suspend call. + + This property is required in idle state nodes of device tree meant + for RISC-V systems. For more details on the suspend_type parameter + refer the SBI specifiation v0.3 (or higher) [7]. local-timer-stop: description: @@ -317,6 +363,8 @@ patternProperties: description: A string used as a descriptive name for the idle state. + additionalProperties: false + required: - compatible - entry-latency-us @@ -658,4 +706,150 @@ examples: }; }; + - | + // Example 3 (RISC-V 64-bit, 4-cpu systems, two clusters): + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x0>; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv48"; + cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0 + &CLUSTER_RET_0 &CLUSTER_NONRET_0>; + + cpu_intc0: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x1>; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv48"; + cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0 + &CLUSTER_RET_0 &CLUSTER_NONRET_0>; + + cpu_intc1: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@10 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x10>; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv48"; + cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0 + &CLUSTER_RET_1 &CLUSTER_NONRET_1>; + + cpu_intc10: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@11 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x11>; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv48"; + cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0 + &CLUSTER_RET_1 &CLUSTER_NONRET_1>; + + cpu_intc11: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + idle-states { + CPU_RET_0_0: cpu-retentive-0-0 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x10000000>; + entry-latency-us = <20>; + exit-latency-us = <40>; + min-residency-us = <80>; + }; + + CPU_NONRET_0_0: cpu-nonretentive-0-0 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x90000000>; + entry-latency-us = <250>; + exit-latency-us = <500>; + min-residency-us = <950>; + }; + + CLUSTER_RET_0: cluster-retentive-0 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x11000000>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <100>; + min-residency-us = <250>; + wakeup-latency-us = <130>; + }; + + CLUSTER_NONRET_0: cluster-nonretentive-0 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x91000000>; + local-timer-stop; + entry-latency-us = <600>; + exit-latency-us = <1100>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + + CPU_RET_1_0: cpu-retentive-1-0 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x10000010>; + entry-latency-us = <20>; + exit-latency-us = <40>; + min-residency-us = <80>; + }; + + CPU_NONRET_1_0: cpu-nonretentive-1-0 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x90000010>; + entry-latency-us = <250>; + exit-latency-us = <500>; + min-residency-us = <950>; + }; + + CLUSTER_RET_1: cluster-retentive-1 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x11000010>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <100>; + min-residency-us = <250>; + wakeup-latency-us = <130>; + }; + + CLUSTER_NONRET_1: cluster-nonretentive-1 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x91000010>; + local-timer-stop; + entry-latency-us = <600>; + exit-latency-us = <1100>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + }; + ... diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index e534f6a7cfa1..482936630525 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -95,6 +95,12 @@ properties: - compatible - interrupt-controller + cpu-idle-states: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: | + List of phandles to idle state nodes supported + by this hart (see ./idle-states.yaml). + required: - riscv,isa - interrupt-controller From patchwork Mon Oct 11 08:18:20 2021 Content-Type: text/plain; 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Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel Subject: [PATCH v8 8/8] RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU virt machine Date: Mon, 11 Oct 2021 13:48:20 +0530 Message-Id: <20211011081820.1135261-9-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011081820.1135261-1-anup.patel@wdc.com> References: <20211011081820.1135261-1-anup.patel@wdc.com> X-ClientProxiedBy: MA1PR01CA0159.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::29) To CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) MIME-Version: 1.0 Received: from wdc.com (122.171.184.84) by MA1PR01CA0159.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4587.18 via Frontend Transport; Mon, 11 Oct 2021 08:19:25 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d34cd952-5dec-48fb-bf92-08d98c8fd909 X-MS-TrafficTypeDiagnostic: CO6PR04MB7874: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:849; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CdhEdwdRWcvOHvjIhVkayTzg2rBAE7f2caSI/UiT1MPvfl5lZG5Cqm+pQLxP6HUbD30DSB1SO6ZLn6zSwvFGfWbx+JeHIufgryx0V74NG63MeP9zGoKjNIUVVXU7AvZN7DypD2grWrdmKNlJRppJ2CcP0MfPVTr2z8S4Mh9Ddc3ocda+WkNNrIMp5vpkrPCy0TRHDgpvTBhE/PSky4sgH8OHy0Dyp5Kgg+iiVJ9TNa9YxnIFSIwGz72Wsi4Xelw1N8gv/hnpzy/bxoZB0RyzhSoiiQENSj+tZ+g8q7VWy8hA6kkuyMtNPvhjaV7yFQqxJlb28IXrOOAddvbkVtYVt3uPCbgycHTmnMZ1dS0QlDZIjDAwIqFBw0wHQZMUmpXwKRaiwt4dIkVXPeGsuuVgEgyK3PwZTD9geOpuFZf86idGoJTIjuzyrn2QfTiLrMf4aJMNtBqVday3k7xoKHkrmu0HZLCEqIX40V8hMHtuscLSSVozTCKPOsfqCI7eWoWIVKo7AV1BozUIt3DuevxZdECJYAjjSIjTzpT1Eq7YcoU18qSgyVhKEZWmQEuw2wLlkAqnXS6LbznQs7oA4XaV/XAY3jQBDTAO45o5wq4Rma0WghIv6HBpm7YBupGfN3bgIFwbp+CGqtPeTasBz2eznBTKfmXf7dH8t5kXv5z0jzNlApAEeJ2ylEdcEmZMitn43VchP8wFbzqrArvLfI71AQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CO6PR04MB7812.namprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(366004)(8886007)(26005)(186003)(86362001)(44832011)(508600001)(2906002)(956004)(4326008)(7416002)(2616005)(52116002)(38350700002)(66946007)(66556008)(316002)(54906003)(110136005)(6666004)(8676002)(5660300002)(1076003)(66476007)(38100700002)(7696005)(8936002)(36756003)(55016002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DmLHpt1fYu0CEZQ5YqVvFrnhCcZFQX9IJjNWwbMcdWeHa6qBLIfhxdYaRSlZ/vvl55ZgmnKskMykkwNZsvesL0R2VuhsO6uV067iLmhfoubVE61HNA3WHlomJjBRtqqwNQNpRv1MtugA/sTRlBIjHIYCVEEQ4+7Dl9B8sVz19qa8hQjQPSYYAe06RSBVt163P04t40fzm88AvdNnNEWsQh8+MfCcM77K5eqvnBbyDs3LCScSu/bmBgJh/E+J8bziLAnWDbD4qdPSE5zc94UW3deKydUUrjOuwRwo44higV/zqigssbAJsmD98PKoGI1mNC9byZeeOG7RGCFq7uO0jdv/vzz8E0XL1a66NpWRN15pPpTFO+7LRLPDKBaVS0aRP7QMJlwgUtAP+oQ0TW5Ivee7b4QHKO00YmwhDUfRREPA7gIBtIvxLQAAfTmbX5foD1K8tp7zrQKS5hRKZtyGtAlAVDtsHDbBv7Y3ke+G0tn/GwRGmu1IjFyosQfHT8xjtQ50M8/JeVkh1lWofI+jPZVuNxGHmVttOn6MGXTo1nf32pGeRQFpBEFP9278YpCtU6PJntl6le/cvxoqzgCk+YxrkJ59kTEVn4tLYyi/USiZ3D2uYtOviX3BIFvkPnjsymegyyqX5HU7/nYGE2qYhtdViIzJh2Eo3yIWyhB10qLHfFyds/M3fzuIUlB7nGehceDZWFT4fZM5q+QdTgxS6fIzaOiDhb7cobDl/IEhyTIfwOIi7ycAcUKvIggxTe8PcabmhAVVfyHUgbej81n7ormFAMXcp4wqmAs2EHscDFoITqdjC5ILKgB0VFRwb0bqPfJpcOn7tbNr0FQvHo1VmYgWAHk73+9h5uOEGinr2P8+g/FYqwzz+or43Vs5KlGtqGmcozR5LbF8iPnyek/XYpACOXOHdxfvAA+VCdwsDWFUZxnjwT5BeQKdNNuiXmHvA4Uq53zQk4AQ9FCy3eWzevMod1mmiCf8FgHcML4d/4k8IB4QUVamnk7mtafAY41+DFmn19TGNEYK+ohvipl6nC1BXZmEm11TRQ1+/lvUz2yFZvkDmtHm2DzgfTGbkXvOhu5z2xEFbC7y5Al1Mi6pJ9l4+PSe9s8MPv9Xvgf5nnVveW1knrmHnh3r6djScEwUhpNvvp/BHk4qYiksgn0a6w4KkGAxztyxFTOfrkFJrNMAUwJ8z7OZFqs04uKfeZsAmYnK1tEYo3a7LftoKQTOMpZBLWgJyXrCQuXs9GRdYgA9hpPkd7d3NlgzvTY2jE8G0TXCAN4LIn2ADV9r81QXpHXDfylNB5T4hTJ3xsr4vAVh3q0iRiTDn7sM12QXlx6R X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: d34cd952-5dec-48fb-bf92-08d98c8fd909 X-MS-Exchange-CrossTenant-AuthSource: CO6PR04MB7812.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Oct 2021 08:19:30.0337 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: MWWcdSZ3lPHppVnMijm2hw51IVIMteKTG+kLiZXZavZTOBWg/D7F1XsHh2OqsewrcBaRqXvsojM3FKDiRdF74A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR04MB7874 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org We enable RISC-V SBI CPU Idle driver for QEMU virt machine to test SBI HSM Supend on QEMU. Signed-off-by: Anup Patel --- arch/riscv/Kconfig.socs | 3 +++ arch/riscv/configs/defconfig | 1 + arch/riscv/configs/rv32_defconfig | 1 + 3 files changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 651da2ed93bc..357299833396 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -29,6 +29,9 @@ config SOC_VIRT select RTC_DRV_GOLDFISH if RTC_CLASS select SIFIVE_PLIC select RISCV_ACLINT_SWI + select PM_GENERIC_DOMAINS if PM + select PM_GENERIC_DOMAINS_OF if PM && OF + select RISCV_SBI_CPUIDLE if CPU_IDLE help This enables support for QEMU Virt Machine. diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 39b4c32e7997..96fb9ba6318b 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -20,6 +20,7 @@ CONFIG_SOC_SIFIVE=y CONFIG_SOC_VIRT=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y +CONFIG_PM=y CONFIG_CPU_IDLE=y CONFIG_VIRTUALIZATION=y CONFIG_KVM=y diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig index fed827c82a9e..066b7be65f49 100644 --- a/arch/riscv/configs/rv32_defconfig +++ b/arch/riscv/configs/rv32_defconfig @@ -20,6 +20,7 @@ CONFIG_SOC_VIRT=y CONFIG_ARCH_RV32I=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y +CONFIG_PM=y CONFIG_CPU_IDLE=y CONFIG_VIRTUALIZATION=y CONFIG_KVM=y