From patchwork Mon Oct 11 20:46:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 12551081 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB842C433F5 for ; Mon, 11 Oct 2021 21:40:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9A0F660E94 for ; Mon, 11 Oct 2021 21:40:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229641AbhJKVmn (ORCPT ); Mon, 11 Oct 2021 17:42:43 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:52728 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235293AbhJKVmm (ORCPT ); Mon, 11 Oct 2021 17:42:42 -0400 X-Greylist: delayed 3227 seconds by postgrey-1.27 at vger.kernel.org; Mon, 11 Oct 2021 17:42:41 EDT Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 19BKkW0m070905; Mon, 11 Oct 2021 15:46:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1633985192; bh=mqz2lz88cZxIXXKJa69T+JAfW3Se31KHQgsxwq0MR14=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=i/RHTVViOUe5kHGTH96/fPfBsPvSKzrYa27+hwWI6XNv4aJUBy35AjRigSF3k5rAG hNIsVnd+g/Iau46dSfoEpsv/c0riP2i5Amj7UxFweFEo6WlM6iShl4ahBMiqr6pDve +v0zD0GOh05Umgbsbdt8r3RPDTI79io/lHuLNztA= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 19BKkWat105012 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 11 Oct 2021 15:46:32 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Mon, 11 Oct 2021 15:46:31 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Mon, 11 Oct 2021 15:46:31 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 19BKkKEf069811; Mon, 11 Oct 2021 15:46:27 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Apurva Nandan , Patrice Chotard , Christophe Kerello , Boris Brezillon , , , CC: Subject: [PATCH v2 01/14] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase Date: Tue, 12 Oct 2021 02:16:06 +0530 Message-ID: <20211011204619.81893-2-a-nandan@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> References: <20211011204619.81893-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Setting dtr field of spi_mem_op is useful when creating templates for DTR ops in spinand.h. Also, 2 bytes cmd phases are required when operating in Octal DTR SPI mode. Create new templates for dtr mode cmd, address, dummy and data phase in spi_mem_op, which set the dtr field to 1 and also allow passing the nbytes for the cmd phase. Signed-off-by: Apurva Nandan --- include/linux/spi/spi-mem.h | 41 +++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 85e2ff7b840d..4a99e26aa0b6 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -20,6 +20,14 @@ .nbytes = 1, \ } +#define SPI_MEM_OP_CMD_DTR(__nbytes, __opcode, __buswidth) \ + { \ + .buswidth = __buswidth, \ + .opcode = __opcode, \ + .nbytes = __nbytes, \ + .dtr = 1, \ + } + #define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth) \ { \ .nbytes = __nbytes, \ @@ -27,6 +35,14 @@ .buswidth = __buswidth, \ } +#define SPI_MEM_OP_ADDR_DTR(__nbytes, __val, __buswidth) \ + { \ + .nbytes = __nbytes, \ + .val = __val, \ + .buswidth = __buswidth, \ + .dtr = 1, \ + } + #define SPI_MEM_OP_NO_ADDR { } #define SPI_MEM_OP_DUMMY(__nbytes, __buswidth) \ @@ -35,6 +51,13 @@ .buswidth = __buswidth, \ } +#define SPI_MEM_OP_DUMMY_DTR(__nbytes, __buswidth) \ + { \ + .nbytes = __nbytes, \ + .buswidth = __buswidth, \ + .dtr = 1, \ + } + #define SPI_MEM_OP_NO_DUMMY { } #define SPI_MEM_OP_DATA_IN(__nbytes, __buf, __buswidth) \ @@ -45,6 +68,15 @@ .buswidth = __buswidth, \ } +#define SPI_MEM_OP_DATA_IN_DTR(__nbytes, __buf, __buswidth) \ + { \ + .dir = SPI_MEM_DATA_IN, \ + .nbytes = __nbytes, \ + .buf.in = __buf, \ + .buswidth = __buswidth, \ + .dtr = 1, \ + } + #define SPI_MEM_OP_DATA_OUT(__nbytes, __buf, __buswidth) \ { \ .dir = SPI_MEM_DATA_OUT, \ @@ -53,6 +85,15 @@ .buswidth = __buswidth, \ } +#define SPI_MEM_OP_DATA_OUT_DTR(__nbytes, __buf, __buswidth) \ + { \ + .dir = SPI_MEM_DATA_OUT, \ + .nbytes = __nbytes, \ + .buf.out = __buf, \ + .buswidth = __buswidth, \ + .dtr = 1, \ + } + #define SPI_MEM_OP_NO_DATA { } /** From patchwork Mon Oct 11 20:46:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 12551023 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A63AC433F5 for ; Mon, 11 Oct 2021 20:46:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 544A760F4B for ; Mon, 11 Oct 2021 20:46:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235041AbhJKUsu (ORCPT ); Mon, 11 Oct 2021 16:48:50 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:43992 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235039AbhJKUsu (ORCPT ); Mon, 11 Oct 2021 16:48:50 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 19BKkbx6120461; Mon, 11 Oct 2021 15:46:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1633985197; bh=Xs0Y2QJh7ZkmtdvZp9Ye38YnqCIgeiTXXKjusd+pz1s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lqakOCvuQbU6OPltcqNu8j+F/1m4SYtPY4lLXk5PoTl7PaAmG6OxGsBrucq6N2laM K2btrN5FyYnW0dJHQpmQW5rCAVnZyCMJlY4mlfianMEkD7HcZtizR26sSdYtUJyCnr hvmD0K9t7N5+8+y7lsmTI3namhZAGn7BZ5ClKMCg= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 19BKkbpB055156 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 11 Oct 2021 15:46:37 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Mon, 11 Oct 2021 15:46:37 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Mon, 11 Oct 2021 15:46:37 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 19BKkKEg069811; Mon, 11 Oct 2021 15:46:32 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Apurva Nandan , Patrice Chotard , Christophe Kerello , Boris Brezillon , , , CC: Subject: [PATCH v2 02/14] mtd: spinand: Add enum spinand_proto to indicate current SPI IO mode Date: Tue, 12 Oct 2021 02:16:07 +0530 Message-ID: <20211011204619.81893-3-a-nandan@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> References: <20211011204619.81893-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Unlike Dual and Quad SPI modes flashes, Octal DTR SPI NAND flashes require all instructions to be made in 8D-8D-8D protocol when the flash is in Octal DTR mode. Hence, storing the current SPI IO mode becomes necessary for correctly generating non-array access operations. Store the current SPI IO mode in the spinand struct using a reg_proto enum. This would act as a flag, denoting that the core should use the given SPI protocol for non-page access operations. Also provide basic macros for extracting buswidth and dtr mode information from the spinand_proto enum. Signed-off-by: Apurva Nandan --- drivers/mtd/nand/spi/core.c | 2 ++ include/linux/mtd/spinand.h | 30 ++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 2c8685f1f2fa..d82a3e6d9bb5 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1155,6 +1155,7 @@ static void spinand_mtd_resume(struct mtd_info *mtd) struct spinand_device *spinand = mtd_to_spinand(mtd); int ret; + spinand->reg_proto = SPINAND_SINGLE_STR; ret = spinand_reset_op(spinand); if (ret) return; @@ -1181,6 +1182,7 @@ static int spinand_init(struct spinand_device *spinand) if (!spinand->scratchbuf) return -ENOMEM; + spinand->reg_proto = SPINAND_SINGLE_STR; ret = spinand_detect(spinand); if (ret) goto err_free_bufs; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 6988956b8492..f6093cd98d7b 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -140,6 +140,31 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(len, buf, 4)) +#define SPINAND_PROTO_BUSWIDTH_MASK GENMASK(6, 0) +#define SPINAND_PROTO_DTR_BIT BIT(7) + +#define SPINAND_PROTO_STR(__buswidth) \ + ((u8)(((__buswidth) - 1) & SPINAND_PROTO_BUSWIDTH_MASK)) +#define SPINAND_PROTO_DTR(__buswidth) \ + (SPINAND_PROTO_DTR_BIT | SPINAND_PROTO_STR(__buswidth)) + +#define SPINAND_PROTO_BUSWIDTH(__proto) \ + ((u8)(((__proto) & SPINAND_PROTO_BUSWIDTH_MASK) + 1)) +#define SPINAND_PROTO_IS_DTR(__proto) (!!((__proto) & SPINAND_PROTO_DTR_BIT)) + +/** + * enum spinand_proto - List allowable SPI protocol variants for read reg, + * write reg, blk erase, write enable/disable, page read + * and program exec operations. + */ +enum spinand_proto { + SPINAND_SINGLE_STR = SPINAND_PROTO_STR(1), + SPINAND_DUAL_STR = SPINAND_PROTO_STR(2), + SPINAND_QUAD_STR = SPINAND_PROTO_STR(4), + SPINAND_OCTAL_STR = SPINAND_PROTO_STR(8), + SPINAND_OCTAL_DTR = SPINAND_PROTO_DTR(8), +}; + /** * Standard SPI NAND flash commands */ @@ -407,6 +432,9 @@ struct spinand_dirmap { * this die. Only required if your chip exposes several dies * @cur_target: currently selected target/die * @eccinfo: on-die ECC information + * @reg_proto: select a variant of SPI IO protocol (single, quad, octal or + * octal DTR) for read_reg/write_reg/erase operations. Update on + * successful transition into a different SPI IO protocol. * @cfg_cache: config register cache. One entry per die * @databuf: bounce buffer for data * @oobbuf: bounce buffer for OOB data @@ -438,6 +466,8 @@ struct spinand_device { struct spinand_ecc_info eccinfo; + enum spinand_proto reg_proto; + u8 *cfg_cache; u8 *databuf; u8 *oobbuf; From patchwork Mon Oct 11 20:46:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 12551089 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D839C4332F for ; Mon, 11 Oct 2021 21:40:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7709960EFE for ; Mon, 11 Oct 2021 21:40:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235353AbhJKVmr (ORCPT ); Mon, 11 Oct 2021 17:42:47 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:52728 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235380AbhJKVmq (ORCPT ); Mon, 11 Oct 2021 17:42:46 -0400 X-Greylist: delayed 3227 seconds by postgrey-1.27 at vger.kernel.org; Mon, 11 Oct 2021 17:42:41 EDT Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 19BKkhNc070935; Mon, 11 Oct 2021 15:46:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1633985203; bh=CASUc+JvQlKfMHsjOUu+uMJGKuCWgnI+FiOL7ZWrJQo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bU+vpQKS461/fk50n4GpL/J16aZYZ+9aHDE6pwvpsSuPxG+D/cN4xnSHUoNmOuUYF TcC6q+NjzlIXSuw9ZW3iYrkK2j8pJZ8xcHlmp4dqOZojnGzVmrb/kkwq7/KhM6VhQp 7BTzltvEiBwmytCaxkTdI1WXgM0ZgGPbO2AFGnwg= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 19BKkhdE055206 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 11 Oct 2021 15:46:43 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Mon, 11 Oct 2021 15:46:43 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Mon, 11 Oct 2021 15:46:43 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 19BKkKEh069811; Mon, 11 Oct 2021 15:46:38 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Apurva Nandan , Patrice Chotard , Christophe Kerello , Boris Brezillon , , , CC: Subject: [PATCH v2 03/14] mtd: spinand: Patch spi_mem_op for the SPI IO protocol using reg_proto Date: Tue, 12 Oct 2021 02:16:08 +0530 Message-ID: <20211011204619.81893-4-a-nandan@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> References: <20211011204619.81893-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Currently, the op macros in spinand.h don't give the option to setup any non-array access instructions for Dual/Quad/Octal DTR SPI bus. Having a function that patches the op based on reg_proto would be better than trying to write all the setup logic in op macros. Create a spimem_patch_op() that would patch cmd, addr, dummy and data phase of the spi_mem op, for the given spinand->reg_proto. And hence, call the spimem_patch_op() before executing any spi_mem op. Note: In this commit, spimem_patch_op() isn't called in the read_reg_op(), write_reg_op() and wait() functions, as they need modifications in address value and data nbytes when in Octal DTR mode. This will be fixed in a later commit. Signed-off-by: Apurva Nandan --- drivers/mtd/nand/spi/core.c | 49 +++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index d82a3e6d9bb5..11746d858f87 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -20,6 +20,49 @@ #include #include +/** + * spinand_patch_op() - Helper function to patch the spi_mem op based on the + * spinand->reg_proto + * @spinand: the spinand device + * @op: the spi_mem op to patch + * + * Set up buswidth and dtr fields for cmd, addr, dummy and data phase. Also + * adjust cmd opcode and dummy nbytes. This function doesn't make any changes + * to addr val or data buf. + */ +static void spinand_patch_op(const struct spinand_device *spinand, + struct spi_mem_op *op) +{ + u8 op_buswidth = SPINAND_PROTO_BUSWIDTH(spinand->reg_proto); + u8 op_is_dtr = SPINAND_PROTO_IS_DTR(spinand->reg_proto); + + if (spinand->reg_proto == SPINAND_SINGLE_STR) + return; + + op->cmd.buswidth = op_buswidth; + op->cmd.dtr = op_is_dtr; + if (spinand->reg_proto == SPINAND_OCTAL_DTR) { + op->cmd.opcode = (op->cmd.opcode << 8) | op->cmd.opcode; + op->cmd.nbytes = 2; + } + + if (op->addr.nbytes) { + op->addr.buswidth = op_buswidth; + op->addr.dtr = op_is_dtr; + } + + if (op->dummy.nbytes) { + op->dummy.buswidth = op_buswidth; + op->dummy.dtr = op_is_dtr; + op->dummy.nbytes <<= op_is_dtr; + } + + if (op->data.nbytes) { + op->data.buswidth = op_buswidth; + op->data.dtr = op_is_dtr; + } +} + static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) { struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg, @@ -343,6 +386,7 @@ static int spinand_write_enable_op(struct spinand_device *spinand) { struct spi_mem_op op = SPINAND_WR_EN_DIS_OP(true); + spinand_patch_op(spinand, &op); return spi_mem_exec_op(spinand->spimem, &op); } @@ -353,6 +397,7 @@ static int spinand_load_page_op(struct spinand_device *spinand, unsigned int row = nanddev_pos_to_row(nand, &req->pos); struct spi_mem_op op = SPINAND_PAGE_READ_OP(row); + spinand_patch_op(spinand, &op); return spi_mem_exec_op(spinand->spimem, &op); } @@ -477,6 +522,7 @@ static int spinand_program_op(struct spinand_device *spinand, unsigned int row = nanddev_pos_to_row(nand, &req->pos); struct spi_mem_op op = SPINAND_PROG_EXEC_OP(row); + spinand_patch_op(spinand, &op); return spi_mem_exec_op(spinand->spimem, &op); } @@ -487,6 +533,7 @@ static int spinand_erase_op(struct spinand_device *spinand, unsigned int row = nanddev_pos_to_row(nand, pos); struct spi_mem_op op = SPINAND_BLK_ERASE_OP(row); + spinand_patch_op(spinand, &op); return spi_mem_exec_op(spinand->spimem, &op); } @@ -533,6 +580,7 @@ static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr, naddr, ndummy, spinand->scratchbuf, SPINAND_MAX_ID_LEN); int ret; + spinand_patch_op(spinand, &op); ret = spi_mem_exec_op(spinand->spimem, &op); if (!ret) memcpy(buf, spinand->scratchbuf, SPINAND_MAX_ID_LEN); @@ -545,6 +593,7 @@ static int spinand_reset_op(struct spinand_device *spinand) struct spi_mem_op op = SPINAND_RESET_OP; int ret; + spinand_patch_op(spinand, &op); ret = spi_mem_exec_op(spinand->spimem, &op); if (ret) return ret; From patchwork Mon Oct 11 20:46:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 12551083 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10CE9C4332F for ; Mon, 11 Oct 2021 21:40:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E567060E54 for ; Mon, 11 Oct 2021 21:40:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235368AbhJKVmo (ORCPT ); Mon, 11 Oct 2021 17:42:44 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:52728 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235353AbhJKVmn (ORCPT ); Mon, 11 Oct 2021 17:42:43 -0400 X-Greylist: delayed 3227 seconds by postgrey-1.27 at vger.kernel.org; Mon, 11 Oct 2021 17:42:41 EDT Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 19BKknQn070955; Mon, 11 Oct 2021 15:46:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1633985209; bh=zuAnALlNlpxKf8XxKC5WEtmIbZqVguvc3Q0C3DzvGGs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UoLlY5j4IzTnUDuQDYGeq+cA6N1uER9VLr7a5yRy4D+o0pOjrQ8GRvEeXDtAV3r2v 1raSQOPIFVo9vPvYjZUHCNLR7bkxwbzEYUfBS7fIlqOlK56vXSo+j2swtcb4g0TjRc ieR4nfFB8YcIyv2M9cYLAw4fttIY/H4gqsIwnSnI= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 19BKknFl105109 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 11 Oct 2021 15:46:49 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Mon, 11 Oct 2021 15:46:49 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Mon, 11 Oct 2021 15:46:48 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 19BKkKEi069811; Mon, 11 Oct 2021 15:46:43 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Apurva Nandan , Patrice Chotard , Christophe Kerello , Boris Brezillon , , , CC: Subject: [PATCH v2 04/14] mtd: spinand: Fix odd byte addr and data phase in read and write reg op for Octal DTR mode Date: Tue, 12 Oct 2021 02:16:09 +0530 Message-ID: <20211011204619.81893-5-a-nandan@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> References: <20211011204619.81893-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org In Octal DTR SPI mode, 2 bytes of data gets transmitted over one clock cycle, and half-cycle instruction phases aren't supported yet. So, every DTR spi_mem_op needs to have even nbytes in all phases for non-erratic behaviour from the SPI controller. The odd length cmd and dummy phases get handled by spimem_patch_op() but the odd length address and data phases need to be handled according to the use case. For example in Octal DTR mode, read register operation has one byte long address and data phase. So it needs to extend it by adding a suitable extra byte in addr and reading 2 bytes of data, discarding the second byte. Handle address and data phases for Octal DTR mode in read and write register operations by adding a suitable extra byte in the address and data phase. Create spimem_patch_reg_op() helper function to ease setting up read/write register operations in other functions, e.g. wait(). Signed-off-by: Apurva Nandan --- drivers/mtd/nand/spi/core.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 11746d858f87..4da794ae728d 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -63,12 +63,29 @@ static void spinand_patch_op(const struct spinand_device *spinand, } } +static void spinand_patch_reg_op(const struct spinand_device *spinand, + struct spi_mem_op *op) +{ + if (spinand->reg_proto == SPINAND_OCTAL_DTR) { + /* + * Assigning same first and second byte will result in constant + * bits on the SPI bus between positive and negative clock edges + */ + op->addr.val = (op->addr.val << 8) | op->addr.val; + op->addr.nbytes = 2; + op->data.nbytes = 2; + } + + spinand_patch_op(spinand, op); +} + static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) { struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg, spinand->scratchbuf); int ret; + spinand_patch_reg_op(spinand, &op); ret = spi_mem_exec_op(spinand->spimem, &op); if (ret) return ret; @@ -82,7 +99,8 @@ static int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val) struct spi_mem_op op = SPINAND_SET_FEATURE_OP(reg, spinand->scratchbuf); - *spinand->scratchbuf = val; + spinand_patch_reg_op(spinand, &op); + memset(spinand->scratchbuf, val, op.data.nbytes); return spi_mem_exec_op(spinand->spimem, &op); } @@ -547,6 +565,7 @@ static int spinand_wait(struct spinand_device *spinand, u8 status; int ret; + spinand_patch_reg_op(spinand, &op); ret = spi_mem_poll_status(spinand->spimem, &op, STATUS_BUSY, 0, initial_delay_us, poll_delay_us, From patchwork Mon Oct 11 20:46:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 12551027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1E51C433EF for ; Mon, 11 Oct 2021 20:47:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DFF8760462 for ; Mon, 11 Oct 2021 20:47:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235067AbhJKUtO (ORCPT ); Mon, 11 Oct 2021 16:49:14 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:60146 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234618AbhJKUtO (ORCPT ); Mon, 11 Oct 2021 16:49:14 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 19BKksYE036494; Mon, 11 Oct 2021 15:46:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1633985214; bh=on8W3HPPfhJxHFSTbC30TeTqZ/NdxJ0M2DbWqQ2CJCY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IKP5tfY0w35lyYOnrrR2LD22aZXC85Z+5DWM/5Pkt0B287UAaWGBDGjOi+IPfLX65 KhpRhCgIsRl2HISVvq2pVDRbunGUBuBvu/+CN5OjZQMV8pLbCekWmbbnH6nDsnFxN/ dSX3MTzGP99AWgNzTWSS/XMYzrBaBkcnz0CwYkoU= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 19BKksiO055277 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 11 Oct 2021 15:46:54 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Mon, 11 Oct 2021 15:46:54 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Mon, 11 Oct 2021 15:46:54 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 19BKkKEj069811; Mon, 11 Oct 2021 15:46:49 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Apurva Nandan , Patrice Chotard , Christophe Kerello , Boris Brezillon , , , CC: Subject: [PATCH v2 05/14] mtd: spinand: Add adjust_op() in manufacturer_ops to modify the ops for manufacturer specific changes Date: Tue, 12 Oct 2021 02:16:10 +0530 Message-ID: <20211011204619.81893-6-a-nandan@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> References: <20211011204619.81893-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Manufacturers might use a variation of standard SPI NAND flash instructions, e.g. Winbond W35N01JW changes the dummy cycle length for read register commands when in Octal DTR mode. Add new function in manufacturer_ops: adjust_op(), which can be called to correct the spi_mem op for any alteration in the instruction made by the manufacturers. And hence, this function can also be used for incorporating variations of SPI instructions in Octal DTR mode. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by: Apurva Nandan --- drivers/mtd/nand/spi/core.c | 3 +++ include/linux/mtd/spinand.h | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 4da794ae728d..8e6cf7941a0f 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -61,6 +61,9 @@ static void spinand_patch_op(const struct spinand_device *spinand, op->data.buswidth = op_buswidth; op->data.dtr = op_is_dtr; } + + if (spinand->manufacturer->ops->adjust_op) + spinand->manufacturer->ops->adjust_op(op, spinand->reg_proto); } static void spinand_patch_reg_op(const struct spinand_device *spinand, diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index f6093cd98d7b..ebb19b2cec84 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -257,6 +257,8 @@ struct spinand_devid { /** * struct manufacurer_ops - SPI NAND manufacturer specific operations * @init: initialize a SPI NAND device + * @adjust_op: modify the ops for any variation in their cmd, address, dummy or + * data phase by the manufacturer * @cleanup: cleanup a SPI NAND device * * Each SPI NAND manufacturer driver should implement this interface so that @@ -264,6 +266,8 @@ struct spinand_devid { */ struct spinand_manufacturer_ops { int (*init)(struct spinand_device *spinand); + void (*adjust_op)(struct spi_mem_op *op, + const enum spinand_proto reg_proto); void (*cleanup)(struct spinand_device *spinand); }; From patchwork Mon Oct 11 20:46:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 12551025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F817C433F5 for ; Mon, 11 Oct 2021 20:47:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5282D60462 for ; Mon, 11 Oct 2021 20:47:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235039AbhJKUtK (ORCPT ); Mon, 11 Oct 2021 16:49:10 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:44024 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234618AbhJKUtK (ORCPT ); Mon, 11 Oct 2021 16:49:10 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 19BKkxfT120542; Mon, 11 Oct 2021 15:46:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1633985219; bh=W8E5Bn4VYPSr1mS64s78PJRsdrTe25Hy2Dg1pmFYSZE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IZ4Sia+E0XahxqDjV9/u2MDbcDKQ7ffPaz3Dlv81CxewR0z1NjRYLuv4sn9rf8T2m RjiyQjCoe4HSuxTswjFCZ6DphWSGBL0yYJSSaCIrYmEVARbJol1YGt32cZh3kqzXNv 21jtrI9PbdoDOtUV8+WdiVfPCjkxlk2j32hqL9wU= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 19BKkxJ2055305 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 11 Oct 2021 15:46:59 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Mon, 11 Oct 2021 15:46:59 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Mon, 11 Oct 2021 15:46:59 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 19BKkKEk069811; Mon, 11 Oct 2021 15:46:54 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Apurva Nandan , Patrice Chotard , Christophe Kerello , Boris Brezillon , , , CC: Subject: [PATCH v2 06/14] mtd: spinand: Add macros for Octal DTR page read and write operations Date: Tue, 12 Oct 2021 02:16:11 +0530 Message-ID: <20211011204619.81893-7-a-nandan@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> References: <20211011204619.81893-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Define new PAGE_READ_FROM_CACHE and PROG_LOAD op templates for Octal DTR SPI mode. These templates will be used in op_variants and op_templates for defining Octal DTR read from cache and write to cache operations. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by: Apurva Nandan --- include/linux/mtd/spinand.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index ebb19b2cec84..35816b8cfe81 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -122,6 +122,12 @@ SPI_MEM_OP_DUMMY(ndummy, 4), \ SPI_MEM_OP_DATA_IN(len, buf, 4)) +#define SPINAND_PAGE_READ_FROM_CACHE_OCTALIO_DTR_OP(addr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD_DTR(2, 0x9d9d, 8), \ + SPI_MEM_OP_ADDR_DTR(2, addr, 8), \ + SPI_MEM_OP_DUMMY_DTR(ndummy, 8), \ + SPI_MEM_OP_DATA_IN_DTR(len, buf, 8)) + #define SPINAND_PROG_EXEC_OP(addr) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \ SPI_MEM_OP_ADDR(3, addr, 1), \ @@ -140,6 +146,12 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(len, buf, 4)) +#define SPINAND_PROG_LOAD_OCTALIO_DTR(reset, addr, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD_DTR(2, reset ? 0x0202 : 0x8484, 8), \ + SPI_MEM_OP_ADDR_DTR(2, addr, 8), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT_DTR(len, buf, 8)) + #define SPINAND_PROTO_BUSWIDTH_MASK GENMASK(6, 0) #define SPINAND_PROTO_DTR_BIT BIT(7) From patchwork Mon Oct 11 20:46:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 12551085 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39C33C43217 for ; Mon, 11 Oct 2021 21:40:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2576060E54 for ; Mon, 11 Oct 2021 21:40:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235378AbhJKVmp (ORCPT ); Mon, 11 Oct 2021 17:42:45 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:52728 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235377AbhJKVmp (ORCPT ); Mon, 11 Oct 2021 17:42:45 -0400 X-Greylist: delayed 3227 seconds by postgrey-1.27 at vger.kernel.org; Mon, 11 Oct 2021 17:42:41 EDT Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 19BKl5tQ071016; Mon, 11 Oct 2021 15:47:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1633985225; bh=DFZQnhqlxo23Wmwjp8fS/CEqoUGjmQJfz+RoEPGUJNY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=kfL7inrw9Uy0mByZ9k/uXRYknUVv3fhl/s9YeXBtqys0S7OprKf9vkjBfqQSsXzmx xfrjSXaIFUbX4EXf3U4QCCxFoGm0uP3jk8+Dj9jlVoSMjCev7OsTvbsgslxRC2mE5c B8MxSOcUzPobiRs8HCBIPhIZbPVqaQK/PlKN33ZQ= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 19BKl5uM096784 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 11 Oct 2021 15:47:05 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Mon, 11 Oct 2021 15:47:04 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Mon, 11 Oct 2021 15:47:04 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 19BKkKEl069811; Mon, 11 Oct 2021 15:47:00 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Apurva Nandan , Patrice Chotard , Christophe Kerello , Boris Brezillon , , , CC: Subject: [PATCH v2 07/14] mtd: spinand: Allow enabling Octal DTR mode in the core Date: Tue, 12 Oct 2021 02:16:12 +0530 Message-ID: <20211011204619.81893-8-a-nandan@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> References: <20211011204619.81893-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Enable Octal DTR SPI mode, i.e. 8D-8D-8D mode, if the SPI NAND flash device supports it. Mixed OSPI (1S-1S-8S & 1S-8S-8S), mixed DTR modes (1S-1D-8D), etc. aren't supported yet. The method to switch to Octal DTR SPI mode may vary across manufacturers. For example, for Winbond, it is enabled by writing values to the volatile configuration register. So, let the manufacturer's code have their own implementation for switching to Octal DTR SPI mode. Check for the SPI NAND device's support for Octal DTR mode using spinand flags, and if the op_templates allows 8D-8D-8D, call octal_dtr_enable() manufacturer op. If the SPI controller doesn't supports these modes, the selected op_templates will prevent switching to the Octal DTR mode. And finally update the spinand reg_proto on success. Signed-off-by: Apurva Nandan --- drivers/mtd/nand/spi/core.c | 46 +++++++++++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 3 +++ 2 files changed, 49 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 8e6cf7941a0f..1210946f8447 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -257,6 +257,48 @@ static int spinand_init_quad_enable(struct spinand_device *spinand) enable ? CFG_QUAD_ENABLE : 0); } +static bool spinand_op_is_octal_dtr(const struct spi_mem_op *op) +{ + return op->cmd.buswidth == 8 && op->cmd.dtr && + op->addr.buswidth == 8 && op->addr.dtr && + op->data.buswidth == 8 && op->data.dtr; +} + +static int spinand_init_octal_dtr_enable(struct spinand_device *spinand) +{ + struct device *dev = &spinand->spimem->spi->dev; + int ret; + + if (!(spinand->flags & SPINAND_HAS_OCTAL_DTR_BIT)) + return 0; + + if (!(spinand_op_is_octal_dtr(spinand->op_templates.read_cache) && + spinand_op_is_octal_dtr(spinand->op_templates.write_cache) && + spinand_op_is_octal_dtr(spinand->op_templates.update_cache))) + return 0; + + if (!spinand->manufacturer->ops->octal_dtr_enable) { + dev_dbg(dev, + "Missing ->octal_dtr_enable(), unable to switch mode\n"); + return -EINVAL; + } + + ret = spinand->manufacturer->ops->octal_dtr_enable(spinand); + if (ret) { + dev_err(dev, + "Failed to enable Octal DTR SPI mode (err = %d)\n", + ret); + return ret; + } + + spinand->reg_proto = SPINAND_OCTAL_DTR; + + dev_dbg(dev, + "%s SPI NAND switched to Octal DTR SPI (8D-8D-8D) mode\n", + spinand->manufacturer->name); + return 0; +} + static int spinand_ecc_enable(struct spinand_device *spinand, bool enable) { @@ -1192,6 +1234,10 @@ static int spinand_init_flash(struct spinand_device *spinand) if (ret) return ret; + ret = spinand_init_octal_dtr_enable(spinand); + if (ret) + return ret; + ret = spinand_upd_cfg(spinand, CFG_OTP_ENABLE, 0); if (ret) return ret; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 35816b8cfe81..daa2ac5c3110 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -271,6 +271,7 @@ struct spinand_devid { * @init: initialize a SPI NAND device * @adjust_op: modify the ops for any variation in their cmd, address, dummy or * data phase by the manufacturer + * @octal_dtr_enable: switch the SPI NAND flash into Octal DTR SPI mode * @cleanup: cleanup a SPI NAND device * * Each SPI NAND manufacturer driver should implement this interface so that @@ -280,6 +281,7 @@ struct spinand_manufacturer_ops { int (*init)(struct spinand_device *spinand); void (*adjust_op)(struct spi_mem_op *op, const enum spinand_proto reg_proto); + int (*octal_dtr_enable)(struct spinand_device *spinand); void (*cleanup)(struct spinand_device *spinand); }; @@ -348,6 +350,7 @@ struct spinand_ecc_info { #define SPINAND_HAS_QE_BIT BIT(0) #define SPINAND_HAS_CR_FEAT_BIT BIT(1) +#define SPINAND_HAS_OCTAL_DTR_BIT BIT(2) /** * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure From patchwork Mon Oct 11 20:46:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 12551029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 670F1C433EF for ; Mon, 11 Oct 2021 20:47:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4AB5B60462 for ; Mon, 11 Oct 2021 20:47:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234729AbhJKUtb (ORCPT ); Mon, 11 Oct 2021 16:49:31 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:44056 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235088AbhJKUtV (ORCPT ); Mon, 11 Oct 2021 16:49:21 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 19BKlAax120562; Mon, 11 Oct 2021 15:47:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1633985230; bh=Jl27qxWYXXgX0CrAWa8WspGuO5ufeybya3LllQ9alsY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=zHoNajlvtAeI9nc1iQovOs7WA7wAWTRtTAPPI6ksCDk7KsdGYsiy188e4NFuN7J5u mw4CXsQEm+eW818+iPI+tpeCGD1L6kaeN2P5hVKZY9EQ9zWfFZbTiHCdZr7+fpacpL ADruIBkHx2fXjZVylEKWZKz8sfI1BMQZQQKXJRPk= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 19BKlAfZ096615 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 11 Oct 2021 15:47:10 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Mon, 11 Oct 2021 15:47:09 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Mon, 11 Oct 2021 15:47:09 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 19BKkKEm069811; Mon, 11 Oct 2021 15:47:05 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Apurva Nandan , Patrice Chotard , Christophe Kerello , Boris Brezillon , , , CC: Subject: [PATCH v2 08/14] mtd: spinand: winbond: Add support for write volatile configuration register op Date: Tue, 12 Oct 2021 02:16:13 +0530 Message-ID: <20211011204619.81893-9-a-nandan@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> References: <20211011204619.81893-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Volatile configuration register are a different set of configuration registers, i.e. they differ from the status registers. A different SPI instruction is required to write to these registers. Any changes to the Volatile Configuration Register get transferred directly to the Internal Configuration Register and instantly reflect on the device operation. In Winbond W35N01JW, these volatile configuration register must be configured in order to switch to Octal DTR SPI mode. Add support for writing to volatile configuration registers using a new WRITE_VCR_OP template. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by: Apurva Nandan --- drivers/mtd/nand/spi/core.c | 2 +- drivers/mtd/nand/spi/winbond.c | 42 ++++++++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 1 + 3 files changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 1210946f8447..2bea21bd9747 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -445,7 +445,7 @@ static void spinand_ondie_ecc_save_status(struct nand_device *nand, u8 status) engine_conf->status = status; } -static int spinand_write_enable_op(struct spinand_device *spinand) +int spinand_write_enable_op(struct spinand_device *spinand) { struct spi_mem_op op = SPINAND_WR_EN_DIS_OP(true); diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 76684428354e..89d8ee801f56 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -7,6 +7,7 @@ * Boris Brezillon */ +#include #include #include #include @@ -114,6 +115,47 @@ static int winbond_spinand_init(struct spinand_device *spinand) return 0; } +/** + * winbond_write_vcr_op() - write values onto the volatile configuration + * registers (VCR) + * @spinand: the spinand device + * @reg: the address of the particular reg in the VCR to be written on + * @val: the value to be written on the reg in the VCR + * + * Volatile configuration registers are a separate set of configuration + * registers, i.e. they differ from the status registers SR-1/2/3. A different + * SPI instruction is required to write to these registers. Any changes + * to the Volatile Configuration Register get transferred directly to + * the Internal Configuration Register and instantly reflect on the + * device operation. + */ +static int winbond_write_vcr_op(struct spinand_device *spinand, u8 reg, u8 val) +{ + int ret; + struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x81, 1), + SPI_MEM_OP_ADDR(3, reg, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, spinand->scratchbuf, 1)); + + *spinand->scratchbuf = val; + + ret = spinand_write_enable_op(spinand); + if (ret) + return ret; + + ret = spi_mem_exec_op(spinand->spimem, &op); + if (ret) + return ret; + + /* + * Write VCR operation doesn't set the busy bit in SR, so can't perform + * a status poll. Minimum time of 50ns is needed to complete the write. + * So, give thrice the minimum required delay. + */ + ndelay(150); + return 0; +} + static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = { .init = winbond_spinand_init, }; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index daa2ac5c3110..21a4e5adcd59 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -560,5 +560,6 @@ int spinand_match_and_init(struct spinand_device *spinand, int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val); int spinand_select_target(struct spinand_device *spinand, unsigned int target); +int spinand_write_enable_op(struct spinand_device *spinand); #endif /* __LINUX_MTD_SPINAND_H */ From patchwork Mon Oct 11 20:46:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 12551039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF556C433EF for ; Mon, 11 Oct 2021 20:49:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D77D260462 for ; Mon, 11 Oct 2021 20:49:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232898AbhJKUvL (ORCPT ); Mon, 11 Oct 2021 16:51:11 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:44178 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235103AbhJKUt0 (ORCPT ); Mon, 11 Oct 2021 16:49:26 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 19BKlFUd120594; Mon, 11 Oct 2021 15:47:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1633985235; bh=w7E6JyxIZUA2SdyIeNyt39TQ5DAkOg+qhHKv0x4dNcg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OVQDwQByzoAHGuXrcyHr7ywvQdjNu304uTfkpW5s7TDx6lcFcUO71dg+2+jbZJZJ2 NSWtoP8PC6V9weaQAlORVzPYzGgqnZWM1XO17aVi5r/pRvDCKANJUpa4RrFaho1i/h /J3mwA4QmOSh+OmSUZ5Dke0/8ST3M11fPt2rrP8s= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 19BKlFEA096742 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 11 Oct 2021 15:47:15 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Mon, 11 Oct 2021 15:47:15 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Mon, 11 Oct 2021 15:47:15 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 19BKkKEn069811; Mon, 11 Oct 2021 15:47:10 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Apurva Nandan , Patrice Chotard , Christophe Kerello , Boris Brezillon , , , CC: Subject: [PATCH v2 09/14] mtd: spinand: winbond: Add octal_dtr_enable() for manufacturer_ops Date: Tue, 12 Oct 2021 02:16:14 +0530 Message-ID: <20211011204619.81893-10-a-nandan@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> References: <20211011204619.81893-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add implementation of octal_dtr_enable() manufacturer_ops for Winbond. To switch to Ocatl DTR mode, setting programmable dummy cycles and SPI IO mode using the volatile configuration register is required. To function at max 120MHz SPI clock in Octal DTR mode, 12 programmable dummy clock cycle setting is required. (Default number of dummy cycle are 8 clocks) Set the programmable dummy cycle to 12 clocks, and SPI IO mode to Octal DTR with Data Strobe in the VCR. Also, perform a READ ID operation in Octal DTR SPI mode to ensure the switch was successful. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by: Apurva Nandan --- drivers/mtd/nand/spi/winbond.c | 42 ++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 89d8ee801f56..e2cb82d68f96 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -16,6 +16,14 @@ #define WINBOND_CFG_BUF_READ BIT(3) +/* Octal DTR SPI mode (8D-8D-8D) with Data Strobe output*/ +#define WINBOND_IO_MODE_VCR_OCTAL_DTR 0xE7 +#define WINBOND_IO_MODE_VCR_ADDR 0x00 + +/* Use 12 dummy clk cycles for using Octal DTR SPI at max 120MHZ */ +#define WINBOND_DUMMY_CLK_COUNT 12 +#define WINBOND_DUMMY_CLK_VCR_ADDR 0x01 + static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), @@ -156,8 +164,42 @@ static int winbond_write_vcr_op(struct spinand_device *spinand, u8 reg, u8 val) return 0; } +static int winbond_spinand_octal_dtr_enable(struct spinand_device *spinand) +{ + int ret; + struct spi_mem_op op; + + ret = winbond_write_vcr_op(spinand, WINBOND_DUMMY_CLK_VCR_ADDR, + WINBOND_DUMMY_CLK_COUNT); + if (ret) + return ret; + + ret = winbond_write_vcr_op(spinand, WINBOND_IO_MODE_VCR_ADDR, + WINBOND_IO_MODE_VCR_OCTAL_DTR); + if (ret) + return ret; + + /* Read flash ID to make sure the switch was successful. */ + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD_DTR(2, 0x9f9f, 8), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_DUMMY_DTR(16, 8), + SPI_MEM_OP_DATA_IN_DTR(SPINAND_MAX_ID_LEN, + spinand->scratchbuf, 8)); + + ret = spi_mem_exec_op(spinand->spimem, &op); + if (ret) + return ret; + + if (memcmp(spinand->scratchbuf, spinand->id.data, SPINAND_MAX_ID_LEN)) + return -EINVAL; + + return 0; +} + static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = { .init = winbond_spinand_init, + .octal_dtr_enable = winbond_spinand_octal_dtr_enable, }; const struct spinand_manufacturer winbond_spinand_manufacturer = { From patchwork Mon Oct 11 20:46:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 12551031 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFC86C433EF for ; Mon, 11 Oct 2021 20:47:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9215760462 for ; Mon, 11 Oct 2021 20:47:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235088AbhJKUtd (ORCPT ); Mon, 11 Oct 2021 16:49:33 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:44214 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235066AbhJKUtc (ORCPT ); Mon, 11 Oct 2021 16:49:32 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 19BKlMaR120704; Mon, 11 Oct 2021 15:47:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1633985242; bh=hBEDCpCpkhr3SrNZvFGRX6rQTq6Kf0koSfT3CM+ThKQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pWIhzd3oeF7jkKgeAsZvwS1ZbJqh6F6rAMek4Chk38aYOdU7o5SipFdQYnnCScPgL Hudnwts3jkcUyLkcXHxZweaS0yJ5WCIl0d/zV8aljQWOOyDoy4x31S49WUx/Yccp6e jaQ6MIIRykLABlifs4MrD73TgrYPQsxsvTWU8AR4= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 19BKlME9096816 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 11 Oct 2021 15:47:22 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Mon, 11 Oct 2021 15:47:22 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Mon, 11 Oct 2021 15:47:22 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 19BKkKEo069811; Mon, 11 Oct 2021 15:47:16 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Apurva Nandan , Patrice Chotard , Christophe Kerello , Boris Brezillon , , , CC: Subject: [PATCH v2 10/14] mtd: spinand: Add support for Power-on-Reset (PoR) instruction Date: Tue, 12 Oct 2021 02:16:15 +0530 Message-ID: <20211011204619.81893-11-a-nandan@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> References: <20211011204619.81893-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Manufacturers like Gigadevice and Winbond are adding Power-on-Reset functionality in their SPI NAND flash chips. PoR instruction consists of a 66h command followed by 99h command, and is different from the FFh reset. The reset command FFh just clears the status only registers, while the PoR command erases all the configurations written to the flash and is equivalent to a power-down -> power-up cycle. Add support for the Power-on-Reset command for any flash that provides this feature. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by: Apurva Nandan --- drivers/mtd/nand/spi/core.c | 43 +++++++++++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 17 +++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 2bea21bd9747..9b570570ee81 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -9,6 +9,7 @@ #define pr_fmt(fmt) "spi-nand: " fmt +#include #include #include #include @@ -668,6 +669,48 @@ static int spinand_reset_op(struct spinand_device *spinand) NULL); } +static int spinand_power_on_rst_op(struct spinand_device *spinand) +{ + struct spi_mem_op op; + int ret; + + if (!(spinand->flags & SPINAND_HAS_POR_CMD_BIT)) + return -EOPNOTSUPP; + + /* + * If flash is in a busy state, wait for it to finish the operation. + * As the operation is unknown, use reset poll delays here. + */ + ret = spinand_wait(spinand, + SPINAND_RESET_INITIAL_DELAY_US, + SPINAND_RESET_POLL_DELAY_US, + NULL); + if (ret) + return ret; + + op = (struct spi_mem_op)SPINAND_EN_POWER_ON_RST_OP; + + spinand_patch_op(spinand, &op); + ret = spi_mem_exec_op(spinand->spimem, &op); + if (ret) + return ret; + + op = (struct spi_mem_op)SPINAND_POWER_ON_RST_OP; + + spinand_patch_op(spinand, &op); + ret = spi_mem_exec_op(spinand->spimem, &op); + if (ret) + return ret; + + /* PoR can take max 500 us to complete, so sleep for 600 to 700 us*/ + usleep_range(SPINAND_POR_MIN_DELAY_US, SPINAND_POR_MAX_DELAY_US); + + dev_dbg(&spinand->spimem->spi->dev, + "%s SPI NAND reset to Power-On-Reset state.\n", + spinand->manufacturer->name); + return 0; +} + static int spinand_lock_block(struct spinand_device *spinand, u8 lock) { return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock); diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 21a4e5adcd59..baaf8e94f301 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -26,6 +26,18 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) +#define SPINAND_EN_POWER_ON_RST_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x66, 1), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPINAND_POWER_ON_RST_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x99, 1), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + #define SPINAND_WR_EN_DIS_OP(enable) \ SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \ SPI_MEM_OP_NO_ADDR, \ @@ -218,6 +230,8 @@ struct spinand_device; * reading/programming/erasing when the RESET occurs. Since we always * issue a RESET when the device is IDLE, 5us is selected for both initial * and poll delay. + * Power on Reset can take upto 500 us to complete, so sleep for 600 us + * to 700 us safely. */ #define SPINAND_READ_INITIAL_DELAY_US 6 #define SPINAND_READ_POLL_DELAY_US 5 @@ -227,6 +241,8 @@ struct spinand_device; #define SPINAND_WRITE_POLL_DELAY_US 15 #define SPINAND_ERASE_INITIAL_DELAY_US 250 #define SPINAND_ERASE_POLL_DELAY_US 50 +#define SPINAND_POR_MIN_DELAY_US 600 +#define SPINAND_POR_MAX_DELAY_US 700 #define SPINAND_WAITRDY_TIMEOUT_MS 400 @@ -351,6 +367,7 @@ struct spinand_ecc_info { #define SPINAND_HAS_QE_BIT BIT(0) #define SPINAND_HAS_CR_FEAT_BIT BIT(1) #define SPINAND_HAS_OCTAL_DTR_BIT BIT(2) +#define SPINAND_HAS_POR_CMD_BIT BIT(3) /** * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure From patchwork Mon Oct 11 20:46:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 12551079 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8B4CC433EF for ; Mon, 11 Oct 2021 21:40:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A9D0E60E54 for ; Mon, 11 Oct 2021 21:40:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235342AbhJKVmm (ORCPT ); Mon, 11 Oct 2021 17:42:42 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:52728 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229641AbhJKVml (ORCPT ); Mon, 11 Oct 2021 17:42:41 -0400 X-Greylist: delayed 3227 seconds by postgrey-1.27 at vger.kernel.org; Mon, 11 Oct 2021 17:42:41 EDT Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 19BKlSFS071163; Mon, 11 Oct 2021 15:47:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1633985248; bh=JsMJVwDttgmG/vVRT1b55ya+HKmXPSJxJ7o0HOFrZPc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZQjRBXuHJxJb5yA6WKWJqItXM6OGAChveEydtd36qYfsgp/00/bzx4xX+r/znG7IB vaBghenKIP+0YWw9InzK3KdbpKnbERKTkYGAVHm1U6b4mNySXIWh3VvLemospM4fOq swjp5UN89acG5e6zLtxtSPg63JEc0QvGArfY8IRo= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 19BKlSst106134 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 11 Oct 2021 15:47:28 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Mon, 11 Oct 2021 15:47:28 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Mon, 11 Oct 2021 15:47:28 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 19BKkKEp069811; Mon, 11 Oct 2021 15:47:23 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Apurva Nandan , Patrice Chotard , Christophe Kerello , Boris Brezillon , , , CC: Subject: [PATCH v2 11/14] mtd: spinand: Perform Power-on-Reset on the flash in mtd_suspend() Date: Tue, 12 Oct 2021 02:16:16 +0530 Message-ID: <20211011204619.81893-12-a-nandan@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> References: <20211011204619.81893-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org A soft reset using FFh command doesn't erase the flash's configuration and doesn't reset the SPI IO mode also. This can result in the flash being in a different SPI IO mode, e.g. Octal DTR, when resuming from sleep. This could put the flash in an unrecognized SPI IO mode, making it unusable. Perform a Power-on-Reset (PoR), if available in the flash, when performing mtd_suspend(). This would set the flash to clean state for reinitialization during resume and would also ensure that it is in standard SPI IO mode (1S-1S-1S) before the resume begins. Signed-off-by: Apurva Nandan --- drivers/mtd/nand/spi/core.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 9b570570ee81..60408531979a 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1316,6 +1316,11 @@ static void spinand_mtd_resume(struct mtd_info *mtd) int ret; spinand->reg_proto = SPINAND_SINGLE_STR; + /* + * PoR Reset (if available by the manufacturer) is performed at the suspend + * time. Hence, those flashes remain in power-on-state at this point, in a + * standard SPI IO mode. So, now the core unanimously performs a soft reset. + */ ret = spinand_reset_op(spinand); if (ret) return; @@ -1327,6 +1332,21 @@ static void spinand_mtd_resume(struct mtd_info *mtd) spinand_ecc_enable(spinand, false); } +static int spinand_mtd_suspend(struct mtd_info *mtd) +{ + struct spinand_device *spinand = mtd_to_spinand(mtd); + int ret; + + if (!(spinand->flags & SPINAND_HAS_POR_CMD_BIT)) + return 0; + + ret = spinand_power_on_rst_op(spinand); + if (ret) + dev_err(&spinand->spimem->spi->dev, "suspend() failed\n"); + + return ret; +} + static int spinand_init(struct spinand_device *spinand) { struct device *dev = &spinand->spimem->spi->dev; @@ -1399,6 +1419,7 @@ static int spinand_init(struct spinand_device *spinand) mtd->_erase = spinand_mtd_erase; mtd->_max_bad_blocks = nanddev_mtd_max_bad_blocks; mtd->_resume = spinand_mtd_resume; + mtd->_suspend = spinand_mtd_suspend; if (nand->ecc.engine) { ret = mtd_ooblayout_count_freebytes(mtd); From patchwork Mon Oct 11 20:46:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 12551033 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70FA2C433EF for ; Mon, 11 Oct 2021 20:47:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5BFC660462 for ; Mon, 11 Oct 2021 20:47:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235058AbhJKUtq (ORCPT ); Mon, 11 Oct 2021 16:49:46 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:44240 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230152AbhJKUtp (ORCPT ); Mon, 11 Oct 2021 16:49:45 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 19BKlYhB120796; Mon, 11 Oct 2021 15:47:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1633985254; bh=aE9h+iCpn2bT2W0hUbw4QOpt5bFgcYuqQIMWifBo9M0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OPgGLEnbJb7axirW0W1zFlv74snzAqIf0bWAf1HoyT7tD9lRYkpf8xzCu9rUQHcBm lXaLFLHpSB/MxQcb7bFDJQFXmWoJHqdkcIf/W8Ligi7RwB7omNjB2ZvPCzfAMIir3r 5LSEKeNIeP1T87laksN2XJ98wgITQsvEHIVoMxfs= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 19BKlYOt097449 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 11 Oct 2021 15:47:34 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Mon, 11 Oct 2021 15:47:34 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Mon, 11 Oct 2021 15:47:34 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 19BKkKEq069811; Mon, 11 Oct 2021 15:47:28 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Apurva Nandan , Patrice Chotard , Christophe Kerello , Boris Brezillon , , , CC: Subject: [PATCH v2 12/14] mtd: spinand: Add adjust_op() in Winbond manufacturer_ops Date: Tue, 12 Oct 2021 02:16:17 +0530 Message-ID: <20211011204619.81893-13-a-nandan@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> References: <20211011204619.81893-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add implementation of adjust_op() manufacturer_ops for Winbond. This handles the variations introduced in read register, read vcr, blk erase, page read and program exec ops when operating in Octal DTR mode. Read register operation requires 7 dummy cycles and read VCR operation requires 8 dummy cycles in Octal DTR mode instead of default 0 dummy cycle. Block erase, page read and program exec operations require 2 byte address in Octal DTR mode instead of default 3 bytes. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by: Apurva Nandan --- drivers/mtd/nand/spi/winbond.c | 45 ++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index e2cb82d68f96..d962221d4082 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -16,6 +16,13 @@ #define WINBOND_CFG_BUF_READ BIT(3) +#define WINBOND_BLK_ERASE_OPCODE 0xD8 +#define WINBOND_PAGE_READ_OPCODE 0x13 +#define WINBOND_PROG_EXEC_OPCODE 0x10 +#define WINBOND_READ_REG_OPCODE_1 0x05 +#define WINBOND_READ_REG_OPCODE_2 0x0F +#define WINBOND_READ_VCR_OPCODE 0x85 + /* Octal DTR SPI mode (8D-8D-8D) with Data Strobe output*/ #define WINBOND_IO_MODE_VCR_OCTAL_DTR 0xE7 #define WINBOND_IO_MODE_VCR_ADDR 0x00 @@ -197,9 +204,47 @@ static int winbond_spinand_octal_dtr_enable(struct spinand_device *spinand) return 0; } +static void winbond_spinand_adjust_op(struct spi_mem_op *op, + const enum spinand_proto reg_proto) +{ + /* + * To support both 1 byte opcode and 2 byte opcodes, extract the MSB + * byte from the opcode as the LSB byte in 2 byte opcode is treated as + * don't care. + */ + u8 opcode = op->cmd.opcode >> (8 * (op->cmd.nbytes - 1)); + + if (reg_proto == SPINAND_OCTAL_DTR) { + switch (opcode) { + case WINBOND_READ_REG_OPCODE_1: + case WINBOND_READ_REG_OPCODE_2: + op->dummy.nbytes = 14; + op->dummy.buswidth = 8; + op->dummy.dtr = true; + return; + + case WINBOND_READ_VCR_OPCODE: + op->dummy.nbytes = 16; + op->dummy.buswidth = 8; + op->dummy.dtr = true; + return; + + case WINBOND_BLK_ERASE_OPCODE: + case WINBOND_PAGE_READ_OPCODE: + case WINBOND_PROG_EXEC_OPCODE: + op->addr.nbytes = 2; + return; + + default: + return; + } + } +} + static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = { .init = winbond_spinand_init, .octal_dtr_enable = winbond_spinand_octal_dtr_enable, + .adjust_op = winbond_spinand_adjust_op, }; const struct spinand_manufacturer winbond_spinand_manufacturer = { From patchwork Mon Oct 11 20:46:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 12551035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B319C433F5 for ; Mon, 11 Oct 2021 20:47:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2338060462 for ; Mon, 11 Oct 2021 20:47:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235152AbhJKUtu (ORCPT ); Mon, 11 Oct 2021 16:49:50 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:44256 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235151AbhJKUtu (ORCPT ); Mon, 11 Oct 2021 16:49:50 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 19BKldmj120808; Mon, 11 Oct 2021 15:47:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1633985259; bh=dMVkJuUTqKoo3F2P0BflCjFyT83ni7c2ZoatqXxrVJg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xnvCZcMTePJms8lfhBp0nMlFR78ZEVRXsIInBUK9B+e4MmS06VlHLgBKImy7hhJr+ wLSXsPzJkOGIzsrpieyssuzWvx1Hljfj0vQmgPTrRLPIuQdoJzMUghFny190cFwJ3B TtZKGD2Fb7mrcEHP6thp2OwgSAll/4SLumSosKzw= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 19BKldJM097494 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 11 Oct 2021 15:47:39 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Mon, 11 Oct 2021 15:47:39 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Mon, 11 Oct 2021 15:47:39 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 19BKkKEr069811; Mon, 11 Oct 2021 15:47:34 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Apurva Nandan , Patrice Chotard , Christophe Kerello , Boris Brezillon , , , CC: Subject: [PATCH v2 13/14] mtd: spinand: winbond: Rename cache op_variants struct variable Date: Tue, 12 Oct 2021 02:16:18 +0530 Message-ID: <20211011204619.81893-14-a-nandan@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> References: <20211011204619.81893-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Till now, supported Winbond SPI NAND flashes had same supported op_variants. W35N01JW introduces Octal DTR SPI IO mode, so now different op_variants struct variables are required for different Winbond flashes. Hence, rename and append the flash name in the op_variants struct variable. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by: Apurva Nandan --- drivers/mtd/nand/spi/winbond.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index d962221d4082..1857836f19d0 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -31,7 +31,7 @@ #define WINBOND_DUMMY_CLK_COUNT 12 #define WINBOND_DUMMY_CLK_VCR_ADDR 0x01 -static SPINAND_OP_VARIANTS(read_cache_variants, +static SPINAND_OP_VARIANTS(read_cache_variants_w25xxgv, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), @@ -39,11 +39,11 @@ static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); -static SPINAND_OP_VARIANTS(write_cache_variants, +static SPINAND_OP_VARIANTS(write_cache_variants_w25xxgv, SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), SPINAND_PROG_LOAD(true, 0, NULL, 0)); -static SPINAND_OP_VARIANTS(update_cache_variants, +static SPINAND_OP_VARIANTS(update_cache_variants_w25xxgv, SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), SPINAND_PROG_LOAD(false, 0, NULL, 0)); @@ -95,9 +95,9 @@ static const struct spinand_info winbond_spinand_table[] = { SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab), NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 2), NAND_ECCREQ(1, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, - &write_cache_variants, - &update_cache_variants), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_w25xxgv, + &write_cache_variants_w25xxgv, + &update_cache_variants_w25xxgv), 0, SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL), SPINAND_SELECT_TARGET(w25m02gv_select_target)), @@ -105,9 +105,9 @@ static const struct spinand_info winbond_spinand_table[] = { SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa), NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), NAND_ECCREQ(1, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, - &write_cache_variants, - &update_cache_variants), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_w25xxgv, + &write_cache_variants_w25xxgv, + &update_cache_variants_w25xxgv), 0, SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)), }; From patchwork Mon Oct 11 20:46:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 12551087 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DF96C433FE for ; Mon, 11 Oct 2021 21:40:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8A73260E54 for ; Mon, 11 Oct 2021 21:40:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235384AbhJKVmq (ORCPT ); Mon, 11 Oct 2021 17:42:46 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:52728 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235360AbhJKVmo (ORCPT ); Mon, 11 Oct 2021 17:42:44 -0400 X-Greylist: delayed 3227 seconds by postgrey-1.27 at vger.kernel.org; Mon, 11 Oct 2021 17:42:41 EDT Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 19BKlj8w071329; Mon, 11 Oct 2021 15:47:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1633985265; bh=tuvJGDtfmxbDxCYN89TxVrBjoYFXrDF0qurPeskISLc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=kKP2rKImMUnTwX9DAdlXkCDeabMU7funQMvaz1zCJvBl/nsAK5KxpzCvGE9Cd3Ykf uCe9iN0c/UOJ2aMXSzj3ptuTE/LvnaUJIu5BcvUevsm+zQxoiRxNv7HtdL3NGowKjE GQWYVhykAfFYgUoKR4zhoSE25ohcbmPtu78fTmZU= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 19BKli6H056294 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 11 Oct 2021 15:47:45 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Mon, 11 Oct 2021 15:47:44 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Mon, 11 Oct 2021 15:47:44 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 19BKkKEs069811; Mon, 11 Oct 2021 15:47:40 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Apurva Nandan , Patrice Chotard , Christophe Kerello , Boris Brezillon , , , CC: Subject: [PATCH v2 14/14] mtd: spinand: winbond: Add support for Winbond W35N01JW SPI NAND flash Date: Tue, 12 Oct 2021 02:16:19 +0530 Message-ID: <20211011204619.81893-15-a-nandan@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> References: <20211011204619.81893-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Winbond W35N01JW is a SPI NAND flash supporting Octal DTR SPI protocol. Add op_variants for W35N01JW, which include the Octal DTR read/write page ops as well. Add W35N01JW's OOB layout functions for the mtd_ooblayout_ops. Finally, add an entry for W35N01JW in spinand_info table. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by: Apurva Nandan --- drivers/mtd/nand/spi/winbond.c | 53 ++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 1857836f19d0..8f687b6a6697 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -47,6 +47,19 @@ static SPINAND_OP_VARIANTS(update_cache_variants_w25xxgv, SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), SPINAND_PROG_LOAD(false, 0, NULL, 0)); +static SPINAND_OP_VARIANTS(read_cache_variants_w35n01jw, + SPINAND_PAGE_READ_FROM_CACHE_OCTALIO_DTR_OP(0, 24, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + +static SPINAND_OP_VARIANTS(write_cache_variants_w35n01jw, + SPINAND_PROG_LOAD_OCTALIO_DTR(true, 0, NULL, 0), + SPINAND_PROG_LOAD(true, 0, NULL, 0)); + +static SPINAND_OP_VARIANTS(update_cache_variants_w35n01jw, + SPINAND_PROG_LOAD_OCTALIO_DTR(false, 0, NULL, 0), + SPINAND_PROG_LOAD(false, 0, NULL, 0)); + static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *region) { @@ -71,11 +84,40 @@ static int w25m02gv_ooblayout_free(struct mtd_info *mtd, int section, return 0; } +static int w35n01jw_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section > 7) + return -ERANGE; + + region->offset = (16 * section) + 12; + region->length = 4; + + return 0; +} + +static int w35n01jw_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section > 7) + return -ERANGE; + + region->offset = (16 * section) + 2; + region->length = 10; + + return 0; +} + static const struct mtd_ooblayout_ops w25m02gv_ooblayout = { .ecc = w25m02gv_ooblayout_ecc, .free = w25m02gv_ooblayout_free, }; +static const struct mtd_ooblayout_ops w35n01jw_ooblayout = { + .ecc = w35n01jw_ooblayout_ecc, + .free = w35n01jw_ooblayout_free, +}; + static int w25m02gv_select_target(struct spinand_device *spinand, unsigned int target) { @@ -110,6 +152,17 @@ static const struct spinand_info winbond_spinand_table[] = { &update_cache_variants_w25xxgv), 0, SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)), + SPINAND_INFO("W35N01JW", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdc), + NAND_MEMORG(1, 4096, 128, 64, 512, 20, 1, 1, 1), + NAND_ECCREQ(1, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_w35n01jw, + &write_cache_variants_w35n01jw, + &update_cache_variants_w35n01jw), + SPINAND_HAS_OCTAL_DTR_BIT | SPINAND_HAS_POR_CMD_BIT | + SPINAND_HAS_CR_FEAT_BIT, + SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL)), + }; static int winbond_spinand_init(struct spinand_device *spinand)