From patchwork Tue Oct 12 11:42:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Horatiu Vultur X-Patchwork-Id: 12552255 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AB77C433F5 for ; Tue, 12 Oct 2021 11:44:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1829B60EFE for ; Tue, 12 Oct 2021 11:44:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1829B60EFE Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=uSLJxJ9UtXQhlRYeD7SfOBt8Xqe9e8EahWBSn1Rr+JA=; b=MCd0OpJ9CEp6Dt NN7jrKAB4frUEsja3e+x9VH0gjLz4CpAswaEAT/UboKyz+FDzYuFcXywheHI/mrwX+UEyDnejRy/r XhrvaCkDQQ1y4UcbrljKxjNDC1oxoVqIFTmxoZwLgglNxdlwWx57Ig1SsDxqOmcSC1ZnT1fZRKwbh luan4qxqxgS0qYkSeUEeyi0Om4oKnDc8RE1QjJZMMej4AheLJCTr8rnEbHZ/f5pzItJONB/6EUQdi 8F8XMMU3i87LSnmD6VFawbqV7qelhGwPKJQ2ll4Gwgy4wEfpLgCEP13Nod/tRg3/S/IXY2XPNdnJ5 RnXVgWpWqKnpO7RoDwow==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1maGAL-00Cg3I-ED; Tue, 12 Oct 2021 11:41:53 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1maG9n-00Cfrj-Fi for linux-arm-kernel@lists.infradead.org; Tue, 12 Oct 2021 11:41:20 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634038880; x=1665574880; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1WE6/5/aJUTcV6BB/n4Nfkh2cDfIknqMkN9l0AVkzEM=; b=O2AE9bu24IWLEvvmjsn9DBK0nn2Rq5b3aU6vkM1FRkjmWjmlQ4hk7QDw eORpBP5rEURBJXFkwS6nu6Px4q4qCyN0ufelYNt8KTbiMr3aIapRbzoNu 3bVKuEyCOSBOZILIRTiajf80WtnogZhRWESmMHWu9rSdCBjrWAm7kJGpr gBCzal9uiXvfFHYdpsC81fwwJoXg7vWvwyGWHPoU2QazG8tYo2UbYh6pk M89e9P/iot/fcWOzd7v7urGXI6CDH3nFZ+wAVPNn8XHlUW2/otAruOEpr bY7u0DDMUMe7na0+NCs9Pp2V0KndfteT2IcoFKjy/8mlrWmIZkCcEB+6g Q==; IronPort-SDR: s688RxBiOkkeeMoERwZJ5tkhet3UxEiGz9mt4L8AYk46XtDO32vgDMUF8Fa2ulxcj49GQd/XIA 11+AocGyerkxxBB+1yjpdQQubH3d5cNpQIDejIHYLsEIvbYyy8QZS2kYdtT5Mp+/RamYOKZcgO cCm+e/YfQ4opLO0PkkQ15Z24d/WgbDSs5Y3JG8e7kSpBcRX35FxsZuaBiCMf5GCIN60yAWVGTr V2ssgZEk1yXT8cM2ier8+yLWD1Z9AFF150NeRDwTix8BDnC5d5N6XLPfi1ujI0pd/hLOlxUrRM NBcPxN/nsJ6pdgQSCD0PUz+O X-IronPort-AV: E=Sophos;i="5.85,367,1624345200"; d="scan'208";a="139395342" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 12 Oct 2021 04:41:18 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 12 Oct 2021 04:41:16 -0700 Received: from soft-dev3-1.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 12 Oct 2021 04:41:14 -0700 From: Horatiu Vultur To: , , , , , , , , CC: Horatiu Vultur Subject: [PATCH v2 1/2] dt-bindings: reset: Add lan966x support Date: Tue, 12 Oct 2021 13:42:37 +0200 Message-ID: <20211012114238.2060101-2-horatiu.vultur@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211012114238.2060101-1-horatiu.vultur@microchip.com> References: <20211012114238.2060101-1-horatiu.vultur@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211012_044119_583414_FFE05AC3 X-CRM114-Status: UNSURE ( 9.95 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds support for lan966x. Signed-off-by: Horatiu Vultur --- .../devicetree/bindings/reset/microchip,rst.yaml | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml b/Documentation/devicetree/bindings/reset/microchip,rst.yaml index 370579aeeca1..622cf3d0455d 100644 --- a/Documentation/devicetree/bindings/reset/microchip,rst.yaml +++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml @@ -20,7 +20,11 @@ properties: pattern: "^reset-controller@[0-9a-f]+$" compatible: - const: microchip,sparx5-switch-reset + oneOf: + - items: + - const: microchip,sparx5-switch-reset + - items: + - const: microchip,lan966x-switch-reset reg: items: @@ -37,6 +41,14 @@ properties: $ref: "/schemas/types.yaml#/definitions/phandle" description: syscon used to access CPU reset + cuphy-syscon: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: syscon used to access CuPHY + + gpios: + description: used for release of reset of the external PHY + maxItems: 1 + required: - compatible - reg From patchwork Tue Oct 12 11:42:38 2021 Content-Type: text/plain; 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d="scan'208";a="139395349" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 12 Oct 2021 04:41:21 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 12 Oct 2021 04:41:19 -0700 Received: from soft-dev3-1.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 12 Oct 2021 04:41:17 -0700 From: Horatiu Vultur To: , , , , , , , , CC: Horatiu Vultur Subject: [PATCH v2 2/2] reset: mchp: sparx5: Extend support for lan966x Date: Tue, 12 Oct 2021 13:42:38 +0200 Message-ID: <20211012114238.2060101-3-horatiu.vultur@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211012114238.2060101-1-horatiu.vultur@microchip.com> References: <20211012114238.2060101-1-horatiu.vultur@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211012_044120_880706_E560B6B0 X-CRM114-Status: GOOD ( 22.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch extends sparx5 driver to support also the lan966x. The process to reset the switch is the same only it has different offsets. Therefore make the driver more generic and add support for lan966x. Signed-off-by: Horatiu Vultur Reviewed-by: Andrew Lunn --- drivers/reset/Kconfig | 2 +- drivers/reset/reset-microchip-sparx5.c | 80 +++++++++++++++++++++++--- 2 files changed, 73 insertions(+), 9 deletions(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index be799a5abf8a..36ce6c8bcf1e 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -116,7 +116,7 @@ config RESET_LPC18XX config RESET_MCHP_SPARX5 bool "Microchip Sparx5 reset driver" - depends on ARCH_SPARX5 || COMPILE_TEST + depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST default y if SPARX5_SWITCH select MFD_SYSCON help diff --git a/drivers/reset/reset-microchip-sparx5.c b/drivers/reset/reset-microchip-sparx5.c index f01e7db8e83b..6594ab5c15fe 100644 --- a/drivers/reset/reset-microchip-sparx5.c +++ b/drivers/reset/reset-microchip-sparx5.c @@ -6,6 +6,7 @@ * The Sparx5 Chip Register Model can be browsed at this location: * https://github.com/microchip-ung/sparx-5_reginfo */ +#include #include #include #include @@ -13,15 +14,22 @@ #include #include -#define PROTECT_REG 0x84 -#define PROTECT_BIT BIT(10) -#define SOFT_RESET_REG 0x00 -#define SOFT_RESET_BIT BIT(1) +struct reset_props { + u32 protect_reg; + u32 protect_bit; + u32 reset_reg; + u32 reset_bit; + u32 cuphy_reg; + u32 cuphy_bit; +}; struct mchp_reset_context { struct regmap *cpu_ctrl; struct regmap *gcb_ctrl; + struct regmap *cuphy_ctrl; struct reset_controller_dev rcdev; + const struct reset_props *props; + struct gpio_desc *reset_gpio; }; static struct regmap_config sparx5_reset_regmap_config = { @@ -36,17 +44,39 @@ static int sparx5_switch_reset(struct reset_controller_dev *rcdev, struct mchp_reset_context *ctx = container_of(rcdev, struct mchp_reset_context, rcdev); u32 val; + int err; /* Make sure the core is PROTECTED from reset */ - regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT, PROTECT_BIT); + regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg, + ctx->props->protect_bit, ctx->props->protect_bit); /* Start soft reset */ - regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT); + regmap_write(ctx->gcb_ctrl, ctx->props->reset_reg, + ctx->props->reset_bit); /* Wait for soft reset done */ - return regmap_read_poll_timeout(ctx->gcb_ctrl, SOFT_RESET_REG, val, - (val & SOFT_RESET_BIT) == 0, + err = regmap_read_poll_timeout(ctx->gcb_ctrl, ctx->props->reset_reg, val, + (val & ctx->props->reset_bit) == 0, 1, 100); + if (err) + return err; + + if (!ctx->cuphy_ctrl) + return 0; + + /* In case there are external PHYs toggle the GPIO to release the reset + * of the PHYs + */ + if (ctx->reset_gpio) { + gpiod_direction_output(ctx->reset_gpio, 1); + gpiod_set_value(ctx->reset_gpio, 0); + gpiod_set_value(ctx->reset_gpio, 1); + gpiod_set_value(ctx->reset_gpio, 0); + } + + /* Release the reset of internal PHY */ + return regmap_update_bits(ctx->cuphy_ctrl, ctx->props->cuphy_reg, + ctx->props->cuphy_bit, ctx->props->cuphy_bit); } static const struct reset_control_ops sparx5_reset_ops = { @@ -111,17 +141,51 @@ static int mchp_sparx5_reset_probe(struct platform_device *pdev) if (err) return err; + /* This resource is required on lan966x, to take the internal PHYs out + * of reset + */ + err = mchp_sparx5_map_syscon(pdev, "cuphy-syscon", &ctx->cuphy_ctrl); + if (err && err != -ENODEV) + return err; + ctx->rcdev.owner = THIS_MODULE; ctx->rcdev.nr_resets = 1; ctx->rcdev.ops = &sparx5_reset_ops; ctx->rcdev.of_node = dn; + ctx->props = device_get_match_data(&pdev->dev); + + ctx->reset_gpio = devm_gpiod_get_optional(&pdev->dev, NULL, GPIOD_OUT_LOW); + if (IS_ERR(ctx->reset_gpio)) { + dev_err(&pdev->dev, "Could not get reset GPIO\n"); + return PTR_ERR(ctx->reset_gpio); + } return devm_reset_controller_register(&pdev->dev, &ctx->rcdev); } +static const struct reset_props reset_props_sparx5 = { + .protect_reg = 0x84, + .protect_bit = BIT(10), + .reset_reg = 0x0, + .reset_bit = BIT(1), +}; + +static const struct reset_props reset_props_lan966x = { + .protect_reg = 0x88, + .protect_bit = BIT(5), + .reset_reg = 0x0, + .reset_bit = BIT(1), + .cuphy_reg = 0x10, + .cuphy_bit = BIT(0), +}; + static const struct of_device_id mchp_sparx5_reset_of_match[] = { { .compatible = "microchip,sparx5-switch-reset", + .data = &reset_props_sparx5, + }, { + .compatible = "microchip,lan966x-switch-reset", + .data = &reset_props_lan966x, }, { } };