From patchwork Thu Oct 14 17:12:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 12559045 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0568C433EF for ; Thu, 14 Oct 2021 17:43:18 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 728AA61039 for ; Thu, 14 Oct 2021 17:43:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 728AA61039 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 01A886E1E6; Thu, 14 Oct 2021 17:43:17 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 18E356E1B6 for ; Thu, 14 Oct 2021 17:43:15 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10137"; a="225204555" X-IronPort-AV: E=Sophos;i="5.85,373,1624345200"; d="scan'208";a="225204555" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2021 10:13:03 -0700 X-IronPort-AV: E=Sophos;i="5.85,372,1624345200"; d="scan'208";a="442908963" Received: from dnvo-mobl.amr.corp.intel.com (HELO rdvivi-mobl4.intel.com) ([10.212.120.113]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2021 10:13:01 -0700 From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Cc: Rodrigo Vivi , Jani Nikula , Matthew Brost Date: Thu, 14 Oct 2021 13:12:53 -0400 Message-Id: <20211014171257.1615604-1-rodrigo.vivi@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/5] drm/i915: Clean-up bonding debug message. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We should stop using the gen name and the "+" to reference the newer platforms. And on this case specifically we can simplify the debug message even further. Cc: Jani Nikula Cc: Matthew Brost Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index d225d3dd0b40..30759b651180 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -479,7 +479,7 @@ set_proto_ctx_engines_bond(struct i915_user_extension __user *base, void *data) if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915) && !IS_ROCKETLAKE(i915) && !IS_ALDERLAKE_S(i915)) { drm_dbg(&i915->drm, - "Bonding on gen12+ aside from TGL, RKL, and ADL_S not supported\n"); + "Bonding not supported on this platform\n"); return -ENODEV; } From patchwork Thu Oct 14 17:12:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 12559041 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAA0DC433EF for ; Thu, 14 Oct 2021 17:43:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B353961039 for ; Thu, 14 Oct 2021 17:43:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B353961039 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4F8036E1B6; Thu, 14 Oct 2021 17:43:15 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id B3FAD6E1B6 for ; Thu, 14 Oct 2021 17:43:14 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10137"; a="225204560" X-IronPort-AV: E=Sophos;i="5.85,373,1624345200"; d="scan'208";a="225204560" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2021 10:13:04 -0700 X-IronPort-AV: E=Sophos;i="5.85,372,1624345200"; d="scan'208";a="442908980" Received: from dnvo-mobl.amr.corp.intel.com (HELO rdvivi-mobl4.intel.com) ([10.212.120.113]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2021 10:13:02 -0700 From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Cc: Rodrigo Vivi , Alan Previn , Daniele Ceraolo Spurio Date: Thu, 14 Oct 2021 13:12:54 -0400 Message-Id: <20211014171257.1615604-2-rodrigo.vivi@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211014171257.1615604-1-rodrigo.vivi@intel.com> References: <20211014171257.1615604-1-rodrigo.vivi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/5] drm/i915: Clean up PXP Kconfig info. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" During the review I focused on stop the using of the "+" to reference the newer platforms, but I forgot that we are in a process of making things more clear and differentiate graphics and display versions. So, let me to clean up this a bit. Also, we don't need any version mentioned in the config menu entry, only in the help. Cc: Alan Previn Cc: Daniele Ceraolo Spurio Signed-off-by: Rodrigo Vivi Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/Kconfig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 8859444943a0..bf041b26ffec 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -132,15 +132,15 @@ config DRM_I915_GVT_KVMGT Intel GVT-g. config DRM_I915_PXP - bool "Enable Intel PXP support for Intel Gen12 and newer platform" + bool "Enable Intel PXP support" depends on DRM_I915 depends on INTEL_MEI && INTEL_MEI_PXP default n help - PXP (Protected Xe Path) is an i915 component, available on GEN12 and - newer GPUs, that helps to establish the hardware protected session and - manage the status of the alive software session, as well as its life - cycle. + PXP (Protected Xe Path) is an i915 component, available on graphics + version 12 and newer GPUs, that helps to establish the hardware + protected session and manage the status of the alive software session, + as well as its life cycle. menu "drm/i915 Debugging" depends on DRM_I915 From patchwork Thu Oct 14 17:12:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 12559043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F1FBC433F5 for ; Thu, 14 Oct 2021 17:43:17 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 604DF61037 for ; Thu, 14 Oct 2021 17:43:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 604DF61037 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EF7FE6E1D6; Thu, 14 Oct 2021 17:43:16 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4697F6E1D6 for ; Thu, 14 Oct 2021 17:43:15 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10137"; a="225204566" X-IronPort-AV: E=Sophos;i="5.85,373,1624345200"; d="scan'208";a="225204566" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2021 10:13:04 -0700 X-IronPort-AV: E=Sophos;i="5.85,372,1624345200"; d="scan'208";a="442908995" Received: from dnvo-mobl.amr.corp.intel.com (HELO rdvivi-mobl4.intel.com) ([10.212.120.113]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2021 10:13:04 -0700 From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Cc: Rodrigo Vivi , Jani Nikula Date: Thu, 14 Oct 2021 13:12:55 -0400 Message-Id: <20211014171257.1615604-3-rodrigo.vivi@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211014171257.1615604-1-rodrigo.vivi@intel.com> References: <20211014171257.1615604-1-rodrigo.vivi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/5] drm/i915/display: Random clean up of comments around display version. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We should prefer Display version over the old global "gen" thing. Of course we are not changing functions and variables and the legacy there, but at least let's start to document things properly and set some good examples. Cc: Jani Nikula Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +- drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- drivers/gpu/drm/i915/display/intel_display_types.h | 6 +++--- drivers/gpu/drm/i915/display/intel_dsb.c | 2 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 10 +++++----- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index e04767695530..08ffea6e1ae3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -2244,7 +2244,7 @@ static int i915_lpsp_capability_show(struct seq_file *m, void *data) /* * Actually TGL can drive LPSP on port till DDI_C * but there is no physical connected DDI_C on TGL sku's, - * even driver is not initilizing DDI_C port for gen12. + * even driver is not initilizing DDI_C port for display 12. */ lpsp_capable = encoder->port <= PORT_B; else if (DISPLAY_VER(i915) == 11) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 1672604f9ef7..7f94ef997ea7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5287,7 +5287,7 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv) MBUS_ABOX_BW_CREDIT(1); /* - * gen12 platforms that use abox1 and abox2 for pixel data reads still + * Display 12 platforms using abox1 and abox2 for pixel data reads still * expect us to program the abox_ctl0 register as well, even though * we don't have to program other instance-0 registers like BW_BUDDY. */ diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 39e11eaec1a3..73c8500c79d1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -506,9 +506,9 @@ struct intel_hdcp { int cp_irq_count_cached; /* - * HDCP register access for gen12+ need the transcoder associated. - * Transcoder attached to the connector could be changed at modeset. - * Hence caching the transcoder here. + * HDCP register access for display 12 and newer platforms need the + * transcoder associated. Transcoder attached to the connector could be + * changed at modeset. Hence caching the transcoder here. */ enum transcoder cpu_transcoder; /* Only used for DP MST stream encryption */ diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 62a8a69f9f5d..e759d98bb766 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -18,7 +18,7 @@ * engine that can be programmed to download the DSB from memory. * It allows driver to batch submit display HW programming. This helps to * reduce loading time and CPU activity, thereby making the context switch - * faster. DSB Support added from Gen12 Intel graphics based platform. + * faster. DSB Support is introduced on Display Version 12. * * DSB's can access only the pipe, plane, and transcoder Data Island Packet * registers. diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 4509fe7438e8..e377a192b744 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -2188,7 +2188,7 @@ static int initialize_hdcp_port_data(struct intel_connector *connector, /* * As associated transcoder is set and modified at modeset, here fw_tc * is initialized to zero (invalid transcoder index). This will be - * retained for fw_tc = MEI_INVALID_TRANSCODER; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 7a205fd5023b..920b86f165a1 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -68,7 +68,7 @@ * * DC3CO (DC3 clock off) * - * On top of PSR2, GEN12 adds a intermediate power savings state that turns + * On top of PSR2, Display 12 adds a intermediate power savings state that turns * clock off automatically during PSR2 idle state. * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep * entry/exit allows the HW to enter a low-power state even when page flipping @@ -117,9 +117,9 @@ static void psr_irq_control(struct intel_dp *intel_dp) u32 mask, val; /* - * gen12+ has registers relative to transcoder and one per transcoder - * using the same bit definition: handle it as TRANSCODER_EDP to force - * 0 shift in bit definition + * Display 12 and newer platforms have registers relative to transcoder + * and one per transcoder using the same bit definition: handle it as + * TRANSCODER_EDP to force 0 shift in bit definition. */ if (DISPLAY_VER(dev_priv) >= 12) { trans_shift = 0; @@ -2193,7 +2193,7 @@ void intel_psr_init(struct intel_dp *intel_dp) * than eDP one. * For now it only supports one instance of PSR for BDW, GEN9 and GEN11. * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11. - * But GEN12 supports a instance of PSR registers per transcoder. + * But Display 12 supports a instance of PSR registers per transcoder. */ if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) { drm_dbg_kms(&dev_priv->drm, From patchwork Thu Oct 14 17:12:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 12559049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E00C7C433FE for ; Thu, 14 Oct 2021 17:43:24 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A92076105A for ; Thu, 14 Oct 2021 17:43:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A92076105A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 47F966E2C0; Thu, 14 Oct 2021 17:43:24 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id C2B646E1D6 for ; Thu, 14 Oct 2021 17:43:15 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10137"; a="225204570" X-IronPort-AV: E=Sophos;i="5.85,373,1624345200"; d="scan'208";a="225204570" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2021 10:13:06 -0700 X-IronPort-AV: E=Sophos;i="5.85,372,1624345200"; d="scan'208";a="442909011" Received: from dnvo-mobl.amr.corp.intel.com (HELO rdvivi-mobl4.intel.com) ([10.212.120.113]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2021 10:13:05 -0700 From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Cc: Rodrigo Vivi , Joonas Lahtinen Date: Thu, 14 Oct 2021 13:12:56 -0400 Message-Id: <20211014171257.1615604-4-rodrigo.vivi@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211014171257.1615604-1-rodrigo.vivi@intel.com> References: <20211014171257.1615604-1-rodrigo.vivi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/5] drm/i915/gt: Random clean up of comments around display version. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Although gen12 is a valid thing for the gt side on TGL, we should prefer graphics version over the old global "gen" thing. Of course we are not changing functions and variables and the legacy there, but at least let's start to document things properly and set some good examples. Cc: Joonas Lahtinen Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 73a79c2acd3a..b6b9d324f519 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -1650,7 +1650,7 @@ static void invalidate_csb_entries(const u64 *first, const u64 *last) } /* - * Starting with Gen12, the status has a new format: + * Starting with Graphics version 12, the status has a new format: * * bit 0: switched to new queue * bit 1: reserved diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 3ef9eaf8c50e..ed0f0e81bb56 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -611,10 +611,10 @@ static const u8 dg2_rcs_offsets[] = { static const u8 *reg_offsets(const struct intel_engine_cs *engine) { /* - * The gen12+ lists only have the registers we program in the basic - * default state. We rely on the context image using relative - * addressing to automatic fixup the register state between the - * physical engines for virtual engine. + * The graphics 12 and newer platforms, lists only have the registers we + * program in the basic default state. We rely on the context image + * using relative addressing to automatic fixup the register state + * between the physical engines for virtual engine. */ GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 && !intel_engine_has_relative_mmio(engine)); From patchwork Thu Oct 14 17:12:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 12559047 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B5F6C433F5 for ; Thu, 14 Oct 2021 17:43:22 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 13DAD61037 for ; Thu, 14 Oct 2021 17:43:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 13DAD61037 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 933516E1F4; Thu, 14 Oct 2021 17:43:21 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id CB1856E1E6 for ; Thu, 14 Oct 2021 17:43:15 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10137"; a="225204581" X-IronPort-AV: E=Sophos;i="5.85,373,1624345200"; d="scan'208";a="225204581" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2021 10:13:06 -0700 X-IronPort-AV: E=Sophos;i="5.85,372,1624345200"; d="scan'208";a="442909020" Received: from dnvo-mobl.amr.corp.intel.com (HELO rdvivi-mobl4.intel.com) ([10.212.120.113]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2021 10:13:06 -0700 From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Cc: Rodrigo Vivi , Jani Nikula , Joonas Lahtinen Date: Thu, 14 Oct 2021 13:12:57 -0400 Message-Id: <20211014171257.1615604-5-rodrigo.vivi@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211014171257.1615604-1-rodrigo.vivi@intel.com> References: <20211014171257.1615604-1-rodrigo.vivi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/5] drm/i915: Other random display and graphics version comment clean-ups X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We should prefer Graphics and Display version over the old global "gen" thing. Of course we are not changing functions and variables and the legacy there, but at least let's start to document things properly and set some good examples. Cc: Jani Nikula Cc: Joonas Lahtinen Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_irq.c | 2 +- drivers/gpu/drm/i915/i915_perf.c | 8 ++++---- drivers/gpu/drm/i915/i915_reg.h | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 77680bca46ee..c50ae0843757 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2362,7 +2362,7 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) intel_psr_irq_handler(intel_dp, psr_iir); - /* prior GEN12 only have one EDP PSR */ + /* prior Display 12 only have one EDP PSR */ if (DISPLAY_VER(dev_priv) < 12) break; } diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 2f01b8c0284c..44e149a4cae8 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -3444,10 +3444,10 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf, * MI_REPORT_PERF_COUNT commands and so consider it a privileged op to * enable the OA unit by default. * - * For Gen12+ we gain a new OAR unit that only monitors the RCS on a - * per context basis. So we can relax requirements there if the user - * doesn't request global stream access (i.e. query based sampling - * using MI_RECORD_PERF_COUNT. + * For Graphics 12 and newer platforms, we gain a new OAR unit that only + * monitors the RCS on a per context basis. So we can relax requirements + * there if the user doesn't request global stream access (i.e. query + * based sampling using MI_RECORD_PERF_COUNT. */ if (IS_HASWELL(perf->i915) && specific_ctx) privileged_op = false; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a897f4abea0c..b01fe09729ef 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8264,8 +8264,8 @@ enum { #define DISP_IPC_ENABLE (1 << 3) /* - * The below are numbered starting from "S1" on gen11/gen12, but starting - * with gen13 display, the bspec switches to a 0-based numbering scheme + * The below are numbered starting from "S1" on display versions 11 and 12, but + * starting with display 13, the bspec switches to a 0-based numbering scheme * (although the addresses stay the same so new S0 = old S1, new S1 = old S2). * We'll just use the 0-based numbering here for all platforms since it's the * way things will be named by the hardware team going forward, plus it's more