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Fri, 15 Oct 2021 09:01:46 +0000 From: Ioana Ciornei To: davem@davemloft.net, kuba@kernel.org Cc: youri.querry_1@nxp.com, leoyang.li@nxp.com, netdev@vger.kernel.org, Ioana Ciornei Subject: [PATCH v2 net-next 1/5] soc: fsl: dpio: extract the QBMAN clock frequency from the attributes Date: Fri, 15 Oct 2021 12:01:23 +0300 Message-Id: <20211015090127.241910-2-ioana.ciornei@nxp.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211015090127.241910-1-ioana.ciornei@nxp.com> References: <20211015090127.241910-1-ioana.ciornei@nxp.com> X-ClientProxiedBy: AM8P190CA0018.EURP190.PROD.OUTLOOK.COM (2603:10a6:20b:219::23) To AM4PR0401MB2308.eurprd04.prod.outlook.com (2603:10a6:200:4f::13) MIME-Version: 1.0 Received: from yoga-910.localhost (188.26.184.231) by AM8P190CA0018.EURP190.PROD.OUTLOOK.COM (2603:10a6:20b:219::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.15 via Frontend Transport; Fri, 15 Oct 2021 09:01:46 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 453e63b0-198d-4e8a-6306-08d98fba6ab9 X-MS-TrafficTypeDiagnostic: AM0PR04MB5988: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: s5btT35vfCkseJP+GWpHoeGk/KhS95LAGcInu+mUPxkkHlyNydE6NR/VQiVrf7c1fLMysCK9XuVZo0aXEaB0Ec1h2S/zHWGckVSFyqpWrbI3yckLthi+e9HnrJU5ZTj0u5eyMbI1fp/EOFGWYMPWP58wzdmaeUfyzn/3JDFfEsSeTCPD6LwkhIMQzGluOBb9P946qNOH4gJnhrIlfwiKCjGQFeEWa3kEgVH1uBniHhxdbsCCTQEmwPPkgpYRonJ9FxLtk7HqbCVmH0p53g5pRGGnlbIFmr0NWLE1P8gTMqCuDptpKcWLaZOC8zP9GlNbUvRIo5+UW+u8yfZJl+Sroi7sCoSWnBEQIrDQ6QNKqkrNn6xvPOKomvsF7l3PDo8OwmpFd687k65ljj8m/CHVh0cDoB0co4mU127ZHdPSLA4A0MwKv5Rs24RK5WzM7vYK4JhilfMSDip9zyvkLpttwyn7G1JUJp2Gv23Lw/4zRU6t8WglpObcXJCkF+x49kHBZmq6H+znJ7w1HIUBjZywLUz74n3PD/93AZI2ZJllZPFjuSqjHrqa8ygIcnkyyA8xCfUDtTBhg7nSrdOiBCAmJIBf+9RyX17yERizwZAMdCgpb/q45Z5RL9QY7ZFvH1u1rFxsXZLI3eA84ElVOo/1BG0PsidJGI5dkSSSMoTpVVCexHd4LzHiNgP3zvlq0UFGueL34L63eW6bomwGVMPn1w2wa96wlDb9RHcgItZV1wNzL+HCPyQbLEmSuV3RhPEY9c0SG3L2edswr6Z5bnC/VpBYQysitBDV6R7EpRjJ9upvj85jDSLEntHMJtimb7goYMDc8FvaDwGbe7LLfIZ9ACl7wXIsWKRvTXhqlrLlxLXzQd60JF2DweS0zb0WePW8oh4jGk6GBiv8EytLN3CKOMSFAXMjT8wMb7RCxj+xoVwQE6YPH1jhLpwiIuX7v7i0DjJhEadfCuQlbY5aZ6Q1SCwjLqeX+SWC0BHxHCfC7pOScrMvBCOPABQFBSG3SSZRUZitEALWCpV4ThibqLdmxXKjACqfszi2pjgNYP+7doUlTi1Yz+fOk3hAdqF7Yu3vYjNPtB82KiYUnVLlVVMth9euQb1x17H7942hp/cibwzkGek+udPMs5JFJO2w9MDBh9yuAnVOUsWv69W6xPlSjthazm5NXIu8y4NZ3/JpO+z2VjGQxiuWqw74A4A4MpyaecUKMMKmHsKBZwViKvfQpPV9iQExmchc13j/wCdbl1NUBVHOM46kaEKhOFf6gEU/TwH+Wv6732nhRTyv3ImVD/Qbd1FlOrSE9E7GHPP5dtwsUdOIPqAgIg+arSDnWNg1 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 453e63b0-198d-4e8a-6306-08d98fba6ab9 X-MS-Exchange-CrossTenant-AuthSource: AM4PR0401MB2308.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2021 09:01:46.8588 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NaSKzSh6qE64d4nY9uwMYglqgir6UoXYbyiSJX/CRroxaULqBUmTFw9J0AaSmPTVVhqaal8Wqwm6PVmtNMqUbg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB5988 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Through the dpio_get_attributes() firmware call the dpio driver has access to the QBMAN clock frequency. Extend the structure which holds the firmware's response so that we can have access to this information. This will be needed in the next patches which also add support for interrupt coalescing which needs to be configured based on the frequency. Signed-off-by: Ioana Ciornei --- Changes in v2: - documented the new qman_clk field drivers/soc/fsl/dpio/dpio-cmd.h | 3 +++ drivers/soc/fsl/dpio/dpio-driver.c | 1 + drivers/soc/fsl/dpio/dpio-service.c | 1 + drivers/soc/fsl/dpio/dpio.c | 1 + drivers/soc/fsl/dpio/dpio.h | 2 ++ drivers/soc/fsl/dpio/qbman-portal.h | 1 + include/soc/fsl/dpaa2-io.h | 2 ++ 7 files changed, 11 insertions(+) diff --git a/drivers/soc/fsl/dpio/dpio-cmd.h b/drivers/soc/fsl/dpio/dpio-cmd.h index e13fd3ac1939..2fbcb78cdaaf 100644 --- a/drivers/soc/fsl/dpio/dpio-cmd.h +++ b/drivers/soc/fsl/dpio/dpio-cmd.h @@ -46,6 +46,9 @@ struct dpio_rsp_get_attr { __le64 qbman_portal_ci_addr; /* cmd word 3 */ __le32 qbman_version; + __le32 pad1; + /* cmd word 4 */ + __le32 clk; }; struct dpio_stashing_dest { diff --git a/drivers/soc/fsl/dpio/dpio-driver.c b/drivers/soc/fsl/dpio/dpio-driver.c index 7f397b4ad878..dd948889eeab 100644 --- a/drivers/soc/fsl/dpio/dpio-driver.c +++ b/drivers/soc/fsl/dpio/dpio-driver.c @@ -162,6 +162,7 @@ static int dpaa2_dpio_probe(struct fsl_mc_device *dpio_dev) goto err_get_attr; } desc.qman_version = dpio_attrs.qbman_version; + desc.qman_clk = dpio_attrs.clk; err = dpio_enable(dpio_dev->mc_io, 0, dpio_dev->mc_handle); if (err) { diff --git a/drivers/soc/fsl/dpio/dpio-service.c b/drivers/soc/fsl/dpio/dpio-service.c index 7351f3030550..2acbb96c5e45 100644 --- a/drivers/soc/fsl/dpio/dpio-service.c +++ b/drivers/soc/fsl/dpio/dpio-service.c @@ -127,6 +127,7 @@ struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc, obj->dpio_desc = *desc; obj->swp_desc.cena_bar = obj->dpio_desc.regs_cena; obj->swp_desc.cinh_bar = obj->dpio_desc.regs_cinh; + obj->swp_desc.qman_clk = obj->dpio_desc.qman_clk; obj->swp_desc.qman_version = obj->dpio_desc.qman_version; obj->swp = qbman_swp_init(&obj->swp_desc); diff --git a/drivers/soc/fsl/dpio/dpio.c b/drivers/soc/fsl/dpio/dpio.c index af74c597a675..8ed606ffaac5 100644 --- a/drivers/soc/fsl/dpio/dpio.c +++ b/drivers/soc/fsl/dpio/dpio.c @@ -162,6 +162,7 @@ int dpio_get_attributes(struct fsl_mc_io *mc_io, attr->qbman_portal_ci_offset = le64_to_cpu(dpio_rsp->qbman_portal_ci_addr); attr->qbman_version = le32_to_cpu(dpio_rsp->qbman_version); + attr->clk = le32_to_cpu(dpio_rsp->clk); return 0; } diff --git a/drivers/soc/fsl/dpio/dpio.h b/drivers/soc/fsl/dpio/dpio.h index da06f7258098..7fda44f0d7f4 100644 --- a/drivers/soc/fsl/dpio/dpio.h +++ b/drivers/soc/fsl/dpio/dpio.h @@ -59,6 +59,7 @@ int dpio_disable(struct fsl_mc_io *mc_io, * @num_priorities: Number of priorities for the notification channel (1-8); * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL' * @qbman_version: QBMAN version + * @clk: QBMAN clock frequency value in Hz */ struct dpio_attr { int id; @@ -68,6 +69,7 @@ struct dpio_attr { enum dpio_channel_mode channel_mode; u8 num_priorities; u32 qbman_version; + u32 clk; }; int dpio_get_attributes(struct fsl_mc_io *mc_io, diff --git a/drivers/soc/fsl/dpio/qbman-portal.h b/drivers/soc/fsl/dpio/qbman-portal.h index c7c2225b7d91..f058289416af 100644 --- a/drivers/soc/fsl/dpio/qbman-portal.h +++ b/drivers/soc/fsl/dpio/qbman-portal.h @@ -24,6 +24,7 @@ struct qbman_swp_desc { void *cena_bar; /* Cache-enabled portal base address */ void __iomem *cinh_bar; /* Cache-inhibited portal base address */ u32 qman_version; + u32 qman_clk; }; #define QBMAN_SWP_INTERRUPT_EQRI 0x01 diff --git a/include/soc/fsl/dpaa2-io.h b/include/soc/fsl/dpaa2-io.h index c9d849924f89..041ebf7d804c 100644 --- a/include/soc/fsl/dpaa2-io.h +++ b/include/soc/fsl/dpaa2-io.h @@ -44,6 +44,7 @@ struct device; * @regs_cinh: The cache inhibited regs * @dpio_id: The dpio index * @qman_version: The qman version + * @qman_clk: The qman clock frequency in Hz * * Describes the attributes and features of the DPIO object. */ @@ -55,6 +56,7 @@ struct dpaa2_io_desc { void __iomem *regs_cinh; int dpio_id; u32 qman_version; + u32 qman_clk; }; struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc, From patchwork Fri Oct 15 09:01:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ioana Ciornei X-Patchwork-Id: 12560803 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F1BAC433EF for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fY0cjno2H/rF3GqewDXIeAbl2pQ91IPblExG0r27iD29OL5Td5te2+LmD+R0uEXYGQNiP626uMqNHmyBo08W5qWQQANSZHGcOXkggHVdbHHR7yZlEuC4N9sbq+uHjv7iE/mhR32rvG5HOucICgUEncPUF3CKRsADqfGF28wlucX9KLuyueFpKJ5cKy8xp7rsJS/rFly+upr8Px20DnQgT5K0BeJZgGMNBw51XM66BLisAsieweyBIn4JPRVk8LD7GEfC3hrvQWZXp5PKgIeL6cuFZE4z/9WYo31J/uM07EJ3jzekTTWu4MDPq++C235KzkkxBCTfAXrxDZt22ClEZkaqo1XqHMnnVt2QkeuQ0dDTTFAryGKKp4QQoUuyooTaEwFaB4hNDh0KX2IkQA1awEi4lPUr8aDBLnP7xrnKCVDjJKbCdEZZGVJ1CEPssLmhUNFDAEG/SJIdXPbAdX2ROFjIHX3cRhiwYsNYyrBYV4AAXSUsDxHwVIBBRrRV8MpSNCNZHlJaKa23Cxf7S5LxEZEAkvKAQszX5g5xOF8fokwZFaOwKlKI3TAFWJqlJj0NzgBglw1Jh0Xga/MGI6ZNU+VGIB1++vKAM0qc27cT25e8CsXQXyR/9MrFlMHquoM5xHXdi4eH9seKXZKfd45u3qoh2NOdE90KDtvC1o8Dl1grjnOGLxTfkQ5wrEimM2tcmnxaR+873mDSUfzCa+VFZwz6BHxBJK8g3KwE0z38+jukET+g7778UEuMnaVkIUUNn6nsBDknQhhYe3ivsDcZ9vIXsNvfJ+IBdQTRFZIn2R7nDdPqon4C12Fr/9hzIXDNXUwPQl7NlHod8BIg5Xa5pwwefoiXXuf+DzcZYEAEuZ81Crxmr8GPPQdBEhkqJw0QC+SoUsHVkAhyxJcy3AGPDAgk1ERqU3EUxIcfkcFBPebnoZ2iWZxRTRH8jnkcXLOwqL7krpmUE39dg9QCz4V4Q867uMkXwRMS5zW1loOb1IHKrwenB+OnBcnODjr/CVjbsCyILf0NeqEgoY150OuHfNdurrIyI5vRspg5ot+j6TDaSi3oQprqmKgYZO+zq58xtjcBVjN8+V1ud95pLdrQqq9zYeX9Fq7PUL0CgQf0oqoomty9OYiIB1J+g/+QHJhRFHeaS8AJdCgmXrsc9t8XpFuibto8HEth26UsIJ4yD3tarx8breYK+DlS3VQ78oKgxtudEyEbR0SiGrHXxef43gH3rFzBzTmJ4VxHlHIK8JH5rSti9UF7B2yBd8TzjFNAXUT/gZQTCdDt0JyJbzggZm005I5SJXmo4MD2V/pK4u6LWfOw6uViYeofuinmBcSk X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c4af7c91-56ab-4a0e-d842-08d98fba6b47 X-MS-Exchange-CrossTenant-AuthSource: AM4PR0401MB2308.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2021 09:01:47.7844 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: zheNbAVc3jT74TzTZx5HLnNNyMrQA3WPwMtJZyjeR3DF3ebiEI2oms5kQmowlNbLjfpdy7UFIwGSdkHmiH6Q5g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB5988 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org In DPAA2 based SoCs, the IRQ coalesing support per software portal has 2 configurable parameters: - the IRQ timeout period (QBMAN_CINH_SWP_ITPR): how many 256 QBMAN cycles need to pass until a dequeue interrupt is asserted. - the IRQ threshold (QBMAN_CINH_SWP_DQRR_ITR): how many dequeue responses in the DQRR ring would generate an IRQ. Add support for setting up and querying these IRQ coalescing related parameters. Signed-off-by: Ioana Ciornei --- Changes in v2: - none drivers/soc/fsl/dpio/dpio-service.c | 37 ++++++++++++++++++ drivers/soc/fsl/dpio/qbman-portal.c | 59 +++++++++++++++++++++++++++++ drivers/soc/fsl/dpio/qbman-portal.h | 11 ++++++ include/soc/fsl/dpaa2-io.h | 4 ++ 4 files changed, 111 insertions(+) diff --git a/drivers/soc/fsl/dpio/dpio-service.c b/drivers/soc/fsl/dpio/dpio-service.c index 2acbb96c5e45..44fafed045ca 100644 --- a/drivers/soc/fsl/dpio/dpio-service.c +++ b/drivers/soc/fsl/dpio/dpio-service.c @@ -114,6 +114,7 @@ struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc, struct device *dev) { struct dpaa2_io *obj = kmalloc(sizeof(*obj), GFP_KERNEL); + u32 qman_256_cycles_per_ns; if (!obj) return NULL; @@ -129,6 +130,13 @@ struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc, obj->swp_desc.cinh_bar = obj->dpio_desc.regs_cinh; obj->swp_desc.qman_clk = obj->dpio_desc.qman_clk; obj->swp_desc.qman_version = obj->dpio_desc.qman_version; + + /* Compute how many 256 QBMAN cycles fit into one ns. This is because + * the interrupt timeout period register needs to be specified in QBMAN + * clock cycles in increments of 256. + */ + qman_256_cycles_per_ns = 256000 / (obj->swp_desc.qman_clk / 1000000); + obj->swp_desc.qman_256_cycles_per_ns = qman_256_cycles_per_ns; obj->swp = qbman_swp_init(&obj->swp_desc); if (!obj->swp) { @@ -780,3 +788,32 @@ int dpaa2_io_query_bp_count(struct dpaa2_io *d, u16 bpid, u32 *num) return 0; } EXPORT_SYMBOL_GPL(dpaa2_io_query_bp_count); + +/** + * dpaa2_io_set_irq_coalescing() - Set new IRQ coalescing values + * @d: the given DPIO object + * @irq_holdoff: interrupt holdoff (timeout) period in us + * + * Return 0 for success, or negative error code on error. + */ +int dpaa2_io_set_irq_coalescing(struct dpaa2_io *d, u32 irq_holdoff) +{ + struct qbman_swp *swp = d->swp; + + return qbman_swp_set_irq_coalescing(swp, swp->dqrr.dqrr_size - 1, + irq_holdoff); +} +EXPORT_SYMBOL(dpaa2_io_set_irq_coalescing); + +/** + * dpaa2_io_get_irq_coalescing() - Get the current IRQ coalescing parameters + * @d: the given DPIO object + * @irq_holdoff: interrupt holdoff (timeout) period in us + */ +void dpaa2_io_get_irq_coalescing(struct dpaa2_io *d, u32 *irq_holdoff) +{ + struct qbman_swp *swp = d->swp; + + qbman_swp_get_irq_coalescing(swp, NULL, irq_holdoff); +} +EXPORT_SYMBOL(dpaa2_io_get_irq_coalescing); diff --git a/drivers/soc/fsl/dpio/qbman-portal.c b/drivers/soc/fsl/dpio/qbman-portal.c index f13da4d7d1c5..d3c58df6240d 100644 --- a/drivers/soc/fsl/dpio/qbman-portal.c +++ b/drivers/soc/fsl/dpio/qbman-portal.c @@ -29,6 +29,7 @@ #define QBMAN_CINH_SWP_EQCR_AM_RT 0x980 #define QBMAN_CINH_SWP_RCR_AM_RT 0x9c0 #define QBMAN_CINH_SWP_DQPI 0xa00 +#define QBMAN_CINH_SWP_DQRR_ITR 0xa80 #define QBMAN_CINH_SWP_DCAP 0xac0 #define QBMAN_CINH_SWP_SDQCR 0xb00 #define QBMAN_CINH_SWP_EQCR_AM_RT2 0xb40 @@ -38,6 +39,7 @@ #define QBMAN_CINH_SWP_IER 0xe40 #define QBMAN_CINH_SWP_ISDR 0xe80 #define QBMAN_CINH_SWP_IIR 0xec0 +#define QBMAN_CINH_SWP_ITPR 0xf40 /* CENA register offsets */ #define QBMAN_CENA_SWP_EQCR(n) (0x000 + ((u32)(n) << 6)) @@ -355,6 +357,9 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d) & p->eqcr.pi_ci_mask; p->eqcr.available = p->eqcr.pi_ring_size; + /* Initialize the software portal with a irq timeout period of 0us */ + qbman_swp_set_irq_coalescing(p, p->dqrr.dqrr_size - 1, 0); + return p; } @@ -1796,3 +1801,57 @@ u32 qbman_bp_info_num_free_bufs(struct qbman_bp_query_rslt *a) { return le32_to_cpu(a->fill); } + +/** + * qbman_swp_set_irq_coalescing() - Set new IRQ coalescing values + * @p: the software portal object + * @irq_threshold: interrupt threshold + * @irq_holdoff: interrupt holdoff (timeout) period in us + * + * Return 0 for success, or negative error code on error. + */ +int qbman_swp_set_irq_coalescing(struct qbman_swp *p, u32 irq_threshold, + u32 irq_holdoff) +{ + u32 itp, max_holdoff; + + /* Convert irq_holdoff value from usecs to 256 QBMAN clock cycles + * increments. This depends to the QBMAN internal frequency. + */ + itp = (irq_holdoff * 1000) / p->desc->qman_256_cycles_per_ns; + if (itp < 0 || itp > 4096) { + max_holdoff = (p->desc->qman_256_cycles_per_ns * 4096) / 1000; + pr_err("irq_holdoff must be between 0..%dus\n", max_holdoff); + return -EINVAL; + } + + if (irq_threshold >= p->dqrr.dqrr_size || irq_threshold < 0) { + pr_err("irq_threshold must be between 0..%d\n", + p->dqrr.dqrr_size - 1); + return -EINVAL; + } + + p->irq_threshold = irq_threshold; + p->irq_holdoff = irq_holdoff; + + qbman_write_register(p, QBMAN_CINH_SWP_DQRR_ITR, irq_threshold); + qbman_write_register(p, QBMAN_CINH_SWP_ITPR, itp); + + return 0; +} + +/** + * qbman_swp_get_irq_coalescing() - Get the current IRQ coalescing parameters + * @p: the software portal object + * @irq_threshold: interrupt threshold (an IRQ is generated when there are more + * DQRR entries in the portal than the threshold) + * @irq_holdoff: interrupt holdoff (timeout) period in us + */ +void qbman_swp_get_irq_coalescing(struct qbman_swp *p, u32 *irq_threshold, + u32 *irq_holdoff) +{ + if (irq_threshold) + *irq_threshold = p->irq_threshold; + if (irq_holdoff) + *irq_holdoff = p->irq_holdoff; +} diff --git a/drivers/soc/fsl/dpio/qbman-portal.h b/drivers/soc/fsl/dpio/qbman-portal.h index f058289416af..4ea2dd950a2a 100644 --- a/drivers/soc/fsl/dpio/qbman-portal.h +++ b/drivers/soc/fsl/dpio/qbman-portal.h @@ -25,6 +25,7 @@ struct qbman_swp_desc { void __iomem *cinh_bar; /* Cache-inhibited portal base address */ u32 qman_version; u32 qman_clk; + u32 qman_256_cycles_per_ns; }; #define QBMAN_SWP_INTERRUPT_EQRI 0x01 @@ -157,6 +158,10 @@ struct qbman_swp { } eqcr; spinlock_t access_spinlock; + + /* Interrupt coalescing */ + u32 irq_threshold; + u32 irq_holdoff; }; /* Function pointers */ @@ -649,4 +654,10 @@ static inline const struct dpaa2_dq *qbman_swp_dqrr_next(struct qbman_swp *s) return qbman_swp_dqrr_next_ptr(s); } +int qbman_swp_set_irq_coalescing(struct qbman_swp *p, u32 irq_threshold, + u32 irq_holdoff); + +void qbman_swp_get_irq_coalescing(struct qbman_swp *p, u32 *irq_threshold, + u32 *irq_holdoff); + #endif /* __FSL_QBMAN_PORTAL_H */ diff --git a/include/soc/fsl/dpaa2-io.h b/include/soc/fsl/dpaa2-io.h index 041ebf7d804c..9bff280fe8f4 100644 --- a/include/soc/fsl/dpaa2-io.h +++ b/include/soc/fsl/dpaa2-io.h @@ -131,4 +131,8 @@ int dpaa2_io_query_fq_count(struct dpaa2_io *d, u32 fqid, u32 *fcnt, u32 *bcnt); int dpaa2_io_query_bp_count(struct dpaa2_io *d, u16 bpid, u32 *num); + +int dpaa2_io_set_irq_coalescing(struct dpaa2_io *d, u32 irq_holdoff); +void dpaa2_io_get_irq_coalescing(struct dpaa2_io *d, u32 *irq_holdoff); + #endif /* __FSL_DPAA2_IO_H */ From patchwork Fri Oct 15 09:01:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ioana Ciornei X-Patchwork-Id: 12560805 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E408CC433EF for ; Fri, 15 Oct 2021 09:01:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C67F861184 for ; Fri, 15 Oct 2021 09:01:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236314AbhJOJD5 (ORCPT ); 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ccLHE4ON1JSlaWY/L+bAWL7JUcL9xKXc5SPCgLEK67TH8ty/8iBP8kzv/O9qe9GSYtG6L+X2HDk8F/lO0XPhrUMROHUti6UGjXsZtY94II1RIa7XGrXwU81IgLElBf9CkS8XyYp7t0L3fk9aLNDCWoDVFIRe0Hf8FhJUqjqdXjCoWjDPHIz7H9F4HiRxmI0Srs+bbwxWayXVp96vOrgQ9lfqrlc7jPcC3BzETgYaGRSG7rSLgt3yFyex13yzntdu3tYmyzc9d32zzi6d3/jPIBTxO+JDCAzTT+GUmcEGdqeStQqVxu3rtj1aaZL6mPF8SrQRbOn1J576BFF/iqkYZjEGXgcWfrFQoTU/dehbnHX2blheUcP2alvPTcCJsz5BLk6kWmkCanqW4YJz0xwMNqVXDdACry8ZuCNMHUbZXGsy0pE0wV8fh1/qlh+nVGk37noogvMkrxZuQ3j9tRTp7Ohb6z/UMphk+lSK7SHUKHctprPxW1Ie8qiD62tVaXNdwvvcs3gTJISu8K3gUPGdnpfmSApL0GbPWT/eL89gVJsRa93b3SXB0NVo0kvKFiKUPQkHCBHlKpFN6ZQeNr+rELpkF2aPvxPDFNIxlGmQ0AiNNVhjLSlvAvVmNa81OXspwfBu9YaKsuLintRCuDcbIRiEEDgaccYBhWznTeCnAJ6QgxcNYLLs3inYlSxi0SmXunzQxM3wA1mDPITX3A1A1m3uYinH0M9WykjNmLmVL2YNWaI02vawRB2LhOE3Gq8rW/S0uozDp8eLwoTnbnrH6heXQHa6bNrW84J1bbv5A9P5B7CNMR8EGnZgUqS6lC8I9JaXsNzdZizitGSumNBA/U5ohxSF36qwRPjDRrZGL+u61+XwvzIeysczy3sf5yI+d5lZVcIb6nz8scu/oKLU9x1NVQvD+wE/6oPyruydDxWPDnj/xCUfdrcQ6iDKdLScWHvkv+23bh1+TDNArd3lCurZQ79hZ2vIvg3CY2CdYYGYb273Qmyp/mQo3WtbsEuB9nsfByiZiNNZc91MSS/SIjakMtkReQfLAqfDokSObWR+cSmPKJA6+x+a7A0iIlXM38QpwOoBw7wuYVZ05AcQ74dFP6N7OzbovSSI47V1ofsQQFBV91Pl9zgnunkFwRWLH9GzA8nA8VtMSjunnuCj1bxVaS6YBoQjyKWCkbf0pb9rImyoH90B9w6LH7S9LpfJqE9iBrlVf8qJS0/LZ1+77tO4zhJL34G1cpjmmOXp0TfnXYGqHc+o95W1TrCZm5BsrUAcLJw/GfElZT6AMEIcK5E/0tsA3tUz22nzMV/rdT8h0sy124m90rxOTmJ4BBMU X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 23e57a5a-6957-43ed-5604-08d98fba6bdb X-MS-Exchange-CrossTenant-AuthSource: AM4PR0401MB2308.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2021 09:01:48.7740 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NbOL9MmX2hkurE6H6aOOHx+Udcoc984zmCQaez4R+dmRDNUCmPAe2hHfENq9Mrwk5QvSodbLY6SKqgwRu4YLzQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB5988 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Use the newly exported dpio driver API to manually configure the IRQ coalescing parameters requested by the user. The .get_coalesce() and .set_coalesce() net_device callbacks are implemented and directly export or setup the rx-usecs on all the channels configured. Signed-off-by: Ioana Ciornei --- Changes in v2: - none .../ethernet/freescale/dpaa2/dpaa2-ethtool.c | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c index 2da5f881f630..69a6860e11fa 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c @@ -820,7 +820,56 @@ static int dpaa2_eth_set_tunable(struct net_device *net_dev, return err; } +static int dpaa2_eth_get_coalesce(struct net_device *dev, + struct ethtool_coalesce *ic, + struct kernel_ethtool_coalesce *kernel_coal, + struct netlink_ext_ack *extack) +{ + struct dpaa2_eth_priv *priv = netdev_priv(dev); + struct dpaa2_io *dpio = priv->channel[0]->dpio; + + dpaa2_io_get_irq_coalescing(dpio, &ic->rx_coalesce_usecs); + + return 0; +} + +static int dpaa2_eth_set_coalesce(struct net_device *dev, + struct ethtool_coalesce *ic, + struct kernel_ethtool_coalesce *kernel_coal, + struct netlink_ext_ack *extack) +{ + struct dpaa2_eth_priv *priv = netdev_priv(dev); + struct dpaa2_io *dpio; + u32 prev_rx_usecs; + int i, j, err; + + /* Keep track of the previous value, just in case we fail */ + dpio = priv->channel[0]->dpio; + dpaa2_io_get_irq_coalescing(dpio, &prev_rx_usecs); + + /* Setup new value for rx coalescing */ + for (i = 0; i < priv->num_channels; i++) { + dpio = priv->channel[i]->dpio; + + err = dpaa2_io_set_irq_coalescing(dpio, ic->rx_coalesce_usecs); + if (err) + goto restore_rx_usecs; + } + + return 0; + +restore_rx_usecs: + for (j = 0; j < i; j++) { + dpio = priv->channel[j]->dpio; + + dpaa2_io_set_irq_coalescing(dpio, prev_rx_usecs); + } + + return err; +} + const struct ethtool_ops dpaa2_ethtool_ops = { + .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS, .get_drvinfo = dpaa2_eth_get_drvinfo, .nway_reset = dpaa2_eth_nway_reset, .get_link = ethtool_op_get_link, @@ -836,4 +885,6 @@ const struct ethtool_ops dpaa2_ethtool_ops = { .get_ts_info = dpaa2_eth_get_ts_info, .get_tunable = dpaa2_eth_get_tunable, .set_tunable = dpaa2_eth_set_tunable, + .get_coalesce = dpaa2_eth_get_coalesce, + .set_coalesce = dpaa2_eth_set_coalesce, }; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Ss28xkmS1pwinYEXIiQNDNPLLdZcB9X53qiA2Z3oMD8uoOem5WU2ONAp4FIat9B/kIvwAtDdfLMvSyHlIhpKdSOEp7Tfh1Q5JR75uwfYyWX9lpO9Js8KLlr77kRxgjIqe1jGJaJ4AutqItBpufe26FDM9kikc8ifxkHSEcbdVcpg9SEXG8xix6fSFXzEqpO/oqvQTpmN+08vb9TFA2+K4PmO6jKkhNSzStAGuTQ9OnOvgK6ZInANC5CgVg2Rnlyw/r6kWphTP3dlvPYkpyfN1wwrd9+QjgFenQrvRFhw4aVPjJ2zLn0v5oq8aHg+ha2Z9pYBNyqdKWjfn6ouDBTCZXZfJd8m3Q84Jyf71r4I1bQ30CJJH3ynMG3kxmoJvWjrfApp7GIzpo0VY17xlpQgZLbkY9lHeLj+EmQrt5A0PmOhsafdF9BI/Lcr6cp9A4LhhKeYn5DU3/ABE7jHV0dEMWwscn48ofq9BBAZSgl81YSZumgj/QQaCaWDDDpaio8G58KHbpuqmefU75Qw8JdCxFgM2U+JEXVqqrbq0XNa+aU/SKBRJ/rfMkMAF6DVuhHeJLRAHHGIFn3pGB2yF7M/MCbZ1TAiLquXmyuO303GkzTy2O1Aa14YltPT2LiNvPpODYz4FxXCRMR/0WH0Q8T+dHrC8PpcXk73AVlL/fWXRbAIQI2Rr1AP+CIp8BLid3Leow/8Yy9vY/Nwfrp6RvrUxmqjOSd9Pu5StOpVrspk5+w80ZWmuKFXx4UPDyZVu/0Z0slFofGRI3qdh2LfwWcOveaJAp9b4Ruyg6KdYx3NZEt3wWRelgAZM5Kpapt9jMWJpit7UiFEqc13NdC3PGi5CEhnRLg7W27qUK/E5EIo81U6p8HSl430eJnUGlvAdDMaIuRJGfQuZd37G7k/XHyBye/uz8Zlk45LCKZO4YJVHwv3qHotaqlpX8vxTsX/lmZ5eEZ1Ck7PTh9dR6c2DFnHnh37sEa9W5ViCr5Q3VepbZGNb+CKA12h0bxkvJfTXvwW2+gV4WD2nV94vQ2TMKx4HCy+xstMjAH0Qoks/NorNEVaOWNODINiPzhzXqZlJ9GBpTDcnfjL9v6WvfrirxmFKr2NDKBHyuu1nnEDB7K8b8usHAOu3RGKWWJWFR/TmlPpych/1pzqU7dpCD+Y199zknC8ImaD1TFj1DqBvHn8B9noyEIVdRVbheUTnMeBu6SkpCugn4XbxXj7ygzaomROoylr09o04ZhRjaiC6s8kN1aUsQ3kUb4LH/05TMITj2JvpBbfKSZorWnHv0MDoRMq97j4/qKiPS7rpO6cq32FLbxcHusLSRdc4acqzDMCsXII X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3ac2aadc-01fd-471f-3382-08d98fba6c67 X-MS-Exchange-CrossTenant-AuthSource: AM4PR0401MB2308.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2021 09:01:49.7696 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: EN3snhpftYKQo7clyOMNmdnnzJv+ICWZMi9B2i/aO1+HXFsHpBYe8A717ZgWCXKKMUDUZ3OqTuHT5CX+nY/GXQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB5988 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Use the generic dynamic interrupt moderation (dim) framework to implement adaptive interrupt coalescing on Rx. With the per-packet interrupt scheme, a high interrupt rate has been noted for moderate traffic flows leading to high CPU utilization. The dpio driver exports new functions to enable/disable adaptive IRQ coalescing on a DPIO object, to query the state or to update Net DIM with a new set of bytes and frames dequeued. Signed-off-by: Ioana Ciornei --- Changes in v2: - none drivers/soc/fsl/Kconfig | 1 + drivers/soc/fsl/dpio/dpio-service.c | 79 +++++++++++++++++++++++++++++ drivers/soc/fsl/dpio/qbman-portal.h | 1 + include/soc/fsl/dpaa2-io.h | 5 +- 4 files changed, 85 insertions(+), 1 deletion(-) diff --git a/drivers/soc/fsl/Kconfig b/drivers/soc/fsl/Kconfig index 4df32bc4c7a6..07d52cafbb31 100644 --- a/drivers/soc/fsl/Kconfig +++ b/drivers/soc/fsl/Kconfig @@ -24,6 +24,7 @@ config FSL_MC_DPIO tristate "QorIQ DPAA2 DPIO driver" depends on FSL_MC_BUS select SOC_BUS + select DIMLIB help Driver for the DPAA2 DPIO object. A DPIO provides queue and buffer management facilities for software to interact with diff --git a/drivers/soc/fsl/dpio/dpio-service.c b/drivers/soc/fsl/dpio/dpio-service.c index 44fafed045ca..3fd0d0840287 100644 --- a/drivers/soc/fsl/dpio/dpio-service.c +++ b/drivers/soc/fsl/dpio/dpio-service.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include "dpio.h" @@ -28,6 +29,14 @@ struct dpaa2_io { spinlock_t lock_notifications; struct list_head notifications; struct device *dev; + + /* Net DIM */ + struct dim rx_dim; + /* protect against concurrent Net DIM updates */ + spinlock_t dim_lock; + u16 event_ctr; + u64 bytes; + u64 frames; }; struct dpaa2_io_store { @@ -100,6 +109,17 @@ struct dpaa2_io *dpaa2_io_service_select(int cpu) } EXPORT_SYMBOL_GPL(dpaa2_io_service_select); +static void dpaa2_io_dim_work(struct work_struct *w) +{ + struct dim *dim = container_of(w, struct dim, work); + struct dim_cq_moder moder = + net_dim_get_rx_moderation(dim->mode, dim->profile_ix); + struct dpaa2_io *d = container_of(dim, struct dpaa2_io, rx_dim); + + dpaa2_io_set_irq_coalescing(d, moder.usec); + dim->state = DIM_START_MEASURE; +} + /** * dpaa2_io_create() - create a dpaa2_io object. * @desc: the dpaa2_io descriptor @@ -147,6 +167,7 @@ struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc, INIT_LIST_HEAD(&obj->node); spin_lock_init(&obj->lock_mgmt_cmd); spin_lock_init(&obj->lock_notifications); + spin_lock_init(&obj->dim_lock); INIT_LIST_HEAD(&obj->notifications); /* For now only enable DQRR interrupts */ @@ -164,6 +185,12 @@ struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc, obj->dev = dev; + memset(&obj->rx_dim, 0, sizeof(obj->rx_dim)); + INIT_WORK(&obj->rx_dim.work, dpaa2_io_dim_work); + obj->event_ctr = 0; + obj->bytes = 0; + obj->frames = 0; + return obj; } @@ -203,6 +230,8 @@ irqreturn_t dpaa2_io_irq(struct dpaa2_io *obj) struct qbman_swp *swp; u32 status; + obj->event_ctr++; + swp = obj->swp; status = qbman_swp_interrupt_read_status(swp); if (!status) @@ -817,3 +846,53 @@ void dpaa2_io_get_irq_coalescing(struct dpaa2_io *d, u32 *irq_holdoff) qbman_swp_get_irq_coalescing(swp, NULL, irq_holdoff); } EXPORT_SYMBOL(dpaa2_io_get_irq_coalescing); + +/** + * dpaa2_io_set_adaptive_coalescing() - Enable/disable adaptive coalescing + * @d: the given DPIO object + * @use_adaptive_rx_coalesce: adaptive coalescing state + */ +void dpaa2_io_set_adaptive_coalescing(struct dpaa2_io *d, + int use_adaptive_rx_coalesce) +{ + d->swp->use_adaptive_rx_coalesce = use_adaptive_rx_coalesce; +} +EXPORT_SYMBOL(dpaa2_io_set_adaptive_coalescing); + +/** + * dpaa2_io_get_adaptive_coalescing() - Query adaptive coalescing state + * @d: the given DPIO object + * + * Return 1 when adaptive coalescing is enabled on the DPIO object and 0 + * otherwise. + */ +int dpaa2_io_get_adaptive_coalescing(struct dpaa2_io *d) +{ + return d->swp->use_adaptive_rx_coalesce; +} +EXPORT_SYMBOL(dpaa2_io_get_adaptive_coalescing); + +/** + * dpaa2_io_update_net_dim() - Update Net DIM + * @d: the given DPIO object + * @frames: how many frames have been dequeued by the user since the last call + * @bytes: how many bytes have been dequeued by the user since the last call + */ +void dpaa2_io_update_net_dim(struct dpaa2_io *d, __u64 frames, __u64 bytes) +{ + struct dim_sample dim_sample = {}; + + if (!d->swp->use_adaptive_rx_coalesce) + return; + + spin_lock(&d->dim_lock); + + d->bytes += bytes; + d->frames += frames; + + dim_update_sample(d->event_ctr, d->frames, d->bytes, &dim_sample); + net_dim(&d->rx_dim, dim_sample); + + spin_unlock(&d->dim_lock); +} +EXPORT_SYMBOL(dpaa2_io_update_net_dim); diff --git a/drivers/soc/fsl/dpio/qbman-portal.h b/drivers/soc/fsl/dpio/qbman-portal.h index 4ea2dd950a2a..b23883dd2725 100644 --- a/drivers/soc/fsl/dpio/qbman-portal.h +++ b/drivers/soc/fsl/dpio/qbman-portal.h @@ -162,6 +162,7 @@ struct qbman_swp { /* Interrupt coalescing */ u32 irq_threshold; u32 irq_holdoff; + int use_adaptive_rx_coalesce; }; /* Function pointers */ diff --git a/include/soc/fsl/dpaa2-io.h b/include/soc/fsl/dpaa2-io.h index 9bff280fe8f4..4bf62de2e00e 100644 --- a/include/soc/fsl/dpaa2-io.h +++ b/include/soc/fsl/dpaa2-io.h @@ -134,5 +134,8 @@ int dpaa2_io_query_bp_count(struct dpaa2_io *d, u16 bpid, int dpaa2_io_set_irq_coalescing(struct dpaa2_io *d, u32 irq_holdoff); void dpaa2_io_get_irq_coalescing(struct dpaa2_io *d, u32 *irq_holdoff); - +void dpaa2_io_set_adaptive_coalescing(struct dpaa2_io *d, + int use_adaptive_rx_coalesce); +int dpaa2_io_get_adaptive_coalescing(struct dpaa2_io *d); +void dpaa2_io_update_net_dim(struct dpaa2_io *d, __u64 frames, __u64 bytes); #endif /* __FSL_DPAA2_IO_H */ From patchwork Fri Oct 15 09:01:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ioana Ciornei X-Patchwork-Id: 12560809 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85A25C433EF for ; Fri, 15 Oct 2021 09:02:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6C56C61184 for ; Fri, 15 Oct 2021 09:02:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236340AbhJOJEE (ORCPT ); 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: evDIlcQcQoj6sY5SRpjTXlAXPR5uu9e1AHkdqwny7Sp+oeV4HAXFaWQ8kzOVO9EABxFbXB5xAqszBNKjKoSk6+AwSkGAi3PgEHpPp9CG7iNtrPTRGiEcQMlE0vHTJci9/H5JkDTB/0cIOCsGldKLLEqJ1ErCp0vvPpRi0q9EIBGJk+S9hUs32JDkgpV94UMlkylSe+DMYSJAk0rBcH0XiF03Yit5hKmRAQEf/lt5NH4uQqEF6CaVTw9uV/IhLARFozOQfAm1eaYnh5Qhws4p28Sh6PZ1h66q8Ax2RSd5YYCKrczwdvpzW0adlZQkfa87vm7SSHovtors/A/boVPSZBkTs4mKiqWtlQOMKP9hFYb9wQ6dmUEnRnuK9j34qdXrUxwqERmiWBXXYroMFd2QSiGM9lpqB2fVRT+JRCmqUwXAdi284sABF0HIYcBmCOgkx774RbqWoiekrQCPzb8HQ2qiETnxtev1DD9pp6mK9lLla3mOFOeqECB+eox3om/n1Od9HHSLPtnXntWdY/KkOB9Bea5zivuJwisTITlPjXcwNslWxxuhm3cXfk7t2qXXHQ8A8IjGPVV9LARuTLLit1esK9XcPbHRDqKzgS25PHC2NdlVH2OkCcrl3224PwfRkHOlgN1h55A1SJbNUezdQ6equLYTMIeVN/89pBdjXar8iWnYL1IhfdpCrliTd9m253gnGrj0zWAWyPJbxFUqNPd//KigjbheyffULU8tuEGnaVJBmoE9XqsPEqpxvJPYI8wCbzjDNZofCe6wGeSeBS/R6n/DeylzeiiGAogkGSg/jGX6qgWqBWdwvARv0nVstHEMxzsTJwg46ehBk21qc4KRldgxxf8KlZ7FOfrvON9pvIHnqiKc0fDoDq416Cl+W5q24kAyPllHR7JUdcLBcnQjqOxcuT82jJOx4tME9EnqugkenTV2YNyhJf0F7hCduUzebFFn3vKqSgpwBQzd+ttAoU6KpSNlIm26E8WTM6BSTDAsLiDJSvGTzppexgjYJSHjFX9RlVmp3Z/36K5xuT/OL8/Mm5/+Ch4w0vrXf+141tNXjLUUQds17dvRYXg6xNum/MSsfwI/r6NK91BJvvPW5E5a8htK8lOCI42MXFutrXpoq1uLQMKO63MGJ0/CMoOje84iwGUAIZwq0Mg5cU1fRiSh9fh5/g3WW2fV/MZsDIMDJUR4JyCk+dzXsLJtDpWTAwQOATaM7hnKbL9Y2KRkBM7OZrLlQHaUSB+Xjx74T6J3ORXEqH1MI3Jjfi/7gj1wTSEeGgTgd5fyuTv2FMvQ1o4z1kUBqYTu9zC3iyGS920eAAXrlxhNZ3qEEToy X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: cf885cbf-5a05-415f-3b0d-08d98fba6d1e X-MS-Exchange-CrossTenant-AuthSource: AM4PR0401MB2308.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2021 09:01:50.9251 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: KtfEQm8sk5TB4gZT5KikJGXPuFtrmEreyNcbW22vfSl5voGYZZh03BJ0hvuvETXbx+rg+fpXQfu/3Dd5g8daqA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB5988 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add support for adaptive interrupt coalescing to the dpaa2-eth driver. First of all, ETHTOOL_COALESCE_USE_ADAPTIVE_RX is defined as a supported coalesce parameter and the requested state is configured through the dpio APIs added in the previous patch. Besides the ethtool API interaction, we keep track of how many bytes and frames are dequeued per CDAN (Channel Data Availability Notification) and update the Net DIM instance through the dpaa2_io_update_net_dim() API. Signed-off-by: Ioana Ciornei --- Changes in v2: - none drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c | 11 ++++++++++- drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h | 2 ++ drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c | 9 ++++++++- 3 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c index 34f189271ef2..714e961e7a77 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c @@ -533,6 +533,7 @@ static void dpaa2_eth_rx(struct dpaa2_eth_priv *priv, percpu_stats->rx_packets++; percpu_stats->rx_bytes += dpaa2_fd_get_len(fd); + ch->stats.bytes_per_cdan += dpaa2_fd_get_len(fd); list_add_tail(&skb->list, ch->rx_list); @@ -641,6 +642,7 @@ static int dpaa2_eth_consume_frames(struct dpaa2_eth_channel *ch, fq->stats.frames += cleaned; ch->stats.frames += cleaned; + ch->stats.frames_per_cdan += cleaned; /* A dequeue operation only pulls frames from a single queue * into the store. Return the frame queue as an out param. @@ -1264,7 +1266,7 @@ static netdev_tx_t dpaa2_eth_tx(struct sk_buff *skb, struct net_device *net_dev) /* Tx confirmation frame processing routine */ static void dpaa2_eth_tx_conf(struct dpaa2_eth_priv *priv, - struct dpaa2_eth_channel *ch __always_unused, + struct dpaa2_eth_channel *ch, const struct dpaa2_fd *fd, struct dpaa2_eth_fq *fq) { @@ -1279,6 +1281,7 @@ static void dpaa2_eth_tx_conf(struct dpaa2_eth_priv *priv, percpu_extras = this_cpu_ptr(priv->percpu_extras); percpu_extras->tx_conf_frames++; percpu_extras->tx_conf_bytes += fd_len; + ch->stats.bytes_per_cdan += fd_len; /* Check frame errors in the FD field */ fd_errors = dpaa2_fd_get_ctrl(fd) & DPAA2_FD_TX_ERR_MASK; @@ -1601,6 +1604,12 @@ static int dpaa2_eth_poll(struct napi_struct *napi, int budget) } } while (store_cleaned); + /* Update NET DIM with the values for this CDAN */ + dpaa2_io_update_net_dim(ch->dpio, ch->stats.frames_per_cdan, + ch->stats.bytes_per_cdan); + ch->stats.frames_per_cdan = 0; + ch->stats.bytes_per_cdan = 0; + /* We didn't consume the entire budget, so finish napi and * re-enable data availability notifications */ diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h index 628d2d45f045..2085844227fe 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h @@ -384,6 +384,8 @@ struct dpaa2_eth_ch_stats { __u64 xdp_redirect; /* Must be last, does not show up in ethtool stats */ __u64 frames; + __u64 frames_per_cdan; + __u64 bytes_per_cdan; }; /* Maximum number of queues associated with a DPNI */ diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c index 69a6860e11fa..adb8ce5306ee 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c @@ -829,6 +829,7 @@ static int dpaa2_eth_get_coalesce(struct net_device *dev, struct dpaa2_io *dpio = priv->channel[0]->dpio; dpaa2_io_get_irq_coalescing(dpio, &ic->rx_coalesce_usecs); + ic->use_adaptive_rx_coalesce = dpaa2_io_get_adaptive_coalescing(dpio); return 0; } @@ -840,17 +841,21 @@ static int dpaa2_eth_set_coalesce(struct net_device *dev, { struct dpaa2_eth_priv *priv = netdev_priv(dev); struct dpaa2_io *dpio; + int prev_adaptive; u32 prev_rx_usecs; int i, j, err; /* Keep track of the previous value, just in case we fail */ dpio = priv->channel[0]->dpio; dpaa2_io_get_irq_coalescing(dpio, &prev_rx_usecs); + prev_adaptive = dpaa2_io_get_adaptive_coalescing(dpio); /* Setup new value for rx coalescing */ for (i = 0; i < priv->num_channels; i++) { dpio = priv->channel[i]->dpio; + dpaa2_io_set_adaptive_coalescing(dpio, + ic->use_adaptive_rx_coalesce); err = dpaa2_io_set_irq_coalescing(dpio, ic->rx_coalesce_usecs); if (err) goto restore_rx_usecs; @@ -863,13 +868,15 @@ static int dpaa2_eth_set_coalesce(struct net_device *dev, dpio = priv->channel[j]->dpio; dpaa2_io_set_irq_coalescing(dpio, prev_rx_usecs); + dpaa2_io_set_adaptive_coalescing(dpio, prev_adaptive); } return err; } const struct ethtool_ops dpaa2_ethtool_ops = { - .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS, + .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | + ETHTOOL_COALESCE_USE_ADAPTIVE_RX, .get_drvinfo = dpaa2_eth_get_drvinfo, .nway_reset = dpaa2_eth_nway_reset, .get_link = ethtool_op_get_link,