From patchwork Thu Dec 13 20:21:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10729799 X-Patchwork-Delegate: kieran@bingham.xyz Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 30D656C5 for ; Thu, 13 Dec 2018 20:22:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 23A512C9FD for ; Thu, 13 Dec 2018 20:22:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 17BD62CAD4; Thu, 13 Dec 2018 20:22:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B787B2C9FD for ; Thu, 13 Dec 2018 20:22:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726442AbeLMUWI (ORCPT ); Thu, 13 Dec 2018 15:22:08 -0500 Received: from relmlor2.renesas.com ([210.160.252.172]:23680 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726408AbeLMUWI (ORCPT ); Thu, 13 Dec 2018 15:22:08 -0500 X-IronPort-AV: E=Sophos;i="5.56,349,1539615600"; d="scan'208";a="2555724" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 Dec 2018 05:22:05 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.37.69]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id CC9B94072C54; Fri, 14 Dec 2018 05:22:02 +0900 (JST) From: Fabrizio Castro To: Mauro Carvalho Chehab , Rob Herring , Mark Rutland Cc: Fabrizio Castro , =?utf-8?q?Niklas_S?= =?utf-8?q?=C3=B6derlund?= , linux-media@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Simon Horman , Geert Uytterhoeven , Chris Paterson , Biju Das Subject: [PATCH] media: dt-bindings: rcar-vin: Add R8A774C0 support Date: Thu, 13 Dec 2018 20:21:59 +0000 Message-Id: <1544732519-6956-1-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the compatible string for RZ/G2E (a.k.a. R8A774C0) to the list of SoCs supported by rcar-vin driver. Signed-off-by: Fabrizio Castro Reviewed-by: Simon Horman Reviewed-by: Niklas Söderlund Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/media/rcar_vin.txt | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt index 7c878ca..34dcd28 100644 --- a/Documentation/devicetree/bindings/media/rcar_vin.txt +++ b/Documentation/devicetree/bindings/media/rcar_vin.txt @@ -7,12 +7,13 @@ family of devices. Each VIN instance has a single parallel input that supports RGB and YUV video, with both external synchronization and BT.656 synchronization for the latter. Depending on the instance the VIN input is connected to external SoC pins, or -on Gen3 platforms to a CSI-2 receiver. +on Gen3 and RZ/G2 platforms to a CSI-2 receiver. - compatible: Must be one or more of the following - "renesas,vin-r8a7743" for the R8A7743 device - "renesas,vin-r8a7744" for the R8A7744 device - "renesas,vin-r8a7745" for the R8A7745 device + - "renesas,vin-r8a774c0" for the R8A774C0 device - "renesas,vin-r8a7778" for the R8A7778 device - "renesas,vin-r8a7779" for the R8A7779 device - "renesas,vin-r8a7790" for the R8A7790 device @@ -60,10 +61,10 @@ The per-board settings Gen2 platforms: - data-enable-active: polarity of CLKENB signal, see [1] for description. Default is active high. -The per-board settings Gen3 platforms: +The per-board settings Gen3 and RZ/G2 platforms: -Gen3 platforms can support both a single connected parallel input source -from external SoC pins (port@0) and/or multiple parallel input sources +Gen3 and RZ/G2 platforms can support both a single connected parallel input +source from external SoC pins (port@0) and/or multiple parallel input sources from local SoC CSI-2 receivers (port@1) depending on SoC. - renesas,id - ID number of the VIN, VINx in the documentation.