From patchwork Tue Oct 19 09:34:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Schneider-Pargmann X-Patchwork-Id: 12569239 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D169C4332F for ; Tue, 19 Oct 2021 09:36:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 06ACE6137E for ; Tue, 19 Oct 2021 09:36:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235110AbhJSJin (ORCPT ); Tue, 19 Oct 2021 05:38:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235086AbhJSJil (ORCPT ); Tue, 19 Oct 2021 05:38:41 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00242C061749 for ; Tue, 19 Oct 2021 02:36:28 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id l38-20020a05600c1d2600b0030d80c3667aso2413335wms.5 for ; Tue, 19 Oct 2021 02:36:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CJsCWcU0YdDyrwMeRQ7adfzbBn9rJ1IRoawBpqp6LUY=; b=a4CDa4TY8RYsyf7Ov/rhPNU9JCjBEheWYFGjZ6M0fICmzqhK5+vkmDMKU/YI/iPSAe dhQdYbJ5sngCM+Yg0WcU+C1SnMh7BBiM7XI8Y4zFepF/ek5KXIV2uFha4YAd+n89I4fd hAkiABx3Q3nVhuCHGuvvTldrFhel/udGiW5h33GXk4Vh/NmEIOUMeZoSOcRPSnEzHhpr e9nRg3t/1KKxaflSVB4zdNl6a8RS7Tbp6DaHUriiI7T1AZQyW5+F/y4xjmzQzqE1yjxP 0zfmI8Wwr3FkiwXL37JohYx0k0eXxdkKvxEHEnvohFXM52RGPKtwcu5WjB0TK3fouwbs 5wUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CJsCWcU0YdDyrwMeRQ7adfzbBn9rJ1IRoawBpqp6LUY=; b=om61uTgWQKjIQ/a4C6azvIwj583CkoKKYmhWnNXSfaBYhtW1aWbgAnbwk+moT2nNsT WQ3Qe+vhcDQXFXh8ssPGk+PQ8YfURMKxQVbOFwBCcThd5MO1ZfcjKTe9poutI43GeN/y Pi8NplrDw75LDTfl8cC7YpU7dGZGgDWNQi1qi4EJSl2+USvLbizAlbbKZWeLSqKzf/w+ oIlwILzdbU32YRt94dwct8SgRvox51+dztiBFswQ8rq6649ZqB/txNxKT4LSeZV14nVZ 1v1gaDVbfKO5Ab6BsyLAc4d5BZs2nq/2ZTVrlqt4JLenxgU1labOC00XcHmf5BuI3BYu vPYQ== X-Gm-Message-State: AOAM532gOoZ8WN6ZnG0qGyAmvBEpDvOj+9S0f4CXXRfmW6VKRjlTHIOi dRtqCUqgsf06WWhekP+mLgTQyQ== X-Google-Smtp-Source: ABdhPJzhrEXmzMbsOs77lioFuMQGNrVk6F0Mecc/zs/NbpM2tEsMZAwoONXUBlPSFvrPfNoD8x+fiA== X-Received: by 2002:a1c:cc0f:: with SMTP id h15mr4821476wmb.37.1634636187595; Tue, 19 Oct 2021 02:36:27 -0700 (PDT) Received: from blmsp.lan ([2a02:2454:3e6:c900:5142:5fbb:5821:5dc3]) by smtp.gmail.com with ESMTPSA id o23sm1765765wms.18.2021.10.19.02.36.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 02:36:27 -0700 (PDT) From: Markus Schneider-Pargmann To: Zhang Rui , Daniel Lezcano , Matthias Brugger , Rob Herring Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, fparent@baylibre.com, khilman@baylibre.com, Markus Schneider-Pargmann Subject: [PATCH v2 1/4] dt-bindings: thermal: mediatek: Add mt8365 Date: Tue, 19 Oct 2021 11:34:01 +0200 Message-Id: <20211019093404.1913357-2-msp@baylibre.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019093404.1913357-1-msp@baylibre.com> References: <20211019093404.1913357-1-msp@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This unit is present on the mt8365 SoC as well. But there is a difference in the usage of an apmixed register. This patch adds a distinct mt8365 to the list of compatibles. Signed-off-by: Markus Schneider-Pargmann Acked-by: Rob Herring --- Documentation/devicetree/bindings/thermal/mediatek-thermal.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt index 5c7e7bdd029a..ba4ebffeade4 100644 --- a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt @@ -14,6 +14,7 @@ Required properties: - "mediatek,mt2712-thermal" : For MT2712 family of SoCs - "mediatek,mt7622-thermal" : For MT7622 SoC - "mediatek,mt8183-thermal" : For MT8183 family of SoCs + - "mediatek,mt8365-thermal" : For MT8365 family of SoCs - "mediatek,mt8516-thermal", "mediatek,mt2701-thermal : For MT8516 family of SoCs - reg: Address range of the thermal controller - interrupts: IRQ for the thermal controller From patchwork Tue Oct 19 09:34:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Schneider-Pargmann X-Patchwork-Id: 12569241 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EB54C433EF for ; Tue, 19 Oct 2021 09:36:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8A2EB6137E for ; Tue, 19 Oct 2021 09:36:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235094AbhJSJip (ORCPT ); Tue, 19 Oct 2021 05:38:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235108AbhJSJim (ORCPT ); Tue, 19 Oct 2021 05:38:42 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BBB27C061768 for ; Tue, 19 Oct 2021 02:36:29 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id r7so46655317wrc.10 for ; Tue, 19 Oct 2021 02:36:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=31i1xoK4zj6WYEXJeZOG+hCuryOlTysPNDj29OD14Qs=; b=Y2eamLP67cGTLHdzxPbLdUPEYihkfZRXjLmtnxWMV7V8ha/xCyyiXWo24W7cKen6+2 AGmoxk8bAW1ZE6wRgyRZos2ZQJMvNmw3sEuikrcYvIIJYL03YACYQOa86okD3Erk21lV zAulkyr2f+gShgG97UnqzhdNrdO4Ua/xG4LPoWuamUHLjChfopvT3lP+voMhWfkt75tD zuNwqbKJobK755qHzpRhFHg3/uXIWAqhCAsc34J2OyIwWG2lZJkVUYczpRjmhcaddgYi S+iJFqHmqysc2aP70TNig3aAyHEkcBamDT9NGvGMwzizmPHMQZX9kKJlZVFcn3mFIdL5 Ioew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=31i1xoK4zj6WYEXJeZOG+hCuryOlTysPNDj29OD14Qs=; b=p2z91iE/sRQG2t+QnZuY67Wi4jIfCsFWx1AaHvRi4ecFlp1f8ni8ij9uJAjpL59xVX i4Axsb+z6eoB2i7Y8tbPHqaRogpTwwS5KdKTMKTdYOnih/v28+wRMLVE7lLIKHtM3X6X qA4RxSmw12n7aVzW+juTkzdYbJW0StDpILZolZ7h4TO6EtMAGmx8CFIVGYXl/wjY4vPN ZIfoynn1NjynSeKMJlrHrvfKeYOHE+syTI/ZxF2GYu5jGC+ufpyZYpoebuejoQxlFZcY mFWShgQ35w5pAogCYhNTkcqn0RBBkWdRE2Vu+CRPUgKjJ0CxkEScBPHJF+bYpO48+FDt t6Lg== X-Gm-Message-State: AOAM533U+W0+gZUv7td72nxcZ0hhaXIFcYtDxzEk8irvs5GLgKBd4Q9q k5XOUZMRuBg/ruIOzESxhXN77Q== X-Google-Smtp-Source: ABdhPJw4NYs7gbiGNwWpmbKhDuahGeNvec/NydYON0RX/wR9CskYqy79yYN2c7zZkDO3NcrXwh+8DA== X-Received: by 2002:adf:f812:: with SMTP id s18mr5519018wrp.347.1634636188391; Tue, 19 Oct 2021 02:36:28 -0700 (PDT) Received: from blmsp.lan ([2a02:2454:3e6:c900:5142:5fbb:5821:5dc3]) by smtp.gmail.com with ESMTPSA id o23sm1765765wms.18.2021.10.19.02.36.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 02:36:28 -0700 (PDT) From: Markus Schneider-Pargmann To: Zhang Rui , Daniel Lezcano , Matthias Brugger , Rob Herring Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, fparent@baylibre.com, khilman@baylibre.com, Markus Schneider-Pargmann Subject: [PATCH v2 2/4] thermal: mediatek: Fix apmixed error message Date: Tue, 19 Oct 2021 11:34:02 +0200 Message-Id: <20211019093404.1913357-3-msp@baylibre.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019093404.1913357-1-msp@baylibre.com> References: <20211019093404.1913357-1-msp@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Seems to be a copy and paste mistake, this is the apmixed address, not auxadc. Signed-off-by: Markus Schneider-Pargmann Fixes: a92db1c8089e (thermal: Add Mediatek thermal controller support) --- drivers/thermal/mtk_thermal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c index ede94eadddda..93ee043d70da 100644 --- a/drivers/thermal/mtk_thermal.c +++ b/drivers/thermal/mtk_thermal.c @@ -1050,7 +1050,7 @@ static int mtk_thermal_probe(struct platform_device *pdev) of_node_put(apmixedsys); if (apmixed_phys_base == OF_BAD_ADDR) { - dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + dev_err(&pdev->dev, "Can't get apmixed phys address\n"); return -EINVAL; } From patchwork Tue Oct 19 09:34:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Schneider-Pargmann X-Patchwork-Id: 12569243 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32FB9C433FE for ; Tue, 19 Oct 2021 09:36:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1A98F61177 for ; Tue, 19 Oct 2021 09:36:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235101AbhJSJiq (ORCPT ); Tue, 19 Oct 2021 05:38:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235102AbhJSJin (ORCPT ); Tue, 19 Oct 2021 05:38:43 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B05BC06161C for ; Tue, 19 Oct 2021 02:36:30 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id 67-20020a1c1946000000b0030d4c90fa87so2422812wmz.2 for ; Tue, 19 Oct 2021 02:36:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4iBt5PaBb/SQkmIAGIPWPkHg9L+YHvcMfnSpD3LPoVg=; b=RK+5r5PwEA/nuA6SQzYqBleLenuGSzS9bmVPSgmr30nYakGL83fg5O29IqmUhqTMSz 7Gcz6od5O0ScvHxpYw0qK/0TwGLi3UWhkIfrTfMGbSwCLg5oaQx9td5xU7dA+1t42YNS u5hERCsAx9QENchxYFqV61KzePoxXK+NZXQ+e9kBphHBFw/qeQ0V6w5NeIVUthLNaA5e xHwd3UTYdP3K4iZYTZcCrBuz2qpb/+kToloaGtsFIYqF1Tr9+OavLKXW99ZOKyJFtmg9 buEnZ1+oqdBqcvf30QXT0uh+is2HrMukQHi68HyrBp6FuwEVzhWH0SaghAHfuqtjPo6Z Faew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4iBt5PaBb/SQkmIAGIPWPkHg9L+YHvcMfnSpD3LPoVg=; b=x7KkUcqIZuuOF0EfNz224qZnlqZbVNys1hw+HWjDjTlDWfvnqqn53bDc2TFEgmAxmc dTwf5MqW9LXWxwO3rHxU5GNOTEh7mWAAFSKmEifiyqoBAZb0UO/ma7FFL7g7r8LpPnhh vOV9RX3wgEPm51mCTQ3XBxIA43O+/5HyklJUWPlEGKmUZpZ+qsLUErvyp44a0c/cv48R 1KKaHnoUlzEAGU46QPHYQKWLngABz7luZMfIYEtgP+0SBd6taIIQL87uylOxZrW237KA MH9bpn/G/j6A+3HbV701/uxUU0HDGQ/Lfwwz9InK35pQND9GyDWSgDlyCbGX0mpLR4YS t7Bg== X-Gm-Message-State: AOAM5300g28agkCxJbXziZAk87eubgDYUSdcqwJRKq3rNxnvKQ3JI+B3 7SlTxeH6YqM43R3vjnTBltC1Kw== X-Google-Smtp-Source: ABdhPJyWlQB++OW76/yEH4NmsYV5AtI/qYWUDcxm+rP4W3MU5xU76g2eBRuPCVnJT3D8VtWE+sU+Ow== X-Received: by 2002:a1c:4b08:: with SMTP id y8mr5016066wma.98.1634636189302; Tue, 19 Oct 2021 02:36:29 -0700 (PDT) Received: from blmsp.lan ([2a02:2454:3e6:c900:5142:5fbb:5821:5dc3]) by smtp.gmail.com with ESMTPSA id o23sm1765765wms.18.2021.10.19.02.36.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 02:36:28 -0700 (PDT) From: Markus Schneider-Pargmann To: Zhang Rui , Daniel Lezcano , Matthias Brugger , Rob Herring Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, fparent@baylibre.com, khilman@baylibre.com, Markus Schneider-Pargmann Subject: [PATCH v2 3/4] thermal: mediatek: Remove data void casts Date: Tue, 19 Oct 2021 11:34:03 +0200 Message-Id: <20211019093404.1913357-4-msp@baylibre.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019093404.1913357-1-msp@baylibre.com> References: <20211019093404.1913357-1-msp@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org It is not necessary to cast struct mtk_thermal_data to (void*). This patch removes these casts. Signed-off-by: Markus Schneider-Pargmann --- drivers/thermal/mtk_thermal.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c index 93ee043d70da..af6cd11eb221 100644 --- a/drivers/thermal/mtk_thermal.c +++ b/drivers/thermal/mtk_thermal.c @@ -941,23 +941,23 @@ static int mtk_thermal_get_calibration_data(struct device *dev, static const struct of_device_id mtk_thermal_of_match[] = { { .compatible = "mediatek,mt8173-thermal", - .data = (void *)&mt8173_thermal_data, + .data = &mt8173_thermal_data, }, { .compatible = "mediatek,mt2701-thermal", - .data = (void *)&mt2701_thermal_data, + .data = &mt2701_thermal_data, }, { .compatible = "mediatek,mt2712-thermal", - .data = (void *)&mt2712_thermal_data, + .data = &mt2712_thermal_data, }, { .compatible = "mediatek,mt7622-thermal", - .data = (void *)&mt7622_thermal_data, + .data = &mt7622_thermal_data, }, { .compatible = "mediatek,mt8183-thermal", - .data = (void *)&mt8183_thermal_data, + .data = &mt8183_thermal_data, }, { }, }; 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Tue, 19 Oct 2021 02:36:29 -0700 (PDT) From: Markus Schneider-Pargmann To: Zhang Rui , Daniel Lezcano , Matthias Brugger , Rob Herring Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, fparent@baylibre.com, khilman@baylibre.com, Markus Schneider-Pargmann Subject: [PATCH v2 4/4] thermal: mediatek: add MT8365 thermal driver support Date: Tue, 19 Oct 2021 11:34:04 +0200 Message-Id: <20211019093404.1913357-5-msp@baylibre.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019093404.1913357-1-msp@baylibre.com> References: <20211019093404.1913357-1-msp@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Fabien Parent mt8365 is similar to the other SoCs supported by the driver. It has only one bank and 3 sensors that can be multiplexed. Additionally the buffer has to be enabled and connected to AUXADC similar to the V2 version but at a different register offset. That's why I added three new configuration values to define the register, mask and bits to be set to be able to use it for both V2 and mt8365. Signed-off-by: Fabien Parent [Added apmixed control register logic] Signed-off-by: Markus Schneider-Pargmann --- Notes: Changes v1 -> v2: - Use of ARRAY_SIZE to avoid NUM macros. - Remove (void*) cast. - Use macros for mt7622 buffer_ctl operations. drivers/thermal/mtk_thermal.c | 90 ++++++++++++++++++++++++++++++++--- 1 file changed, 84 insertions(+), 6 deletions(-) diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c index af6cd11eb221..fc4ea58d00ec 100644 --- a/drivers/thermal/mtk_thermal.c +++ b/drivers/thermal/mtk_thermal.c @@ -31,6 +31,7 @@ #define AUXADC_CON2_V 0x010 #define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define APMIXED_SYS_TS_CON0 0x600 #define APMIXED_SYS_TS_CON1 0x604 /* Thermal Controller Registers */ @@ -212,6 +213,8 @@ enum mtk_thermal_version { #define MT7622_NUM_SENSORS_PER_ZONE 1 #define MT7622_TS1 0 #define MT7622_NUM_CONTROLLER 1 +#define MT7622_BUFFER_CTL_MASK ~0x37 +#define MT7622_BUFFER_CTL_SET 0x1 /* The maximum number of banks */ #define MAX_NUM_ZONES 8 @@ -245,6 +248,14 @@ enum mtk_thermal_version { /* The calibration coefficient of sensor */ #define MT8183_CALIBRATION 153 +/* MT8365 */ +#define MT8365_TEMP_AUXADC_CHANNEL 11 +#define MT8365_CALIBRATION 164 +#define MT8365_NUM_BANKS 1 +#define MT8365_TS1 0 +#define MT8365_TS2 1 +#define MT8365_TS3 2 + struct mtk_thermal; struct thermal_bank_cfg { @@ -271,6 +282,9 @@ struct mtk_thermal_data { bool need_switch_bank; struct thermal_bank_cfg bank_data[MAX_NUM_ZONES]; enum mtk_thermal_version version; + u32 apmixed_buffer_ctl_reg; + u32 apmixed_buffer_ctl_mask; + u32 apmixed_buffer_ctl_set; }; struct mtk_thermal { @@ -386,6 +400,25 @@ static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, }; static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, }; +/* MT8365 thermal sensor data */ +static const int mt8365_bank_data[] = { + MT8365_TS1, MT8365_TS2, MT8365_TS3 +}; + +static const int mt8365_msr[ARRAY_SIZE(mt8365_bank_data)] = { + TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 +}; + +static const int mt8365_adcpnp[ARRAY_SIZE(mt8365_bank_data)] = { + TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 +}; + +static const int mt8365_mux_values[ARRAY_SIZE(mt8365_bank_data)] = { 0, 1, 2 }; +static const int mt8365_tc_offset[] = { 0 }; + +static const int mt8365_vts_index[ARRAY_SIZE(mt8365_bank_data)] = { VTS1, VTS2, + VTS3 }; + /* * The MT8173 thermal controller has four banks. Each bank can read up to * four temperature sensors simultaneously. The MT8173 has a total of 5 @@ -460,6 +493,39 @@ static const struct mtk_thermal_data mt2701_thermal_data = { .version = MTK_THERMAL_V1, }; +/* + * The MT8365 thermal controller has one bank, which can read up to + * four temperature sensors simultaneously. The MT8365 has a total of 3 + * temperature sensors. + * + * The thermal core only gets the maximum temperature of this one bank, + * so the bank concept wouldn't be necessary here. However, the SVS (Smart + * Voltage Scaling) unit makes its decisions based on the same bank + * data. + */ +static const struct mtk_thermal_data mt8365_thermal_data = { + .auxadc_channel = MT8365_TEMP_AUXADC_CHANNEL, + .num_banks = MT8365_NUM_BANKS, + .num_sensors = ARRAY_SIZE(mt8365_bank_data), + .vts_index = mt8365_vts_index, + .cali_val = MT8365_CALIBRATION, + .num_controller = ARRAY_SIZE(mt8365_tc_offset), + .controller_offset = mt8365_tc_offset, + .need_switch_bank = false, + .bank_data = { + { + .num_sensors = ARRAY_SIZE(mt8365_bank_data), + .sensors = mt8365_bank_data + }, + }, + .msr = mt8365_msr, + .adcpnp = mt8365_adcpnp, + .sensor_mux_values = mt8365_mux_values, + .version = MTK_THERMAL_V1, + .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON0, + .apmixed_buffer_ctl_mask = ~(u32)GENMASK(29, 28), +}; + /* * The MT2712 thermal controller has one bank, which can read up to * four temperature sensors simultaneously. The MT2712 has a total of 4 @@ -514,6 +580,9 @@ static const struct mtk_thermal_data mt7622_thermal_data = { .adcpnp = mt7622_adcpnp, .sensor_mux_values = mt7622_mux_values, .version = MTK_THERMAL_V2, + .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1, + .apmixed_buffer_ctl_mask = MT7622_BUFFER_CTL_MASK, + .apmixed_buffer_ctl_set = MT7622_BUFFER_CTL_SET, }; /* @@ -958,19 +1027,27 @@ static const struct of_device_id mtk_thermal_of_match[] = { { .compatible = "mediatek,mt8183-thermal", .data = &mt8183_thermal_data, + }, + { + .compatible = "mediatek,mt8365-thermal", + .data = &mt8365_thermal_data, }, { }, }; MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); -static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base) +static void mtk_thermal_turn_on_buffer(struct mtk_thermal *mt, + void __iomem *apmixed_base) { int tmp; - tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1); - tmp &= ~(0x37); - tmp |= 0x1; - writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1); + if (!mt->conf->apmixed_buffer_ctl_reg) + return; + + tmp = readl(apmixed_base + mt->conf->apmixed_buffer_ctl_reg); + tmp &= mt->conf->apmixed_buffer_ctl_mask; + tmp |= mt->conf->apmixed_buffer_ctl_set; + writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg); udelay(200); } @@ -1070,8 +1147,9 @@ static int mtk_thermal_probe(struct platform_device *pdev) goto err_disable_clk_auxadc; } + mtk_thermal_turn_on_buffer(mt, apmixed_base); + if (mt->conf->version == MTK_THERMAL_V2) { - mtk_thermal_turn_on_buffer(apmixed_base); mtk_thermal_release_periodic_ts(mt, auxadc_base); }