From patchwork Tue Oct 19 21:58:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hugh Cole-Baker X-Patchwork-Id: 12571183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7AA4C433F5 for ; Tue, 19 Oct 2021 22:00:45 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B8EC160FDA for ; Tue, 19 Oct 2021 22:00:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B8EC160FDA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3c9G+/Yqp/0CiRUIGq6TtG8Lvcolnofsfe7uPr757Yo=; b=yDuDynR8vhzEtj LJqGnPoM89jl8yo1ezJI6/IjLVhr+EYcdwaMUzqLuE0t/tIPiNzwJ8BaAQok7xSpg/ZAif+BDplWX ROT2tLTxsCLL3IgAqMmpcHPRwZ2e+rcuUM9Ye/V0hy2o41BQtbleN5/uVn85JAwOiXN2z1kRvbMGa HHseJBmh4SD4UGYha4oBj3C6tkJl2CNcgXAzHzF5qoaBba4Z8MIl+iaZd5xOzrFZ1cVJ+SGW7fE5w Tbb1RPO9jhZWLaeWuzARfA3u0JSx8AwoRKFRJQsUNaI9EZbfkj9gzgwcD9ta4QyiU+Ijqfk+qVV/u 7o0bGXYtjmqOg+TppOxQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mcx8c-002is2-0H; Tue, 19 Oct 2021 21:59:14 +0000 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mcx8J-002ihZ-Mf; Tue, 19 Oct 2021 21:58:57 +0000 Received: by mail-wm1-x32e.google.com with SMTP id z77-20020a1c7e50000000b0030db7b70b6bso5870939wmc.1; Tue, 19 Oct 2021 14:58:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ws77StmGP8OqTFmlkQUufLolF3RfQn4nI0VMLqEcX8s=; b=dGZQ8Q3orJrTzIZ4Gs9rn9dr9PAu9PCjkmUK5Lr6UkhpNzYMcMd3020nPpiG6Sqqpy iLRrSxDSXQ7kSYllOPk2BtvQUGsDdBHD7NGzfb5c2CazkxrvtoLOMJXxZabDfp9dJ33y Nc6l+vslIYyFBqsf5MjBRyT1WWM8BbqdLViNK1jE0RWT9LaZ+QLmNI1goCpLxyjClx5q BHWHbXcWTtSRVC5h7zAbVkeTp5sxkU/JgDJP/NlgaeLhv5fT3vRPg7iwOgHc91kIXC5y UrXcfWoKPWR5+n9loBQ6PqrQbibvW07GBRJNMSRCw72SB0r9diQgYYeWronJNwIqWDmB vHpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ws77StmGP8OqTFmlkQUufLolF3RfQn4nI0VMLqEcX8s=; b=sxveNLJpyeHIxAc0lLGzMi6dTwpuj5EC2Nq5+ypLTJu+vH83R/yV+whpVpI4yQbNQZ uZfjds+vUF8T/kr+k9v72xQGg5VmtKIm4Al4j8+OdPupdsjUqwymsp40RUA476Pc1yX+ DjIRdfFWS6YDp5foNGlLXHefuI4S/4fvGmW53BI7ZoEGldia25la5PCHUspe2VZI4Lgn ZchGK4aT1RbEL0KBThFjSVt4mGon+KeHk8bjW5CI4EUuAAf4/jpppC69B5Cy+myMU/WE Tujt2FKA0MGVxprviL1MniA81m5IEvewvG5eZhO59TnXKq+XY47lK0n5TGag9jEdT2LT fcsg== X-Gm-Message-State: AOAM533AZaW6ntLxS4JBa7mC0O7lveBcmLsJQF9kcmDdUxInS38G3xBI I/e9THNRFXBr5BPQpV/GwEc= X-Google-Smtp-Source: ABdhPJxlnImj2nZarYrS7pboEsot76oZv/a0I0DfIZ6Yn6Tqye98tM7z2na6Er6vRQMM1xsYYiNxOg== X-Received: by 2002:adf:97d0:: with SMTP id t16mr45716779wrb.124.1634680732995; Tue, 19 Oct 2021 14:58:52 -0700 (PDT) Received: from apple.sigmaris.info (ebrouter.sigmaris.info. [82.69.107.165]) by smtp.gmail.com with ESMTPSA id s3sm178540wrm.40.2021.10.19.14.58.52 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Oct 2021 14:58:52 -0700 (PDT) From: Hugh Cole-Baker To: heiko@sntech.de, hjc@rock-chips.com Cc: dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, ezequiel@collabora.com, Hugh Cole-Baker Subject: [PATCH v2 1/3] drm/rockchip: define gamma registers for RK3399 Date: Tue, 19 Oct 2021 22:58:41 +0100 Message-Id: <20211019215843.42718-2-sigmaris@gmail.com> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20211019215843.42718-1-sigmaris@gmail.com> References: <20211019215843.42718-1-sigmaris@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211019_145855_763472_DAE885F2 X-CRM114-Status: GOOD ( 15.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The VOP on RK3399 has a different approach from previous versions for setting a gamma lookup table, using an update_gamma_lut register. As this differs from RK3288, give RK3399 its own set of "common" register definitions. Signed-off-by: Hugh Cole-Baker Tested-by: "Milan P. Stanić" Tested-by: Linus Heckemann --- Changes from v1: no changes in this patch drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 2 ++ drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 24 +++++++++++++++++++-- drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 1 + 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 857d97cdc67c..14179e89bd21 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -99,6 +99,8 @@ struct vop_common { struct vop_reg dither_down_en; struct vop_reg dither_up; struct vop_reg dsp_lut_en; + struct vop_reg update_gamma_lut; + struct vop_reg lut_buffer_index; struct vop_reg gate_en; struct vop_reg mmu_en; struct vop_reg out_mode; diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index ca7cc82125cb..bfb7e130f09b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -865,6 +865,24 @@ static const struct vop_output rk3399_output = { .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3), }; +static const struct vop_common rk3399_common = { + .standby = VOP_REG_SYNC(RK3399_SYS_CTRL, 0x1, 22), + .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23), + .mmu_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 20), + .dither_down_sel = VOP_REG(RK3399_DSP_CTRL1, 0x1, 4), + .dither_down_mode = VOP_REG(RK3399_DSP_CTRL1, 0x1, 3), + .dither_down_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 2), + .pre_dither_down = VOP_REG(RK3399_DSP_CTRL1, 0x1, 1), + .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6), + .dsp_lut_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 0), + .update_gamma_lut = VOP_REG(RK3399_DSP_CTRL1, 0x1, 7), + .lut_buffer_index = VOP_REG(RK3399_DBG_POST_REG1, 0x1, 1), + .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19), + .dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18), + .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0), + .cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0), +}; + static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = { .y2r_coefficients = { VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 0), @@ -944,7 +962,7 @@ static const struct vop_data rk3399_vop_big = { .version = VOP_VERSION(3, 5), .feature = VOP_FEATURE_OUTPUT_RGB10, .intr = &rk3366_vop_intr, - .common = &rk3288_common, + .common = &rk3399_common, .modeset = &rk3288_modeset, .output = &rk3399_output, .afbc = &rk3399_vop_afbc, @@ -952,6 +970,7 @@ static const struct vop_data rk3399_vop_big = { .win = rk3399_vop_win_data, .win_size = ARRAY_SIZE(rk3399_vop_win_data), .win_yuv2yuv = rk3399_vop_big_win_yuv2yuv_data, + .lut_size = 1024, }; static const struct vop_win_data rk3399_vop_lit_win_data[] = { @@ -970,13 +989,14 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = { static const struct vop_data rk3399_vop_lit = { .version = VOP_VERSION(3, 6), .intr = &rk3366_vop_intr, - .common = &rk3288_common, + .common = &rk3399_common, .modeset = &rk3288_modeset, .output = &rk3399_output, .misc = &rk3368_misc, .win = rk3399_vop_lit_win_data, .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data), .win_yuv2yuv = rk3399_vop_lit_win_yuv2yuv_data, + .lut_size = 256, }; static const struct vop_win_data rk3228_vop_win_data[] = { diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index 0b3cd65ba5c1..406e981c75bd 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -628,6 +628,7 @@ #define RK3399_YUV2YUV_WIN 0x02c0 #define RK3399_YUV2YUV_POST 0x02c4 #define RK3399_AUTO_GATING_EN 0x02cc +#define RK3399_DBG_POST_REG1 0x036c #define RK3399_WIN0_CSC_COE 0x03a0 #define RK3399_WIN1_CSC_COE 0x03c0 #define RK3399_WIN2_CSC_COE 0x03e0 From patchwork Tue Oct 19 21:58:42 2021 Content-Type: text/plain; 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[82.69.107.165]) by smtp.gmail.com with ESMTPSA id s3sm178540wrm.40.2021.10.19.14.58.57 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Oct 2021 14:58:57 -0700 (PDT) From: Hugh Cole-Baker To: heiko@sntech.de, hjc@rock-chips.com Cc: dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, ezequiel@collabora.com, Hugh Cole-Baker Subject: [PATCH v2 2/3] drm/rockchip: support gamma control on RK3399 Date: Tue, 19 Oct 2021 22:58:42 +0100 Message-Id: <20211019215843.42718-3-sigmaris@gmail.com> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20211019215843.42718-1-sigmaris@gmail.com> References: <20211019215843.42718-1-sigmaris@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211019_145901_258532_1013C062 X-CRM114-Status: GOOD ( 23.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The RK3399 has a 1024-entry gamma LUT with 10 bits per component on its "big" VOP and a 256-entry, 8 bit per component LUT on the "little" VOP. Compared to the RK3288, it no longer requires disabling gamma while updating the LUT. On the RK3399, the LUT can be updated at any time as the hardware has two LUT buffers, one can be written while the other is in use. A swap of the buffers is triggered by writing 1 to the update_gamma_lut register. Signed-off-by: Hugh Cole-Baker --- Changes from v1: Moved the vop_crtc_gamma_set call to the end of vop_crtc_atomic_enable after the clocks and CRTC are enabled. drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 105 +++++++++++++------- 1 file changed, 71 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index ba9e14da41b4..e2c97f1b26da 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -66,6 +67,9 @@ #define VOP_REG_SET(vop, group, name, v) \ vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) +#define VOP_HAS_REG(vop, group, name) \ + (!!(vop->data->group->name.mask)) + #define VOP_INTR_SET_TYPE(vop, name, type, v) \ do { \ int i, reg = 0, mask = 0; \ @@ -1204,17 +1208,22 @@ static bool vop_dsp_lut_is_enabled(struct vop *vop) return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en); } +static u32 vop_lut_buffer_index(struct vop *vop) +{ + return vop_read_reg(vop, 0, &vop->data->common->lut_buffer_index); +} + static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) { struct drm_color_lut *lut = crtc->state->gamma_lut->data; - unsigned int i; + unsigned int i, bpc = ilog2(vop->data->lut_size); for (i = 0; i < crtc->gamma_size; i++) { u32 word; - word = (drm_color_lut_extract(lut[i].red, 10) << 20) | - (drm_color_lut_extract(lut[i].green, 10) << 10) | - drm_color_lut_extract(lut[i].blue, 10); + word = (drm_color_lut_extract(lut[i].red, bpc) << (2 * bpc)) | + (drm_color_lut_extract(lut[i].green, bpc) << bpc) | + drm_color_lut_extract(lut[i].blue, bpc); writel(word, vop->lut_regs + i * 4); } } @@ -1224,38 +1233,66 @@ static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, { struct drm_crtc_state *state = crtc->state; unsigned int idle; + u32 lut_idx, old_idx; int ret; if (!vop->lut_regs) return; - /* - * To disable gamma (gamma_lut is null) or to write - * an update to the LUT, clear dsp_lut_en. - */ - spin_lock(&vop->reg_lock); - VOP_REG_SET(vop, common, dsp_lut_en, 0); - vop_cfg_done(vop); - spin_unlock(&vop->reg_lock); - /* - * In order to write the LUT to the internal memory, - * we need to first make sure the dsp_lut_en bit is cleared. - */ - ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, - idle, !idle, 5, 30 * 1000); - if (ret) { - DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); - return; - } + if (!state->gamma_lut || !VOP_HAS_REG(vop, common, update_gamma_lut)) { + /* + * To disable gamma (gamma_lut is null) or to write + * an update to the LUT, clear dsp_lut_en. + */ + spin_lock(&vop->reg_lock); + VOP_REG_SET(vop, common, dsp_lut_en, 0); + vop_cfg_done(vop); + spin_unlock(&vop->reg_lock); - if (!state->gamma_lut) - return; + /* + * In order to write the LUT to the internal memory, + * we need to first make sure the dsp_lut_en bit is cleared. + */ + ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, + idle, !idle, 5, 30 * 1000); + if (ret) { + DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); + return; + } + + if (!state->gamma_lut) + return; + } else { + /* + * On RK3399 the gamma LUT can updated without clearing dsp_lut_en, + * by setting update_gamma_lut then waiting for lut_buffer_index change + */ + old_idx = vop_lut_buffer_index(vop); + } spin_lock(&vop->reg_lock); vop_crtc_write_gamma_lut(vop, crtc); VOP_REG_SET(vop, common, dsp_lut_en, 1); + VOP_REG_SET(vop, common, update_gamma_lut, 1); vop_cfg_done(vop); spin_unlock(&vop->reg_lock); + + if (VOP_HAS_REG(vop, common, update_gamma_lut)) { + ret = readx_poll_timeout(vop_lut_buffer_index, vop, + lut_idx, lut_idx != old_idx, 5, 30 * 1000); + if (ret) { + DRM_DEV_ERROR(vop->dev, "gamma LUT update timeout!\n"); + return; + } + + /* + * update_gamma_lut is auto cleared by HW, but write 0 to clear the bit + * in our backup of the regs. + */ + spin_lock(&vop->reg_lock); + VOP_REG_SET(vop, common, update_gamma_lut, 0); + spin_unlock(&vop->reg_lock); + } } static void vop_crtc_atomic_begin(struct drm_crtc *crtc, @@ -1305,14 +1342,6 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, return; } - /* - * If we have a GAMMA LUT in the state, then let's make sure - * it's updated. We might be coming out of suspend, - * which means the LUT internal memory needs to be re-written. - */ - if (crtc->state->gamma_lut) - vop_crtc_gamma_set(vop, crtc, old_state); - mutex_lock(&vop->vop_lock); WARN_ON(vop->event); @@ -1403,6 +1432,14 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, VOP_REG_SET(vop, common, standby, 0); mutex_unlock(&vop->vop_lock); + + /* + * If we have a GAMMA LUT in the state, then let's make sure + * it's updated. We might be coming out of suspend, + * which means the LUT internal memory needs to be re-written. + */ + if (crtc->state->gamma_lut) + vop_crtc_gamma_set(vop, crtc, old_state); } static bool vop_fs_irq_is_pending(struct vop *vop) @@ -2125,8 +2162,8 @@ static int vop_bind(struct device *dev, struct device *master, void *data) res = platform_get_resource(pdev, IORESOURCE_MEM, 1); if (res) { - if (!vop_data->lut_size) { - DRM_DEV_ERROR(dev, "no gamma LUT size defined\n"); + if (vop_data->lut_size != 1024 && vop_data->lut_size != 256) { + DRM_DEV_ERROR(dev, "unsupported gamma LUT size %d\n", vop_data->lut_size); return -EINVAL; } vop->lut_regs = devm_ioremap_resource(dev, res); From patchwork Tue Oct 19 21:58:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugh Cole-Baker X-Patchwork-Id: 12571191 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D004C433EF for ; Tue, 19 Oct 2021 22:01:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2B2DF6113D for ; Tue, 19 Oct 2021 22:01:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2B2DF6113D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=fklF6BpURx9SDaqt5ayxyS3mxnEIg7gCy04cM/zfdzk=; b=0vkhaGXZawi2h6 gmz6jb/131cV+dXfmE7IagTDDcZR2rasvntSX5ys1acUK6rlOHSqjWp+zdoRanO/uWBAQTzX1yDpi 8V/HIXe3x8HOr88kY6Rp8oUDe6lEdwrdnaU8hHnh16BlZp3sodVPI5LALC0bOY/8tgjWcd6NKa8bH S0tqsr0p7sXFcouVxGcQgQiV98tzvWxULGu0i5jfEv9W7mxuDEjYo+78FP8jH3rPb1P5MzH91fsgx YLUA7tpO51EjHNr36gB9aXx3FFjeM2/UPs8DGgqeS0kLqZrIFU8H5CUWH3Q22zDH8Q94Sl+Ds00Im 6TVuvJ9WdOTx/qhxEEbA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mcx9v-002jYx-IE; Tue, 19 Oct 2021 22:00:35 +0000 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mcx8P-002ikX-LK; Tue, 19 Oct 2021 21:59:04 +0000 Received: by mail-wm1-x332.google.com with SMTP id a140-20020a1c7f92000000b0030d8315b593so5820655wmd.5; Tue, 19 Oct 2021 14:59:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uCZAM1vvyZIsuTswhisB5UCt6gNS7FCdaVGaaFS3YV4=; b=N9x2DcoC3Zq7l+EXYxzzDvYTGb6e0oKBL/owgOeCIM34js4lC6qA/TCA1k1opUXEUK iJyLxAfyGd/1irS6OFaK6/VaWbkuhUSrXcg5VejFWZOTCNEheBAERgim9vZebgpODSTB 0zfpE8VREGwYumyR5wQB7OI+ZVttjvlGw4zUdGt1trfhORiUkTkmFI/a6PYbJB9TlFRb I4/WknNvC/do0cuW/idOQdbadmwvcobJTrlHbgf+cZmrX4RxL7vwtJjMvYku0e8WGnjY iS38SlU6UOMwxnLaCRBqu8RVDT19yUl9mcbSU9vrJpfbI91HZeeKpD3RKOsshqR4E+dm lwBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uCZAM1vvyZIsuTswhisB5UCt6gNS7FCdaVGaaFS3YV4=; b=ZtozeJ/Sb8WHJMd0KU8pz9+jU0TGMxtub9urEkLpu0peP+z2iuJ2IC1R1fHuveNHM9 qHCTWYIko+2U8h6BiSzTBkwKYqtNCH+3e85ImJhtwyX6QbEcNfwrOrShf+PSsYkfunx1 0CBcvHQB3SMQ983RS4X8YXtjeKYhUhJtCq45tsXs2DiMPP1/NiiNRQvqFnX+mlbRos0f 1XrbESWVB/tYzAtCRK2IIyD7dtp8BYkhoudKR0Z0Hc1Q6BomDWFG9H0VV3yNWRgHwdp3 FN+/YFLCLWmVhGZclMvqFYxIKZpr9nWPpTx6TYTWKFpPCTm4wtv3+U6EakPiCKZdZ84f SKJw== X-Gm-Message-State: AOAM532tmkKpoFPpmG1bg92UfYgCYfs57494dXW9qNEbXkobGNhzn4uH U3AFIO+Y+oMp3e1o2nrxeyTtLUEVnPd/ho9y X-Google-Smtp-Source: ABdhPJxx3QAL6lyP35xXPqTB47LPyaFAa19cRinJBEnDBpBQBMv+2xmSW5ECPRIbVOY9Eer57KphDw== X-Received: by 2002:adf:a413:: with SMTP id d19mr48203915wra.246.1634680739774; Tue, 19 Oct 2021 14:58:59 -0700 (PDT) Received: from apple.sigmaris.info (ebrouter.sigmaris.info. [82.69.107.165]) by smtp.gmail.com with ESMTPSA id s3sm178540wrm.40.2021.10.19.14.58.59 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Oct 2021 14:58:59 -0700 (PDT) From: Hugh Cole-Baker To: heiko@sntech.de, hjc@rock-chips.com Cc: dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, ezequiel@collabora.com, Hugh Cole-Baker Subject: [PATCH v2 3/3] arm64: dts: rockchip: enable gamma control on RK3399 Date: Tue, 19 Oct 2021 22:58:43 +0100 Message-Id: <20211019215843.42718-4-sigmaris@gmail.com> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20211019215843.42718-1-sigmaris@gmail.com> References: <20211019215843.42718-1-sigmaris@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211019_145901_757551_331C36C9 X-CRM114-Status: GOOD ( 11.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Define the memory region on RK3399 VOPs containing the gamma LUT at base+0x2000. Signed-off-by: Hugh Cole-Baker --- Changes from v1: no changes in this patch arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 3871c7fd83b0..9cbf6ccdd256 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1619,7 +1619,7 @@ i2s2: i2s@ff8a0000 { vopl: vop@ff8f0000 { compatible = "rockchip,rk3399-vop-lit"; - reg = <0x0 0xff8f0000 0x0 0x3efc>; + reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>; interrupts = ; assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; assigned-clock-rates = <400000000>, <100000000>; @@ -1676,7 +1676,7 @@ vopl_mmu: iommu@ff8f3f00 { vopb: vop@ff900000 { compatible = "rockchip,rk3399-vop-big"; - reg = <0x0 0xff900000 0x0 0x3efc>; + reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>; interrupts = ; assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; assigned-clock-rates = <400000000>, <100000000>;