From patchwork Wed Oct 20 07:14:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "roy-cw.yeh" X-Patchwork-Id: 12571783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89876C433EF for ; Wed, 20 Oct 2021 07:27:27 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3F29660F02 for ; Wed, 20 Oct 2021 07:27:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 3F29660F02 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=84vVxBETtW7ToykRYAznIgzwPViiA9yQR0Ioe51DfOw=; b=ItKFe2BqzPlmHB eB0sDbY8ewUiuBUyFN5V74xMtDyWFIGtuZiNbE8rYzW6DU+m3LZcwHCk42AgPjy6E9YZw9AikIQ/+ xLv3rA19nK1RGoZgmsFnhRa+v3yiV19FQoC9fRdlNmGEuEEj+FolTByXdJju0Rn/2STM1h+Zw1nkJ 2q/7dO2F9Lma1sweEHamd5Ue+uOXHLePxfasGIzheHYzxGcXWj4Ga+3CuJ3mZ9Hz7CFsH+xSWw34w WYmY1EdCD4RDqZcDPdP83BuDurSRLlws0wHxsf+vrxuLtl2QN5a1QkTNj/8ik2/hQvlwHN3kBqxn8 lCvEsudnTF81nh2oh6ng==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1md60I-003dDa-24; Wed, 20 Oct 2021 07:27:14 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1md5yf-003ceq-Ir; Wed, 20 Oct 2021 07:25:35 +0000 X-UUID: 04ac2b30dec640559ebfa179466e1a87-20211020 X-UUID: 04ac2b30dec640559ebfa179466e1a87-20211020 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1406641701; Wed, 20 Oct 2021 00:25:30 -0700 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Oct 2021 00:15:28 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Oct 2021 15:15:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Oct 2021 15:15:26 +0800 From: roy-cw.yeh To: Rob Herring , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Kuang Hu CC: Mauro Carvalho Chehab , Fabien Parent , "Roy-CW . Yeh" , "jason-jh . lin" , daoyuan huang , Ping-Hsun Wu , Moudy Ho , "river . cheng" , Enric Balletbo i Serra , Yongqiang Niu , , , , , Subject: [PATCH v2 1/9] soc: mediatek: mmsys: expand MDP enum for chip independence architecture Date: Wed, 20 Oct 2021 15:14:40 +0800 Message-ID: <20211020071448.14187-2-roy-cw.yeh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211020071448.14187-1-roy-cw.yeh@mediatek.com> References: <20211020071448.14187-1-roy-cw.yeh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211020_002533_650248_5607C2A2 X-CRM114-Status: GOOD ( 12.59 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: "Roy-CW.Yeh" Expand mdp related enum for chip independence architecture Signed-off-by: Roy-CW.Yeh Acked-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-mmsys.c | 2 - include/linux/soc/mediatek/mtk-mmsys.h | 89 ++++++++++++++++++++------ 2 files changed, 70 insertions(+), 21 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index b16e6a2628c5..cbae8063a187 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -128,7 +128,6 @@ void mtk_mmsys_mdp_connect(struct device *dev, struct mmsys_cmdq_cmd *cmd, int i; WARN_ON(!routes); - WARN_ON(mmsys->subsys_id == 0); for (i = 0; i < mmsys->data->mdp_num_routes; i++) if (cur == routes[i].from_comp && next == routes[i].to_comp) cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, @@ -145,7 +144,6 @@ void mtk_mmsys_mdp_disconnect(struct device *dev, struct mmsys_cmdq_cmd *cmd, const struct mtk_mmsys_routes *routes = mmsys->data->mdp_routes; int i; - WARN_ON(mmsys->subsys_id == 0); for (i = 0; i < mmsys->data->mdp_num_routes; i++) if (cur == routes[i].from_comp && next == routes[i].to_comp) cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 113d33e2155f..acf4bd3deac1 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -76,33 +76,84 @@ enum mtk_mdp_comp_id { /* MDP */ MDP_COMP_CAMIN, /* 9 */ MDP_COMP_CAMIN2, /* 10 */ - MDP_COMP_RDMA0, /* 11 */ - MDP_COMP_AAL0, /* 12 */ - MDP_COMP_CCORR0, /* 13 */ - MDP_COMP_RSZ0, /* 14 */ - MDP_COMP_RSZ1, /* 15 */ - MDP_COMP_TDSHP0, /* 16 */ - MDP_COMP_COLOR0, /* 17 */ - MDP_COMP_PATH0_SOUT, /* 18 */ - MDP_COMP_PATH1_SOUT, /* 19 */ - MDP_COMP_WROT0, /* 20 */ - MDP_COMP_WDMA, /* 21 */ - - /* Dummy Engine */ - MDP_COMP_RDMA1, /* 22 */ - MDP_COMP_RSZ2, /* 23 */ - MDP_COMP_TDSHP1, /* 24 */ - MDP_COMP_WROT1, /* 25 */ + MDP_COMP_SPLIT, /* 11 */ + MDP_COMP_SPLIT2, /* 12 */ + MDP_COMP_RDMA0, /* 13 */ + MDP_COMP_RDMA1, /* 14 */ + MDP_COMP_RDMA2, /* 15 */ + MDP_COMP_RDMA3, /* 16 */ + MDP_COMP_STITCH, /* 17 */ + MDP_COMP_FG0, /* 18 */ + MDP_COMP_FG1, /* 19 */ + MDP_COMP_FG2, /* 20 */ + MDP_COMP_FG3, /* 21 */ + MDP_COMP_TO_SVPP2MOUT, /* 22 */ + MDP_COMP_TO_SVPP3MOUT, /* 23 */ + MDP_COMP_TO_WARP0MOUT, /* 24 */ + MDP_COMP_TO_WARP1MOUT, /* 25 */ + MDP_COMP_VPP0_SOUT, /* 26 */ + MDP_COMP_VPP1_SOUT, /* 27 */ + MDP_COMP_PQ0_SOUT, /* 28 */ + MDP_COMP_PQ1_SOUT, /* 29 */ + MDP_COMP_HDR0, /* 30 */ + MDP_COMP_HDR1, /* 31 */ + MDP_COMP_HDR2, /* 32 */ + MDP_COMP_HDR3, /* 33 */ + MDP_COMP_AAL0, /* 34 */ + MDP_COMP_AAL1, /* 35 */ + MDP_COMP_AAL2, /* 36 */ + MDP_COMP_AAL3, /* 37 */ + MDP_COMP_CCORR0, /* 38 */ + MDP_COMP_RSZ0, /* 39 */ + MDP_COMP_RSZ1, /* 40 */ + MDP_COMP_RSZ2, /* 41 */ + MDP_COMP_RSZ3, /* 42 */ + MDP_COMP_TDSHP0, /* 43 */ + MDP_COMP_TDSHP1, /* 44 */ + MDP_COMP_TDSHP2, /* 45 */ + MDP_COMP_TDSHP3, /* 46 */ + MDP_COMP_COLOR0, /* 47 */ + MDP_COMP_COLOR1, /* 48 */ + MDP_COMP_COLOR2, /* 49 */ + MDP_COMP_COLOR3, /* 50 */ + MDP_COMP_OVL0, /* 51 */ + MDP_COMP_OVL1, /* 52 */ + MDP_COMP_PAD0, /* 53 */ + MDP_COMP_PAD1, /* 54 */ + MDP_COMP_PAD2, /* 55 */ + MDP_COMP_PAD3, /* 56 */ + MDP_COMP_TCC0, /* 56 */ + MDP_COMP_TCC1, /* 57 */ + MDP_COMP_WROT0, /* 58 */ + MDP_COMP_WROT1, /* 59 */ + MDP_COMP_WROT2, /* 60 */ + MDP_COMP_WROT3, /* 61 */ + MDP_COMP_WDMA, /* 62 */ + MDP_COMP_MERGE2, /* 63 */ + MDP_COMP_MERGE3, /* 64 */ + MDP_COMP_PATH0_SOUT, /* 65 */ + MDP_COMP_PATH1_SOUT, /* 66 */ + MDP_COMP_VDO0DL0, /* 67 */ + MDP_COMP_VDO1DL0, /* 68 */ + MDP_COMP_VDO0DL1, /* 69 */ + MDP_COMP_VDO1DL1, /* 70 */ MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */ }; enum mtk_mdp_pipe_id { + MDP_PIPE_IMGI = 0, MDP_PIPE_RDMA0, - MDP_PIPE_IMGI, MDP_PIPE_WPEI, MDP_PIPE_WPEI2, - MDP_PIPE_MAX + MDP_PIPE_RDMA1, + MDP_PIPE_RDMA2, + MDP_PIPE_RDMA3, + MDP_PIPE_SPLIT, + MDP_PIPE_SPLIT2, + MDP_PIPE_VPP0_SOUT, + MDP_PIPE_VPP1_SOUT, + MDP_PIPE_MAX, }; enum mtk_isp_ctrl { From patchwork Wed Oct 20 07:14:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "roy-cw.yeh" X-Patchwork-Id: 12571747 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E02A2C433EF for ; Wed, 20 Oct 2021 07:17:09 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A3C0960524 for ; Wed, 20 Oct 2021 07:17:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A3C0960524 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=uEu1V7D1HCMTbQHbkRn1x7eoE7dNmDQ/YTjz79pLQx8=; b=nSHLLIcUOe9NP6 UsahBFwWIs/PnEJHZO5jhpVNRawuQi3HmYV2w5ib9b7LsXmF5+QMRg7VeBa6Z1Ln6u3aTzhnX8tof jTooPFCygdtkWRUI5zcGYlt8xrMgxoFCc2i0pQnbj/v3sLjjYuZYmY0Mq1TNAELcOFyqm2+1ILJNp EWXeB4PuehcvPnF0HfCZJ6I664cUMseGcbU+P21VNHBREkHW61tpXM+M+dyedSnN6nl7URHxmtTrR +D7I/ouyluB5HchizUi0r7/MhwWEciOIo1PJOv6hT9/yI3JsZ22cqptPqESu3Btw0jaHrs4+hnFeZ 0jkITHEUFklIXxn5hlWg==; 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Wed, 20 Oct 2021 15:15:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Oct 2021 15:15:26 +0800 From: roy-cw.yeh To: Rob Herring , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Kuang Hu CC: Mauro Carvalho Chehab , Fabien Parent , "Roy-CW . Yeh" , "jason-jh . lin" , daoyuan huang , Ping-Hsun Wu , Moudy Ho , "river . cheng" , Enric Balletbo i Serra , Yongqiang Niu , , , , , Subject: [PATCH v2 2/9] soc: mediatek: mutex: expand parameter for mdp mutex function Date: Wed, 20 Oct 2021 15:14:41 +0800 Message-ID: <20211020071448.14187-3-roy-cw.yeh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211020071448.14187-1-roy-cw.yeh@mediatek.com> References: <20211020071448.14187-1-roy-cw.yeh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211020_001533_678370_23067DEE X-CRM114-Status: GOOD ( 14.81 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: "Roy-CW.Yeh" Expand parameter for mdp mutex function Signed-off-by: Roy-CW.Yeh Acked-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-mutex.c | 26 ++++++++++++++++++-------- include/linux/soc/mediatek/mtk-mutex.h | 2 +- 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 814f58f692cf..c100a5249016 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -25,8 +25,9 @@ #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) -#define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n)) -#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n)) +#define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) ((mutex_mod_reg) + 0x20 * (n)) +#define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n) ((mutex_mod_reg) + 0x20 * (n) + 0x4) +#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) ((mutex_sof_reg) + 0x20 * (n)) #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) #define INT_MUTEX BIT(1) @@ -116,6 +117,11 @@ #define MT8183_MUTEX_MDP_MOD_MASK 0x07FFFFFF #define MT8183_MUTEX_MDP_SOF_MASK 0x00000007 +#define MT8183_MDP_PIPE_IMGI MT8183_MUTEX_MDP_START +#define MT8183_MDP_PIPE_RDMA0 (MT8183_MUTEX_MDP_START + 1) +#define MT8183_MDP_PIPE_WPEI (MT8183_MUTEX_MDP_START + 2) +#define MT8183_MDP_PIPE_WPEI2 (MT8183_MUTEX_MDP_START + 3) + struct mtk_mutex { int id; bool claimed; @@ -254,10 +260,10 @@ static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { /* indicate which mutex is used by each pipepline */ static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = { - [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START, - [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1, - [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2, - [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3 + [MDP_PIPE_IMGI] = MT8183_MDP_PIPE_IMGI, + [MDP_PIPE_RDMA0] = MT8183_MDP_PIPE_RDMA0, + [MDP_PIPE_WPEI] = MT8183_MDP_PIPE_WPEI, + [MDP_PIPE_WPEI2] = MT8183_MDP_PIPE_WPEI2, }; static const struct mtk_mutex_data mt2701_mutex_driver_data = { @@ -410,7 +416,7 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex, EXPORT_SYMBOL_GPL(mtk_mutex_add_comp); void mtk_mutex_add_mdp_mod(struct mtk_mutex *mutex, u32 mod, - struct mmsys_cmdq_cmd *cmd) + u32 mod1, u32 sof, struct mmsys_cmdq_cmd *cmd) { struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, mutex[mutex->id]); @@ -422,9 +428,13 @@ void mtk_mutex_add_mdp_mod(struct mtk_mutex *mutex, u32 mod, cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset, mod, mtx->data->mutex_mdp_mod_mask); + offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg, mutex->id); + cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset, + mod1, mtx->data->mutex_mdp_mod_mask); + offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id); cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset, - 0, mtx->data->mutex_mdp_sof_mask); + sof, mtx->data->mutex_mdp_sof_mask); } EXPORT_SYMBOL_GPL(mtk_mutex_add_mdp_mod); diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h index d08b98419dd9..a2b81ce55b5d 100644 --- a/include/linux/soc/mediatek/mtk-mutex.h +++ b/include/linux/soc/mediatek/mtk-mutex.h @@ -17,7 +17,7 @@ int mtk_mutex_prepare(struct mtk_mutex *mutex); void mtk_mutex_add_comp(struct mtk_mutex *mutex, enum mtk_ddp_comp_id id); void mtk_mutex_add_mdp_mod(struct mtk_mutex *mutex, u32 mod, - struct mmsys_cmdq_cmd *cmd); + u32 mod1, u32 sof, struct mmsys_cmdq_cmd *cmd); void mtk_mutex_enable(struct mtk_mutex *mutex); void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex, struct mmsys_cmdq_cmd *cmd); From patchwork Wed Oct 20 07:14:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "roy-cw.yeh" X-Patchwork-Id: 12571779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CD6DC433EF for ; Wed, 20 Oct 2021 07:21:00 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CE12860F59 for ; Wed, 20 Oct 2021 07:20:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org CE12860F59 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; 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Wed, 20 Oct 2021 07:16:06 +0000 X-UUID: 1f267a4bff494bb39bc10a63a38e45f4-20211020 X-UUID: 1f267a4bff494bb39bc10a63a38e45f4-20211020 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1527368958; Wed, 20 Oct 2021 00:15:30 -0700 Received: from mtkmbs10n1.mediatek.inc (172.21.101.34) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Oct 2021 00:15:28 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 20 Oct 2021 15:15:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Oct 2021 15:15:26 +0800 From: roy-cw.yeh To: Rob Herring , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Kuang Hu CC: Mauro Carvalho Chehab , Fabien Parent , "Roy-CW . Yeh" , "jason-jh . lin" , daoyuan huang , Ping-Hsun Wu , Moudy Ho , "river . cheng" , Enric Balletbo i Serra , Yongqiang Niu , , , , , Subject: [PATCH v2 3/9] media: platform: mtk-mdp3: add chip independence architecture Date: Wed, 20 Oct 2021 15:14:42 +0800 Message-ID: <20211020071448.14187-4-roy-cw.yeh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211020071448.14187-1-roy-cw.yeh@mediatek.com> References: <20211020071448.14187-1-roy-cw.yeh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211020_001546_099224_EA8E6CDB X-CRM114-Status: GOOD ( 21.55 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: "Roy-CW.Yeh" Add chip independence architecture - Add hal architecture for mt8183 - Add driver data to adapt other soc Signed-off-by: Roy-CW.Yeh Acked-by: AngeloGioacchino Del Regno --- .../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 154 ++++--- .../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 181 ++++----- .../media/platform/mtk-mdp3/mtk-mdp3-comp.h | 193 ++++++++- .../media/platform/mtk-mdp3/mtk-mdp3-core.c | 383 +++++++++++++++++- .../media/platform/mtk-mdp3/mtk-mdp3-core.h | 19 + .../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 10 +- .../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 259 +----------- .../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 268 ++++++------ 8 files changed, 925 insertions(+), 542 deletions(-) diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c index 1636b60251ce..8972cb8de755 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c @@ -42,16 +42,43 @@ static bool is_output_disable(const struct img_compparam *param, u32 count) true; } +static int mdp_get_mutex_idx(const struct mtk_mdp_driver_data *data, enum mtk_mdp_pipe_id pipe_id) +{ + int i = 0; + + for (i = 0; i < data->pipe_info_len; i++) { + if (pipe_id == data->pipe_info[i].pipe_id) + return i; + } + + return -ENODEV; +} + +int mdp_get_event_idx(struct mdp_dev *mdp, enum mdp_comp_event event) +{ + int i = 0; + + for (i = 0; i < mdp->mdp_data->event_len; i++) { + if (event == mdp->mdp_data->event[i]) + return i; + } + + return -ENODEV; +} + static int mdp_path_subfrm_require(struct mdp_path_subfrm *subfrm, const struct mdp_path *path, struct mmsys_cmdq_cmd *cmd, u32 count) { const struct img_config *config = path->config; const struct mdp_comp_ctx *ctx; + const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data; struct device *dev = &path->mdp_dev->pdev->dev; struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex; s32 mutex_id = -1; - int index; + u32 mutex_sof = 0; + int index, j; + enum mtk_mdp_comp_id mtk_comp_id = MDP_COMP_NONE; /* Default value */ memset(subfrm, 0, sizeof(*subfrm)); @@ -60,62 +87,54 @@ static int mdp_path_subfrm_require(struct mdp_path_subfrm *subfrm, ctx = &path->comps[index]; if (is_output_disable(ctx->param, count)) continue; - switch (ctx->comp->id) { - /********************************************** - * Name MSB LSB - * DISP_MUTEX_MOD 23 0 - * - * Specifies which modules are in this mutex. - * Every bit denotes a module. Bit definition: - * 2 mdp_rdma0 - * 4 mdp_rsz0 - * 5 mdp_rsz1 - * 6 mdp_tdshp - * 7 mdp_wrot0 - * 8 mdp_wdma - * 13 mdp_color - * 23 mdp_aal - * 24 mdp_ccorr - **********************************************/ + + mtk_comp_id = data->comp_data[ctx->comp->id].match.public_id; + switch (mtk_comp_id) { case MDP_COMP_AAL0: - subfrm->mutex_mod |= 1 << 23; + subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; break; case MDP_COMP_CCORR0: - subfrm->mutex_mod |= 1 << 24; + subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; break; case MDP_COMP_WDMA: - subfrm->mutex_mod |= 1 << 8; + subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WDMA; break; case MDP_COMP_WROT0: - subfrm->mutex_mod |= 1 << 7; + subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WROT0; break; case MDP_COMP_TDSHP0: - subfrm->mutex_mod |= 1 << 6; + subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_TDSHP0; break; case MDP_COMP_RSZ1: - subfrm->mutex_mod |= 1 << 5; + subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RSZ1; break; case MDP_COMP_RSZ0: - subfrm->mutex_mod |= 1 << 4; + subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RSZ0; break; case MDP_COMP_RDMA0: - mutex_id = MDP_PIPE_RDMA0; - subfrm->mutex_mod |= 1 << 2; + j = mdp_get_mutex_idx(data, MDP_PIPE_RDMA0); + mutex_id = data->pipe_info[j].mutex_id; + subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RDMA0; break; case MDP_COMP_ISP_IMGI: - mutex_id = MDP_PIPE_IMGI; + j = mdp_get_mutex_idx(data, MDP_PIPE_IMGI); + mutex_id = data->pipe_info[j].mutex_id; break; case MDP_COMP_WPEI: - mutex_id = MDP_PIPE_WPEI; + j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI); + mutex_id = data->pipe_info[j].mutex_id; + subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; break; case MDP_COMP_WPEI2: - mutex_id = MDP_PIPE_WPEI2; + j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI2); + mutex_id = data->pipe_info[j].mutex_id; + subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; break; default: break; @@ -129,8 +148,10 @@ static int mdp_path_subfrm_require(struct mdp_path_subfrm *subfrm, } /* Set mutex modules */ - if (subfrm->mutex_mod) - mtk_mutex_add_mdp_mod(mutex[mutex_id], subfrm->mutex_mod, cmd); + if (subfrm->mutex_mod) { + mtk_mutex_add_mdp_mod(mutex[mutex_id], subfrm->mutex_mod, + 0, mutex_sof, cmd); + } return 0; } @@ -149,33 +170,36 @@ static int mdp_path_subfrm_run(const struct mdp_path_subfrm *subfrm, } if (subfrm->mutex_mod) { - int index; + int index, evt; /* Wait WROT SRAM shared to DISP RDMA */ /* Clear SOF event for each engine */ for (index = 0; index < subfrm->num_sofs; index++) { switch (subfrm->sofs[index]) { case MDP_COMP_RDMA0: - MM_REG_CLEAR(cmd, RDMA0_SOF); + evt = mdp_get_event_idx(path->mdp_dev, RDMA0_SOF); break; case MDP_COMP_TDSHP0: - MM_REG_CLEAR(cmd, TDSHP0_SOF); + evt = mdp_get_event_idx(path->mdp_dev, TDSHP0_SOF); break; case MDP_COMP_RSZ0: - MM_REG_CLEAR(cmd, RSZ0_SOF); + evt = mdp_get_event_idx(path->mdp_dev, RSZ0_SOF); break; case MDP_COMP_RSZ1: - MM_REG_CLEAR(cmd, RSZ1_SOF); + evt = mdp_get_event_idx(path->mdp_dev, RSZ1_SOF); break; case MDP_COMP_WDMA: - MM_REG_CLEAR(cmd, WDMA0_SOF); + evt = mdp_get_event_idx(path->mdp_dev, WDMA0_SOF); break; case MDP_COMP_WROT0: - MM_REG_CLEAR(cmd, WROT0_SOF); + evt = mdp_get_event_idx(path->mdp_dev, WROT0_SOF); break; default: + evt = -1; break; } + if (evt > 0) + MM_REG_CLEAR(cmd, evt); } /* Enable the mutex */ @@ -185,26 +209,29 @@ static int mdp_path_subfrm_run(const struct mdp_path_subfrm *subfrm, for (index = 0; index < subfrm->num_sofs; index++) { switch (subfrm->sofs[index]) { case MDP_COMP_RDMA0: - MM_REG_WAIT(cmd, RDMA0_SOF); + evt = mdp_get_event_idx(path->mdp_dev, RDMA0_SOF); break; case MDP_COMP_TDSHP0: - MM_REG_WAIT(cmd, TDSHP0_SOF); + evt = mdp_get_event_idx(path->mdp_dev, TDSHP0_SOF); break; case MDP_COMP_RSZ0: - MM_REG_WAIT(cmd, RSZ0_SOF); + evt = mdp_get_event_idx(path->mdp_dev, RSZ0_SOF); break; case MDP_COMP_RSZ1: - MM_REG_WAIT(cmd, RSZ1_SOF); + evt = mdp_get_event_idx(path->mdp_dev, RSZ1_SOF); break; case MDP_COMP_WDMA: - MM_REG_WAIT(cmd, WDMA0_SOF); + evt = mdp_get_event_idx(path->mdp_dev, WDMA0_SOF); break; case MDP_COMP_WROT0: - MM_REG_WAIT(cmd, WROT0_SOF); + evt = mdp_get_event_idx(path->mdp_dev, WROT0_SOF); break; default: + evt = -1; break; } + if (evt > 0) + MM_REG_WAIT(cmd, evt); } } return 0; @@ -235,7 +262,9 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd, struct mdp_path_subfrm subfrm; const struct img_config *config = path->config; struct device *mmsys_dev = path->mdp_dev->mdp_mmsys; + const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data; struct mdp_comp_ctx *ctx; + enum mdp_comp_id cur, next; int index, ret; /* Acquire components */ @@ -243,10 +272,14 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd, if (ret) return ret; /* Enable mux settings */ - for (index = 0; index < (config->num_components - 1); index++) + for (index = 0; index < (config->num_components - 1); index++) { + cur = path->comps[index].comp->id; + next = path->comps[index + 1].comp->id; mtk_mmsys_mdp_connect(mmsys_dev, cmd, - path->comps[index].comp->id, - path->comps[index + 1].comp->id); + data->comp_data[cur].match.public_id, + data->comp_data[next].match.public_id); + } + /* Config sub-frame information */ for (index = (config->num_components - 1); index >= 0; index--) { ctx = &path->comps[index]; @@ -277,10 +310,14 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd, return ret; } /* Disable mux settings */ - for (index = 0; index < (config->num_components - 1); index++) + for (index = 0; index < (config->num_components - 1); index++) { + cur = path->comps[index].comp->id; + next = path->comps[index + 1].comp->id; mtk_mmsys_mdp_disconnect(mmsys_dev, cmd, - path->comps[index].comp->id, - path->comps[index + 1].comp->id); + data->comp_data[cur].match.public_id, + data->comp_data[next].match.public_id); + } + return 0; } @@ -330,12 +367,14 @@ static void mdp_auto_release_work(struct work_struct *work) { struct mdp_cmdq_cb_param *cb_param; struct mdp_dev *mdp; + int i; cb_param = container_of(work, struct mdp_cmdq_cb_param, auto_release_work); mdp = cb_param->mdp; - mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]); + i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0); + mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]); mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps, cb_param->num_comps); @@ -351,6 +390,7 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data) struct mdp_cmdq_cb_param *cb_param; struct mdp_dev *mdp; struct device *dev; + int i; if (!data.data) { pr_info("%s:no callback data\n", __func__); @@ -376,7 +416,8 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data) INIT_WORK(&cb_param->auto_release_work, mdp_auto_release_work); if (!queue_work(mdp->clock_wq, &cb_param->auto_release_work)) { dev_err(dev, "%s:queue_work fail!\n", __func__); - mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]); + i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0); + mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]); mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps, cb_param->num_comps); @@ -430,7 +471,9 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) goto err_destroy_pkt; } - mtk_mutex_prepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]); + i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0); + mtk_mutex_prepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]); + for (i = 0; i < param->config->num_components; i++) mdp_comp_clock_on(&mdp->pdev->dev, path.comps[i].comp); @@ -475,7 +518,8 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) return 0; err_clock_off: - mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]); + i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0); + mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]); mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps, cb_param->num_comps); err_destroy_pkt: diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c index 27c70289cc90..f690502ee42b 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c @@ -19,6 +19,38 @@ #include "mdp_reg_wdma.h" #include "mdp_reg_isp.h" +static struct mdp_comp_list comp_list; + +enum mdp_comp_id get_comp_camin(void) +{ + return comp_list.camin; +} + +enum mdp_comp_id get_comp_camin2(void) +{ + return comp_list.camin2; +} + +enum mdp_comp_id get_comp_rdma0(void) +{ + return comp_list.rdma0; +} + +enum mdp_comp_id get_comp_rsz1(void) +{ + return comp_list.rsz1; +} + +enum mdp_comp_id get_comp_merge2(void) +{ + return comp_list.merge2; +} + +enum mdp_comp_id get_comp_merge3(void) +{ + return comp_list.merge3; +} + static const struct mdp_platform_config *__get_plat_cfg(const struct mdp_comp_ctx *ctx) { if (!ctx) @@ -32,8 +64,8 @@ static s64 get_comp_flag(const struct mdp_comp_ctx *ctx) const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); if (mdp_cfg && mdp_cfg->rdma_rsz1_sram_sharing) - if (ctx->comp->id == MDP_COMP_RDMA0) - return (1 << MDP_COMP_RDMA0) | (1 << MDP_COMP_RSZ1); + if (ctx->comp->id == MDP_RDMA0) + return (1 << MDP_RDMA0) | (1 << MDP_RSZ1); return 1 << ctx->comp->id; } @@ -45,10 +77,10 @@ static int init_rdma(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) u8 subsys_id = ctx->comp->subsys_id; if (mdp_cfg && mdp_cfg->rdma_support_10bit) { - struct mdp_comp *prz1 = ctx->comp->mdp_dev->comp[MDP_COMP_RSZ1]; + struct mdp_comp *prz1 = ctx->comp->mdp_dev->comp[MDP_RSZ1]; /* Disable RSZ1 */ - if (ctx->comp->id == MDP_COMP_RDMA0 && prz1) + if (ctx->comp->id == MDP_RDMA0 && prz1) MM_REG_WRITE(cmd, subsys_id, prz1->reg_base, PRZ_ENABLE, 0x00000000, 0x00000001); } @@ -197,12 +229,15 @@ static int wait_rdma_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) { phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + int evt = -1; if (ctx->comp->alias_id == 0) - MM_REG_WAIT(cmd, RDMA0_DONE); + evt = mdp_get_event_idx(ctx->comp->mdp_dev, RDMA0_DONE); else pr_err("Do not support RDMA1_DONE event\n"); + if (evt > 0) + MM_REG_WAIT(cmd, evt); /* Disable RDMA */ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, 0x00000000, 0x00000001); @@ -438,12 +473,16 @@ static int wait_wrot_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + int evt = -1; if (ctx->comp->alias_id == 0) - MM_REG_WAIT(cmd, WROT0_DONE); + evt = mdp_get_event_idx(ctx->comp->mdp_dev, WROT0_DONE); else pr_err("Do not support WROT1_DONE event\n"); + if (evt > 0) + MM_REG_WAIT(cmd, evt); + if (mdp_cfg && mdp_cfg->wrot_filter_constraint) MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 0, 0x00000077); @@ -549,8 +588,11 @@ static int wait_wdma_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) { phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + int evt; - MM_REG_WAIT(cmd, WDMA0_DONE); + evt = mdp_get_event_idx(ctx->comp->mdp_dev, WDMA0_DONE); + if (evt > 0) + MM_REG_WAIT(cmd, evt); /* Disable WDMA */ MM_REG_WRITE(cmd, subsys_id, base, WDMA_EN, 0x00, 0x00000001); return 0; @@ -619,13 +661,13 @@ static int init_isp(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) const struct isp_data *isp = &ctx->param->isp; /* Direct link */ - if (isp->dl_flags & (1 << MDP_COMP_CAMIN)) { - dev_info(dev, "SW_RST ASYNC"); + if (isp->dl_flags & (1 << MDP_CAMIN)) { + dev_err(dev, "SW_RST ASYNC"); mtk_mmsys_mdp_isp_ctrl(dev, cmd, MDP_COMP_CAMIN); } - if (isp->dl_flags & (1 << MDP_COMP_CAMIN2)) { - dev_info(dev, "SW_RST ASYNC2"); + if (isp->dl_flags & (1 << MDP_CAMIN2)) { + dev_err(dev, "SW_RST ASYNC2"); mtk_mmsys_mdp_isp_ctrl(dev, cmd, MDP_COMP_CAMIN2); } @@ -736,13 +778,14 @@ static int wait_isp_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) struct device *dev = &ctx->comp->mdp_dev->pdev->dev; phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + int evt; /* MDP_DL_SEL: select MDP_CROP */ - if (isp->dl_flags & (1 << MDP_COMP_CAMIN)) + if (isp->dl_flags & (1 << MDP_CAMIN)) MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x0030, 0x00000000, 0x00000200); /* MDP2_DL_SEL: select MDP_CROP2 */ - if (isp->dl_flags & (1 << MDP_COMP_CAMIN2)) + if (isp->dl_flags & (1 << MDP_CAMIN2)) MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x0030, 0x00000000, 0x00000C00); @@ -750,68 +793,70 @@ static int wait_isp_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) case ISP_DRV_DIP_CQ_THRE0: MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0001, 0x00000001); - MM_REG_WAIT(cmd, ISP_P2_0_DONE); + evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_0_DONE); break; case ISP_DRV_DIP_CQ_THRE1: MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0002, 0x00000002); - MM_REG_WAIT(cmd, ISP_P2_1_DONE); + evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_1_DONE); break; case ISP_DRV_DIP_CQ_THRE2: MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0004, 0x00000004); - MM_REG_WAIT(cmd, ISP_P2_2_DONE); + evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_2_DONE); break; case ISP_DRV_DIP_CQ_THRE3: MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0008, 0x00000008); - MM_REG_WAIT(cmd, ISP_P2_3_DONE); + evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_3_DONE); break; case ISP_DRV_DIP_CQ_THRE4: MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0010, 0x00000010); - MM_REG_WAIT(cmd, ISP_P2_4_DONE); + evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_4_DONE); break; case ISP_DRV_DIP_CQ_THRE5: MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0020, 0x00000020); - MM_REG_WAIT(cmd, ISP_P2_5_DONE); + evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_5_DONE); break; case ISP_DRV_DIP_CQ_THRE6: MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0040, 0x00000040); - MM_REG_WAIT(cmd, ISP_P2_6_DONE); + evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_6_DONE); break; case ISP_DRV_DIP_CQ_THRE7: MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0080, 0x00000080); - MM_REG_WAIT(cmd, ISP_P2_7_DONE); + evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_7_DONE); break; case ISP_DRV_DIP_CQ_THRE8: MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0100, 0x00000100); - MM_REG_WAIT(cmd, ISP_P2_8_DONE); + evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_8_DONE); break; case ISP_DRV_DIP_CQ_THRE9: MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0200, 0x00000200); - MM_REG_WAIT(cmd, ISP_P2_9_DONE); + evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_9_DONE); break; case ISP_DRV_DIP_CQ_THRE10: MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0400, 0x00000400); - MM_REG_WAIT(cmd, ISP_P2_10_DONE); + evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_10_DONE); break; case ISP_DRV_DIP_CQ_THRE11: MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0800, 0x00000800); - MM_REG_WAIT(cmd, ISP_P2_11_DONE); + evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_11_DONE); break; default: dev_err(dev, "Do not support this cq (%d)", isp->cq_idx); return -EINVAL; } + MM_REG_WAIT(cmd, evt); + return 0; } @@ -874,32 +919,6 @@ static const struct mdp_comp_ops *mdp_comp_ops[MDP_COMP_TYPE_COUNT] = { [MDP_COMP_TYPE_DL_PATH2] = &camin_ops, }; -struct mdp_comp_match { - enum mdp_comp_type type; - u32 alias_id; -}; - -static const struct mdp_comp_match mdp_comp_matches[MDP_MAX_COMP_COUNT] = { - [MDP_COMP_WPEI] = { MDP_COMP_TYPE_WPEI, 0 }, - [MDP_COMP_WPEO] = { MDP_COMP_TYPE_EXTO, 2 }, - [MDP_COMP_WPEI2] = { MDP_COMP_TYPE_WPEI, 1 }, - [MDP_COMP_WPEO2] = { MDP_COMP_TYPE_EXTO, 3 }, - [MDP_COMP_ISP_IMGI] = { MDP_COMP_TYPE_IMGI, 0 }, - [MDP_COMP_ISP_IMGO] = { MDP_COMP_TYPE_EXTO, 0 }, - [MDP_COMP_ISP_IMG2O] = { MDP_COMP_TYPE_EXTO, 1 }, - - [MDP_COMP_CAMIN] = { MDP_COMP_TYPE_DL_PATH1, 0 }, - [MDP_COMP_CAMIN2] = { MDP_COMP_TYPE_DL_PATH2, 1 }, - [MDP_COMP_RDMA0] = { MDP_COMP_TYPE_RDMA, 0 }, - [MDP_COMP_CCORR0] = { MDP_COMP_TYPE_CCORR, 0 }, - [MDP_COMP_RSZ0] = { MDP_COMP_TYPE_RSZ, 0 }, - [MDP_COMP_RSZ1] = { MDP_COMP_TYPE_RSZ, 1 }, - [MDP_COMP_PATH0_SOUT] = { MDP_COMP_TYPE_PATH1, 0 }, - [MDP_COMP_PATH1_SOUT] = { MDP_COMP_TYPE_PATH2, 1 }, - [MDP_COMP_WROT0] = { MDP_COMP_TYPE_WROT, 0 }, - [MDP_COMP_WDMA] = { MDP_COMP_TYPE_WDMA, 0 }, -}; - static const struct of_device_id mdp_comp_dt_ids[] = { { .compatible = "mediatek,mt8183-mdp3-rdma", @@ -943,34 +962,13 @@ static const struct of_device_id mdp_sub_comp_dt_ids[] = { {} }; -/* Used to describe the item order in MDP property */ -struct mdp_comp_info { - u32 clk_num; - u32 clk_ofst; - u32 dts_reg_ofst; -}; - -static const struct mdp_comp_info mdp_comp_dt_info[MDP_COMP_TYPE_COUNT] = { - [MDP_COMP_TYPE_RDMA] = {2, 0, 0}, - [MDP_COMP_TYPE_RSZ] = {1, 0, 0}, - [MDP_COMP_TYPE_WROT] = {1, 0, 0}, - [MDP_COMP_TYPE_WDMA] = {1, 0, 0}, - [MDP_COMP_TYPE_PATH1] = {0, 0, 2}, - [MDP_COMP_TYPE_PATH2] = {0, 0, 3}, - [MDP_COMP_TYPE_CCORR] = {1, 0, 0}, - [MDP_COMP_TYPE_IMGI] = {0, 0, 4}, - [MDP_COMP_TYPE_EXTO] = {0, 0, 4}, - [MDP_COMP_TYPE_DL_PATH1] = {2, 2, 1}, - [MDP_COMP_TYPE_DL_PATH2] = {2, 4, 1}, -}; - -static int mdp_comp_get_id(enum mdp_comp_type type, u32 alias_id) +static int mdp_comp_get_id(struct mdp_dev *mdp, enum mdp_comp_type type, u32 alias_id) { int i; - for (i = 0; i < ARRAY_SIZE(mdp_comp_matches); i++) - if (mdp_comp_matches[i].type == type && - mdp_comp_matches[i].alias_id == alias_id) + for (i = 0; i < mdp->mdp_data->comp_data_len; i++) + if (mdp->mdp_data->comp_data[i].match.type == type && + mdp->mdp_data->comp_data[i].match.alias_id == alias_id) return i; return -ENODEV; } @@ -1028,7 +1026,7 @@ void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num) mdp_comp_clock_off(dev, &comps[i]); } -static int mdp_get_subsys_id(struct device *dev, struct device_node *node, +static int mdp_get_subsys_id(struct mdp_dev *mdp, struct device *dev, struct device_node *node, struct mdp_comp *comp) { struct platform_device *comp_pdev; @@ -1047,7 +1045,7 @@ static int mdp_get_subsys_id(struct device *dev, struct device_node *node, return -ENODEV; } - index = mdp_comp_dt_info[comp->type].dts_reg_ofst; + index = mdp->mdp_data->comp_info[comp->type].dts_reg_ofst; ret = cmdq_dev_get_client_reg(&comp_pdev->dev, &cmdq_reg, index); if (ret != 0) { dev_err(&comp_pdev->dev, "cmdq_dev_get_subsys fail!\n"); @@ -1065,7 +1063,7 @@ static void __mdp_comp_init(struct mdp_dev *mdp, struct device_node *node, { struct resource res; phys_addr_t base; - int index = mdp_comp_dt_info[comp->type].dts_reg_ofst; + int index = mdp->mdp_data->comp_info[comp->type].dts_reg_ofst; if (of_address_to_resource(node, index, &res) < 0) base = 0L; @@ -1078,7 +1076,7 @@ static void __mdp_comp_init(struct mdp_dev *mdp, struct device_node *node, } static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node, - struct mdp_comp *comp, enum mtk_mdp_comp_id id) + struct mdp_comp *comp, enum mdp_comp_id id) { struct device *dev = &mdp->pdev->dev; int clk_num; @@ -1090,14 +1088,14 @@ static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node, return -EINVAL; } - comp->type = mdp_comp_matches[id].type; + comp->type = mdp->mdp_data->comp_data[id].match.type; comp->id = id; - comp->alias_id = mdp_comp_matches[id].alias_id; + comp->alias_id = mdp->mdp_data->comp_data[id].match.alias_id; comp->ops = mdp_comp_ops[comp->type]; __mdp_comp_init(mdp, node, comp); - clk_num = mdp_comp_dt_info[comp->type].clk_num; - clk_ofst = mdp_comp_dt_info[comp->type].clk_ofst; + clk_num = mdp->mdp_data->comp_info[comp->type].clk_num; + clk_ofst = mdp->mdp_data->comp_info[comp->type].clk_ofst; for (i = 0; i < clk_num; i++) { comp->clks[i] = of_clk_get(node, i + clk_ofst); @@ -1105,14 +1103,14 @@ static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node, break; } - mdp_get_subsys_id(dev, node, comp); + mdp_get_subsys_id(mdp, dev, node, comp); return 0; } static struct mdp_comp *mdp_comp_create(struct mdp_dev *mdp, struct device_node *node, - enum mtk_mdp_comp_id id) + enum mdp_comp_id id) { struct device *dev = &mdp->pdev->dev; struct mdp_comp *comp; @@ -1148,7 +1146,7 @@ static int mdp_sub_comps_create(struct mdp_dev *mdp, struct device_node *node) of_property_for_each_string(node, "mdp3-comps", prop, name) { const struct of_device_id *matches = mdp_sub_comp_dt_ids; - enum mdp_comp_type type = MDP_COMP_NONE; + enum mdp_comp_type type = MDP_COMP_INVALID; u32 alias_id; int id, ret; struct mdp_comp *comp; @@ -1168,7 +1166,7 @@ static int mdp_sub_comps_create(struct mdp_dev *mdp, struct device_node *node) return ret; } - id = mdp_comp_get_id(type, alias_id); + id = mdp_comp_get_id(mdp, type, alias_id); if (id < 0) { dev_err(dev, "Failed to get comp id: %s (%d, %d)\n", name, type, alias_id); @@ -1197,8 +1195,8 @@ void mdp_component_deinit(struct mdp_dev *mdp) { int i; - for (i = 0; i < MDP_PIPE_MAX; i++) - mtk_mutex_put(mdp->mdp_mutex[i]); + for (i = 0; i < mdp->mdp_data->pipe_info_len; i++) + mtk_mutex_put(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].pipe_id]); for (i = 0; i < ARRAY_SIZE(mdp->comp); i++) { if (mdp->comp[i]) { @@ -1216,6 +1214,7 @@ int mdp_component_init(struct mdp_dev *mdp) u32 alias_id; int i, ret; + memcpy(&comp_list, mdp->mdp_data->comp_list, sizeof(struct mdp_comp_list)); parent = dev->of_node->parent; /* Iterate over sibling MDP function blocks */ for_each_child_of_node(parent, node) { @@ -1241,7 +1240,7 @@ int mdp_component_init(struct mdp_dev *mdp) node); continue; } - id = mdp_comp_get_id(type, alias_id); + id = mdp_comp_get_id(mdp, type, alias_id); if (id < 0) { dev_err(dev, "Fail to get component id: type %d alias %d\n", diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h index 7b34f9c42410..02957abd12d0 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h @@ -38,31 +38,94 @@ (((mask) & (ofst##_MASK)) == (ofst##_MASK)) ? \ (0xffffffff) : (mask), ##__VA_ARGS__) +#define MDP_CAMIN get_comp_camin() +#define MDP_CAMIN2 get_comp_camin2() +#define MDP_RDMA0 get_comp_rdma0() +#define MDP_RSZ1 get_comp_rsz1() +#define MDP_MERGE2 get_comp_merge2() +#define MDP_MERGE3 get_comp_merge3() + enum mdp_comp_type { MDP_COMP_TYPE_INVALID = 0, + MDP_COMP_TYPE_IMGI, + MDP_COMP_TYPE_WPEI, + MDP_COMP_TYPE_RDMA, MDP_COMP_TYPE_RSZ, MDP_COMP_TYPE_WROT, MDP_COMP_TYPE_WDMA, MDP_COMP_TYPE_PATH1, MDP_COMP_TYPE_PATH2, + MDP_COMP_TYPE_SPLIT, + MDP_COMP_TYPE_STITCH, + MDP_COMP_TYPE_FG, + MDP_COMP_TYPE_OVL, + MDP_COMP_TYPE_PAD, + MDP_COMP_TYPE_MERGE, MDP_COMP_TYPE_TDSHP, MDP_COMP_TYPE_COLOR, MDP_COMP_TYPE_DRE, MDP_COMP_TYPE_CCORR, MDP_COMP_TYPE_HDR, + MDP_COMP_TYPE_AAL, + MDP_COMP_TYPE_TCC, - MDP_COMP_TYPE_IMGI, - MDP_COMP_TYPE_WPEI, MDP_COMP_TYPE_EXTO, /* External path */ MDP_COMP_TYPE_DL_PATH1, /* Direct-link path1 */ MDP_COMP_TYPE_DL_PATH2, /* Direct-link path2 */ + MDP_COMP_TYPE_DL_PATH3, /* Direct-link path3 */ + MDP_COMP_TYPE_DL_PATH4, /* Direct-link path4 */ + MDP_COMP_TYPE_DL_PATH5, /* Direct-link path5 */ + MDP_COMP_TYPE_DL_PATH6, /* Direct-link path6 */ + MDP_COMP_TYPE_DUMMY, MDP_COMP_TYPE_COUNT /* ALWAYS keep at the end */ }; +enum mdp_comp_id { + MDP_COMP_INVALID = -1, /* Invalid engine */ + + /* MT8183 Comp id */ + /* ISP */ + MT8183_MDP_COMP_WPEI = 0, + MT8183_MDP_COMP_WPEO, /* 1 */ + MT8183_MDP_COMP_WPEI2, /* 2 */ + MT8183_MDP_COMP_WPEO2, /* 3 */ + MT8183_MDP_COMP_ISP_IMGI, /* 4 */ + MT8183_MDP_COMP_ISP_IMGO, /* 5 */ + MT8183_MDP_COMP_ISP_IMG2O, /* 6 */ + + /* IPU */ + MT8183_MDP_COMP_IPUI, /* 7 */ + MT8183_MDP_COMP_IPUO, /* 8 */ + + /* MDP */ + MT8183_MDP_COMP_CAMIN, /* 9 */ + MT8183_MDP_COMP_CAMIN2, /* 10 */ + MT8183_MDP_COMP_RDMA0, /* 11 */ + MT8183_MDP_COMP_AAL0, /* 12 */ + MT8183_MDP_COMP_CCORR0, /* 13 */ + MT8183_MDP_COMP_RSZ0, /* 14 */ + MT8183_MDP_COMP_RSZ1, /* 15 */ + MT8183_MDP_COMP_TDSHP0, /* 16 */ + MT8183_MDP_COMP_COLOR0, /* 17 */ + MT8183_MDP_COMP_PATH0_SOUT, /* 18 */ + MT8183_MDP_COMP_PATH1_SOUT, /* 19 */ + MT8183_MDP_COMP_WROT0, /* 20 */ + MT8183_MDP_COMP_WDMA, /* 21 */ + + /* Dummy Engine */ + MT8183_MDP_COMP_RDMA1, /* 22 */ + MT8183_MDP_COMP_RSZ2, /* 23 */ + MT8183_MDP_COMP_TDSHP1, /* 24 */ + MT8183_MDP_COMP_WROT1, /* 25 */ + MT8183_MDP_MAX_COMP_COUNT, + + MDP_MAX_COMP /* ALWAYS keep at the end */ +}; + enum mdp_comp_event { RDMA0_SOF, RDMA0_DONE, @@ -73,6 +136,18 @@ enum mdp_comp_event { WROT0_DONE, WDMA0_SOF, WDMA0_DONE, + RDMA1_SOF, + RDMA2_SOF, + RDMA3_SOF, + WROT1_SOF, + WROT2_SOF, + WROT3_SOF, + RDMA1_FRAME_DONE, + RDMA2_FRAME_DONE, + RDMA3_FRAME_DONE, + WROT1_FRAME_DONE, + WROT2_FRAME_DONE, + WROT3_FRAME_DONE, ISP_P2_0_DONE, ISP_P2_1_DONE, @@ -96,6 +171,104 @@ enum mdp_comp_event { MDP_MAX_EVENT_COUNT /* ALWAYS keep at the end */ }; +enum mdp_mmsys_config_id { + CONFIG_VPP0_HW_DCM_1ST_DIS0, + CONFIG_VPP0_DL_IRELAY_WR, + CONFIG_VPP1_HW_DCM_1ST_DIS0, + CONFIG_VPP1_HW_DCM_1ST_DIS1, + CONFIG_VPP1_HW_DCM_2ND_DIS0, + CONFIG_VPP1_HW_DCM_2ND_DIS1, + CONFIG_SVPP2_BUF_BF_RSZ_SWITCH, + CONFIG_SVPP3_BUF_BF_RSZ_SWITCH, + MDP_MAX_CONFIG_COUNT +}; + +struct mdp_comp_list { + enum mdp_comp_id wpei; + enum mdp_comp_id wpeo; + enum mdp_comp_id wpei2; + enum mdp_comp_id wpeo2; + enum mdp_comp_id camin; + enum mdp_comp_id camin2; + enum mdp_comp_id split; + enum mdp_comp_id split2; + enum mdp_comp_id rdma0; + enum mdp_comp_id rdma1; + enum mdp_comp_id rdma2; + enum mdp_comp_id rdma3; + enum mdp_comp_id stitch; + enum mdp_comp_id fg0; + enum mdp_comp_id fg1; + enum mdp_comp_id fg2; + enum mdp_comp_id fg3; + enum mdp_comp_id hdr0; + enum mdp_comp_id hdr1; + enum mdp_comp_id hdr2; + enum mdp_comp_id hdr3; + enum mdp_comp_id aal0; + enum mdp_comp_id aal1; + enum mdp_comp_id aal2; + enum mdp_comp_id aal3; + enum mdp_comp_id rsz0; + enum mdp_comp_id rsz1; + enum mdp_comp_id rsz2; + enum mdp_comp_id rsz3; + enum mdp_comp_id tdshp0; + enum mdp_comp_id tdshp1; + enum mdp_comp_id tdshp2; + enum mdp_comp_id tdshp3; + enum mdp_comp_id color0; + enum mdp_comp_id color1; + enum mdp_comp_id color2; + enum mdp_comp_id color3; + enum mdp_comp_id ccorr0; + enum mdp_comp_id ovl0; + enum mdp_comp_id ovl1; + enum mdp_comp_id pad0; + enum mdp_comp_id pad1; + enum mdp_comp_id pad2; + enum mdp_comp_id pad3; + enum mdp_comp_id tcc0; + enum mdp_comp_id tcc1; + enum mdp_comp_id wrot0; + enum mdp_comp_id wrot1; + enum mdp_comp_id wrot2; + enum mdp_comp_id wrot3; + enum mdp_comp_id merge2; + enum mdp_comp_id merge3; + enum mdp_comp_id wdma; + enum mdp_comp_id vdo0dl0; + enum mdp_comp_id vdo1dl0; + enum mdp_comp_id vdo0dl1; + enum mdp_comp_id vdo1dl1; + enum mdp_comp_id path0_sout; + enum mdp_comp_id path1_sout; +}; + +struct mdp_comp_match { + enum mdp_comp_type type; + u32 alias_id; + enum mtk_mdp_comp_id public_id; +}; + +struct mdp_mutex_info { + u32 mmsys_id; + u32 mod; + u32 mod2; +}; + +struct mdp_comp_data { + struct mdp_comp_match match; + struct mdp_mutex_info mutex; +}; + +/* Used to describe the item order in MDP property */ +struct mdp_comp_info { + u32 clk_num; + u32 clk_ofst; + u32 dts_reg_ofst; +}; + struct mdp_comp_ops; struct mdp_comp { @@ -106,7 +279,7 @@ struct mdp_comp { struct clk *clks[6]; struct device *comp_dev; enum mdp_comp_type type; - enum mtk_mdp_comp_id id; + enum mdp_comp_id id; u32 alias_id; const struct mdp_comp_ops *ops; }; @@ -134,6 +307,18 @@ struct mdp_comp_ops { struct mdp_dev; +enum mdp_comp_id get_comp_camin(void); +enum mdp_comp_id get_comp_camin2(void); +enum mdp_comp_id get_comp_rdma0(void); +enum mdp_comp_id get_comp_aal0(void); +enum mdp_comp_id get_comp_ccorr0(void); +enum mdp_comp_id get_comp_rsz0(void); +enum mdp_comp_id get_comp_rsz1(void); +enum mdp_comp_id get_comp_tdshp0(void); +enum mdp_comp_id get_comp_color0(void); +enum mdp_comp_id get_comp_wrot0(void); +enum mdp_comp_id get_comp_wdma(void); + int mdp_component_init(struct mdp_dev *mdp); void mdp_component_deinit(struct mdp_dev *mdp); void mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp); @@ -144,4 +329,6 @@ int mdp_comp_ctx_init(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx, const struct img_compparam *param, const struct img_ipi_frameparam *frame); +int mdp_get_event_idx(struct mdp_dev *mdp, enum mdp_comp_event event); + #endif /* __MTK_MDP3_COMP_H__ */ diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c index 8459b0afa84c..4f7d8bc1bf24 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c @@ -26,8 +26,375 @@ static const struct mdp_platform_config mt8183_plat_cfg = { .gce_event_offset = 0, }; +static const struct mdp_comp_list mt8183_comp_list = { + .wpei = MT8183_MDP_COMP_WPEI, + .wpeo = MT8183_MDP_COMP_WPEO, + .wpei2 = MT8183_MDP_COMP_WPEI2, + .wpeo2 = MT8183_MDP_COMP_WPEO2, + .camin = MT8183_MDP_COMP_CAMIN, + .camin2 = MT8183_MDP_COMP_CAMIN2, + .split = MDP_COMP_INVALID, + .split2 = MDP_COMP_INVALID, + .rdma0 = MT8183_MDP_COMP_RDMA0, + .rdma1 = MDP_COMP_INVALID, + .rdma2 = MDP_COMP_INVALID, + .rdma3 = MDP_COMP_INVALID, + .stitch = MDP_COMP_INVALID, + .fg0 = MDP_COMP_INVALID, + .fg1 = MDP_COMP_INVALID, + .fg2 = MDP_COMP_INVALID, + .fg3 = MDP_COMP_INVALID, + .hdr0 = MDP_COMP_INVALID, + .hdr1 = MDP_COMP_INVALID, + .hdr2 = MDP_COMP_INVALID, + .hdr3 = MDP_COMP_INVALID, + .aal0 = MT8183_MDP_COMP_AAL0, + .aal1 = MDP_COMP_INVALID, + .aal2 = MDP_COMP_INVALID, + .aal3 = MDP_COMP_INVALID, + .rsz0 = MT8183_MDP_COMP_RSZ0, + .rsz1 = MT8183_MDP_COMP_RSZ1, + .rsz2 = MDP_COMP_INVALID, + .rsz3 = MDP_COMP_INVALID, + .tdshp0 = MT8183_MDP_COMP_TDSHP0, + .tdshp1 = MDP_COMP_INVALID, + .tdshp2 = MDP_COMP_INVALID, + .tdshp3 = MDP_COMP_INVALID, + .color0 = MT8183_MDP_COMP_COLOR0, + .color1 = MDP_COMP_INVALID, + .color2 = MDP_COMP_INVALID, + .color3 = MDP_COMP_INVALID, + .ccorr0 = MT8183_MDP_COMP_CCORR0, + .ovl0 = MDP_COMP_INVALID, + .ovl1 = MDP_COMP_INVALID, + .pad0 = MDP_COMP_INVALID, + .pad1 = MDP_COMP_INVALID, + .pad2 = MDP_COMP_INVALID, + .pad3 = MDP_COMP_INVALID, + .tcc0 = MDP_COMP_INVALID, + .tcc1 = MDP_COMP_INVALID, + .wrot0 = MT8183_MDP_COMP_WROT0, + .wrot1 = MDP_COMP_INVALID, + .wrot2 = MDP_COMP_INVALID, + .wrot3 = MDP_COMP_INVALID, + .merge2 = MDP_COMP_INVALID, + .merge3 = MDP_COMP_INVALID, + .wdma = MT8183_MDP_COMP_WDMA, + .vdo0dl0 = MDP_COMP_INVALID, + .vdo1dl0 = MDP_COMP_INVALID, + .vdo0dl1 = MDP_COMP_INVALID, + .vdo1dl1 = MDP_COMP_INVALID, + .path0_sout = MT8183_MDP_COMP_PATH0_SOUT, + .path1_sout = MT8183_MDP_COMP_PATH1_SOUT, +}; + +static const struct mdp_comp_data mt8183_mdp_comp_data[MT8183_MDP_MAX_COMP_COUNT] = { + [MT8183_MDP_COMP_WPEI] = { {MDP_COMP_TYPE_WPEI, 0, MDP_COMP_WPEI}, {0, 0, 0} }, + [MT8183_MDP_COMP_WPEO] = { {MDP_COMP_TYPE_EXTO, 2, MDP_COMP_WPEO}, {0, 0, 0} }, + [MT8183_MDP_COMP_WPEI2] = { {MDP_COMP_TYPE_WPEI, 1, MDP_COMP_WPEI2}, {0, 0, 0} }, + [MT8183_MDP_COMP_WPEO2] = { {MDP_COMP_TYPE_EXTO, 3, MDP_COMP_WPEO2}, {0, 0, 0} }, + [MT8183_MDP_COMP_ISP_IMGI] = { {MDP_COMP_TYPE_IMGI, 0, MDP_COMP_ISP_IMGI}, {0, 0, 0} }, + [MT8183_MDP_COMP_ISP_IMGO] = { {MDP_COMP_TYPE_EXTO, 0, MDP_COMP_ISP_IMGO}, {0, 0, 0} }, + [MT8183_MDP_COMP_ISP_IMG2O] = { {MDP_COMP_TYPE_EXTO, 1, MDP_COMP_ISP_IMG2O}, {0, 0, 0} }, + + [MT8183_MDP_COMP_CAMIN] = { {MDP_COMP_TYPE_DL_PATH1, 0, MDP_COMP_CAMIN}, {0, 0, 0} }, + [MT8183_MDP_COMP_CAMIN2] = { {MDP_COMP_TYPE_DL_PATH2, 1, MDP_COMP_CAMIN2}, {0, 0, 0} }, + [MT8183_MDP_COMP_RDMA0] = { {MDP_COMP_TYPE_RDMA, 0, MDP_COMP_RDMA0}, {0, BIT(2), 0} }, + [MT8183_MDP_COMP_AAL0] = { {MDP_COMP_TYPE_AAL, 0, MDP_COMP_AAL0}, {0, BIT(23), 0} }, + [MT8183_MDP_COMP_CCORR0] = { {MDP_COMP_TYPE_CCORR, 0, MDP_COMP_CCORR0}, {0, BIT(24), 0} }, + [MT8183_MDP_COMP_RSZ0] = { {MDP_COMP_TYPE_RSZ, 0, MDP_COMP_RSZ0}, {0, BIT(4), 0} }, + [MT8183_MDP_COMP_RSZ1] = { {MDP_COMP_TYPE_RSZ, 1, MDP_COMP_RSZ1}, {0, BIT(5), 0} }, + [MT8183_MDP_COMP_TDSHP0] = { {MDP_COMP_TYPE_TDSHP, 0, MDP_COMP_TDSHP0}, {0, BIT(6), 0} }, + [MT8183_MDP_COMP_PATH0_SOUT] = { {MDP_COMP_TYPE_PATH1, 0, MDP_COMP_PATH0_SOUT}, {0, 0, 0} }, + [MT8183_MDP_COMP_PATH1_SOUT] = { {MDP_COMP_TYPE_PATH2, 1, MDP_COMP_PATH1_SOUT}, {0, 0, 0} }, + [MT8183_MDP_COMP_WROT0] = { {MDP_COMP_TYPE_WROT, 0, MDP_COMP_WROT0}, {0, BIT(7), 0} }, + [MT8183_MDP_COMP_WDMA] = { {MDP_COMP_TYPE_WDMA, 0, MDP_COMP_WDMA}, {0, BIT(8), 0} }, +}; + +static const enum mdp_comp_event mt8183_mdp_event[] = { + RDMA0_SOF, + RDMA0_DONE, + RSZ0_SOF, + RSZ1_SOF, + TDSHP0_SOF, + WROT0_SOF, + WROT0_DONE, + WDMA0_SOF, + WDMA0_DONE, + ISP_P2_0_DONE, + ISP_P2_1_DONE, + ISP_P2_2_DONE, + ISP_P2_3_DONE, + ISP_P2_4_DONE, + ISP_P2_5_DONE, + ISP_P2_6_DONE, + ISP_P2_7_DONE, + ISP_P2_8_DONE, + ISP_P2_9_DONE, + ISP_P2_10_DONE, + ISP_P2_11_DONE, + ISP_P2_12_DONE, + ISP_P2_13_DONE, + ISP_P2_14_DONE, + WPE_DONE, + WPE_B_DONE +}; + +static const struct mdp_comp_info mt8183_comp_dt_info[] = { + [MDP_COMP_TYPE_RDMA] = {2, 0, 0}, + [MDP_COMP_TYPE_RSZ] = {1, 0, 0}, + [MDP_COMP_TYPE_WROT] = {1, 0, 0}, + [MDP_COMP_TYPE_WDMA] = {1, 0, 0}, + [MDP_COMP_TYPE_PATH1] = {0, 0, 2}, + [MDP_COMP_TYPE_PATH2] = {0, 0, 3}, + [MDP_COMP_TYPE_CCORR] = {1, 0, 0}, + [MDP_COMP_TYPE_IMGI] = {0, 0, 2}, + [MDP_COMP_TYPE_EXTO] = {0, 0, 2}, + [MDP_COMP_TYPE_DL_PATH1] = {2, 2, 1}, + [MDP_COMP_TYPE_DL_PATH2] = {2, 4, 1}, +}; + +static const struct mdp_pipe_info mt8183_pipe_info[] = { + {MDP_PIPE_IMGI, 0, 0}, + {MDP_PIPE_RDMA0, 0, 1}, + {MDP_PIPE_WPEI, 0, 2}, + {MDP_PIPE_WPEI2, 0, 3} +}; + +static const struct mdp_format mt8183_formats[] = { + { + .pixelformat = V4L2_PIX_FMT_GREY, + .mdp_color = MDP_COLOR_GREY, + .depth = { 8 }, + .row_depth = { 8 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_RGB565X, + .mdp_color = MDP_COLOR_RGB565, + .depth = { 16 }, + .row_depth = { 16 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_RGB565, + .mdp_color = MDP_COLOR_BGR565, + .depth = { 16 }, + .row_depth = { 16 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_RGB24, + .mdp_color = MDP_COLOR_RGB888, + .depth = { 24 }, + .row_depth = { 24 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_BGR24, + .mdp_color = MDP_COLOR_BGR888, + .depth = { 24 }, + .row_depth = { 24 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_ABGR32, + .mdp_color = MDP_COLOR_BGRA8888, + .depth = { 32 }, + .row_depth = { 32 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_ARGB32, + .mdp_color = MDP_COLOR_ARGB8888, + .depth = { 32 }, + .row_depth = { 32 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_UYVY, + .mdp_color = MDP_COLOR_UYVY, + .depth = { 16 }, + .row_depth = { 16 }, + .num_planes = 1, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_VYUY, + .mdp_color = MDP_COLOR_VYUY, + .depth = { 16 }, + .row_depth = { 16 }, + .num_planes = 1, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_YUYV, + .mdp_color = MDP_COLOR_YUYV, + .depth = { 16 }, + .row_depth = { 16 }, + .num_planes = 1, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_YVYU, + .mdp_color = MDP_COLOR_YVYU, + .depth = { 16 }, + .row_depth = { 16 }, + .num_planes = 1, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_YUV420, + .mdp_color = MDP_COLOR_I420, + .depth = { 12 }, + .row_depth = { 8 }, + .num_planes = 1, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_YVU420, + .mdp_color = MDP_COLOR_YV12, + .depth = { 12 }, + .row_depth = { 8 }, + .num_planes = 1, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_NV12, + .mdp_color = MDP_COLOR_NV12, + .depth = { 12 }, + .row_depth = { 8 }, + .num_planes = 1, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_NV21, + .mdp_color = MDP_COLOR_NV21, + .depth = { 12 }, + .row_depth = { 8 }, + .num_planes = 1, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_NV16, + .mdp_color = MDP_COLOR_NV16, + .depth = { 16 }, + .row_depth = { 8 }, + .num_planes = 1, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT, + }, { + .pixelformat = V4L2_PIX_FMT_NV61, + .mdp_color = MDP_COLOR_NV61, + .depth = { 16 }, + .row_depth = { 8 }, + .num_planes = 1, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT, + }, { + .pixelformat = V4L2_PIX_FMT_NV24, + .mdp_color = MDP_COLOR_NV24, + .depth = { 24 }, + .row_depth = { 8 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT, + }, { + .pixelformat = V4L2_PIX_FMT_NV42, + .mdp_color = MDP_COLOR_NV42, + .depth = { 24 }, + .row_depth = { 8 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT, + }, { + .pixelformat = V4L2_PIX_FMT_MT21C, + .mdp_color = MDP_COLOR_420_BLKP_UFO, + .depth = { 8, 4 }, + .row_depth = { 8, 8 }, + .num_planes = 2, + .walign = 4, + .halign = 5, + .flags = MDP_FMT_FLAG_OUTPUT, + }, { + .pixelformat = V4L2_PIX_FMT_MM21, + .mdp_color = MDP_COLOR_420_BLKP, + .depth = { 8, 4 }, + .row_depth = { 8, 8 }, + .num_planes = 2, + .walign = 4, + .halign = 5, + .flags = MDP_FMT_FLAG_OUTPUT, + }, { + .pixelformat = V4L2_PIX_FMT_NV12M, + .mdp_color = MDP_COLOR_NV12, + .depth = { 8, 4 }, + .row_depth = { 8, 8 }, + .num_planes = 2, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_NV21M, + .mdp_color = MDP_COLOR_NV21, + .depth = { 8, 4 }, + .row_depth = { 8, 8 }, + .num_planes = 2, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_NV16M, + .mdp_color = MDP_COLOR_NV16, + .depth = { 8, 8 }, + .row_depth = { 8, 8 }, + .num_planes = 2, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT, + }, { + .pixelformat = V4L2_PIX_FMT_NV61M, + .mdp_color = MDP_COLOR_NV61, + .depth = { 8, 8 }, + .row_depth = { 8, 8 }, + .num_planes = 2, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT, + }, { + .pixelformat = V4L2_PIX_FMT_YUV420M, + .mdp_color = MDP_COLOR_I420, + .depth = { 8, 2, 2 }, + .row_depth = { 8, 4, 4 }, + .num_planes = 3, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_YVU420M, + .mdp_color = MDP_COLOR_YV12, + .depth = { 8, 2, 2 }, + .row_depth = { 8, 4, 4 }, + .num_planes = 3, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + } +}; + static const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { .mdp_cfg = &mt8183_plat_cfg, + .event = mt8183_mdp_event, + .event_len = ARRAY_SIZE(mt8183_mdp_event), + .comp_list = &mt8183_comp_list, + .comp_data = mt8183_mdp_comp_data, + .comp_data_len = ARRAY_SIZE(mt8183_mdp_comp_data), + .comp_info = mt8183_comp_dt_info, + .comp_info_len = ARRAY_SIZE(mt8183_comp_dt_info), + .pipe_info = mt8183_pipe_info, + .pipe_info_len = ARRAY_SIZE(mt8183_pipe_info), + .format = mt8183_formats, + .format_len = ARRAY_SIZE(mt8183_formats), }; static const struct of_device_id mdp_of_ids[] = { @@ -119,7 +486,7 @@ static int mdp_probe(struct platform_device *pdev) struct device_node *mdp_node; struct platform_device *mm_pdev; u32 i, event_ofst; - int ret; + int ret, i, mutex_id; mdp = devm_kzalloc(dev, sizeof(*mdp), GFP_KERNEL); if (!mdp) { @@ -143,7 +510,7 @@ static int mdp_probe(struct platform_device *pdev) } event_ofst = mdp->mdp_data->mdp_cfg->gce_event_offset; - for (i = RDMA0_SOF; i < MDP_MAX_EVENT_COUNT; i++) { + for (i = 0; i < mdp->mdp_data->event_len; i++) { s32 event_id; if (!dev) @@ -167,9 +534,15 @@ static int mdp_probe(struct platform_device *pdev) goto err_return; } - for (i = 0; i < MDP_PIPE_MAX; i++) { - mdp->mdp_mutex[i] = mtk_mutex_mdp_get(&mm_pdev->dev, i); - if (!mdp->mdp_mutex[i]) { + for (i = 0; i < mdp->mdp_data->pipe_info_len; i++) { + mutex_id = mdp->mdp_data->pipe_info[i].mutex_id; + if (mdp->mdp_mutex[mutex_id]) + continue; + + mdp->mdp_mutex[mutex_id] = + mtk_mutex_mdp_get(&mm_pdev->dev, mdp->mdp_data->pipe_info[i].pipe_id); + + if (!mdp->mdp_mutex[mutex_id]) { ret = -ENODEV; goto err_return; } diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h index d996d9e71356..f6d70af80b3e 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h @@ -35,6 +35,18 @@ struct mdp_platform_config { struct mtk_mdp_driver_data { const struct mdp_platform_config *mdp_cfg; + const enum mdp_comp_event *event; + unsigned int event_len; + const struct mdp_comp_list *comp_list; + const struct mdp_comp_data *comp_data; + unsigned int comp_data_len; + const struct mdp_comp_info *comp_info; + unsigned int comp_info_len; + const struct mdp_pipe_info *pipe_info; + unsigned int pipe_info_len; + const struct mdp_format *format; + unsigned int format_len; + const enum mdp_mmsys_config_id *config_table; }; struct mdp_dev { @@ -67,6 +79,13 @@ struct mdp_dev { atomic_t job_count; }; +struct mdp_pipe_info { + enum mtk_mdp_pipe_id pipe_id; + u32 mmsys_id; + u32 mutex_id; + u32 sof; +}; + int mdp_vpu_get_locked(struct mdp_dev *mdp); void mdp_vpu_put_locked(struct mdp_dev *mdp); int mdp_vpu_register(struct mdp_dev *mdp); diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c index 584804ef7bc4..0b81f8ea16a8 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c @@ -286,7 +286,9 @@ static int mdp_m2m_querycap(struct file *file, void *fh, static int mdp_m2m_enum_fmt_mplane(struct file *file, void *fh, struct v4l2_fmtdesc *f) { - return mdp_enum_fmt_mplane(f); + struct mdp_m2m_ctx *ctx = fh_to_ctx(fh); + + return mdp_enum_fmt_mplane(ctx->mdp_dev, f); } static int mdp_m2m_g_fmt_mplane(struct file *file, void *fh, @@ -323,7 +325,7 @@ static int mdp_m2m_s_fmt_mplane(struct file *file, void *fh, dev_info(dev, "[%d] type:%d", ctx->id, f->type); - fmt = mdp_try_fmt_mplane(f, &ctx->curr_param, ctx->id); + fmt = mdp_try_fmt_mplane(ctx->mdp_dev, f, &ctx->curr_param, ctx->id); if (!fmt) { dev_info(dev, "[%d] try_fmt failed, type:%d", ctx->id, f->type); return -EINVAL; @@ -370,7 +372,7 @@ static int mdp_m2m_try_fmt_mplane(struct file *file, void *fh, { struct mdp_m2m_ctx *ctx = fh_to_ctx(fh); - if (!mdp_try_fmt_mplane(f, &ctx->curr_param, ctx->id)) + if (!mdp_try_fmt_mplane(ctx->mdp_dev, f, &ctx->curr_param, ctx->id)) return -EINVAL; return 0; @@ -662,7 +664,7 @@ static int mdp_m2m_open(struct file *file) INIT_WORK(&ctx->work, mdp_m2m_worker); - ret = mdp_frameparam_init(&ctx->curr_param); + ret = mdp_frameparam_init(mdp, &ctx->curr_param); if (ret) { dev_err(dev, "Failed to initialize mdp parameter\n"); goto err_release_m2m_ctx; diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c index a6caefb097be..50fd5430a565 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c @@ -10,227 +10,6 @@ #include "mtk-mdp3-core.h" #include "mtk-mdp3-regs.h" -static const struct mdp_format mdp_formats[] = { - { - .pixelformat = V4L2_PIX_FMT_GREY, - .mdp_color = MDP_COLOR_GREY, - .depth = { 8 }, - .row_depth = { 8 }, - .num_planes = 1, - .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, - }, { - .pixelformat = V4L2_PIX_FMT_RGB565X, - .mdp_color = MDP_COLOR_RGB565, - .depth = { 16 }, - .row_depth = { 16 }, - .num_planes = 1, - .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, - }, { - .pixelformat = V4L2_PIX_FMT_RGB565, - .mdp_color = MDP_COLOR_BGR565, - .depth = { 16 }, - .row_depth = { 16 }, - .num_planes = 1, - .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, - }, { - .pixelformat = V4L2_PIX_FMT_RGB24, - .mdp_color = MDP_COLOR_RGB888, - .depth = { 24 }, - .row_depth = { 24 }, - .num_planes = 1, - .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, - }, { - .pixelformat = V4L2_PIX_FMT_BGR24, - .mdp_color = MDP_COLOR_BGR888, - .depth = { 24 }, - .row_depth = { 24 }, - .num_planes = 1, - .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, - }, { - .pixelformat = V4L2_PIX_FMT_ABGR32, - .mdp_color = MDP_COLOR_BGRA8888, - .depth = { 32 }, - .row_depth = { 32 }, - .num_planes = 1, - .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, - }, { - .pixelformat = V4L2_PIX_FMT_ARGB32, - .mdp_color = MDP_COLOR_ARGB8888, - .depth = { 32 }, - .row_depth = { 32 }, - .num_planes = 1, - .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, - }, { - .pixelformat = V4L2_PIX_FMT_UYVY, - .mdp_color = MDP_COLOR_UYVY, - .depth = { 16 }, - .row_depth = { 16 }, - .num_planes = 1, - .walign = 1, - .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, - }, { - .pixelformat = V4L2_PIX_FMT_VYUY, - .mdp_color = MDP_COLOR_VYUY, - .depth = { 16 }, - .row_depth = { 16 }, - .num_planes = 1, - .walign = 1, - .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, - }, { - .pixelformat = V4L2_PIX_FMT_YUYV, - .mdp_color = MDP_COLOR_YUYV, - .depth = { 16 }, - .row_depth = { 16 }, - .num_planes = 1, - .walign = 1, - .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, - }, { - .pixelformat = V4L2_PIX_FMT_YVYU, - .mdp_color = MDP_COLOR_YVYU, - .depth = { 16 }, - .row_depth = { 16 }, - .num_planes = 1, - .walign = 1, - .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, - }, { - .pixelformat = V4L2_PIX_FMT_YUV420, - .mdp_color = MDP_COLOR_I420, - .depth = { 12 }, - .row_depth = { 8 }, - .num_planes = 1, - .walign = 1, - .halign = 1, - .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, - }, { - .pixelformat = V4L2_PIX_FMT_YVU420, - .mdp_color = MDP_COLOR_YV12, - .depth = { 12 }, - .row_depth = { 8 }, - .num_planes = 1, - .walign = 1, - .halign = 1, - .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, - }, { - .pixelformat = V4L2_PIX_FMT_NV12, - .mdp_color = MDP_COLOR_NV12, - .depth = { 12 }, - .row_depth = { 8 }, - .num_planes = 1, - .walign = 1, - .halign = 1, - .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, - }, { - .pixelformat = V4L2_PIX_FMT_NV21, - .mdp_color = MDP_COLOR_NV21, - .depth = { 12 }, - .row_depth = { 8 }, - .num_planes = 1, - .walign = 1, - .halign = 1, - .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, - }, { - .pixelformat = V4L2_PIX_FMT_NV16, - .mdp_color = MDP_COLOR_NV16, - .depth = { 16 }, - .row_depth = { 8 }, - .num_planes = 1, - .walign = 1, - .flags = MDP_FMT_FLAG_OUTPUT, - }, { - .pixelformat = V4L2_PIX_FMT_NV61, - .mdp_color = MDP_COLOR_NV61, - .depth = { 16 }, - .row_depth = { 8 }, - .num_planes = 1, - .walign = 1, - .flags = MDP_FMT_FLAG_OUTPUT, - }, { - .pixelformat = V4L2_PIX_FMT_NV24, - .mdp_color = MDP_COLOR_NV24, - .depth = { 24 }, - .row_depth = { 8 }, - .num_planes = 1, - .flags = MDP_FMT_FLAG_OUTPUT, - }, { - .pixelformat = V4L2_PIX_FMT_NV42, - .mdp_color = MDP_COLOR_NV42, - .depth = { 24 }, - .row_depth = { 8 }, - .num_planes = 1, - .flags = MDP_FMT_FLAG_OUTPUT, - }, { - .pixelformat = V4L2_PIX_FMT_MT21C, - .mdp_color = MDP_COLOR_420_BLK_UFO, - .depth = { 8, 4 }, - .row_depth = { 8, 8 }, - .num_planes = 2, - .walign = 4, - .halign = 5, - .flags = MDP_FMT_FLAG_OUTPUT, - }, { - .pixelformat = V4L2_PIX_FMT_MM21, - .mdp_color = MDP_COLOR_420_BLK, - .depth = { 8, 4 }, - .row_depth = { 8, 8 }, - .num_planes = 2, - .walign = 4, - .halign = 5, - .flags = MDP_FMT_FLAG_OUTPUT, - }, { - .pixelformat = V4L2_PIX_FMT_NV12M, - .mdp_color = MDP_COLOR_NV12, - .depth = { 8, 4 }, - .row_depth = { 8, 8 }, - .num_planes = 2, - .walign = 1, - .halign = 1, - .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, - }, { - .pixelformat = V4L2_PIX_FMT_NV21M, - .mdp_color = MDP_COLOR_NV21, - .depth = { 8, 4 }, - .row_depth = { 8, 8 }, - .num_planes = 2, - .walign = 1, - .halign = 1, - .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, - }, { - .pixelformat = V4L2_PIX_FMT_NV16M, - .mdp_color = MDP_COLOR_NV16, - .depth = { 8, 8 }, - .row_depth = { 8, 8 }, - .num_planes = 2, - .walign = 1, - .flags = MDP_FMT_FLAG_OUTPUT, - }, { - .pixelformat = V4L2_PIX_FMT_NV61M, - .mdp_color = MDP_COLOR_NV61, - .depth = { 8, 8 }, - .row_depth = { 8, 8 }, - .num_planes = 2, - .walign = 1, - .flags = MDP_FMT_FLAG_OUTPUT, - }, { - .pixelformat = V4L2_PIX_FMT_YUV420M, - .mdp_color = MDP_COLOR_I420, - .depth = { 8, 2, 2 }, - .row_depth = { 8, 4, 4 }, - .num_planes = 3, - .walign = 1, - .halign = 1, - .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, - }, { - .pixelformat = V4L2_PIX_FMT_YVU420M, - .mdp_color = MDP_COLOR_YV12, - .depth = { 8, 2, 2 }, - .row_depth = { 8, 4, 4 }, - .num_planes = 3, - .walign = 1, - .halign = 1, - .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, - } -}; - static const struct mdp_limit mdp_def_limit = { .out_limit = { .wmin = 16, @@ -250,32 +29,34 @@ static const struct mdp_limit mdp_def_limit = { .v_scale_down_max = 128, }; -static const struct mdp_format *mdp_find_fmt(u32 pixelformat, u32 type) +static const struct mdp_format *mdp_find_fmt(const struct mtk_mdp_driver_data *mdp_data, + u32 pixelformat, u32 type) { u32 i, flag; flag = V4L2_TYPE_IS_OUTPUT(type) ? MDP_FMT_FLAG_OUTPUT : MDP_FMT_FLAG_CAPTURE; - for (i = 0; i < ARRAY_SIZE(mdp_formats); ++i) { - if (!(mdp_formats[i].flags & flag)) + for (i = 0; i < mdp_data->format_len; ++i) { + if (!(mdp_data->format[i].flags & flag)) continue; - if (mdp_formats[i].pixelformat == pixelformat) - return &mdp_formats[i]; + if (mdp_data->format[i].pixelformat == pixelformat) + return &mdp_data->format[i]; } return NULL; } -static const struct mdp_format *mdp_find_fmt_by_index(u32 index, u32 type) +static const struct mdp_format *mdp_find_fmt_by_index(const struct mtk_mdp_driver_data *mdp_data, + u32 index, u32 type) { u32 i, flag, num = 0; flag = V4L2_TYPE_IS_OUTPUT(type) ? MDP_FMT_FLAG_OUTPUT : MDP_FMT_FLAG_CAPTURE; - for (i = 0; i < ARRAY_SIZE(mdp_formats); ++i) { - if (!(mdp_formats[i].flags & flag)) + for (i = 0; i < mdp_data->format_len; ++i) { + if (!(mdp_data->format[i].flags & flag)) continue; if (index == num) - return &mdp_formats[i]; + return &mdp_data->format[i]; num++; } return NULL; @@ -352,14 +133,14 @@ static int mdp_clamp_align(s32 *x, int min, int max, unsigned int align) return 0; } -int mdp_enum_fmt_mplane(struct v4l2_fmtdesc *f) +int mdp_enum_fmt_mplane(struct mdp_dev *mdp, struct v4l2_fmtdesc *f) { const struct mdp_format *fmt; if (!V4L2_TYPE_IS_MULTIPLANAR(f->type)) return -EINVAL; - fmt = mdp_find_fmt_by_index(f->index, f->type); + fmt = mdp_find_fmt_by_index(mdp->mdp_data, f->index, f->type); if (!fmt) return -EINVAL; @@ -368,7 +149,8 @@ int mdp_enum_fmt_mplane(struct v4l2_fmtdesc *f) return 0; } -const struct mdp_format *mdp_try_fmt_mplane(struct v4l2_format *f, +const struct mdp_format *mdp_try_fmt_mplane(struct mdp_dev *mdp, + struct v4l2_format *f, struct mdp_frameparam *param, u32 ctx_id) { @@ -381,9 +163,9 @@ const struct mdp_format *mdp_try_fmt_mplane(struct v4l2_format *f, if (!V4L2_TYPE_IS_MULTIPLANAR(f->type)) return NULL; - fmt = mdp_find_fmt(pix_mp->pixelformat, f->type); + fmt = mdp_find_fmt(mdp->mdp_data, pix_mp->pixelformat, f->type); if (!fmt) - fmt = mdp_find_fmt_by_index(0, f->type); + fmt = mdp_find_fmt_by_index(mdp->mdp_data, 0, f->type); if (!fmt) { pr_err("[%s:%d] pixelformat %c%c%c%c invalid", __func__, ctx_id, (pix_mp->pixelformat & 0xff), @@ -709,7 +491,7 @@ void mdp_set_dst_config(struct img_output *out, /* out->flags |= ; */ /* sharpness, dither */ } -int mdp_frameparam_init(struct mdp_frameparam *param) +int mdp_frameparam_init(struct mdp_dev *mdp, struct mdp_frameparam *param) { struct mdp_frame *frame; @@ -723,7 +505,7 @@ int mdp_frameparam_init(struct mdp_frameparam *param) frame = ¶m->output; frame->format.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; - frame->mdp_fmt = mdp_try_fmt_mplane(&frame->format, param, 0); + frame->mdp_fmt = mdp_try_fmt_mplane(mdp, &frame->format, param, 0); frame->ycbcr_prof = mdp_map_ycbcr_prof_mplane(&frame->format, frame->mdp_fmt->mdp_color); @@ -732,7 +514,7 @@ int mdp_frameparam_init(struct mdp_frameparam *param) param->num_captures = 1; frame = ¶m->captures[0]; frame->format.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; - frame->mdp_fmt = mdp_try_fmt_mplane(&frame->format, param, 0); + frame->mdp_fmt = mdp_try_fmt_mplane(mdp, &frame->format, param, 0); frame->ycbcr_prof = mdp_map_ycbcr_prof_mplane(&frame->format, frame->mdp_fmt->mdp_color); @@ -744,3 +526,4 @@ int mdp_frameparam_init(struct mdp_frameparam *param) return 0; } + diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h index b3aaef8eb7eb..4b6afaaa8645 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h @@ -18,14 +18,17 @@ * V-subsample: 0, 1 * Color group: 0-RGB, 1-YUV, 2-raw */ -#define MDP_COLOR(PACKED, LOOSE, VIDEO, PLANE, HF, VF, BITS, GROUP, SWAP, ID)\ - (((PACKED) << 27) | ((LOOSE) << 26) | ((VIDEO) << 23) |\ +#define MDP_COLOR(COMPRESS, PACKED, LOOSE, VIDEO, PLANE, HF, VF, BITS, GROUP, SWAP, ID)\ + (((COMPRESS) << 29) | ((PACKED) << 28) | ((LOOSE) << 27) | ((VIDEO) << 23) |\ ((PLANE) << 21) | ((HF) << 19) | ((VF) << 18) | ((BITS) << 8) |\ ((GROUP) << 6) | ((SWAP) << 5) | ((ID) << 0)) -#define MDP_COLOR_IS_10BIT_PACKED(c) ((0x08000000 & (c)) >> 27) -#define MDP_COLOR_IS_10BIT_LOOSE(c) (((0x0c000000 & (c)) >> 26) == 1) -#define MDP_COLOR_IS_10BIT_TILE(c) (((0x0c000000 & (c)) >> 26) == 3) +#define MDP_COLOR_IS_HYFBC_COMPRESS(c) ((0x40000000 & (c)) >> 30) +#define MDP_COLOR_IS_COMPRESS(c) ((0x20000000 & (c)) >> 29) +#define MDP_COLOR_IS_10BIT_PACKED(c) ((0x10000000 & (c)) >> 28) +#define MDP_COLOR_IS_10BIT_LOOSE(c) (((0x18000000 & (c)) >> 27) == 1) +#define MDP_COLOR_IS_10BIT_TILE(c) (((0x18000000 & (c)) >> 27) == 3) +#define MDP_COLOR_IS_10BIT_JUMP(c) ((0x04000000 & (c)) >> 26) #define MDP_COLOR_IS_UFP(c) ((0x02000000 & (c)) >> 25) #define MDP_COLOR_IS_INTERLACED(c) ((0x01000000 & (c)) >> 24) #define MDP_COLOR_IS_BLOCK_MODE(c) ((0x00800000 & (c)) >> 23) @@ -42,148 +45,120 @@ #define MDP_COLOR_IS_YUV(c) (MDP_COLOR_GET_GROUP(c) == 1) #define MDP_COLOR_IS_UV_COPLANE(c) ((MDP_COLOR_GET_PLANE_COUNT(c) == 2) &&\ MDP_COLOR_IS_YUV(c)) +#define MDP_COLOR_IS_10BIT(c) (((0x18000000 & (c)) >> 27) != 0) +#define MDP_COLOR_GET_AUO_MODE(c) (MDP_COLOR_IS_10BIT_JUMP(c)) enum mdp_color { MDP_COLOR_UNKNOWN = 0, - //MDP_COLOR_FULLG8, - MDP_COLOR_FULLG8_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 2, 0, 21), - MDP_COLOR_FULLG8_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 8, 2, 0, 21), - MDP_COLOR_FULLG8_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 8, 2, 0, 21), - MDP_COLOR_FULLG8_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 8, 2, 0, 21), - MDP_COLOR_FULLG8 = MDP_COLOR_FULLG8_BGGR, - - //MDP_COLOR_FULLG10, - MDP_COLOR_FULLG10_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 21), - MDP_COLOR_FULLG10_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 10, 2, 0, 21), - MDP_COLOR_FULLG10_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 10, 2, 0, 21), - MDP_COLOR_FULLG10_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 10, 2, 0, 21), - MDP_COLOR_FULLG10 = MDP_COLOR_FULLG10_BGGR, - - //MDP_COLOR_FULLG12, - MDP_COLOR_FULLG12_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 12, 2, 0, 21), - MDP_COLOR_FULLG12_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 12, 2, 0, 21), - MDP_COLOR_FULLG12_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 12, 2, 0, 21), - MDP_COLOR_FULLG12_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 12, 2, 0, 21), - MDP_COLOR_FULLG12 = MDP_COLOR_FULLG12_BGGR, - - //MDP_COLOR_FULLG14, - MDP_COLOR_FULLG14_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 14, 2, 0, 21), - MDP_COLOR_FULLG14_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 14, 2, 0, 21), - MDP_COLOR_FULLG14_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 14, 2, 0, 21), - MDP_COLOR_FULLG14_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 14, 2, 0, 21), - MDP_COLOR_FULLG14 = MDP_COLOR_FULLG14_BGGR, - - MDP_COLOR_UFO10 = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 24), - - //MDP_COLOR_BAYER8, - MDP_COLOR_BAYER8_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 2, 0, 20), - MDP_COLOR_BAYER8_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 8, 2, 0, 20), - MDP_COLOR_BAYER8_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 8, 2, 0, 20), - MDP_COLOR_BAYER8_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 8, 2, 0, 20), - MDP_COLOR_BAYER8 = MDP_COLOR_BAYER8_BGGR, - - //MDP_COLOR_BAYER10, - MDP_COLOR_BAYER10_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 20), - MDP_COLOR_BAYER10_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 10, 2, 0, 20), - MDP_COLOR_BAYER10_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 10, 2, 0, 20), - MDP_COLOR_BAYER10_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 10, 2, 0, 20), - MDP_COLOR_BAYER10 = MDP_COLOR_BAYER10_BGGR, - - //MDP_COLOR_BAYER12, - MDP_COLOR_BAYER12_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 12, 2, 0, 20), - MDP_COLOR_BAYER12_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 12, 2, 0, 20), - MDP_COLOR_BAYER12_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 12, 2, 0, 20), - MDP_COLOR_BAYER12_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 12, 2, 0, 20), - MDP_COLOR_BAYER12 = MDP_COLOR_BAYER12_BGGR, - - //MDP_COLOR_BAYER14, - MDP_COLOR_BAYER14_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 14, 2, 0, 20), - MDP_COLOR_BAYER14_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 14, 2, 0, 20), - MDP_COLOR_BAYER14_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 14, 2, 0, 20), - MDP_COLOR_BAYER14_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 14, 2, 0, 20), - MDP_COLOR_BAYER14 = MDP_COLOR_BAYER14_BGGR, - - MDP_COLOR_RGB48 = MDP_COLOR(0, 0, 0, 1, 0, 0, 48, 0, 0, 23), - /* For bayer+mono raw-16 */ - MDP_COLOR_RGB565_RAW = MDP_COLOR(0, 0, 0, 1, 0, 0, 16, 2, 0, 0), - - MDP_COLOR_BAYER8_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 2, 0, 22), - MDP_COLOR_BAYER10_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 22), - MDP_COLOR_BAYER12_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 12, 2, 0, 22), - MDP_COLOR_BAYER14_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 14, 2, 0, 22), - - /* Unified formats */ - MDP_COLOR_GREY = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 1, 0, 7), - - MDP_COLOR_RGB565 = MDP_COLOR(0, 0, 0, 1, 0, 0, 16, 0, 0, 0), - MDP_COLOR_BGR565 = MDP_COLOR(0, 0, 0, 1, 0, 0, 16, 0, 1, 0), - MDP_COLOR_RGB888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 0, 1, 1), - MDP_COLOR_BGR888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 0, 0, 1), - MDP_COLOR_RGBA8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 1, 2), - MDP_COLOR_BGRA8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 0, 2), - MDP_COLOR_ARGB8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 1, 3), - MDP_COLOR_ABGR8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 0, 3), - - MDP_COLOR_UYVY = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 0, 4), - MDP_COLOR_VYUY = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 1, 4), - MDP_COLOR_YUYV = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 0, 5), - MDP_COLOR_YVYU = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 1, 5), - - MDP_COLOR_I420 = MDP_COLOR(0, 0, 0, 3, 1, 1, 8, 1, 0, 8), - MDP_COLOR_YV12 = MDP_COLOR(0, 0, 0, 3, 1, 1, 8, 1, 1, 8), - MDP_COLOR_I422 = MDP_COLOR(0, 0, 0, 3, 1, 0, 8, 1, 0, 9), - MDP_COLOR_YV16 = MDP_COLOR(0, 0, 0, 3, 1, 0, 8, 1, 1, 9), - MDP_COLOR_I444 = MDP_COLOR(0, 0, 0, 3, 0, 0, 8, 1, 0, 10), - MDP_COLOR_YV24 = MDP_COLOR(0, 0, 0, 3, 0, 0, 8, 1, 1, 10), - - MDP_COLOR_NV12 = MDP_COLOR(0, 0, 0, 2, 1, 1, 8, 1, 0, 12), - MDP_COLOR_NV21 = MDP_COLOR(0, 0, 0, 2, 1, 1, 8, 1, 1, 12), - MDP_COLOR_NV16 = MDP_COLOR(0, 0, 0, 2, 1, 0, 8, 1, 0, 13), - MDP_COLOR_NV61 = MDP_COLOR(0, 0, 0, 2, 1, 0, 8, 1, 1, 13), - MDP_COLOR_NV24 = MDP_COLOR(0, 0, 0, 2, 0, 0, 8, 1, 0, 14), - MDP_COLOR_NV42 = MDP_COLOR(0, 0, 0, 2, 0, 0, 8, 1, 1, 14), - - /* Mediatek proprietary formats */ - /* UFO encoded block mode */ - MDP_COLOR_420_BLK_UFO = MDP_COLOR(0, 0, 5, 2, 1, 1, 256, 1, 0, 12), - /* Block mode */ - MDP_COLOR_420_BLK = MDP_COLOR(0, 0, 1, 2, 1, 1, 256, 1, 0, 12), - /* Block mode + field mode */ - MDP_COLOR_420_BLKI = MDP_COLOR(0, 0, 3, 2, 1, 1, 256, 1, 0, 12), - /* Block mode */ - MDP_COLOR_422_BLK = MDP_COLOR(0, 0, 1, 1, 1, 0, 512, 1, 0, 4), - - MDP_COLOR_IYU2 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 1, 0, 25), - MDP_COLOR_YUV444 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 1, 0, 30), - - /* Packed 10-bit formats */ - MDP_COLOR_RGBA1010102 = MDP_COLOR(1, 0, 0, 1, 0, 0, 32, 0, 1, 2), - MDP_COLOR_BGRA1010102 = MDP_COLOR(1, 0, 0, 1, 0, 0, 32, 0, 0, 2), - /* Packed 10-bit UYVY */ - MDP_COLOR_UYVY_10P = MDP_COLOR(1, 0, 0, 1, 1, 0, 20, 1, 0, 4), - /* Packed 10-bit NV21 */ - MDP_COLOR_NV21_10P = MDP_COLOR(1, 0, 0, 2, 1, 1, 10, 1, 1, 12), - /* 10-bit block mode */ - MDP_COLOR_420_BLK_10_H = MDP_COLOR(1, 0, 1, 2, 1, 1, 320, 1, 0, 12), - /* 10-bit HEVC tile mode */ - MDP_COLOR_420_BLK_10_V = MDP_COLOR(1, 1, 1, 2, 1, 1, 320, 1, 0, 12), - /* UFO encoded 10-bit block mode */ - MDP_COLOR_420_BLK_U10_H = MDP_COLOR(1, 0, 5, 2, 1, 1, 320, 1, 0, 12), - /* UFO encoded 10-bit HEVC tile mode */ - MDP_COLOR_420_BLK_U10_V = MDP_COLOR(1, 1, 5, 2, 1, 1, 320, 1, 0, 12), - - /* Loose 10-bit formats */ - MDP_COLOR_UYVY_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 0, 4), - MDP_COLOR_VYUY_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 1, 4), - MDP_COLOR_YUYV_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 0, 5), - MDP_COLOR_YVYU_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 1, 5), - MDP_COLOR_NV12_10L = MDP_COLOR(0, 1, 0, 2, 1, 1, 10, 1, 0, 12), - MDP_COLOR_NV21_10L = MDP_COLOR(0, 1, 0, 2, 1, 1, 10, 1, 1, 12), - MDP_COLOR_NV16_10L = MDP_COLOR(0, 1, 0, 2, 1, 0, 10, 1, 0, 13), - MDP_COLOR_NV61_10L = MDP_COLOR(0, 1, 0, 2, 1, 0, 10, 1, 1, 13), - MDP_COLOR_YV12_10L = MDP_COLOR(0, 1, 0, 3, 1, 1, 10, 1, 1, 8), - MDP_COLOR_I420_10L = MDP_COLOR(0, 1, 0, 3, 1, 1, 10, 1, 0, 8), + // Unified format + MDP_COLOR_GREY = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 8, 1, 0, 7), + + MDP_COLOR_RGB565 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 16, 0, 0, 0), + MDP_COLOR_BGR565 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 16, 0, 1, 0), + MDP_COLOR_RGB888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 0, 1, 1), + MDP_COLOR_BGR888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 0, 0, 1), + MDP_COLOR_RGBA8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 1, 2), + MDP_COLOR_BGRA8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 0, 2), + MDP_COLOR_ARGB8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 1, 3), + MDP_COLOR_ABGR8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 0, 3), + + MDP_COLOR_UYVY = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 0, 4), + MDP_COLOR_VYUY = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 1, 4), + MDP_COLOR_YUYV = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 0, 5), + MDP_COLOR_YVYU = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 1, 5), + + MDP_COLOR_I420 = MDP_COLOR(0, 0, 0, 0, 3, 1, 1, 8, 1, 0, 8), + MDP_COLOR_YV12 = MDP_COLOR(0, 0, 0, 0, 3, 1, 1, 8, 1, 1, 8), + MDP_COLOR_I422 = MDP_COLOR(0, 0, 0, 0, 3, 1, 0, 8, 1, 0, 9), + MDP_COLOR_YV16 = MDP_COLOR(0, 0, 0, 0, 3, 1, 0, 8, 1, 1, 9), + MDP_COLOR_I444 = MDP_COLOR(0, 0, 0, 0, 3, 0, 0, 8, 1, 0, 10), + MDP_COLOR_YV24 = MDP_COLOR(0, 0, 0, 0, 3, 0, 0, 8, 1, 1, 10), + + MDP_COLOR_NV12 = MDP_COLOR(0, 0, 0, 0, 2, 1, 1, 8, 1, 0, 12), + MDP_COLOR_NV21 = MDP_COLOR(0, 0, 0, 0, 2, 1, 1, 8, 1, 1, 12), + MDP_COLOR_NV16 = MDP_COLOR(0, 0, 0, 0, 2, 1, 0, 8, 1, 0, 13), + MDP_COLOR_NV61 = MDP_COLOR(0, 0, 0, 0, 2, 1, 0, 8, 1, 1, 13), + MDP_COLOR_NV24 = MDP_COLOR(0, 0, 0, 0, 2, 0, 0, 8, 1, 0, 14), + MDP_COLOR_NV42 = MDP_COLOR(0, 0, 0, 0, 2, 0, 0, 8, 1, 1, 14), + + // Mediatek proprietary format + //Frame mode + Block mode + UFO + MDP_COLOR_420_BLKP_UFO = MDP_COLOR(0, 0, 0, 5, 2, 1, 1, 256, 1, 0, 12), + //Frame mode + Block mode + UFO AUO + MDP_COLOR_420_BLKP_UFO_AUO = MDP_COLOR(0, 0, 0, 13, 2, 1, 1, 256, 1, 0, 12), + //Frame mode + Block mode + MDP_COLOR_420_BLKP = MDP_COLOR(0, 0, 0, 1, 2, 1, 1, 256, 1, 0, 12), + //Field mode + Block mode + MDP_COLOR_420_BLKI = MDP_COLOR(0, 0, 0, 3, 2, 1, 1, 256, 1, 0, 12), + //Frame mode + MDP_COLOR_422_BLKP = MDP_COLOR(0, 0, 0, 1, 1, 1, 0, 512, 1, 0, 4), + + MDP_COLOR_IYU2 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 1, 0, 25), + MDP_COLOR_YUV444 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 1, 0, 30), + + // Mediatek proprietary 10bit format + MDP_COLOR_RGBA1010102 = MDP_COLOR(0, 1, 0, 0, 1, 0, 0, 32, 0, 1, 2), + MDP_COLOR_BGRA1010102 = MDP_COLOR(0, 1, 0, 0, 1, 0, 0, 32, 0, 0, 2), + MDP_COLOR_ARGB1010102 = MDP_COLOR(0, 1, 0, 0, 1, 0, 0, 32, 0, 1, 3), + MDP_COLOR_ABGR1010102 = MDP_COLOR(0, 1, 0, 0, 1, 0, 0, 32, 0, 0, 3), + //Packed 10bit UYVY + MDP_COLOR_UYVY_10P = MDP_COLOR(0, 1, 0, 0, 1, 1, 0, 20, 1, 0, 4), + //Packed 10bit NV21 + MDP_COLOR_NV12_10P = MDP_COLOR(0, 1, 0, 0, 2, 1, 1, 10, 1, 0, 12), + MDP_COLOR_NV21_10P = MDP_COLOR(0, 1, 0, 0, 2, 1, 1, 10, 1, 1, 12), + //Frame mode + Block mode + MDP_COLOR_420_BLKP_10_H = MDP_COLOR(0, 1, 0, 1, 2, 1, 1, 320, 1, 0, 12), + //Frame mode + HEVC tile mode + MDP_COLOR_420_BLKP_10_V = MDP_COLOR(0, 1, 1, 1, 2, 1, 1, 320, 1, 0, 12), + //Frame mode + Block mode + Jump + MDP_COLOR_420_BLKP_10_H_JUMP = MDP_COLOR(0, 1, 0, 9, 2, 1, 1, 320, 1, 0, 12), + //Frame mode + HEVC tile mode + Jump + MDP_COLOR_420_BLKP_10_V_JUMP = MDP_COLOR(0, 1, 1, 9, 2, 1, 1, 320, 1, 0, 12), + //Frame mode + Block mode + MDP_COLOR_420_BLKP_UFO_10_H = MDP_COLOR(0, 1, 0, 5, 2, 1, 1, 320, 1, 0, 12), + //Frame mode + HEVC tile mode + MDP_COLOR_420_BLKP_UFO_10_V = MDP_COLOR(0, 1, 1, 5, 2, 1, 1, 320, 1, 0, 12), + //Frame mode + Block mode + Jump + MDP_COLOR_420_BLKP_UFO_10_H_JUMP = MDP_COLOR(0, 1, 0, 13, 2, 1, 1, 320, 1, 0, 12), + //Frame mode + HEVC tile mode + Jump + MDP_COLOR_420_BLKP_UFO_10_V_JUMP = MDP_COLOR(0, 1, 1, 13, 2, 1, 1, 320, 1, 0, 12), + + // Loose 10bit format + MDP_COLOR_UYVY_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 0, 4), + MDP_COLOR_VYUY_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 1, 4), + MDP_COLOR_YUYV_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 0, 5), + MDP_COLOR_YVYU_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 1, 5), + MDP_COLOR_NV12_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 1, 16, 1, 0, 12), + MDP_COLOR_NV21_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 1, 16, 1, 1, 12), + MDP_COLOR_NV16_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 0, 16, 1, 0, 13), + MDP_COLOR_NV61_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 0, 16, 1, 1, 13), + MDP_COLOR_YV12_10L = MDP_COLOR(0, 0, 1, 0, 3, 1, 1, 16, 1, 1, 8), + MDP_COLOR_I420_10L = MDP_COLOR(0, 0, 1, 0, 3, 1, 1, 16, 1, 0, 8), + + MDP_COLOR_YV12_10P = MDP_COLOR(0, 1, 0, 0, 3, 1, 1, 10, 1, 1, 8), + MDP_COLOR_I422_10P = MDP_COLOR(0, 1, 0, 0, 3, 1, 0, 10, 1, 0, 9), + MDP_COLOR_NV16_10P = MDP_COLOR(0, 1, 0, 0, 2, 1, 0, 10, 1, 0, 13), + MDP_COLOR_NV61_10P = MDP_COLOR(0, 1, 0, 0, 2, 1, 0, 10, 1, 1, 13), + + MDP_COLOR_I422_10L = MDP_COLOR(0, 0, 1, 0, 3, 1, 0, 16, 1, 0, 9), + + MDP_COLOR_RGBA8888_AFBC = MDP_COLOR(1, 0, 0, 0, 1, 0, 0, 32, 0, 1, 2), + MDP_COLOR_BGRA8888_AFBC = MDP_COLOR(1, 0, 0, 0, 1, 0, 0, 32, 0, 0, 2), + MDP_COLOR_ARGB8888_AFBC = MDP_COLOR(1, 0, 0, 0, 1, 0, 0, 32, 0, 1, 3), + MDP_COLOR_ABGR8888_AFBC = MDP_COLOR(1, 0, 0, 0, 1, 0, 0, 32, 0, 0, 3), + MDP_COLOR_RGBA1010102_AFBC = MDP_COLOR(1, 1, 0, 0, 1, 0, 0, 32, 0, 1, 2), + MDP_COLOR_BGRA1010102_AFBC = MDP_COLOR(1, 1, 0, 0, 1, 0, 0, 32, 0, 0, 2), + MDP_COLOR_ARGB1010102_AFBC = MDP_COLOR(1, 1, 0, 0, 1, 0, 0, 32, 0, 1, 3), + MDP_COLOR_ABGR1010102_AFBC = MDP_COLOR(1, 1, 0, 0, 1, 0, 0, 32, 0, 0, 3), + + MDP_COLOR_NV12_AFBC = MDP_COLOR(1, 0, 0, 0, 2, 1, 1, 12, 1, 0, 12), + MDP_COLOR_P010_AFBC = MDP_COLOR(1, 1, 0, 0, 2, 1, 1, 10, 1, 0, 12), + + MDP_COLOR_NV12_HYFBC = MDP_COLOR(2, 0, 0, 0, 2, 1, 1, 8, 1, 0, 12), + MDP_COLOR_NV21_HYFBC = MDP_COLOR(2, 0, 0, 0, 2, 1, 1, 8, 1, 1, 12), + MDP_COLOR_NV12_10P_HYFBC = MDP_COLOR(2, 1, 0, 0, 2, 1, 1, 10, 1, 0, 12), + MDP_COLOR_NV21_10P_HYFBC = MDP_COLOR(2, 1, 0, 0, 2, 1, 1, 10, 1, 1, 12), }; /* Minimum Y stride that is accepted by MDP HW */ @@ -351,8 +326,9 @@ struct mdp_frameparam { enum v4l2_quantization quant; }; -int mdp_enum_fmt_mplane(struct v4l2_fmtdesc *f); -const struct mdp_format *mdp_try_fmt_mplane(struct v4l2_format *f, +int mdp_enum_fmt_mplane(struct mdp_dev *mdp, struct v4l2_fmtdesc *f); +const struct mdp_format *mdp_try_fmt_mplane(struct mdp_dev *mdp, + struct v4l2_format *f, struct mdp_frameparam *param, u32 ctx_id); enum mdp_ycbcr_profile mdp_map_ycbcr_prof_mplane(struct v4l2_format *f, @@ -367,6 +343,6 @@ void mdp_set_src_config(struct img_input *in, void mdp_set_dst_config(struct img_output *out, struct mdp_frame *frame, struct vb2_buffer *vb); -int mdp_frameparam_init(struct mdp_frameparam *param); +int mdp_frameparam_init(struct mdp_dev *mdp, struct mdp_frameparam *param); #endif /* __MTK_MDP3_REGS_H__ */ From patchwork Wed Oct 20 07:14:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "roy-cw.yeh" X-Patchwork-Id: 12571777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B370AC433F5 for ; Wed, 20 Oct 2021 07:19:45 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 79A9A60524 for ; Wed, 20 Oct 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(TLS) id 15.0.1497.2; Wed, 20 Oct 2021 00:15:28 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Oct 2021 15:15:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Oct 2021 15:15:26 +0800 From: roy-cw.yeh To: Rob Herring , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Kuang Hu CC: Mauro Carvalho Chehab , Fabien Parent , "Roy-CW . Yeh" , "jason-jh . lin" , daoyuan huang , Ping-Hsun Wu , Moudy Ho , "river . cheng" , Enric Balletbo i Serra , Yongqiang Niu , , , , , Subject: [PATCH v2 4/9] dt-bindings: media: mediatek: mdp3: add additional function block yaml Date: Wed, 20 Oct 2021 15:14:43 +0800 Message-ID: <20211020071448.14187-5-roy-cw.yeh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211020071448.14187-1-roy-cw.yeh@mediatek.com> References: <20211020071448.14187-1-roy-cw.yeh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211020_001538_077990_97834F9F X-CRM114-Status: GOOD ( 16.25 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: "Roy-CW.Yeh" Add additional function block yaml in mt8195 Signed-off-by: Roy-CW.Yeh --- .../bindings/arm/mediatek/mediatek,mmsys.yaml | 2 + .../bindings/arm/mediatek/mediatek,mutex.yaml | 4 ++ .../bindings/media/mediatek,mdp3-aal.yaml | 62 +++++++++++++++++ .../bindings/media/mediatek,mdp3-color.yaml | 62 +++++++++++++++++ .../bindings/media/mediatek,mdp3-fg.yaml | 61 +++++++++++++++++ .../bindings/media/mediatek,mdp3-hdr.yaml | 61 +++++++++++++++++ .../bindings/media/mediatek,mdp3-merge.yaml | 62 +++++++++++++++++ .../bindings/media/mediatek,mdp3-ovl.yaml | 61 +++++++++++++++++ .../bindings/media/mediatek,mdp3-pad.yaml | 62 +++++++++++++++++ .../bindings/media/mediatek,mdp3-rdma.yaml | 22 +++++- .../bindings/media/mediatek,mdp3-rsz.yaml | 2 + .../bindings/media/mediatek,mdp3-split.yaml | 67 +++++++++++++++++++ .../bindings/media/mediatek,mdp3-stitch.yaml | 62 +++++++++++++++++ .../bindings/media/mediatek,mdp3-tcc.yaml | 62 +++++++++++++++++ .../bindings/media/mediatek,mdp3-tdshp.yaml | 61 +++++++++++++++++ .../bindings/media/mediatek,mdp3-wrot.yaml | 2 + 16 files changed, 713 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 679437ee2590..7b46b8156a12 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -33,6 +33,8 @@ properties: - mediatek,mt8365-mmsys - mediatek,mt8195-vdosys0 - mediatek,mt8195-vdosys1 + - mediatek,mt8195-vppsys0 + - mediatek,mt8195-vppsys1 - const: syscon - items: - const: mediatek,mt7623-mmsys diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mutex.yaml index 1a1c049aa929..41dc1383131a 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mutex.yaml @@ -37,6 +37,10 @@ properties: - const: mediatek,mt8192-disp-mutex - items: - const: mediatek,mt8195-disp-mutex + - items: + - const: mediatek,mt8195-vpp0-mutex + - items: + - const: mediatek,mt8195-vpp1-mutex reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml new file mode 100644 index 000000000000..54535aac8942 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-aal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Media Data Path 3 AAL Device Tree Bindings + +maintainers: + - Daoyuan Huang + - Moudy Ho + +description: | + One of Media Data Path 3 (MDP3) components is responsible for backlight power saving + and sunlight visibility improving. + +properties: + compatible: + oneOf: + - items: + - mediatek,mt8195-mdp3-aal + + mediatek,mdp3-id: + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + description: | + HW index to distinguish same functionality modules. + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + sub-system id corresponding to the global command engine (GCE) + register address. + $ref: /schemas/mailbox/mtk-gce.txt + + clocks: + minItems: 1 + +required: + - compatible + - mediatek,mdp3-id + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + mdp3_aal0: mdp_aal0@14005000 { + compatible = "mediatek,mt8195-mdp3-aal"; + mediatek,mdp3-id = <0>; + reg = <0 0x14005000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x5000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_AAL>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml new file mode 100644 index 000000000000..4eba4505ed26 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-color.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Media Data Path 3 COLOR Device Tree Bindings + +maintainers: + - Daoyuan Huang + - Moudy Ho + +description: | + One of Media Data Path 3 (MDP3) components used to adjust hue, luma and saturation + to get better picture quality. + +properties: + compatible: + oneOf: + - items: + - mediatek,mt8195-mdp3-color + + mediatek,mdp3-id: + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + description: | + HW index to distinguish same functionality modules. + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + sub-system id corresponding to the global command engine (GCE) + register address. + $ref: /schemas/mailbox/mtk-gce.txt + + clocks: + minItems: 1 + +required: + - compatible + - mediatek,mdp3-id + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + mdp3_color0: mdp_color0@14008000 { + compatible = "mediatek,mt8195-mdp3-color"; + mediatek,mdp3-id = <0>; + reg = <0 0x14008000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x8000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml new file mode 100644 index 000000000000..8a4ea694c44b --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-fg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Media Data Path 3 FG Device Tree Bindings + +maintainers: + - Daoyuan Huang + - Moudy Ho + +description: | + One of Media Data Path 3 (MDP3) components used to add film grain according to AV1 spec. + +properties: + compatible: + oneOf: + - items: + - const: mediatek,mt8195-mdp3-fg + + mediatek,mdp3-id: + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + description: | + HW index to distinguish same functionality modules. + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + sub-system id corresponding to the global command engine (GCE) + register address. + $ref: /schemas/mailbox/mtk-gce.txt + + clocks: + minItems: 1 + +required: + - compatible + - mediatek,mdp3-id + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + mdp3_fg0: mdp_fg0@14002000 { + compatible = "mediatek,mt8195-mdp3-fg"; + mediatek,mdp3-id = <0>; + reg = <0 0x14002000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x2000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_FG>; + }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml new file mode 100644 index 000000000000..4330f2b79697 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-hdr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Media Data Path 3 HDR Device Tree Bindings + +maintainers: + - Daoyuan Huang + - Moudy Ho + +description: | + One of Media Data Path 3 (MDP3) components used to perform HDR to SDR + +properties: + compatible: + oneOf: + - items: + - const: mediatek,mt8195-mdp3-hdr + + mediatek,mdp3-id: + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + description: | + HW index to distinguish same functionality modules. + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + sub-system id corresponding to the global command engine (GCE) + register address. + $ref: /schemas/mailbox/mtk-gce.txt + + clocks: + minItems: 1 + +required: + - compatible + - mediatek,mdp3-id + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + mdp3_hdr0: mdp_hdr0@14004000 + compatible = "mediatek,mt8195-mdp3-hdr"; + mediatek,mdp3-id = <0>; + reg = <0 0x14004000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x4000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_HDR>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml new file mode 100644 index 000000000000..1e48a4636588 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-merge.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Media Data Path 3 MERGE Device Tree Bindings + +maintainers: + - Daoyuan Huang + - Moudy Ho + +description: | + One of Media Data Path 3 (MDP3) components used to merge + two slice-per-line inputs into one side-by-side output. + +properties: + compatible: + oneOf: + - items: + - mediatek,mt8195-mdp3-merge + + mediatek,mdp3-id: + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + description: | + HW index to distinguish same functionality modules. + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + sub-system id corresponding to the global command engine (GCE) + register address. + $ref: /schemas/mailbox/mtk-gce.txt + + clocks: + minItems: 1 + +required: + - compatible + - mediatek,mdp3-id + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + svpp2_mdp3_merge: svpp2_mdp_merge@14f1a000 { + compatible = "mediatek,mt8195-mdp3-merge"; + mediatek,mdp3-id = <2>; + reg = <0 0x14f1a000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0xa000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml new file mode 100644 index 000000000000..4e503d79758b --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-ovl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Media Data Path 3 OVL Device Tree Bindings + +maintainers: + - Daoyuan Huang + - Moudy Ho + +description: | + One of Media Data Path 3 (MDP3) components used to perform alpha blending from the memory. + +properties: + compatible: + oneOf: + - items: + - mediatek,mt8195-mdp3-ovl + + mediatek,mdp3-id: + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + description: | + HW index to distinguish same functionality modules. + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + sub-system id corresponding to the global command engine (GCE) + register address. + $ref: /schemas/mailbox/mtk-gce.txt + + clocks: + minItems: 1 + +required: + - compatible + - mediatek,mdp3-id + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + mdp3_ovl0: mdp_ovl0@14009000 { + compatible = "mediatek,mt8195-mdp3-ovl"; + mediatek,mdp3-id = <0>; + reg = <0 0x14009000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x9000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_OVL>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml new file mode 100644 index 000000000000..1f990c5ce6ab --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-pad.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Media Data Path 3 PADDING Device Tree Bindings + +maintainers: + - Daoyuan Huang + - Moudy Ho + +description: | + One of Media Data Path 3 (MDP3) components used to insert + pre-defined color or alpha value to arbitrary side of image. + +properties: + compatible: + oneOf: + - items: + - mediatek,mt8195-mdp3-pad + + mediatek,mdp3-id: + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + description: | + HW index to distinguish same functionality modules. + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + sub-system id corresponding to the global command engine (GCE) + register address. + $ref: /schemas/mailbox/mtk-gce.txt + + clocks: + minItems: 1 + +required: + - compatible + - mediatek,mdp3-id + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + mdp3_pad0: mdp_pad0@1400a000 { + compatible = "mediatek,mt8195-mdp3-pad"; + mediatek,mdp3-id = <0>; + reg = <0 0x1400a000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0xa000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_PADDING>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml index b355d7fe791e..ce023d9fbef7 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml @@ -20,14 +20,16 @@ properties: oneOf: - items: - enum: - # controller node - mediatek,mt8183-mdp3 + - mediatek,mt8195-mdp3 - enum: - mediatek,mt8183-mdp3-rdma - items: - - enum: # read DMA + - enum: + - mediatek,mt8195-mdp3-rdma + - enum: - mediatek,mt8183-mdp3-rdma mediatek,scp: @@ -55,12 +57,28 @@ properties: - mediatek,mt8183-mdp3-dl1 - enum: - mediatek,mt8183-mdp3-dl2 + - enum: + - mediatek,mt8195-mdp3-dl1 + - enum: + - mediatek,mt8195-mdp3-dl2 + - enum: + - mediatek,mt8195-mdp3-dl3 + - enum: + - mediatek,mt8195-mdp3-dl4 + - enum: + - mediatek,mt8195-mdp3-dl5 + - enum: + - mediatek,mt8195-mdp3-dl6 - enum: # MDP direct-link output path selection, create a # component for path connectedness of HW pipe control - mediatek,mt8183-mdp3-path1 - enum: - mediatek,mt8183-mdp3-path2 + - enum: + - mediatek,mt8195-mdp3-path1 + - enum: + - mediatek,mt8195-mdp3-path2 - enum: # Input DMA of ISP PASS2 (DIP) module for raw image input - mediatek,mt8183-mdp3-imgi diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml index c55a52cd32b7..eaa487ec58cc 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml @@ -16,6 +16,8 @@ description: | properties: compatible: items: + - enum: + - mediatek,mt8195-mdp3-rsz - enum: - mediatek,mt8183-mdp3-rsz diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml new file mode 100644 index 000000000000..40827d577f74 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-solit.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Media Data Path 3 SPLIT Device Tree Bindings + +maintainers: + - Daoyuan Huang + - Moudy Ho + +description: | + One of Media Data Path 3 (MDP3) components used to split hdmi rx into two stream + +properties: + compatible: + oneOf: + - items: + - mediatek,mt8195-mdp3-split + + mediatek,mdp3-id: + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + description: | + HW index to distinguish same functionality modules. + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + sub-system id corresponding to the global command engine (GCE) + register address. + $ref: /schemas/mailbox/mtk-gce.txt + + clocks: + minItems: 1 + +required: + - compatible + - mediatek,mdp3-id + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + vpp_split0: vpp_split0@14f06000 { + compatible = "mediatek,mt8195-mdp3-split"; + mediatek,mdp3-id = <0>; + reg = <0 0x14f06000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0x6000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>, + <&vppsys1 CLK_VPP1_HDMI_META>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>, + <&vppsys1 CLK_VPP1_DGI_IN>, + <&vppsys1 CLK_VPP1_DGI_OUT>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_DGI>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_26M>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml new file mode 100644 index 000000000000..038a9519b2de --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-stitch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Media Data Path 3 STITCH Device Tree Bindings + +maintainers: + - Daoyuan Huang + - Moudy Ho + +description: | + One of Media Data Path 3 (MDP3) components used to combine multiple video frame + with overlapping fields of view to produce a segmented panorame. + +properties: + compatible: + oneOf: + - items: + - const: mediatek,mt8195-mdp3-stitch + + mediatek,mdp3-id: + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + description: | + HW index to distinguish same functionality modules. + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + sub-system id corresponding to the global command engine (GCE) + register address. + $ref: /schemas/mailbox/mtk-gce.txt + + clocks: + minItems: 1 + +required: + - compatible + - mediatek,mdp3-id + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + mdp3_stitch0: mdp_stich0@14003000 { + compatible = "mediatek,mt8195-mdp3-stitch"; + mediatek,mdp3-id = <0>; + reg = <0 0x14003000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x3000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_STITCH>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml new file mode 100644 index 000000000000..63c147cb8d24 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-tcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Media Data Path 3 TCC Device Tree Bindings + +maintainers: + - Daoyuan Huang + - Moudy Ho + +description: | + One of Media Data Path 3 (MDP3) components used to support + HDR gamma curve conversion HDR displays. + +properties: + compatible: + oneOf: + - items: + - mediatek,mt8195-mdp3-tcc + + mediatek,mdp3-id: + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + description: | + HW index to distinguish same functionality modules. + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + sub-system id corresponding to the global command engine (GCE) + register address. + $ref: /schemas/mailbox/mtk-gce.txt + + clocks: + minItems: 1 + +required: + - compatible + - mediatek,mdp3-id + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + mdp3_tcc0: mdp_tcc0@1400b000 { + compatible = "mediatek,mt8195-mdp3-tcc"; + mediatek,mdp3-id = <0>; + reg = <0 0x1400b000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0xb000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml new file mode 100644 index 000000000000..25b4668d93fc --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-tdshp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Media Data Path 3 TDSHP Device Tree Bindings + +maintainers: + - Daoyuan Huang + - Moudy Ho + +description: | + One of Media Data Path 3 (MDP3) components used to improve image sharpness and contrast. + +properties: + compatible: + oneOf: + - items: + - const: mediatek,mt8195-mdp3-tdshp + + mediatek,mdp3-id: + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + description: | + HW index to distinguish same functionality modules. + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + sub-system id corresponding to the global command engine (GCE) + register address. + $ref: /schemas/mailbox/mtk-gce.txt + + clocks: + minItems: 1 + +required: + - compatible + - mediatek,mdp3-id + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + mdp3_tdshp0: mdp_tdshp0@14007000 { + compatible = "mediatek,mt8195-mdp3-tdshp"; + mediatek,mdp3-id = <0>; + reg = <0 0x14007000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x7000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml index 2993da04c562..885e0f0f9e1f 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml @@ -16,6 +16,8 @@ description: | properties: compatible: items: + - enum: + - mediatek,mt8195-mdp3-wrot - enum: - mediatek,mt8183-mdp3-wrot From patchwork Wed Oct 20 07:14:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "roy-cw.yeh" X-Patchwork-Id: 12571775 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F2DFC433EF for ; Wed, 20 Oct 2021 07:19:41 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E35D960524 for ; Wed, 20 Oct 2021 07:19:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org E35D960524 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xD20N1s7jHPwRUKCCXD2MfeAH1qwYdagyxoMV/opNX0=; b=IA39KE3PA1xj8C SIPHpZ5A/Xez9Vpun5f4S1LPDNiha2Ak05ZWmzsxdPyEQj3d0jHq3MTo/jnu0iyQyuOEA3+1qD2o1 qoits1miYRpyO81jBjgGeiV8Rs4XcTxgZaDm/06XbRLiNfrGMXk90BMKx/fPZrIg80ckBGuF8qTSp o3L+hw7/Dk8CgUfM/tyVcrBt3ivyNyctujtkmkkpTKHBY1APu2oMH4aY5R3sjKvQ0lo/VL8Cv+D/N mdC/RQTu+z6wPXtvczjjnaAJKzDqB7n1XZY10BjQcJKnW9vBaRFREdT4RoIQQRSn5P8mo2kB4lNXl QTAYENuQty5gUa2TQ3uQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1md5sl-003a9K-Hr; Wed, 20 Oct 2021 07:19:27 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1md5p3-003Y5g-Mk; Wed, 20 Oct 2021 07:15:54 +0000 X-UUID: e65645276a0d490097958a511e03dcd4-20211020 X-UUID: e65645276a0d490097958a511e03dcd4-20211020 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1945917682; Wed, 20 Oct 2021 00:15:30 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Oct 2021 00:15:29 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Oct 2021 15:15:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Oct 2021 15:15:27 +0800 From: roy-cw.yeh To: Rob Herring , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Kuang Hu CC: Mauro Carvalho Chehab , Fabien Parent , "Roy-CW . Yeh" , "jason-jh . lin" , daoyuan huang , Ping-Hsun Wu , Moudy Ho , "river . cheng" , Enric Balletbo i Serra , Yongqiang Niu , , , , , Subject: [PATCH v2 5/9] arm64: dts: mt8195: add mdp3 node Date: Wed, 20 Oct 2021 15:14:44 +0800 Message-ID: <20211020071448.14187-6-roy-cw.yeh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211020071448.14187-1-roy-cw.yeh@mediatek.com> References: <20211020071448.14187-1-roy-cw.yeh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211020_001537_946177_69A2ED35 X-CRM114-Status: GOOD ( 10.83 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: "Roy-CW.Yeh" Add mdp3 node. Signed-off-by: Roy-CW.Yeh --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 672 ++++++++++++++++++++++- 1 file changed, 669 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 3a44955350ae..727b78535605 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1002,9 +1002,245 @@ vppsys0: syscon@14000000 { compatible = "mediatek,mt8195-vppsys0", "syscon"; reg = <0 0x14000000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0 0x1000>; #clock-cells = <1>; }; + mdp3_rdma0: mdp_rdma0@14001000 { + compatible = "mediatek,mt8195-mdp3", + "mediatek,mt8183-mdp3-rdma"; + mediatek,scp = <&scp>; + mediatek,mdp3-id = <0>; + mdp3-comps = "mediatek,mt8195-mdp3-path1", "mediatek,mt8195-mdp3-path2", + "mediatek,mt8195-mdp3-dl1", "mediatek,mt8195-mdp3-dl2", + "mediatek,mt8195-mdp3-dl3", "mediatek,mt8195-mdp3-dl4", + "mediatek,mt8195-mdp3-dl5", "mediatek,mt8195-mdp3-dl6"; + mdp3-comp-ids = <0 1 0 1 0 0 0 0>; + reg = <0 0x14001000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x1000 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>, + <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>, + <&iommu_vpp M4U_PORT_L4_MDP_WROT>, + <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>, + <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>; + clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>, + <&topckgen CLK_TOP_CFG_VPP0>, + <&topckgen CLK_TOP_CFG_26M_VPP0>, + <&vppsys0 CLK_VPP0_WARP0_ASYNC_TX>, + <&vppsys0 CLK_VPP0_WARP0_RELAY>, + <&vppsys0 CLK_VPP0_WARP0_MDP_DL_ASYNC>, + <&vppsys0 CLK_VPP0_WARP1_ASYNC_TX>, + <&vppsys0 CLK_VPP0_WARP1_RELAY>, + <&vppsys0 CLK_VPP0_WARP1_MDP_DL_ASYNC>, + <&vppsys0 CLK_VPP0_VPP02VPP1_RELAY>, + <&vppsys1 CLK_VPP1_DL_ASYNC>, + <&vppsys1 CLK_VPP1_VPP0_DL_ASYNC>, + <&vppsys1 CLK_VPP1_VPP0_DL_RELAY>, + <&vppsys0 CLK_VPP0_VPP12VPP0_ASYNC>, + <&vppsys1 CLK_VPP1_VPP0_DL1_RELAY>, + <&vppsys1 CLK_VPP1_SVPP2_VDO0_DL_RELAY>, + <&vppsys1 CLK_VPP1_SVPP3_VDO1_DL_RELAY>, + <&vppsys1 CLK_VPP1_SVPP2_VDO1_DL_RELAY>, + <&vppsys1 CLK_VPP1_SVPP3_VDO0_DL_RELAY>; + clock-names = "MDP_RDMA0", + "TOP_CFG_VPP0", + "TOP_CFG_26M_VPP0", + "WARP0_ASYNC_TX", + "WARP0_RELAY", + "WARP0_MDP_DL_ASYNC", + "WARP1_ASYNC_TX", + "WARP1_RELAY", + "WARP1_MDP_DL_ASYNC", + "VPP02VPP1_RELAY", + "VPP0_DL_ASYNC_VPP1", + "VPP0_DL_ASYNC_VPP0", + "VPP0_DL_RELAY", + "VPP12VPP0_ASYNC", + "VPP0_DL1_RELAY", + "SVPP2_VDO0_DL_RELAY", + "SVPP3_VDO1_DL_RELAY", + "SVPP2_VDO1_DL_RELAY", + "SVPP3_VDO0_DL_RELAY"; + mediatek,mmsys2 = <&vppsys1>; + mediatek,mm-mutex2 = <&vpp1_mutex>; + mediatek,mmsys = <&vppsys0>; + mediatek,mm-mutex = <&vpp0_mutex>; + mboxes = + <&gce0 12 CMDQ_THR_PRIO_1>, + <&gce0 13 CMDQ_THR_PRIO_1>, + <&gce0 14 CMDQ_THR_PRIO_1>, + <&gce0 21 CMDQ_THR_PRIO_1>, + <&gce0 22 CMDQ_THR_PRIO_1>; + mdp3-rdma0 = <&mdp3_rdma0>; + mdp3-rdma1 = <&svpp1_mdp3_rdma>; + mdp3-rdma2 = <&svpp2_mdp3_rdma>; + mdp3-rdma3 = <&svpp3_mdp3_rdma>; + mdp3-stitch = <&mdp3_stitch0>; + mdp3-rsz0 = <&mdp3_rsz0>; + mdp3-rsz1 = <&svpp1_mdp3_rsz>; + mdp3-rsz2 = <&svpp2_mdp3_rsz>; + mdp3-rsz3 = <&svpp3_mdp3_rsz>; + mdp3-wrot0 = <&mdp3_wrot0>; + mdp3-wrot1 = <&svpp1_mdp3_wrot>; + mdp3-wrot2 = <&svpp2_mdp3_wrot>; + mdp3-wrot3 = <&svpp3_mdp3_wrot>; + mdp3-tdshp0 = <&mdp3_tdshp0>; + mdp3-tdshp1 = <&svpp1_mdp3_tdshp>; + mdp3-tdshp2 = <&svpp2_mdp3_tdshp>; + mdp3-tdshp3 = <&svpp3_mdp3_tdshp>; + mdp3-aal0 = <&mdp3_aal0>; + mdp3-aal1 = <&svpp1_mdp3_aal>; + mdp3-aal2 = <&svpp2_mdp3_aal>; + mdp3-aal3 = <&svpp3_mdp3_aal>; + mdp3-color0 = <&mdp3_color0>; + mdp3-color1 = <&svpp1_mdp3_color>; + mdp3-color2 = <&svpp2_mdp3_color>; + mdp3-color3 = <&svpp3_mdp3_color>; + mdp3-hdr0 = <&mdp3_hdr0>; + mdp3-hdr1 = <&svpp1_mdp3_hdr>; + mdp3-hdr2 = <&svpp2_mdp3_hdr>; + mdp3-hdr3 = <&svpp3_mdp3_hdr>; + mdp3-fg0 = <&mdp3_fg0>; + mdp3-fg1 = <&svpp1_mdp3_fg>; + mdp3-fg2 = <&svpp2_mdp3_fg>; + mdp3-fg3 = <&svpp3_mdp3_fg>; + mdp3-tcc0 = <&mdp3_tcc0>; + mdp3-tcc1 = <&svpp1_mdp3_tcc>; + mdp3-ovl0 = <&mdp3_ovl0>; + mdp3-ovl1 = <&svpp1_mdp3_ovl>; + mdp3-pad0 = <&mdp3_pad0>; + mdp3-pad1 = <&svpp1_mdp3_pad>; + mdp3-pad2 = <&svpp2_mdp3_pad>; + mdp3-pad3 = <&svpp3_mdp3_pad>; + mdp3-split = <&vpp_split0>; + mdp3-merge2 = <&svpp2_mdp3_merge>; + mdp3-merge3 = <&svpp3_mdp3_merge>; + }; + + mdp3_fg0: mdp_fg0@14002000 { + compatible = "mediatek,mt8195-mdp3-fg"; + mediatek,mdp3-id = <0>; + reg = <0 0x14002000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x2000 0x1000>; + interrupts = ; + clocks = <&vppsys0 CLK_VPP0_MDP_FG>; + clock-names = "MDP_FG0"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3_stitch0: mdp_stich0@14003000 { + compatible = "mediatek,mt8195-mdp3-stitch"; + mediatek,mdp3-id = <0>; + reg = <0 0x14003000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x3000 0x1000>; + interrupts = ; + clocks = <&vppsys0 CLK_VPP0_STITCH>; + clock-names = "MDP_STITCH"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3_hdr0: mdp_hdr0@14004000 { + compatible = "mediatek,mt8195-mdp3-hdr"; + mediatek,mdp3-id = <0>; + reg = <0 0x14004000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x4000 0x1000>; + interrupts = ; + clocks = <&vppsys0 CLK_VPP0_MDP_HDR>; + clock-names = "MDP_HDR0"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3_aal0: mdp_aal0@14005000 { + compatible = "mediatek,mt8195-mdp3-aal"; + mediatek,mdp3-id = <0>; + reg = <0 0x14005000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x5000 0x1000>; + interrupts = ; + clocks = <&vppsys0 CLK_VPP0_MDP_AAL>; + clock-names = "MDP_AAL0"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3_rsz0: mdp_rsz0@14006000 { + compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; + mediatek,mdp3-id = <0>; + reg = <0 0x14006000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x6000 0x1000>; + interrupts = ; + clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>; + clock-names = "MDP_RSZ0"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3_tdshp0: mdp_tdshp0@14007000 { + compatible = "mediatek,mt8195-mdp3-tdshp"; + mediatek,mdp3-id = <0>; + reg = <0 0x14007000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x7000 0x1000>; + interrupts = ; + clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>; + clock-names = "MDP_TDSHP0"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3_color0: mdp_color0@14008000 { + compatible = "mediatek,mt8195-mdp3-color"; + mediatek,mdp3-id = <0>; + reg = <0 0x14008000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x8000 0x1000>; + interrupts = ; + clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>; + clock-names = "MDP_COLOR0"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3_ovl0: mdp_ovl0@14009000 { + compatible = "mediatek,mt8195-mdp3-ovl"; + mediatek,mdp3-id = <0>; + reg = <0 0x14009000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x9000 0x1000>; + interrupts = ; + clocks = <&vppsys0 CLK_VPP0_MDP_OVL>; + clock-names = "MDP_OVL0"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3_pad0: mdp_pad0@1400a000 { + compatible = "mediatek,mt8195-mdp3-pad"; + mediatek,mdp3-id = <0>; + reg = <0 0x1400a000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0xa000 0x1000>; + interrupts = ; + clocks = <&vppsys0 CLK_VPP0_PADDING>; + clock-names = "MDP_PAD0"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3_tcc0: mdp_tcc0@1400b000 { + compatible = "mediatek,mt8195-mdp3-tcc"; + mediatek,mdp3-id = <0>; + reg = <0 0x1400b000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0xb000 0x1000>; + interrupts = ; + clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; + clock-names = "MDP_TCC0"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3_wrot0: mdp_wrot0@1400c000 { + compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; + mediatek,mdp3-id = <0>; + reg = <0 0x1400c000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0xc000 0x1000>; + interrupts = ; + clocks = <&vppsys0 CLK_VPP0_MDP_WROT>; + clock-names = "MDP_WROT0"; + iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + smi_common2: smi@1400e000 { compatible = "mediatek,mt8195-smi-common"; mediatek,common-id = <2>; @@ -1017,6 +1253,34 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; }; + vpp0_mutex: vpp0_mutex@1400f000 { + compatible = "mediatek,mt8195-vpp0-mutex"; + reg = <0 0x1400f000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0xf000 0x1000>; + interrupts = ; + #clocks = <&vppsys0 CLK_VPP0_MUTEX>; + #clock-names = "MDP_MUTEX0"; + clocks = <&vppsys0 CLK_VPP0_MUTEX>; + clock-names = "MDP_MUTEX0"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + mediatek,gce-events = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + smi_common1: smi@14012000 { compatible = "mediatek,mt8195-smi-common"; mediatek,common-id = <1>; @@ -1098,9 +1362,22 @@ vppsys1: syscon@14f00000 { compatible = "mediatek,mt8195-vppsys1", "syscon"; reg = <0 0x14f00000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0 0x1000>; #clock-cells = <1>; }; + vpp1_mutex: vpp1_mutex@14f01000 { + compatible = "mediatek,mt8195-vpp1-mutex"; + reg = <0 0x14f01000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0x1000 0x1000>; + interrupts = ; + #clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; + #clock-names = "DISP_MUTEX"; + clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; + clock-names = "DISP_MUTEX"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + larb5: larb@14f02000 { compatible = "mediatek,mt8195-smi-larb"; reg = <0 0x14f02000 0 0x1000>; @@ -1125,7 +1402,396 @@ clock-names = "apb", "smi", "gals", "gals1"; power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; }; - + + vpp_split0: vpp_split0@14f06000 { + compatible = "mediatek,mt8195-mdp3-split"; + mediatek,mdp3-id = <1>; + reg = <0 0x14f06000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0x6000 0x1000>; + interrupts = , + ; + clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>, + <&vppsys1 CLK_VPP1_HDMI_META>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>, + <&vppsys1 CLK_VPP1_DGI_IN>, + <&vppsys1 CLK_VPP1_DGI_OUT>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_DGI>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_26M>; + clock-names = "MDP_SPLIT", + "HDMI_META", + "SPLIT_HDMI", + "DGI_IN", + "DGI_OUT", + "SPLIT_DGI", + "VPP_SPLIT_26M"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp1_mdp3_tcc: svpp1_mdp_tcc@14f07000 { + compatible = "mediatek,mt8195-mdp3-tcc"; + mediatek,mdp3-id = <1>; + reg = <0 0x14f07000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0x7000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>; + clock-names = "MDP_TCC1"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp1_mdp3_rdma: svpp1_mdp_rdma@14f08000 { + compatible = "mediatek,mt8195-mdp3", + "mediatek,mt8183-mdp3-rdma"; + mediatek,mdp3-id = <1>; + reg = <0 0x14f08000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0x8000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>, + <&topckgen CLK_TOP_CFG_VPP1>, + <&topckgen CLK_TOP_CFG_26M_VPP1>; + clock-names = "MDP_RDMA1", + "TOP_CFG_VPP1", + "TOP_CFG_26M_VPP1"; + iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>, + <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>, + <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>, + <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp2_mdp3_rdma: svpp2_mdp_rdma@14f09000 { + compatible = "mediatek,mt8195-mdp3-rdma", "mediatek,mt8183-mdp3-rdma"; + mediatek,mdp3-id = <2>; + reg = <0 0x14f09000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0x9000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>, + <&topckgen CLK_TOP_CFG_VPP1>, + <&topckgen CLK_TOP_CFG_26M_VPP1>; + clock-names = "MDP_RDMA2", + "TOP_CFG_VPP1", + "TOP_CFG_26M_VPP1"; + iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp3_mdp3_rdma: svpp3_mdp_rdma@14f0a000 { + compatible = "mediatek,mt8195-mdp3-rdma", "mediatek,mt8183-mdp3-rdma"; + mediatek,mdp3-id = <3>; + reg = <0 0x14f0a000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0xa000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>, + <&topckgen CLK_TOP_CFG_VPP1>, + <&topckgen CLK_TOP_CFG_26M_VPP1>; + clock-names = "MDP_RDMA3", + "TOP_CFG_VPP1", + "TOP_CFG_26M_VPP1"; + iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp1_mdp3_fg: svpp1_mdp_fg@14f0b000 { + compatible = "mediatek,mt8195-mdp3-fg"; + mediatek,mdp3-id = <1>; + reg = <0 0x14f0b000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0xb000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>; + clock-names = "MDP_FG1"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp2_mdp3_fg: svpp2_mdp_fg@14f0c000 { + compatible = "mediatek,mt8195-mdp3-fg"; + mediatek,mdp3-id = <2>; + reg = <0 0x14f0c000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0xc000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>; + clock-names = "MDP_FG2"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp3_mdp3_fg: svpp3_mdp_fg@14f0d000 { + compatible = "mediatek,mt8195-mdp3-fg"; + mediatek,mdp3-id = <3>; + reg = <0 0x14f0d000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0xd000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>; + clock-names = "MDP_FG3"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp1_mdp3_hdr: svpp1_mdp_hdr@14f0e000 { + compatible = "mediatek,mt8195-mdp3-hdr"; + mediatek,mdp3-id = <1>; + reg = <0 0x14f0e000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0xe000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>; + clock-names = "MDP_HDR1"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp2_mdp3_hdr: svpp2_mdp_hdr@14f0f000 { + compatible = "mediatek,mt8195-mdp3-hdr"; + mediatek,mdp3-id = <2>; + reg = <0 0x14f0f000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0xf000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>; + clock-names = "MDP_HDR2"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp3_mdp3_hdr: svpp3_mdp_hdr@14f10000 { + compatible = "mediatek,mt8195-mdp3-hdr"; + mediatek,mdp3-id = <3>; + reg = <0 0x14f10000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>; + clock-names = "MDP_HDR3"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp1_mdp3_aal: svpp1_mdp_aal@14f11000 { + compatible = "mediatek,mt8195-mdp3-aal"; + mediatek,mdp3-id = <1>; + reg = <0 0x14f11000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0x1000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>; + clock-names = "MDP_AAL1"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp2_mdp3_aal: svpp2_mdp_aal@14f12000 { + compatible = "mediatek,mt8195-mdp3-aal"; + mediatek,mdp3-id = <2>; + reg = <0 0x14f12000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0x2000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>; + clock-names = "MDP_AAL2"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp3_mdp3_aal: svpp3_mdp_aal@14f13000 { + compatible = "mediatek,mt8195-mdp3-aal"; + mediatek,mdp3-id = <3>; + reg = <0 0x14f13000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0x3000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>; + clock-names = "MDP_AAL3"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp1_mdp3_rsz: svpp1_mdp_rsz@14f14000 { + compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; + mediatek,mdp3-id = <1>; + reg = <0 0x14f14000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0x4000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>; + clock-names = "MDP_RSZ1"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp2_mdp3_rsz: svpp2_mdp_rsz@14f15000 { + compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; + mediatek,mdp3-id = <2>; + reg = <0 0x14f15000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0x5000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>, + <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; + clock-names = "MDP_RSZ2"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp3_mdp3_rsz: svpp3_mdp_rsz@14f16000 { + compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; + mediatek,mdp3-id = <3>; + reg = <0 0x14f16000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0x6000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>, + <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; + clock-names = "MDP_RSZ3"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp1_mdp3_tdshp: svpp1_mdp_tdshp@14f17000 { + compatible = "mediatek,mt8195-mdp3-tdshp"; + mediatek,mdp3-id = <1>; + reg = <0 0x14f17000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0x7000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>; + clock-names = "MDP_TDSHP1"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp2_mdp3_tdshp: svpp2_mdp_tdshp@14f18000 { + compatible = "mediatek,mt8195-mdp3-tdshp"; + mediatek,mdp3-id = <2>; + reg = <0 0x14f18000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0x8000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>; + clock-names = "MDP_TDSHP2"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp3_mdp3_tdshp: svpp3_mdp_tdshp@14f19000 { + compatible = "mediatek,mt8195-mdp3-tdshp"; + mediatek,mdp3-id = <3>; + reg = <0 0x14f19000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0x9000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>; + clock-names = "MDP_TDSHP3"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp2_mdp3_merge: svpp2_mdp_merge@14f1a000 { + compatible = "mediatek,mt8195-mdp3-merge"; + mediatek,mdp3-id = <2>; + reg = <0 0x14f1a000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0xa000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; + clock-names = "MDP_MERGE2"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp3_mdp3_merge: svpp3_mdp_merge@14f1b000 { + compatible = "mediatek,mt8195-mdp3-merge"; + mediatek,mdp3-id = <3>; + reg = <0 0x14f1b000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0xb000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; + clock-names = "MDP_MERGE3"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp1_mdp3_color: svpp1_mdp_color@14f1c000 { + compatible = "mediatek,mt8195-mdp3-color"; + mediatek,mdp3-id = <1>; + reg = <0 0x14f1c000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0xc000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>; + clock-names = "MDP_COLOR1"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp2_mdp3_color: svpp2_mdp_color@14f1d000 { + compatible = "mediatek,mt8195-mdp3-color"; + mediatek,mdp3-id = <2>; + reg = <0 0x14f1d000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0xd000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>; + clock-names = "MDP_COLOR2"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp3_mdp3_color: svpp3_mdp_color@14f1e000 { + compatible = "mediatek,mt8195-mdp3-color"; + mediatek,mdp3-id = <3>; + reg = <0 0x14f1e000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0xe000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>; + clock-names = "MDP_COLOR3"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp1_mdp3_ovl: svpp1_mdp_ovl@14f1f000 { + compatible = "mediatek,mt8195-mdp3-ovl"; + mediatek,mdp3-id = <1>; + reg = <0 0x14f1f000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0xf000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>; + clock-names = "MDP_OVL1"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp1_mdp3_pad: svpp1_mdp_pad@14f20000 { + compatible = "mediatek,mt8195-mdp3-pad"; + mediatek,mdp3-id = <1>; + reg = <0 0x14f20000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f2XXXX 0 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>; + clock-names = "MDP_PAD1"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp2_mdp3_pad: svpp2_mdp_pad@14f21000 { + compatible = "mediatek,mt8195-mdp3-pad"; + mediatek,mdp3-id = <2>; + reg = <0 0x14f21000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f2XXXX 0x1000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>; + clock-names = "MDP_PAD2"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp3_mdp3_pad: svpp3_mdp_pad@14f22000 { + compatible = "mediatek,mt8195-mdp3-pad"; + mediatek,mdp3-id = <3>; + reg = <0 0x14f22000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f2XXXX 0x2000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>; + clock-names = "MDP_PAD3"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp1_mdp3_wrot: svpp1_mdp_wrot@14f23000 { + compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; + mediatek,mdp3-id = <1>; + reg = <0 0x14f23000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f2XXXX 0x3000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>; + clock-names = "MDP_WROT1"; + iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp2_mdp3_wrot: svpp2_mdp_wrot@14f24000 { + compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; + mediatek,mdp3-id = <2>; + reg = <0 0x14f24000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f2XXXX 0x4000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>; + clock-names = "MDP_WROT2"; + iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + svpp3_mdp3_wrot: svpp3_mdp_wrot@14f25000 { + compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; + mediatek,mdp3-id = <3>; + reg = <0 0x14f25000 0 0x1000>; + mediatek,gce-client-reg = <&gce0 SUBSYS_14f2XXXX 0x5000 0x1000>; + interrupts = ; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>; + clock-names = "MDP_WROT3"; + iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + imgsys: syscon@15000000 { compatible = "mediatek,mt8195-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; @@ -1557,7 +2223,7 @@ reg = <0 0x1c100000 0 0x1000>; #clock-cells = <1>; }; - + larb2: larb@1c102000 { compatible = "mediatek,mt8195-smi-larb"; reg = <0 0x1c102000 0 0x1000>; @@ -1580,7 +2246,7 @@ <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; clock-names = "apb", "smi", "gals"; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; - }; + }; }; bring-up { From patchwork Wed Oct 20 07:14:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "roy-cw.yeh" X-Patchwork-Id: 12571785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A34D8C433F5 for ; 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bh=P4sEXPPB1KiDPhyuCudlCmh+FIGjr7/qW5Jv8DjRCgQ=; b=i/uOzCnhxv2C/L nvlMKIjgF1W37bvW+0Oc2ppdsrhmLu9jtlUGafqyuFbdEMZNSrGvrocYN3ZGfpprnzuPaCoelg77U FyR9bfCKb69Uv5SFHKSFJa1MLMQQpHKyTXwe62Rg3Mdq/rZ/cOzpcj6FBaY8+O4GrN7ZyF1jwHqxY Aexn0uKuhvSUdMJ88cThbOah3hW8bwyn71uR1bcEoc010bQSALGrPiHLScYUNxEyph+cldONQuaBy rk0NDGZUS3oot7qPZSZqRGtaxCoBHq/dgFz7yjWlxW5NdwS8enSyDxnGuLgXS8f39REbf8mSqAwPj OJL7kHtj0aivsPKi9s1g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1md60p-003dQX-FN; Wed, 20 Oct 2021 07:27:47 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1md5yg-003cfG-CI; Wed, 20 Oct 2021 07:25:38 +0000 X-UUID: 0a62d64b6c11441db55e5b358f5a80b0-20211020 X-UUID: 0a62d64b6c11441db55e5b358f5a80b0-20211020 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1414430235; Wed, 20 Oct 2021 00:25:30 -0700 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Oct 2021 00:15:29 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Oct 2021 15:15:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Oct 2021 15:15:27 +0800 From: roy-cw.yeh To: Rob Herring , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Kuang Hu CC: Mauro Carvalho Chehab , Fabien Parent , "Roy-CW . Yeh" , "jason-jh . lin" , daoyuan huang , Ping-Hsun Wu , Moudy Ho , "river . cheng" , Enric Balletbo i Serra , Yongqiang Niu , , , , , Subject: [PATCH v2 6/9] soc: mediatek: mmsys: support mt8195 vppsys0/1 Date: Wed, 20 Oct 2021 15:14:45 +0800 Message-ID: <20211020071448.14187-7-roy-cw.yeh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211020071448.14187-1-roy-cw.yeh@mediatek.com> References: <20211020071448.14187-1-roy-cw.yeh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211020_002534_502388_AFBEEBD7 X-CRM114-Status: GOOD ( 13.04 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: "Roy-CW.Yeh" Add mt8195 vppsys clock driver name and routing table to the driver data of mtk-mmsys. Signed-off-by: Roy-CW.Yeh Acked-By: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mt8195-mmsys.h | 716 +++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 42 ++ drivers/soc/mediatek/mtk-mmsys.h | 3 + include/linux/soc/mediatek/mtk-mmsys.h | 4 + 4 files changed, 765 insertions(+) diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h index 0c97a5f016c1..8f843275ba34 100644 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -111,4 +111,720 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { } }; +/* VPPSYS0 MOUT */ +#define MT8195_VPPSYS0_STITCH_MOUT_EN 0xF38 + #define MT8195_VPPSYS0_STITCH_MOUT_TO_PQ_SEL_IN BIT(0) + #define MT8195_VPPSYS0_STITCH_MOUT_TO_VPP1_SEL_IN BIT(1) +#define MT8195_VPPSYS0_WARP0_MOUT_EN 0xF3C + #define MT8195_VPPSYS0_WARP0_MOUT_TO_PQ_SEL_IN BIT(0) + #define MT8195_VPPSYS0_WARP0_MOUT_TO_VPP1_SEL_IN BIT(1) +#define MT8195_VPPSYS0_WARP1_MOUT_EN 0xF40 + #define MT8195_VPPSYS0_WARP1_MOUT_TO_PQ_SEL_IN BIT(0) + #define MT8195_VPPSYS0_WARP1_MOUT_TO_VPP1_SEL_IN BIT(1) +#define MT8195_VPPSYS0_FG_MOUT_EN 0xF44 + #define MT8195_VPPSYS0_FG_MOUT_TO_PQ_SEL_IN BIT(0) + #define MT8195_VPPSYS0_FG_MOUT_TO_VPP1_SEL_IN BIT(1) + +/* VPPSYS1 MOUT */ +#define MT8195_SVPP2_SRC_SEL_MOUT_EN 0xF50 + #define MT8195_SVPP2_MDP_HDR BIT(0) + #define MT8195_SVPP1_HDR_SRC_SEL BIT(1) +#define MT8195_SVPP3_SRC_SEL_MOUT_EN 0xF7C + #define MT8195_SVPP3_MDP_HDR BIT(0) + #define MT8195_VPP0_DL1_SRC_SEL BIT(1) +#define MT8195_SVPP2_MDP_HDR_MOUT_EN 0xF4C + #define MT8195_SVPP2_MDP_AAL BIT(0) + #define MT8195_SVPP1_MDP_AAL_SEL BIT(1) +#define MT8195_SVPP3_MDP_HDR_MOUT_EN 0xF78 + #define MT8195_SVPP3_MDP_AAL BIT(0) + +/* VPPSYS0 SEL_IN */ +#define MT8195_VPPSYS0_PQ_SEL_IN 0xF04 + #define MT8195_VPPSYS0_PQ_SEL_IN_FROM_STITCH 0 + #define MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP0 1 + #define MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP1 2 + #define MT8195_VPPSYS0_PQ_SEL_IN_FROM_MDP_FG 3 +#define MT8195_VPPSYS0_VPP1_SEL_IN 0xF08 + #define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_PADDING_SOUT 0 + #define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_STITCH 1 + #define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP0 2 + #define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP1 3 + #define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_MDP_FG 4 +#define MT8195_VPPSYS0_HDR_SEL_IN 0xF0C + #define MT8195_VPPSYS0_HDR_SEL_IN_FROM_PQ_SOUT 0 + #define MT8195_VPPSYS0_HDR_SEL_IN_FROM_TCC_SOUT 1 + #define MT8195_VPPSYS0_HDR_SEL_IN_FROM_VPP1_IN_SOUT 2 +#define MT8195_VPPSYS0_AAL_SEL_IN 0xF18 + #define MT8195_VPPSYS0_AAL_SEL_IN_FROM_MDP_HDR 0 + #define MT8195_VPPSYS0_AAL_SEL_IN_FROM_VPP1_IN_SOUT 1 +#define MT8195_VPPSYS0_TCC_SEL_IN 0xF10 + #define MT8195_VPPSYS0_TCC_SEL_IN_FROM_PADDING_SOUT 0 + #define MT8195_VPPSYS0_TCC_SEL_IN_FROM_PQ_SOUT 1 +#define MT8195_VPPSYS0_WROT_SEL_IN 0xF14 + #define MT8195_VPPSYS0_WROT_SEL_IN_FROM_TCC_SOUT 0 + #define MT8195_VPPSYS0_WROT_SEL_IN_FROM_PADDING_SOUT 1 + #define MT8195_VPPSYS0_WROT_SEL_IN_FROM_MDP_RDMA 2 + +/* VPPSYS1 SEL_IN */ +#define MT8195_SVPP1_SRC_SEL_IN 0xF1C + #define MT8195_SVPP1_SRC_SEL_IN_FROM_SVPP1_MDP_FG 0 + #define MT8195_SVPP1_SRC_SEL_IN_FROM_VPP0_SRC_SOUT 1 +#define MT8195_SVPP2_SRC_SEL_IN 0xF38 + #define MT8195_SVPP2_SRC_SEL_IN_FROM_SVPP2_MDP_FG 0 + #define MT8195_SVPP2_SRC_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT 1 +#define MT8195_SVPP3_SRC_SEL_IN 0xF64 + #define MT8195_SVPP3_SRC_SEL_IN_FROM_SVPP3_MDP_FG 0 + #define MT8195_SVPP3_SRC_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT 1 +#define MT8195_SVPP1_HDR_SRC_SEL_IN 0xF24 + #define MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT 0 + #define MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT 1 + #define MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP2_SRC_SEL_MOUT 2 +#define MT8195_SVPP1_MDP_AAL_SEL_IN 0xF54 + #define MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP1_MDP_HDR 0 + #define MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP2_MDP_HDR_MOUT 1 +#define MT8195_SVPP1_TCC_SEL_IN 0xF30 + #define MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_PATH_SOUT 0 + #define MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT 1 +#define MT8195_VPP0_DL1_SRC_SEL_IN 0xF80 + #define MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_SRC_SEL_MOUT 0 + #define MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_MDP_HDR_MOUT 1 + #define MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT 2 +#define MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN 0xF44 + #define MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_SVPP2_MDP_AAL 0 + #define MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT 1 +#define MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN 0xF70 + #define MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_SVPP3_MDP_AAL 0 + #define MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT 1 +#define MT8195_SVPP1_WROT_SRC_SEL_IN 0xF2c + #define MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT 0 + #define MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT 1 + #define MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_MDP_RDMA_SOUT 2 +#define MT8195_SVPP2_WROT_SRC_SEL_IN 0xF40 + #define MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT 0 + #define MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_VPP_PAD 1 + #define MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_MDP_RDMA_SOUT 2 +#define MT8195_SVPP3_WROT_SRC_SEL_IN 0xF6c + #define MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_VPP0_SRC_SOUT 0 + #define MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_VPP_PAD 1 + #define MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_MDP_RDMA_SOUT 2 + +/* VPPSYS0 SEL_OUT */ +#define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN 0xF20 + #define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH 0 + #define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP0_MOUT 1 +#define MT8195_VPPSYS0_WARP1_SOUT_SEL_IN 0xF24 + #define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH 0 + #define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP1_MOUT 1 +#define MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN 0xF1C + #define MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_FG 0 + #define MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_WROT_SEL_IN 1 +#define MT8195_VPPSYS0_PQ_SOUT_SEL_IN 0xF28 + #define MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_PQ_SEL_IN 0 + #define MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_TCC_SEL_IN 1 +#define MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN 0xF34 + #define MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_HDR_SEL_IN 0 + #define MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_AAL_SEL_IN 1 + #define MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_MDP_RSZ 2 +#define MT8195_VPPSYS0_PADDING_SOUT_SEL_IN 0xF2C + #define MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_TCC_SEL_IN 0 + #define MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_WROT_SEL_IN 1 + #define MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_VPP1_SEL_IN 2 +#define MT8195_VPPSYS0_TCC_SOUT_SEL_IN 0xF30 + #define MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_WROT_SEL_IN 0 + #define MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_HDR_SEL_IN 1 + +/* VPPSYS1 SEL_OUT */ +#define MT8195_SVPP1_MDP_RDMA_SOUT_SEL 0xF18 + #define MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_MDP_FG 0 + #define MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_RSZ 1 + #define MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL 2 +#define MT8195_SVPP2_MDP_RDMA_SOUT_SEL 0xF90 + #define MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_FG 0 + #define MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL 1 +#define MT8195_SVPP3_MDP_RDMA_SOUT_SEL 0xF60 + #define MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_MDP_FG 0 + #define MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL 1 +#define MT8195_VPP0_SRC_SOUT_SEL 0xF8C + #define MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP1_SRC_SEL 0 + #define MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_MDP_RSZ 1 + #define MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL 2 +#define MT8195_SVPP1_SRC_SEL_SOUT_SEL 0xF20 + #define MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL 0 + #define MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_TCC_SEL 1 + #define MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_VPP0_DL1_SRC_SEL 2 +#define MT8195_SVPP2_COLOR_SOUT_SEL 0xF3c + #define MT8195_SVPP2_COLOR_SOUT_SEL_TO_SVPP2_VPP_PAD 0 + #define MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO0_DL0_RELAY 1 + #define MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO1_DL0_RELAY 2 +#define MT8195_SVPP3_COLOR_SOUT_SEL 0xF68 + #define MT8195_SVPP3_COLOR_SOUT_SEL_TO_SVPP3_VPP_PAD 0 + #define MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO0_DL1_RELAY 1 + #define MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO1_DL1_RELAY 2 +#define MT8195_SVPP1_TCC_SOUT_SEL 0xF34 + #define MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL 0 + #define MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL 1 +#define MT8195_SVPP1_PATH_SOUT_SEL 0xF28 + #define MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_TCC_SEL 0 + #define MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL 1 + #define MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL 2 + +/* VPPSYS0 */ +#define VPPSYS0_HW_DCM_1ST_DIS0 0x050 + +/* VPPSYS1 */ +#define VPPSYS1_HW_DCM_1ST_DIS0 0x150 +#define VPPSYS1_HW_DCM_1ST_DIS1 0x160 +#define VPPSYS1_HW_DCM_2ND_DIS0 0x1a0 +#define VPPSYS1_HW_DCM_2ND_DIS1 0x1b0 +#define VPP0_DL_IRELAY_WR 0x920 +#define SVPP2_BUF_BF_RSZ_SWITCH 0xf48 +#define SVPP3_BUF_BF_RSZ_SWITCH 0xf74 + +static const u32 mmsys_mt8195_mdp_vppsys_config_table[] = { + VPPSYS0_HW_DCM_1ST_DIS0, + VPP0_DL_IRELAY_WR, + VPPSYS1_HW_DCM_1ST_DIS0, + VPPSYS1_HW_DCM_1ST_DIS1, + VPPSYS1_HW_DCM_2ND_DIS0, + VPPSYS1_HW_DCM_2ND_DIS1, + SVPP2_BUF_BF_RSZ_SWITCH, + SVPP3_BUF_BF_RSZ_SWITCH, +}; + +static const struct mtk_mmsys_routes mmsys_mt8195_mdp_routing_table[] = { + /* VPPSYS0 MOUT */ + { + MDP_COMP_STITCH, MDP_COMP_PQ0_SOUT, + MT8195_VPPSYS0_STITCH_MOUT_EN, + MT8195_VPPSYS0_STITCH_MOUT_TO_PQ_SEL_IN, + MT8195_VPPSYS0_STITCH_MOUT_TO_PQ_SEL_IN + }, { + MDP_COMP_STITCH, MDP_COMP_VPP0_SOUT, + MT8195_VPPSYS0_STITCH_MOUT_EN, + MT8195_VPPSYS0_STITCH_MOUT_TO_VPP1_SEL_IN, + MT8195_VPPSYS0_STITCH_MOUT_TO_VPP1_SEL_IN + }, { + MDP_COMP_CAMIN, MDP_COMP_PQ0_SOUT, + MT8195_VPPSYS0_WARP0_MOUT_EN, + MT8195_VPPSYS0_WARP0_MOUT_TO_PQ_SEL_IN, + MT8195_VPPSYS0_WARP0_MOUT_TO_PQ_SEL_IN + }, { + MDP_COMP_CAMIN, MDP_COMP_VPP0_SOUT, + MT8195_VPPSYS0_WARP0_MOUT_EN, + MT8195_VPPSYS0_WARP0_MOUT_TO_VPP1_SEL_IN, + MT8195_VPPSYS0_WARP0_MOUT_TO_VPP1_SEL_IN + }, + { + MDP_COMP_CAMIN2, MDP_COMP_PQ0_SOUT, + MT8195_VPPSYS0_WARP1_MOUT_EN, + MT8195_VPPSYS0_WARP1_MOUT_TO_PQ_SEL_IN, + MT8195_VPPSYS0_WARP1_MOUT_TO_PQ_SEL_IN + }, { + MDP_COMP_CAMIN2, MDP_COMP_VPP0_SOUT, + MT8195_VPPSYS0_WARP1_MOUT_EN, + MT8195_VPPSYS0_WARP1_MOUT_TO_VPP1_SEL_IN, + MT8195_VPPSYS0_WARP1_MOUT_TO_VPP1_SEL_IN + }, { + MDP_COMP_FG0, MDP_COMP_PQ0_SOUT, + MT8195_VPPSYS0_FG_MOUT_EN, + MT8195_VPPSYS0_FG_MOUT_TO_PQ_SEL_IN, + MT8195_VPPSYS0_FG_MOUT_TO_PQ_SEL_IN + }, { + MDP_COMP_FG0, MDP_COMP_VPP0_SOUT, + MT8195_VPPSYS0_FG_MOUT_EN, + MT8195_VPPSYS0_FG_MOUT_TO_VPP1_SEL_IN, + MT8195_VPPSYS0_FG_MOUT_TO_VPP1_SEL_IN + }, + /* VPPSYS1 MOUT */ + { + MDP_COMP_TO_SVPP2MOUT, MDP_COMP_HDR2, + MT8195_SVPP2_SRC_SEL_MOUT_EN, + MT8195_SVPP2_MDP_HDR, + MT8195_SVPP2_MDP_HDR + }, { + MDP_COMP_TO_SVPP2MOUT, MDP_COMP_HDR1, + MT8195_SVPP2_SRC_SEL_MOUT_EN, + MT8195_SVPP1_HDR_SRC_SEL, + MT8195_SVPP1_HDR_SRC_SEL + }, { + MDP_COMP_TO_SVPP3MOUT, MDP_COMP_HDR3, + MT8195_SVPP3_SRC_SEL_MOUT_EN, + MT8195_SVPP3_MDP_HDR, + MT8195_SVPP3_MDP_HDR + }, { + MDP_COMP_TO_SVPP3MOUT, MDP_COMP_VPP1_SOUT, + MT8195_SVPP3_SRC_SEL_MOUT_EN, + MT8195_VPP0_DL1_SRC_SEL, + MT8195_VPP0_DL1_SRC_SEL + }, { + MDP_COMP_HDR2, MDP_COMP_AAL2, + MT8195_SVPP2_MDP_HDR_MOUT_EN, + MT8195_SVPP2_MDP_AAL, + MT8195_SVPP2_MDP_AAL + }, { + MDP_COMP_HDR2, MDP_COMP_AAL1, + MT8195_SVPP2_MDP_HDR_MOUT_EN, + MT8195_SVPP1_MDP_AAL_SEL, + MT8195_SVPP1_MDP_AAL_SEL + }, { + MDP_COMP_HDR3, MDP_COMP_AAL3, + MT8195_SVPP3_MDP_HDR_MOUT_EN, + MT8195_SVPP3_MDP_AAL, + MT8195_SVPP3_MDP_AAL + }, { + MDP_COMP_HDR3, MDP_COMP_VPP1_SOUT, + MT8195_SVPP3_MDP_HDR_MOUT_EN, + MT8195_VPP0_DL1_SRC_SEL, + MT8195_VPP0_DL1_SRC_SEL + }, + /* VPPSYS0 SEL_IN */ + { + MDP_COMP_STITCH, MDP_COMP_PQ0_SOUT, + MT8195_VPPSYS0_PQ_SEL_IN, + MT8195_VPPSYS0_PQ_SEL_IN_FROM_STITCH, + MT8195_VPPSYS0_PQ_SEL_IN_FROM_STITCH + }, { + MDP_COMP_CAMIN, MDP_COMP_PQ0_SOUT, + MT8195_VPPSYS0_PQ_SEL_IN, + MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP0, + MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP0 + }, { + MDP_COMP_CAMIN2, MDP_COMP_PQ0_SOUT, + MT8195_VPPSYS0_PQ_SEL_IN, + MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP1, + MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP1 + }, { + MDP_COMP_FG0, MDP_COMP_PQ0_SOUT, + MT8195_VPPSYS0_PQ_SEL_IN, + MT8195_VPPSYS0_PQ_SEL_IN_FROM_MDP_FG, + MT8195_VPPSYS0_PQ_SEL_IN_FROM_MDP_FG + }, { + MDP_COMP_PAD0, MDP_COMP_VPP0_SOUT, + MT8195_VPPSYS0_VPP1_SEL_IN, + MT8195_VPPSYS0_VPP1_SEL_IN_FROM_PADDING_SOUT, + MT8195_VPPSYS0_VPP1_SEL_IN_FROM_PADDING_SOUT + }, { + MDP_COMP_STITCH, MDP_COMP_VPP0_SOUT, + MT8195_VPPSYS0_VPP1_SEL_IN, + MT8195_VPPSYS0_VPP1_SEL_IN_FROM_STITCH, + MT8195_VPPSYS0_VPP1_SEL_IN_FROM_STITCH + }, { + MDP_COMP_CAMIN, MDP_COMP_VPP0_SOUT, + MT8195_VPPSYS0_VPP1_SEL_IN, + MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP0, + MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP0 + }, { + MDP_COMP_CAMIN2, MDP_COMP_VPP0_SOUT, + MT8195_VPPSYS0_VPP1_SEL_IN, + MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP1, + MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP1 + }, { + MDP_COMP_FG0, MDP_COMP_VPP0_SOUT, + MT8195_VPPSYS0_VPP1_SEL_IN, + MT8195_VPPSYS0_VPP1_SEL_IN_FROM_MDP_FG, + MT8195_VPPSYS0_VPP1_SEL_IN_FROM_MDP_FG + }, { + MDP_COMP_PQ0_SOUT, MDP_COMP_HDR0, + MT8195_VPPSYS0_HDR_SEL_IN, + MT8195_VPPSYS0_HDR_SEL_IN_FROM_PQ_SOUT, + MT8195_VPPSYS0_HDR_SEL_IN_FROM_PQ_SOUT + }, { + MDP_COMP_TCC0, MDP_COMP_HDR0, + MT8195_VPPSYS0_HDR_SEL_IN, + MT8195_VPPSYS0_HDR_SEL_IN_FROM_TCC_SOUT, + MT8195_VPPSYS0_HDR_SEL_IN_FROM_TCC_SOUT + }, { + MDP_COMP_VPP1_SOUT, MDP_COMP_HDR0, + MT8195_VPPSYS0_HDR_SEL_IN, + MT8195_VPPSYS0_HDR_SEL_IN_FROM_VPP1_IN_SOUT, + MT8195_VPPSYS0_HDR_SEL_IN_FROM_VPP1_IN_SOUT + }, { + MDP_COMP_HDR0, MDP_COMP_AAL0, + MT8195_VPPSYS0_AAL_SEL_IN, + MT8195_VPPSYS0_AAL_SEL_IN_FROM_MDP_HDR, + MT8195_VPPSYS0_AAL_SEL_IN_FROM_MDP_HDR + }, { + MDP_COMP_VPP1_SOUT, MDP_COMP_AAL0, + MT8195_VPPSYS0_AAL_SEL_IN, + MT8195_VPPSYS0_AAL_SEL_IN_FROM_VPP1_IN_SOUT, + MT8195_VPPSYS0_AAL_SEL_IN_FROM_VPP1_IN_SOUT + }, { + MDP_COMP_PAD0, MDP_COMP_TCC0, + MT8195_VPPSYS0_TCC_SEL_IN, + MT8195_VPPSYS0_TCC_SEL_IN_FROM_PADDING_SOUT, + MT8195_VPPSYS0_TCC_SEL_IN_FROM_PADDING_SOUT + }, { + MDP_COMP_PQ0_SOUT, MDP_COMP_TCC0, + MT8195_VPPSYS0_TCC_SEL_IN, + MT8195_VPPSYS0_TCC_SEL_IN_FROM_PQ_SOUT, + MT8195_VPPSYS0_TCC_SEL_IN_FROM_PQ_SOUT + }, { + MDP_COMP_TCC0, MDP_COMP_WROT0, + MT8195_VPPSYS0_WROT_SEL_IN, + MT8195_VPPSYS0_WROT_SEL_IN_FROM_TCC_SOUT, + MT8195_VPPSYS0_WROT_SEL_IN_FROM_TCC_SOUT + }, { + MDP_COMP_PAD0, MDP_COMP_WROT0, + MT8195_VPPSYS0_WROT_SEL_IN, + MT8195_VPPSYS0_WROT_SEL_IN_FROM_PADDING_SOUT, + MT8195_VPPSYS0_WROT_SEL_IN_FROM_PADDING_SOUT + }, { + MDP_COMP_RDMA0, MDP_COMP_WROT0, + MT8195_VPPSYS0_WROT_SEL_IN, + MT8195_VPPSYS0_WROT_SEL_IN_FROM_MDP_RDMA, + MT8195_VPPSYS0_WROT_SEL_IN_FROM_MDP_RDMA + }, + /* VPPSYS1 SEL_IN */ + { + MDP_COMP_FG1, MDP_COMP_PQ1_SOUT, + MT8195_SVPP1_SRC_SEL_IN, + MT8195_SVPP1_SRC_SEL_IN_FROM_SVPP1_MDP_FG, + MT8195_SVPP1_SRC_SEL_IN_FROM_SVPP1_MDP_FG + }, { + MDP_COMP_VPP0_SOUT, MDP_COMP_PQ1_SOUT, + MT8195_SVPP1_SRC_SEL_IN, + MT8195_SVPP1_SRC_SEL_IN_FROM_VPP0_SRC_SOUT, + MT8195_SVPP1_SRC_SEL_IN_FROM_VPP0_SRC_SOUT + }, { + MDP_COMP_FG2, MDP_COMP_TO_SVPP2MOUT, + MT8195_SVPP2_SRC_SEL_IN, + MT8195_SVPP2_SRC_SEL_IN_FROM_SVPP2_MDP_FG, + MT8195_SVPP2_SRC_SEL_IN_FROM_SVPP2_MDP_FG + }, { + MDP_COMP_SPLIT, MDP_COMP_TO_SVPP2MOUT, + MT8195_SVPP2_SRC_SEL_IN, + MT8195_SVPP2_SRC_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT, + MT8195_SVPP2_SRC_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT + }, { + MDP_COMP_FG3, MDP_COMP_TO_SVPP3MOUT, + MT8195_SVPP3_SRC_SEL_IN, + MT8195_SVPP3_SRC_SEL_IN_FROM_SVPP3_MDP_FG, + MT8195_SVPP3_SRC_SEL_IN_FROM_SVPP3_MDP_FG + }, { + MDP_COMP_SPLIT2, MDP_COMP_TO_SVPP3MOUT, + MT8195_SVPP3_SRC_SEL_IN, + MT8195_SVPP3_SRC_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT, + MT8195_SVPP3_SRC_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT + }, { + MDP_COMP_PQ1_SOUT, MDP_COMP_HDR1, + MT8195_SVPP1_HDR_SRC_SEL_IN, + MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT, + MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT + }, { + MDP_COMP_TCC1, MDP_COMP_HDR1, + MT8195_SVPP1_HDR_SRC_SEL_IN, + MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT, + MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT + }, { + MDP_COMP_TO_SVPP2MOUT, MDP_COMP_HDR1, + MT8195_SVPP1_HDR_SRC_SEL_IN, + MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP2_SRC_SEL_MOUT, + MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP2_SRC_SEL_MOUT + }, { + MDP_COMP_HDR1, MDP_COMP_AAL1, + MT8195_SVPP1_MDP_AAL_SEL_IN, + MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP1_MDP_HDR, + MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP1_MDP_HDR + }, { + MDP_COMP_HDR2, MDP_COMP_AAL1, + MT8195_SVPP1_MDP_AAL_SEL_IN, + MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP2_MDP_HDR_MOUT, + MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP2_MDP_HDR_MOUT + }, { + MDP_COMP_PAD1, MDP_COMP_TCC1, + MT8195_SVPP1_TCC_SEL_IN, + MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_PATH_SOUT, + MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_PATH_SOUT + }, { + MDP_COMP_PQ1_SOUT, MDP_COMP_TCC1, + MT8195_SVPP1_TCC_SEL_IN, + MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT, + MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT + }, { + MDP_COMP_TO_SVPP3MOUT, MDP_COMP_VPP1_SOUT, + MT8195_VPP0_DL1_SRC_SEL_IN, + MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_SRC_SEL_MOUT, + MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_SRC_SEL_MOUT + }, { + MDP_COMP_HDR3, MDP_COMP_VPP1_SOUT, + MT8195_VPP0_DL1_SRC_SEL_IN, + MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_MDP_HDR_MOUT, + MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_MDP_HDR_MOUT + }, { + MDP_COMP_PQ1_SOUT, MDP_COMP_VPP1_SOUT, + MT8195_VPP0_DL1_SRC_SEL_IN, + MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT, + MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT + }, { + MDP_COMP_AAL2, MDP_COMP_RSZ2, + MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN, + MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_SVPP2_MDP_AAL, + MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_SVPP2_MDP_AAL + }, { + MDP_COMP_SPLIT, MDP_COMP_RSZ2, + MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN, + MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT, + MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT + }, { + MDP_COMP_AAL3, MDP_COMP_RSZ3, + MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN, + MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_SVPP3_MDP_AAL, + MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_SVPP3_MDP_AAL + }, { + MDP_COMP_SPLIT2, MDP_COMP_RSZ3, + MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN, + MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT, + MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT + }, { + MDP_COMP_TCC1, MDP_COMP_WROT1, + MT8195_SVPP1_WROT_SRC_SEL_IN, + MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT, + MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT + }, { + MDP_COMP_PAD1, MDP_COMP_WROT1, + MT8195_SVPP1_WROT_SRC_SEL_IN, + MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT, + MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT + }, { + MDP_COMP_RDMA1, MDP_COMP_WROT1, + MT8195_SVPP1_WROT_SRC_SEL_IN, + MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_MDP_RDMA_SOUT, + MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_MDP_RDMA_SOUT + }, { + MDP_COMP_PAD1, MDP_COMP_WROT2, + MT8195_SVPP2_WROT_SRC_SEL_IN, + MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT, + MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT + }, { + MDP_COMP_PAD2, MDP_COMP_WROT2, + MT8195_SVPP2_WROT_SRC_SEL_IN, + MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_VPP_PAD, + MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_VPP_PAD + }, { + MDP_COMP_RDMA2, MDP_COMP_WROT2, + MT8195_SVPP2_WROT_SRC_SEL_IN, + MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_MDP_RDMA_SOUT, + MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_MDP_RDMA_SOUT + }, { + MDP_COMP_VPP0_SOUT, MDP_COMP_WROT3, + MT8195_SVPP3_WROT_SRC_SEL_IN, + MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_VPP0_SRC_SOUT, + MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_VPP0_SRC_SOUT + }, { + MDP_COMP_PAD3, MDP_COMP_WROT3, + MT8195_SVPP3_WROT_SRC_SEL_IN, + MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_VPP_PAD, + MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_VPP_PAD + }, { + MDP_COMP_RDMA3, MDP_COMP_WROT3, + MT8195_SVPP3_WROT_SRC_SEL_IN, + MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_MDP_RDMA_SOUT, + MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_MDP_RDMA_SOUT + }, + /* VPPSYS0 SEL_OUT */ + { + MDP_COMP_WPEI, MDP_COMP_STITCH, + MT8195_VPPSYS0_WARP0_SOUT_SEL_IN, + MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH, + MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH + }, { + MDP_COMP_WPEI, MDP_COMP_CAMIN, + MT8195_VPPSYS0_WARP0_SOUT_SEL_IN, + MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP0_MOUT, + MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP0_MOUT + }, { + MDP_COMP_WPEI2, MDP_COMP_STITCH, + MT8195_VPPSYS0_WARP1_SOUT_SEL_IN, + MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH, + MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH + }, { + MDP_COMP_WPEI2, MDP_COMP_CAMIN2, + MT8195_VPPSYS0_WARP1_SOUT_SEL_IN, + MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP1_MOUT, + MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP1_MOUT + }, { + MDP_COMP_RDMA0, MDP_COMP_FG0, + MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN, + MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_FG, + MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_FG + }, { + MDP_COMP_RDMA0, MDP_COMP_WROT0, + MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN, + MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_WROT_SEL_IN, + MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_WROT_SEL_IN + }, { + MDP_COMP_PQ0_SOUT, MDP_COMP_HDR0, + MT8195_VPPSYS0_PQ_SOUT_SEL_IN, + MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_PQ_SEL_IN, + MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_PQ_SEL_IN + }, { + MDP_COMP_PQ0_SOUT, MDP_COMP_TCC0, + MT8195_VPPSYS0_PQ_SOUT_SEL_IN, + MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_TCC_SEL_IN, + MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_TCC_SEL_IN + }, { + MDP_COMP_VPP1_SOUT, MDP_COMP_HDR0, + MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN, + MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_HDR_SEL_IN, + MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_HDR_SEL_IN + }, { + MDP_COMP_VPP1_SOUT, MDP_COMP_AAL0, + MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN, + MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_AAL_SEL_IN, + MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_AAL_SEL_IN + }, { + MDP_COMP_VPP1_SOUT, MDP_COMP_RSZ2, + MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN, + MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_MDP_RSZ, + MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_MDP_RSZ + }, { + MDP_COMP_PAD0, MDP_COMP_TCC0, + MT8195_VPPSYS0_PADDING_SOUT_SEL_IN, + MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_TCC_SEL_IN, + MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_TCC_SEL_IN + }, { + MDP_COMP_PAD0, MDP_COMP_WROT0, + MT8195_VPPSYS0_PADDING_SOUT_SEL_IN, + MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_WROT_SEL_IN, + MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_WROT_SEL_IN + }, { + MDP_COMP_PAD0, MDP_COMP_VPP0_SOUT, + MT8195_VPPSYS0_PADDING_SOUT_SEL_IN, + MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_VPP1_SEL_IN, + MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_VPP1_SEL_IN + }, { + MDP_COMP_TCC0, MDP_COMP_WROT0, + MT8195_VPPSYS0_TCC_SOUT_SEL_IN, + MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_WROT_SEL_IN, + MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_WROT_SEL_IN + }, { + MDP_COMP_TCC0, MDP_COMP_HDR0, + MT8195_VPPSYS0_TCC_SOUT_SEL_IN, + MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_HDR_SEL_IN, + MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_HDR_SEL_IN + }, + /* VPPSYS1 SEL_OUT */ + { + MDP_COMP_RDMA1, MDP_COMP_FG1, + MT8195_SVPP1_MDP_RDMA_SOUT_SEL, + MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_MDP_FG, + MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_MDP_FG + }, { + MDP_COMP_RDMA1, MDP_COMP_RSZ2, + MT8195_SVPP1_MDP_RDMA_SOUT_SEL, + MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_RSZ, + MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_RSZ + }, { + MDP_COMP_RDMA1, MDP_COMP_WROT1, + MT8195_SVPP1_MDP_RDMA_SOUT_SEL, + MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL, + MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL + }, { + MDP_COMP_RDMA2, MDP_COMP_FG2, + MT8195_SVPP2_MDP_RDMA_SOUT_SEL, + MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_FG, + MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_FG + }, { + MDP_COMP_RDMA2, MDP_COMP_WROT2, + MT8195_SVPP2_MDP_RDMA_SOUT_SEL, + MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL, + MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL + }, { + MDP_COMP_RDMA3, MDP_COMP_FG3, + MT8195_SVPP3_MDP_RDMA_SOUT_SEL, + MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_MDP_FG, + MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_MDP_FG + }, { + MDP_COMP_RDMA3, MDP_COMP_WROT3, + MT8195_SVPP3_MDP_RDMA_SOUT_SEL, + MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL, + MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL + }, { + MDP_COMP_VPP0_SOUT, MDP_COMP_PQ1_SOUT, + MT8195_VPP0_SRC_SOUT_SEL, + MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP1_SRC_SEL, + MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP1_SRC_SEL + }, { + MDP_COMP_VPP0_SOUT, MDP_COMP_RSZ3, + MT8195_VPP0_SRC_SOUT_SEL, + MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_MDP_RSZ, + MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_MDP_RSZ + }, { + MDP_COMP_VPP0_SOUT, MDP_COMP_WROT3, + MT8195_VPP0_SRC_SOUT_SEL, + MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL, + MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL + }, { + MDP_COMP_PQ1_SOUT, MDP_COMP_HDR1, + MT8195_SVPP1_SRC_SEL_SOUT_SEL, + MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL, + MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL + }, { + MDP_COMP_PQ1_SOUT, MDP_COMP_TCC1, + MT8195_SVPP1_SRC_SEL_SOUT_SEL, + MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_TCC_SEL, + MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_TCC_SEL + }, { + MDP_COMP_PQ1_SOUT, MDP_COMP_VPP1_SOUT, + MT8195_SVPP1_SRC_SEL_SOUT_SEL, + MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_VPP0_DL1_SRC_SEL, + MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_VPP0_DL1_SRC_SEL + }, { + MDP_COMP_COLOR2, MDP_COMP_PAD2, + MT8195_SVPP2_COLOR_SOUT_SEL, + MT8195_SVPP2_COLOR_SOUT_SEL_TO_SVPP2_VPP_PAD, + MT8195_SVPP2_COLOR_SOUT_SEL_TO_SVPP2_VPP_PAD + }, { + MDP_COMP_COLOR2, MDP_COMP_VDO0DL0, + MT8195_SVPP2_COLOR_SOUT_SEL, + MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO0_DL0_RELAY, + MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO0_DL0_RELAY + }, { + MDP_COMP_COLOR2, MDP_COMP_VDO1DL0, + MT8195_SVPP2_COLOR_SOUT_SEL, + MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO1_DL0_RELAY, + MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO1_DL0_RELAY + }, { + MDP_COMP_COLOR3, MDP_COMP_PAD3, + MT8195_SVPP3_COLOR_SOUT_SEL, + MT8195_SVPP3_COLOR_SOUT_SEL_TO_SVPP3_VPP_PAD, + MT8195_SVPP3_COLOR_SOUT_SEL_TO_SVPP3_VPP_PAD + }, { + MDP_COMP_COLOR3, MDP_COMP_VDO0DL1, + MT8195_SVPP3_COLOR_SOUT_SEL, + MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO0_DL1_RELAY, + MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO0_DL1_RELAY + }, { + MDP_COMP_COLOR3, MDP_COMP_VDO1DL1, + MT8195_SVPP3_COLOR_SOUT_SEL, + MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO1_DL1_RELAY, + MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO1_DL1_RELAY + }, { + MDP_COMP_TCC1, MDP_COMP_WROT1, + MT8195_SVPP1_TCC_SOUT_SEL, + MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL, + MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL + }, { + MDP_COMP_TCC1, MDP_COMP_HDR1, + MT8195_SVPP1_TCC_SOUT_SEL, + MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL, + MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL + }, { + MDP_COMP_PAD1, MDP_COMP_TCC1, + MT8195_SVPP1_PATH_SOUT_SEL, + MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_TCC_SEL, + MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_TCC_SEL + }, { + MDP_COMP_PAD1, MDP_COMP_WROT1, + MT8195_SVPP1_PATH_SOUT_SEL, + MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL, + MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL + }, { + MDP_COMP_PAD1, MDP_COMP_WROT2, + MT8195_SVPP1_PATH_SOUT_SEL, + MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL, + MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL + }, +}; + #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index cbae8063a187..f73ed33258b9 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -69,6 +69,24 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { .clk_driver = "clk-mt8195-vdo1", }; +static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data = { + .clk_driver = "clk-mt8195-vpp0", + .mdp_routes = mmsys_mt8195_mdp_routing_table, + .mdp_num_routes = ARRAY_SIZE(mmsys_mt8195_mdp_routing_table), + .mdp_mmsys_configs = mmsys_mt8195_mdp_vppsys_config_table, + .mdp_num_mmsys_configs = ARRAY_SIZE(mmsys_mt8195_mdp_vppsys_config_table), + .vppsys = true, +}; + +static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = { + .clk_driver = "clk-mt8195-vpp1", + .mdp_routes = mmsys_mt8195_mdp_routing_table, + .mdp_num_routes = ARRAY_SIZE(mmsys_mt8195_mdp_routing_table), + .mdp_mmsys_configs = mmsys_mt8195_mdp_vppsys_config_table, + .mdp_num_mmsys_configs = ARRAY_SIZE(mmsys_mt8195_mdp_vppsys_config_table), + .vppsys = true, +}; + static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { .clk_driver = "clk-mt8365-mm", .routes = mt8365_mmsys_routing_table, @@ -263,6 +281,18 @@ void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd, } EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_camin_ctrl); +void mtk_mmsys_write_reg(struct device *dev, + struct mmsys_cmdq_cmd *cmd, + u32 alias_id, u32 value, u32 mask) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + const u32 *configs = mmsys->data->mdp_mmsys_configs; + + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, + mmsys->addr + configs[alias_id], value, mask); +} +EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg); + static int mtk_mmsys_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -301,6 +331,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev) if (IS_ERR(clks)) return PTR_ERR(clks); + if (mmsys->data->vppsys) + goto exit; + drm = platform_device_register_data(&pdev->dev, "mediatek-drm", PLATFORM_DEVID_AUTO, NULL, 0); if (IS_ERR(drm)) { @@ -308,6 +341,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev) return PTR_ERR(drm); } +exit: return 0; } @@ -348,6 +382,14 @@ static const struct of_device_id of_match_mtk_mmsys[] = { .compatible = "mediatek,mt8195-vdosys1", .data = &mt8195_vdosys1_driver_data, }, + { + .compatible = "mediatek,mt8195-vppsys0", + .data = &mt8195_vppsys0_driver_data, + }, + { + .compatible = "mediatek,mt8195-vppsys1", + .data = &mt8195_vppsys1_driver_data, + }, { .compatible = "mediatek,mt8365-mmsys", .data = &mt8365_mmsys_driver_data, diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index b24da589ff64..e52a6ff8c843 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -93,6 +93,9 @@ struct mtk_mmsys_driver_data { const struct mtk_mmsys_routes *mdp_routes; const unsigned int mdp_num_routes; const unsigned int *mdp_isp_ctrl; + const u32 *mdp_mmsys_configs; + const unsigned int mdp_num_mmsys_configs; + bool vppsys; }; /* diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index acf4bd3deac1..ab20aaab6b4b 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -191,4 +191,8 @@ void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd, enum mtk_mdp_comp_id id, u32 camin_w, u32 camin_h); +void mtk_mmsys_write_reg(struct device *dev, + struct mmsys_cmdq_cmd *cmd, + u32 alias_id, u32 value, u32 mask); + #endif /* __MTK_MMSYS_H */ From patchwork Wed Oct 20 07:14:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "roy-cw.yeh" X-Patchwork-Id: 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(Exim 4.94.2 #2 (Red Hat Linux)) id 1md5p0-003Y5g-PN; Wed, 20 Oct 2021 07:15:37 +0000 X-UUID: f34e63b30f374cca9c813f93d7209711-20211020 X-UUID: f34e63b30f374cca9c813f93d7209711-20211020 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1797981576; Wed, 20 Oct 2021 00:15:30 -0700 Received: from mtkmbs10n1.mediatek.inc (172.21.101.34) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Oct 2021 00:15:30 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 20 Oct 2021 15:15:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Oct 2021 15:15:27 +0800 From: roy-cw.yeh To: Rob Herring , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Kuang Hu CC: Mauro Carvalho Chehab , Fabien Parent , "Roy-CW . Yeh" , "jason-jh . lin" , daoyuan huang , Ping-Hsun Wu , Moudy Ho , "river . cheng" , Enric Balletbo i Serra , Yongqiang Niu , , , , , Subject: [PATCH v2 7/9] soc: mediatek: mutex: support mt8195 vppsys0/1 Date: Wed, 20 Oct 2021 15:14:46 +0800 Message-ID: <20211020071448.14187-8-roy-cw.yeh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211020071448.14187-1-roy-cw.yeh@mediatek.com> References: <20211020071448.14187-1-roy-cw.yeh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211020_001534_915050_E3B2C29F X-CRM114-Status: GOOD ( 11.94 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: "Roy-CW.Yeh" Add mt8195 mdp mutex info to driver data of mtk-mutex Signed-off-by: Roy-CW.Yeh Acked-By: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-mutex.c | 53 ++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index c100a5249016..0e66b5ff916f 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -122,6 +122,23 @@ #define MT8183_MDP_PIPE_WPEI (MT8183_MUTEX_MDP_START + 2) #define MT8183_MDP_PIPE_WPEI2 (MT8183_MUTEX_MDP_START + 3) +#define MT8195_MUTEX_MDP_MOD_MASK 0xFFFFFFFF +#define MT8195_MUTEX_MDP_MOD1_MASK 0x000000FF +#define MT8195_MUTEX_MDP_SOF_MASK 0x00000007 + +#define MT8195_MDP_PIPE_WPEI 0 +#define MT8195_MDP_PIPE_WPEI2 1 +#define MT8195_MDP_PIPE_RDMA0 2 +#define MT8195_MDP_PIPE_VPP1_SOUT 3 + +#define MT8195_MDP_PIPE_RDMA1 1 +#define MT8195_MDP_PIPE_RDMA2 2 +#define MT8195_MDP_PIPE_RDMA3 3 + +#define MT8195_MDP_PIPE_SPLIT 2 +#define MT8195_MDP_PIPE_SPLIT2 3 +#define MT8195_MDP_PIPE_VPP0_SOUT 4 + struct mtk_mutex { int id; bool claimed; @@ -266,6 +283,22 @@ static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = { [MDP_PIPE_WPEI2] = MT8183_MDP_PIPE_WPEI2, }; +static const unsigned int mt8195_mutex_vpp0_offset[MDP_PIPE_MAX] = { + [MDP_PIPE_WPEI] = MT8195_MDP_PIPE_WPEI, + [MDP_PIPE_WPEI2] = MT8195_MDP_PIPE_WPEI2, + [MDP_PIPE_RDMA0] = MT8195_MDP_PIPE_RDMA0, + [MDP_PIPE_VPP1_SOUT] = MT8195_MDP_PIPE_VPP1_SOUT, +}; + +static const unsigned int mt8195_mutex_vpp1_offset[MDP_PIPE_MAX] = { + [MDP_PIPE_SPLIT] = MT8195_MDP_PIPE_SPLIT, + [MDP_PIPE_SPLIT2] = MT8195_MDP_PIPE_SPLIT2, + [MDP_PIPE_RDMA1] = MT8195_MDP_PIPE_RDMA1, + [MDP_PIPE_RDMA2] = MT8195_MDP_PIPE_RDMA2, + [MDP_PIPE_RDMA3] = MT8195_MDP_PIPE_RDMA3, + [MDP_PIPE_VPP0_SOUT] = MT8195_MDP_PIPE_SPLIT, +}; + static const struct mtk_mutex_data mt2701_mutex_driver_data = { .mutex_mod = mt2701_mutex_mod, .mutex_sof = mt2712_mutex_sof, @@ -306,6 +339,22 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = { .no_clk = true, }; +static const struct mtk_mutex_data mt8195_vpp0_mutex_driver_data = { + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0, + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF, + .mutex_mdp_offset = mt8195_mutex_vpp0_offset, + .mutex_mdp_mod_mask = MT8195_MUTEX_MDP_MOD_MASK, + .mutex_mdp_sof_mask = MT8195_MUTEX_MDP_SOF_MASK, +}; + +static const struct mtk_mutex_data mt8195_vpp1_mutex_driver_data = { + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0, + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF, + .mutex_mdp_offset = mt8195_mutex_vpp1_offset, + .mutex_mdp_mod_mask = MT8195_MUTEX_MDP_MOD_MASK, + .mutex_mdp_sof_mask = MT8195_MUTEX_MDP_SOF_MASK, +}; + struct mtk_mutex *mtk_mutex_get(struct device *dev) { struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); @@ -614,6 +663,10 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8173_mutex_driver_data}, { .compatible = "mediatek,mt8183-disp-mutex", .data = &mt8183_mutex_driver_data}, + { .compatible = "mediatek,mt8195-vpp0-mutex", + .data = &mt8195_vpp0_mutex_driver_data}, + { .compatible = "mediatek,mt8195-vpp1-mutex", + .data = &mt8195_vpp1_mutex_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); From patchwork Wed Oct 20 07:14:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "roy-cw.yeh" X-Patchwork-Id: 12571793 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6774C433FE for ; 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Wed, 20 Oct 2021 00:25:30 -0700 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Oct 2021 00:15:29 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Oct 2021 15:15:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Oct 2021 15:15:27 +0800 From: roy-cw.yeh To: Rob Herring , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Kuang Hu CC: Mauro Carvalho Chehab , Fabien Parent , "Roy-CW . Yeh" , "jason-jh . lin" , daoyuan huang , Ping-Hsun Wu , Moudy Ho , "river . cheng" , Enric Balletbo i Serra , Yongqiang Niu , , , , , Subject: [PATCH v2 8/9] media: platform: mtk-mdp3: support mt8195 Date: Wed, 20 Oct 2021 15:14:47 +0800 Message-ID: <20211020071448.14187-9-roy-cw.yeh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211020071448.14187-1-roy-cw.yeh@mediatek.com> References: <20211020071448.14187-1-roy-cw.yeh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: "Roy-CW.Yeh" Add mt8195 driver Signed-off-by: Roy-CW.Yeh --- drivers/media/platform/mtk-mdp3/mdp_reg_aal.h | 24 + .../media/platform/mtk-mdp3/mdp_reg_color.h | 29 + drivers/media/platform/mtk-mdp3/mdp_reg_fg.h | 23 + drivers/media/platform/mtk-mdp3/mdp_reg_hdr.h | 31 + .../media/platform/mtk-mdp3/mdp_reg_merge.h | 23 + drivers/media/platform/mtk-mdp3/mdp_reg_ovl.h | 24 + drivers/media/platform/mtk-mdp3/mdp_reg_pad.h | 20 + .../media/platform/mtk-mdp3/mdp_reg_rdma.h | 31 + drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h | 2 + .../media/platform/mtk-mdp3/mdp_reg_tdshp.h | 114 ++ .../media/platform/mtk-mdp3/mdp_reg_wrot.h | 18 + drivers/media/platform/mtk-mdp3/mtk-img-ipi.h | 215 ++- .../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 492 ++++++- .../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 1198 ++++++++++++++++- .../media/platform/mtk-mdp3/mtk-mdp3-comp.h | 83 +- .../media/platform/mtk-mdp3/mtk-mdp3-core.c | 707 +++++++++- .../media/platform/mtk-mdp3/mtk-mdp3-core.h | 31 +- .../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 4 + .../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 143 +- .../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 2 + 20 files changed, 3014 insertions(+), 200 deletions(-) create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_aal.h create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_color.h create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_fg.h create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_hdr.h create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_merge.h create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_ovl.h create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_pad.h create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_tdshp.h diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_aal.h b/drivers/media/platform/mtk-mdp3/mdp_reg_aal.h new file mode 100644 index 000000000000..2275a06fbdf9 --- /dev/null +++ b/drivers/media/platform/mtk-mdp3/mdp_reg_aal.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_AAL_H__ +#define __MDP_REG_AAL_H__ + +#define MDP_AAL_EN (0x000) +#define MDP_AAL_CFG (0x020) +#define MDP_AAL_SIZE (0x030) +#define MDP_AAL_OUTPUT_SIZE (0x034) +#define MDP_AAL_OUTPUT_OFFSET (0x038) +#define MDP_AAL_CFG_MAIN (0x200) + +#define MDP_AAL_EN_MASK (0x01) +#define MDP_AAL_CFG_MASK (0x70FF00B3) +#define MDP_AAL_SIZE_MASK (0x1FFF1FFF) +#define MDP_AAL_OUTPUT_SIZE_MASK (0x1FFF1FFF) +#define MDP_AAL_OUTPUT_OFFSET_MASK (0x0FF00FF) +#define MDP_AAL_CFG_MAIN_MASK (0x0FE) + +#endif // __MDP_REG_AAL_H__ diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_color.h b/drivers/media/platform/mtk-mdp3/mdp_reg_color.h new file mode 100644 index 000000000000..54d917a20362 --- /dev/null +++ b/drivers/media/platform/mtk-mdp3/mdp_reg_color.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_COLOR_H__ +#define __MDP_REG_COLOR_H__ + +#define DISP_COLOR_WIN_X_MAIN (0x40C) +#define DISP_COLOR_WIN_Y_MAIN (0x410) +#define DISP_COLOR_START (0xC00) +#define DISP_COLOR_INTEN (0xC04) +#define DISP_COLOR_OUT_SEL (0xC0C) +#define DISP_COLOR_INTERNAL_IP_WIDTH (0xC50) +#define DISP_COLOR_INTERNAL_IP_HEIGHT (0xC54) +#define DISP_COLOR_CM1_EN (0xC60) +#define DISP_COLOR_CM2_EN (0xCA0) +// MASK +#define DISP_COLOR_WIN_X_MAIN_MASK (0xFFFFFFFF) +#define DISP_COLOR_WIN_Y_MAIN_MASK (0xFFFFFFFF) +#define DISP_COLOR_START_MASK (0x0FF013F) +#define DISP_COLOR_INTEN_MASK (0x07) +#define DISP_COLOR_OUT_SEL_MASK (0x0777) +#define DISP_COLOR_INTERNAL_IP_WIDTH_MASK (0x03FFF) +#define DISP_COLOR_INTERNAL_IP_HEIGHT_MASK (0x03FFF) +#define DISP_COLOR_CM1_EN_MASK (0x03) +#define DISP_COLOR_CM2_EN_MASK (0x017) +#endif // __MDP_REG_COLOR_H__ diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_fg.h b/drivers/media/platform/mtk-mdp3/mdp_reg_fg.h new file mode 100644 index 000000000000..34f68554c0bb --- /dev/null +++ b/drivers/media/platform/mtk-mdp3/mdp_reg_fg.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_FG_H__ +#define __MDP_REG_FG_H__ + +#define MDP_FG_TRIGGER (0x0) +#define MDP_FG_FG_CTRL_0 (0x20) +#define MDP_FG_FG_CK_EN (0x24) +#define MDP_FG_TILE_INFO_0 (0x418) +#define MDP_FG_TILE_INFO_1 (0x41c) + +/* MASK */ +#define MDP_FG_TRIGGER_MASK (0x00000007) +#define MDP_FG_FG_CTRL_0_MASK (0x00000033) +#define MDP_FG_FG_CK_EN_MASK (0x0000000F) +#define MDP_FG_TILE_INFO_0_MASK (0xFFFFFFFF) +#define MDP_FG_TILE_INFO_1_MASK (0xFFFFFFFF) + +#endif //__MDP_REG_FG_H__ diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_hdr.h b/drivers/media/platform/mtk-mdp3/mdp_reg_hdr.h new file mode 100644 index 000000000000..06d0d3a6a139 --- /dev/null +++ b/drivers/media/platform/mtk-mdp3/mdp_reg_hdr.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_HDR_H__ +#define __MDP_REG_HDR_H__ + +#define MDP_HDR_TOP (0x000) +#define MDP_HDR_RELAY (0x004) +#define MDP_HDR_SIZE_0 (0x014) +#define MDP_HDR_SIZE_1 (0x018) +#define MDP_HDR_SIZE_2 (0x01C) +#define MDP_HDR_HIST_CTRL_0 (0x020) +#define MDP_HDR_HIST_CTRL_1 (0x024) +#define MDP_HDR_HIST_ADDR (0x0DC) +#define MDP_HDR_TILE_POS (0x118) + +// MASK +#define MDP_HDR_RELAY_MASK (0x01) +#define MDP_HDR_TOP_MASK (0xFF0FEB6D) +#define MDP_HDR_SIZE_0_MASK (0x1FFF1FFF) +#define MDP_HDR_SIZE_1_MASK (0x1FFF1FFF) +#define MDP_HDR_SIZE_2_MASK (0x1FFF1FFF) +#define MDP_HDR_HIST_CTRL_0_MASK (0x1FFF1FFF) +#define MDP_HDR_HIST_CTRL_1_MASK (0x1FFF1FFF) +#define MDP_HDR_HIST_ADDR_MASK (0xBF3F2F3F) +#define MDP_HDR_TILE_POS_MASK (0x1FFF1FFF) + +#endif // __MDP_REG_HDR_H__ diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_merge.h b/drivers/media/platform/mtk-mdp3/mdp_reg_merge.h new file mode 100644 index 000000000000..d53d58d4ea05 --- /dev/null +++ b/drivers/media/platform/mtk-mdp3/mdp_reg_merge.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_MERGE_H__ +#define __MDP_REG_MERGE_H__ + +#define VPP_MERGE_ENABLE (0x000) +#define VPP_MERGE_CFG_0 (0x010) +#define VPP_MERGE_CFG_4 (0x020) +#define VPP_MERGE_CFG_12 (0x040) +#define VPP_MERGE_CFG_24 (0x070) +#define VPP_MERGE_CFG_25 (0x074) + +#define VPP_MERGE_ENABLE_MASK (0xFFFFFFFF) +#define VPP_MERGE_CFG_0_MASK (0xFFFFFFFF) +#define VPP_MERGE_CFG_4_MASK (0xFFFFFFFF) +#define VPP_MERGE_CFG_12_MASK (0xFFFFFFFF) +#define VPP_MERGE_CFG_24_MASK (0xFFFFFFFF) +#define VPP_MERGE_CFG_25_MASK (0xFFFFFFFF) +#endif diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_ovl.h b/drivers/media/platform/mtk-mdp3/mdp_reg_ovl.h new file mode 100644 index 000000000000..35aa10c763bd --- /dev/null +++ b/drivers/media/platform/mtk-mdp3/mdp_reg_ovl.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_OVL_H__ +#define __MDP_REG_OVL_H__ + +#define OVL_EN (0x00c) +#define OVL_ROI_SIZE (0x020) +#define OVL_DATAPATH_CON (0x024) +#define OVL_SRC_CON (0x02c) +#define OVL_L0_CON (0x030) +#define OVL_L0_SRC_SIZE (0x038) + +#define OVL_DATAPATH_CON_MASK (0x0FFFFFFF) +#define OVL_EN_MASK (0xB07D07B1) +#define OVL_L0_CON_MASK (0xFFFFFFFF) +#define OVL_L0_SRC_SIZE_MASK (0x1FFF1FFF) +#define OVL_ROI_SIZE_MASK (0x1FFF1FFF) +#define OVL_SRC_CON_MASK (0x0000031F) + +#endif //__MDP_REG_OVL_H__ diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_pad.h b/drivers/media/platform/mtk-mdp3/mdp_reg_pad.h new file mode 100644 index 000000000000..f4d6d06a74be --- /dev/null +++ b/drivers/media/platform/mtk-mdp3/mdp_reg_pad.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_PAD_H__ +#define __MDP_REG_PAD_H__ + +#define VPP_PADDING0_PADDING_CON (0x000) +#define VPP_PADDING0_PADDING_PIC_SIZE (0x004) +#define VPP_PADDING0_W_PADDING_SIZE (0x008) +#define VPP_PADDING0_H_PADDING_SIZE (0x00c) + +#define VPP_PADDING0_PADDING_CON_MASK (0x00000007) +#define VPP_PADDING0_PADDING_PIC_SIZE_MASK (0xFFFFFFFF) +#define VPP_PADDING0_W_PADDING_SIZE_MASK (0x1FFF1FFF) +#define VPP_PADDING0_H_PADDING_SIZE_MASK (0x1FFF1FFF) + +#endif // __MDP_REG_PAD_H__ diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h b/drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h index 59d9aae40be6..06dea03ae029 100644 --- a/drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h +++ b/drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h @@ -12,12 +12,14 @@ #define MDP_RDMA_CON 0x020 #define MDP_RDMA_GMCIF_CON 0x028 #define MDP_RDMA_SRC_CON 0x030 +#define MDP_RDMA_COMP_CON 0x038 #define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060 #define MDP_RDMA_MF_BKGD_SIZE_IN_PXL 0x068 #define MDP_RDMA_MF_SRC_SIZE 0x070 #define MDP_RDMA_MF_CLIP_SIZE 0x078 #define MDP_RDMA_MF_OFFSET_1 0x080 #define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090 +#define MDP_RDMA_MF_BKGD_H_SIZE_IN_PXL 0x098 #define MDP_RDMA_SRC_END_0 0x100 #define MDP_RDMA_SRC_END_1 0x108 #define MDP_RDMA_SRC_END_2 0x110 @@ -25,7 +27,20 @@ #define MDP_RDMA_SRC_OFFSET_1 0x120 #define MDP_RDMA_SRC_OFFSET_2 0x128 #define MDP_RDMA_SRC_OFFSET_0_P 0x148 +#define MDP_RDMA_SRC_OFFSET_HP 0x150 #define MDP_RDMA_TRANSFORM_0 0x200 +#define MDP_RDMA_DMABUF_CON_0 0x240 +#define MDP_RDMA_ULTRA_TH_HIGH_CON_0 0x248 +#define MDP_RDMA_ULTRA_TH_LOW_CON_0 0x250 +#define MDP_RDMA_DMABUF_CON_1 0x258 +#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260 +#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268 +#define MDP_RDMA_DMABUF_CON_2 0x270 +#define MDP_RDMA_ULTRA_TH_HIGH_CON_2 0x278 +#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280 +#define MDP_RDMA_DMABUF_CON_3 0x288 +#define MDP_RDMA_ULTRA_TH_HIGH_CON_3 0x290 +#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298 #define MDP_RDMA_RESV_DUMMY_0 0x2a0 #define MDP_RDMA_MON_STA_1 0x408 #define MDP_RDMA_SRC_BASE_0 0xf00 @@ -40,12 +55,14 @@ #define MDP_RDMA_CON_MASK 0x00001110 #define MDP_RDMA_GMCIF_CON_MASK 0xfffb3771 #define MDP_RDMA_SRC_CON_MASK 0xf3ffffff +#define MDP_RDMA_COMP_CON_MASK 0xffffc000 #define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE_MASK 0x001fffff #define MDP_RDMA_MF_BKGD_SIZE_IN_PXL_MASK 0x001fffff #define MDP_RDMA_MF_SRC_SIZE_MASK 0x1fff1fff #define MDP_RDMA_MF_CLIP_SIZE_MASK 0x1fff1fff #define MDP_RDMA_MF_OFFSET_1_MASK 0x003f001f #define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE_MASK 0x001fffff +#define MDP_RDMA_MF_BKGD_H_SIZE_IN_PXL_MASK 0x007fffff #define MDP_RDMA_SRC_END_0_MASK 0xffffffff #define MDP_RDMA_SRC_END_1_MASK 0xffffffff #define MDP_RDMA_SRC_END_2_MASK 0xffffffff @@ -53,7 +70,21 @@ #define MDP_RDMA_SRC_OFFSET_1_MASK 0xffffffff #define MDP_RDMA_SRC_OFFSET_2_MASK 0xffffffff #define MDP_RDMA_SRC_OFFSET_0_P_MASK 0xffffffff +#define MDP_RDMA_SRC_OFFSET_HP_MASK 0xffffffff #define MDP_RDMA_TRANSFORM_0_MASK 0xff110777 +#define MDP_RDMA_DMABUF_CON_0_MASK 0x0fff00ff +#define MDP_RDMA_ULTRA_TH_HIGH_CON_0_MASK 0x3fffffff +#define MDP_RDMA_ULTRA_TH_LOW_CON_0_MASK 0x3fffffff +#define MDP_RDMA_DMABUF_CON_1_MASK 0x0f7f007f +#define MDP_RDMA_ULTRA_TH_HIGH_CON_1_MASK 0x3fffffff +#define MDP_RDMA_ULTRA_TH_LOW_CON_1_MASK 0x3fffffff +#define MDP_RDMA_DMABUF_CON_2_MASK 0x0f3f003f +#define MDP_RDMA_ULTRA_TH_HIGH_CON_2_MASK 0x3fffffff +#define MDP_RDMA_ULTRA_TH_LOW_CON_2_MASK 0x3fffffff +#define MDP_RDMA_DMABUF_CON_3_MASK 0x0f3f003f +#define MDP_RDMA_ULTRA_TH_HIGH_CON_3_MASK 0x3fffffff +#define MDP_RDMA_ULTRA_TH_LOW_CON_3_MASK 0x3fffffff + #define MDP_RDMA_RESV_DUMMY_0_MASK 0xffffffff #define MDP_RDMA_MON_STA_1_MASK 0xffffffff #define MDP_RDMA_SRC_BASE_0_MASK 0xffffffff diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h b/drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h index 051fdb020741..942fd4393eba 100644 --- a/drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h +++ b/drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h @@ -20,6 +20,7 @@ #define PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET 0x02c #define PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET 0x030 #define PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET 0x034 +#define RSZ_ETC_CONTROL 0x22c /* MASK */ #define PRZ_ENABLE_MASK 0x00010001 @@ -35,5 +36,6 @@ #define PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET_MASK 0x001fffff #define PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET_MASK 0x0000ffff #define PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET_MASK 0x001fffff +#define RSZ_ETC_CONTROL_MASK 0xff770000 #endif // __MDP_REG_RSZ_H__ diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_tdshp.h b/drivers/media/platform/mtk-mdp3/mdp_reg_tdshp.h new file mode 100644 index 000000000000..22a3a3bac9d0 --- /dev/null +++ b/drivers/media/platform/mtk-mdp3/mdp_reg_tdshp.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_TDSHP_H__ +#define __MDP_REG_TDSHP_H__ + +#define MDP_HIST_CFG_00 (0x064) +#define MDP_HIST_CFG_01 (0x068) +#define MDP_TDSHP_CTRL (0x100) +#define MDP_TDSHP_CFG (0x110) +#define MDP_TDSHP_INPUT_SIZE (0x120) +#define MDP_TDSHP_OUTPUT_OFFSET (0x124) +#define MDP_TDSHP_OUTPUT_SIZE (0x128) +#define MDP_LUMA_HIST_INIT_00 (0x200) +#define MDP_LUMA_HIST_INIT_01 (0x204) +#define MDP_LUMA_HIST_INIT_02 (0x208) +#define MDP_LUMA_HIST_INIT_03 (0x20C) +#define MDP_LUMA_HIST_INIT_04 (0x210) +#define MDP_LUMA_HIST_INIT_05 (0x214) +#define MDP_LUMA_HIST_INIT_06 (0x218) +#define MDP_LUMA_HIST_INIT_07 (0x21C) +#define MDP_LUMA_HIST_INIT_08 (0x220) +#define MDP_LUMA_HIST_INIT_09 (0x224) +#define MDP_LUMA_HIST_INIT_10 (0x228) +#define MDP_LUMA_HIST_INIT_11 (0x22C) +#define MDP_LUMA_HIST_INIT_12 (0x230) +#define MDP_LUMA_HIST_INIT_13 (0x234) +#define MDP_LUMA_HIST_INIT_14 (0x238) +#define MDP_LUMA_HIST_INIT_15 (0x23C) +#define MDP_LUMA_HIST_INIT_16 (0x240) +#define MDP_LUMA_SUM_INIT (0x244) +#define MDP_CONTOUR_HIST_INIT_00 (0x398) +#define MDP_CONTOUR_HIST_INIT_01 (0x39C) +#define MDP_CONTOUR_HIST_INIT_02 (0x3A0) +#define MDP_CONTOUR_HIST_INIT_03 (0x3A4) +#define MDP_CONTOUR_HIST_INIT_04 (0x3A8) +#define MDP_CONTOUR_HIST_INIT_05 (0x3AC) +#define MDP_CONTOUR_HIST_INIT_06 (0x3B0) +#define MDP_CONTOUR_HIST_INIT_07 (0x3B4) +#define MDP_CONTOUR_HIST_INIT_08 (0x3B8) +#define MDP_CONTOUR_HIST_INIT_09 (0x3BC) +#define MDP_CONTOUR_HIST_INIT_10 (0x3C0) +#define MDP_CONTOUR_HIST_INIT_11 (0x3C4) +#define MDP_CONTOUR_HIST_INIT_12 (0x3C8) +#define MDP_CONTOUR_HIST_INIT_13 (0x3CC) +#define MDP_CONTOUR_HIST_INIT_14 (0x3D0) +#define MDP_CONTOUR_HIST_INIT_15 (0x3D4) +#define MDP_CONTOUR_HIST_INIT_16 (0x3D8) + +// MASK +#define MDP_HIST_CFG_00_MASK (0xFFFFFFFF) +#define MDP_HIST_CFG_01_MASK (0xFFFFFFFF) +#define MDP_LUMA_HIST_00_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_01_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_02_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_03_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_04_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_05_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_06_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_07_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_08_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_09_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_10_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_11_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_12_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_13_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_14_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_15_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_16_MASK (0x07FFFFFF) +#define MDP_TDSHP_CTRL_MASK (0x07) +#define MDP_TDSHP_CFG_MASK (0x03F7) +#define MDP_TDSHP_INPUT_SIZE_MASK (0x1FFF1FFF) +#define MDP_TDSHP_OUTPUT_OFFSET_MASK (0x0FF00FF) +#define MDP_TDSHP_OUTPUT_SIZE_MASK (0x1FFF1FFF) +#define MDP_LUMA_HIST_INIT_00_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_INIT_01_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_INIT_02_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_INIT_03_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_INIT_04_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_INIT_05_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_INIT_06_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_INIT_07_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_INIT_08_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_INIT_09_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_INIT_10_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_INIT_11_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_INIT_12_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_INIT_13_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_INIT_14_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_INIT_15_MASK (0x07FFFFFF) +#define MDP_LUMA_HIST_INIT_16_MASK (0x07FFFFFF) +#define MDP_LUMA_SUM_INIT_MASK (0xFFFFFFFF) +#define MDP_CONTOUR_HIST_INIT_00_MASK (0x07FFFFFF) +#define MDP_CONTOUR_HIST_INIT_01_MASK (0x07FFFFFF) +#define MDP_CONTOUR_HIST_INIT_02_MASK (0x07FFFFFF) +#define MDP_CONTOUR_HIST_INIT_03_MASK (0x07FFFFFF) +#define MDP_CONTOUR_HIST_INIT_04_MASK (0x07FFFFFF) +#define MDP_CONTOUR_HIST_INIT_05_MASK (0x07FFFFFF) +#define MDP_CONTOUR_HIST_INIT_06_MASK (0x07FFFFFF) +#define MDP_CONTOUR_HIST_INIT_07_MASK (0x07FFFFFF) +#define MDP_CONTOUR_HIST_INIT_08_MASK (0x07FFFFFF) +#define MDP_CONTOUR_HIST_INIT_09_MASK (0x07FFFFFF) +#define MDP_CONTOUR_HIST_INIT_10_MASK (0x07FFFFFF) +#define MDP_CONTOUR_HIST_INIT_11_MASK (0x07FFFFFF) +#define MDP_CONTOUR_HIST_INIT_12_MASK (0x07FFFFFF) +#define MDP_CONTOUR_HIST_INIT_13_MASK (0x07FFFFFF) +#define MDP_CONTOUR_HIST_INIT_14_MASK (0x07FFFFFF) +#define MDP_CONTOUR_HIST_INIT_15_MASK (0x07FFFFFF) +#define MDP_CONTOUR_HIST_INIT_16_MASK (0x07FFFFFF) + +#endif // __MDP_REG_TDSHP_H__ diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h b/drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h index 39b8785f89eb..81a7c46c1aef 100644 --- a/drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h +++ b/drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h @@ -11,23 +11,32 @@ #define VIDO_MAIN_BUF_SIZE 0x008 #define VIDO_SOFT_RST 0x010 #define VIDO_SOFT_RST_STAT 0x014 +#define VIDO_INT 0x01c #define VIDO_CROP_OFST 0x020 #define VIDO_TAR_SIZE 0x024 +#define VIDO_FRAME_SIZE 0x028 #define VIDO_OFST_ADDR 0x02c #define VIDO_STRIDE 0x030 +#define VIDO_BKGD 0x034 #define VIDO_OFST_ADDR_C 0x038 #define VIDO_STRIDE_C 0x03c +#define VIDO_CTRL_2 0x048 #define VIDO_DITHER 0x054 #define VIDO_STRIDE_V 0x06c #define VIDO_OFST_ADDR_V 0x068 #define VIDO_RSV_1 0x070 +#define VIDO_DMA_PREULTRA 0x074 #define VIDO_IN_SIZE 0x078 #define VIDO_ROT_EN 0x07c #define VIDO_FIFO_TEST 0x080 #define VIDO_MAT_CTRL 0x084 +#define VIDO_PVRIC 0x0d8 +#define VIDO_SCAN_10BIT 0x0dc +#define VIDO_PENDING_ZERO 0x0e0 #define VIDO_BASE_ADDR 0xf00 #define VIDO_BASE_ADDR_C 0xf04 #define VIDO_BASE_ADDR_V 0xf08 +#define VIDO_AFBC_YUVTRANS 0xf2c /* MASK */ #define VIDO_CTRL_MASK 0xf530711f @@ -36,6 +45,7 @@ #define VIDO_SOFT_RST_STAT_MASK 0x00000001 #define VIDO_TAR_SIZE_MASK 0x1fff1fff #define VIDO_CROP_OFST_MASK 0x1fff1fff +#define VIDO_INT_MASK 0x00000007 #define VIDO_OFST_ADDR_MASK 0x0fffffff #define VIDO_STRIDE_MASK 0x0000ffff #define VIDO_OFST_ADDR_C_MASK 0x0fffffff @@ -51,5 +61,13 @@ #define VIDO_BASE_ADDR_MASK 0xffffffff #define VIDO_BASE_ADDR_C_MASK 0xffffffff #define VIDO_BASE_ADDR_V_MASK 0xffffffff +#define VIDO_DMA_PREULTRA_MASK 0x00ffffff +#define VIDO_FRAME_SIZE_MASK 0xffffffff +#define VIDO_BKGD_MASK 0xffffffff +#define VIDO_CTRL_2_MASK 0x0000000f +#define VIDO_PVRIC_MASK 0x00000003 +#define VIDO_SCAN_10BIT_MASK 0x0000000f +#define VIDO_PENDING_ZERO_MASK 0x07ffffff +#define VIDO_AFBC_YUVTRANS_MASK 0x00000001 #endif // __MDP_REG_WROT_H__ diff --git a/drivers/media/platform/mtk-mdp3/mtk-img-ipi.h b/drivers/media/platform/mtk-mdp3/mtk-img-ipi.h index f8560dad87da..469f54d0565f 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-img-ipi.h +++ b/drivers/media/platform/mtk-mdp3/mtk-img-ipi.h @@ -42,14 +42,14 @@ struct img_sw_addr { struct img_plane_format { u32 size; - u16 stride; + u32 stride; } __packed; struct img_pix_format { - u16 width; - u16 height; + u32 width; + u32 height; u32 colorformat; /* enum mdp_color */ - u16 ycbcr_prof; /* enum mdp_ycbcr_profile */ + u32 ycbcr_prof; /* enum mdp_ycbcr_profile */ struct img_plane_format plane_fmt[IMG_MAX_PLANES]; } __packed; @@ -63,10 +63,10 @@ struct img_image_buffer { #define IMG_SUBPIXEL_SHIFT 20 struct img_crop { - s16 left; - s16 top; - u16 width; - u16 height; + s32 left; + s32 top; + u32 width; + u32 height; u32 left_subpix; u32 top_subpix; u32 width_subpix; @@ -78,27 +78,29 @@ struct img_crop { #define IMG_CTRL_FLAG_SHARPNESS BIT(4) #define IMG_CTRL_FLAG_HDR BIT(5) #define IMG_CTRL_FLAG_DRE BIT(6) +#define IMG_CTRL_FLAG_RSZ BIT(7) struct img_input { struct img_image_buffer buffer; - u16 flags; /* HDR, DRE, dither */ + u32 flags; /* HDR, DRE, dither */ } __packed; struct img_output { struct img_image_buffer buffer; struct img_crop crop; - s16 rotation; - u16 flags; /* H-flip, sharpness, dither */ + s32 rotation; + u32 flags; /* H-flip, sharpness, dither */ + u64 pqid; } __packed; struct img_ipi_frameparam { u32 index; u32 frame_no; u64 timestamp; - u8 type; /* enum mdp_stream_type */ - u8 state; - u8 num_inputs; - u8 num_outputs; + u32 type; /* enum mdp_stream_type */ + u32 state; + u32 num_inputs; + u32 num_outputs; u64 drv_data; struct img_input inputs[IMG_MAX_HW_INPUTS]; struct img_output outputs[IMG_MAX_HW_OUTPUTS]; @@ -106,6 +108,7 @@ struct img_ipi_frameparam { struct img_addr subfrm_data; struct img_sw_addr config_data; struct img_sw_addr self_data; + u32 frame_change; } __packed; struct img_sw_buffer { @@ -114,7 +117,7 @@ struct img_sw_buffer { } __packed; struct img_ipi_param { - u8 usage; + u32 usage; struct img_sw_buffer frm_param; } __packed; @@ -126,39 +129,39 @@ struct img_frameparam { /* ISP-MDP generic output information */ struct img_comp_frame { - u32 output_disable:1; - u32 bypass:1; - u16 in_width; - u16 in_height; - u16 out_width; - u16 out_height; + u32 output_disable; + u32 bypass; + u32 in_width; + u32 in_height; + u32 out_width; + u32 out_height; struct img_crop crop; - u16 in_total_width; - u16 out_total_width; + u32 in_total_width; + u32 out_total_width; } __packed; struct img_region { - s16 left; - s16 right; - s16 top; - s16 bottom; + s32 left; + s32 right; + s32 top; + s32 bottom; } __packed; struct img_offset { - s16 left; - s16 top; + s32 left; + s32 top; u32 left_subpix; u32 top_subpix; } __packed; struct img_comp_subfrm { - u32 tile_disable:1; + u32 tile_disable; struct img_region in; struct img_region out; struct img_offset luma; struct img_offset chroma; - s16 out_vertical; /* Output vertical index */ - s16 out_horizontal; /* Output horizontal index */ + s32 out_vertical; /* Output vertical index */ + s32 out_horizontal; /* Output horizontal index */ } __packed; #define IMG_MAX_SUBFRAMES 14 @@ -169,10 +172,13 @@ struct mdp_rdma_subfrm { u32 src; u32 clip; u32 clip_ofst; + u32 in_tile_xleft; + u32 in_tile_ytop; } __packed; struct mdp_rdma_data { u32 src_ctrl; + u32 comp_ctrl; u32 control; u32 iova[IMG_MAX_PLANES]; u32 iova_end[IMG_MAX_PLANES]; @@ -182,13 +188,72 @@ struct mdp_rdma_data { u32 ufo_dec_y; u32 ufo_dec_c; u32 transform; + u32 dmabuf_con0; + u32 ultra_th_high_con0; + u32 ultra_th_low_con0; + u32 dmabuf_con1; + u32 ultra_th_high_con1; + u32 ultra_th_low_con1; + u32 dmabuf_con2; + u32 ultra_th_high_con2; + u32 ultra_th_low_con2; + u32 dmabuf_con3; struct mdp_rdma_subfrm subfrms[IMG_MAX_SUBFRAMES]; } __packed; +struct mdp_fg_subfrm { + u32 info_0; + u32 info_1; +} __packed; + +struct mdp_fg_data { + u32 ctrl_0; + u32 ck_en; + struct mdp_fg_subfrm subfrms[IMG_MAX_SUBFRAMES]; +} __packed; + +struct mdp_hdr_subfrm { + u32 win_size; + u32 src; + u32 clip_ofst0; + u32 clip_ofst1; + u32 hist_ctrl_0; + u32 hist_ctrl_1; + u32 hdr_top; + u32 hist_addr; +} __packed; + +struct mdp_hdr_data { + u32 top; + u32 relay; + struct mdp_hdr_subfrm subfrms[IMG_MAX_SUBFRAMES]; +} __packed; + +struct mdp_aal_subfrm { + u32 src; + u32 clip; + u32 clip_ofst; +} __packed; + +struct mdp_aal_data { + u32 cfg_main; + u32 cfg; + struct mdp_aal_subfrm subfrms[IMG_MAX_SUBFRAMES]; +} __packed; + struct mdp_rsz_subfrm { u32 control2; u32 src; u32 clip; + u32 hdmirx_en; + u32 luma_h_int_ofst; + u32 luma_h_sub_ofst; + u32 luma_v_int_ofst; + u32 luma_v_sub_ofst; + u32 chroma_h_int_ofst; + u32 chroma_h_sub_ofst; + u32 rsz_switch; + u32 merge_cfg; } __packed; struct mdp_rsz_data { @@ -196,9 +261,70 @@ struct mdp_rsz_data { u32 coeff_step_y; u32 control1; u32 control2; + u32 etc_control; + u32 prz_enable; + u32 ibse_softclip; + u32 tap_adapt; + u32 ibse_gaincontrol1; + u32 ibse_gaincontrol2; + u32 ibse_ylevel_1; + u32 ibse_ylevel_2; + u32 ibse_ylevel_3; + u32 ibse_ylevel_4; + u32 ibse_ylevel_5; struct mdp_rsz_subfrm subfrms[IMG_MAX_SUBFRAMES]; } __packed; +struct mdp_tdshp_subfrm { + u32 src; + u32 clip; + u32 clip_ofst; + u32 hist_cfg_0; + u32 hist_cfg_1; +} __packed; + +struct mdp_tdshp_data { + u32 cfg; + struct mdp_tdshp_subfrm subfrms[IMG_MAX_SUBFRAMES]; +} __packed; + +struct mdp_color_subfrm { + u32 in_hsize; + u32 in_vsize; +} __packed; + +struct mdp_color_data { + u32 start; + struct mdp_color_subfrm subfrms[IMG_MAX_SUBFRAMES]; +} __packed; + +struct mdp_ovl_subfrm { + u32 L0_src_size; + u32 roi_size; +} __packed; + +struct mdp_ovl_data { + u32 L0_con; + u32 src_con; + struct mdp_ovl_subfrm subfrms[IMG_MAX_SUBFRAMES]; +} __packed; + +struct mdp_pad_subfrm { + u32 pic_size; +} __packed; + +struct mdp_pad_data { + struct mdp_pad_subfrm subfrms[IMG_MAX_SUBFRAMES]; +} __packed; + +struct mdp_tcc_subfrm { + u32 pic_size; +} __packed; + +struct mdp_tcc_data { + struct mdp_tcc_subfrm subfrms[IMG_MAX_SUBFRAMES]; +} __packed; + struct mdp_wrot_subfrm { u32 offset[IMG_MAX_PLANES]; u32 src; @@ -214,6 +340,14 @@ struct mdp_wrot_data { u32 mat_ctrl; u32 fifo_test; u32 filter; + u32 pre_ultra; + u32 framesize; + u32 afbc_yuvtrans; + u32 scan_10bit; + u32 pending_zero; + u32 bit_number; + u32 pvric; + u32 vpp02vpp1; struct mdp_wrot_subfrm subfrms[IMG_MAX_SUBFRAMES]; } __packed; @@ -241,8 +375,8 @@ struct isp_data { } __packed; struct img_compparam { - u16 type; /* enum mdp_comp_type */ - u16 id; /* enum mtk_mdp_comp_id */ + u32 type; /* enum mdp_comp_id */ + u32 id; /* engine alias_id */ u32 input; u32 outputs[IMG_MAX_HW_OUTPUTS]; u32 num_outputs; @@ -251,7 +385,15 @@ struct img_compparam { u32 num_subfrms; union { struct mdp_rdma_data rdma; + struct mdp_fg_data fg; + struct mdp_hdr_data hdr; + struct mdp_aal_data aal; struct mdp_rsz_data rsz; + struct mdp_tdshp_data tdshp; + struct mdp_color_data color; + struct mdp_ovl_data ovl; + struct mdp_pad_data pad; + struct mdp_tcc_data tcc; struct mdp_wrot_data wrot; struct mdp_wdma_data wdma; struct isp_data isp; @@ -263,7 +405,8 @@ struct img_compparam { struct img_mux { u32 reg; u32 value; -}; + u32 vpp_id; +} __packed; struct img_mmsys_ctrl { struct img_mux sets[IMG_MAX_COMPONENTS * 2]; diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c index 8972cb8de755..afa114fe9817 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c @@ -27,11 +27,21 @@ struct mdp_path { #define call_op(ctx, op, ...) \ (has_op(ctx, op) ? (ctx)->comp->ops->op(ctx, ##__VA_ARGS__) : 0) +#define is_dummy_engine(mdp, id) \ + ((mdp)->mdp_data->comp_data[id].match.type == MDP_COMP_TYPE_DUMMY) + struct mdp_path_subfrm { s32 mutex_id; u32 mutex_mod; + u32 mutex_mod2; s32 sofs[MDP_PATH_MAX_COMPS]; u32 num_sofs; + + s32 mutex2_id; + u32 mutex2_mod; + u32 mutex2_mod2; + s32 sof2s[MDP_PATH_MAX_COMPS]; + u32 num_sof2s; }; static bool is_output_disable(const struct img_compparam *param, u32 count) @@ -75,8 +85,11 @@ static int mdp_path_subfrm_require(struct mdp_path_subfrm *subfrm, const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data; struct device *dev = &path->mdp_dev->pdev->dev; struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex; + struct mtk_mutex **mutex2 = path->mdp_dev->mdp_mutex2; s32 mutex_id = -1; + s32 mutex2_id = -1; u32 mutex_sof = 0; + u32 mutex2_sof = 0; int index, j; enum mtk_mdp_comp_id mtk_comp_id = MDP_COMP_NONE; @@ -84,57 +97,225 @@ static int mdp_path_subfrm_require(struct mdp_path_subfrm *subfrm, memset(subfrm, 0, sizeof(*subfrm)); for (index = 0; index < config->num_components; index++) { + if (is_dummy_engine(path->mdp_dev, config->components[index].type)) + continue; + ctx = &path->comps[index]; if (is_output_disable(ctx->param, count)) continue; mtk_comp_id = data->comp_data[ctx->comp->id].match.public_id; switch (mtk_comp_id) { - case MDP_COMP_AAL0: + case MDP_COMP_ISP_IMGI: + j = mdp_get_mutex_idx(data, MDP_PIPE_IMGI); + mutex_id = data->pipe_info[j].mutex_id; + break; + case MDP_COMP_WPEI: + j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI); + mutex_id = data->pipe_info[j].mutex_id; subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; break; - case MDP_COMP_CCORR0: + case MDP_COMP_WPEI2: + j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI2); + mutex_id = data->pipe_info[j].mutex_id; subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; break; - case MDP_COMP_WDMA: + case MDP_COMP_RDMA0: + j = mdp_get_mutex_idx(data, MDP_PIPE_RDMA0); + mutex_id = data->pipe_info[j].mutex_id; subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; - subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WDMA; + subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RDMA0; break; - case MDP_COMP_WROT0: + case MDP_COMP_VPP1_SOUT: + j = mdp_get_mutex_idx(data, MDP_PIPE_VPP1_SOUT); + mutex_id = data->pipe_info[j].mutex_id; subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; - subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WROT0; + subfrm->mutex2_mod2 |= data->comp_data[ctx->comp->id].mutex.mod2; break; - case MDP_COMP_TDSHP0: + case MDP_COMP_FG0: subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; - subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_TDSHP0; break; - case MDP_COMP_RSZ1: + case MDP_COMP_STITCH: + subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_HDR0: + subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_AAL0: subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; - subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RSZ1; break; case MDP_COMP_RSZ0: subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RSZ0; break; - case MDP_COMP_RDMA0: - j = mdp_get_mutex_idx(data, MDP_PIPE_RDMA0); - mutex_id = data->pipe_info[j].mutex_id; + case MDP_COMP_TDSHP0: subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; - subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RDMA0; + subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_TDSHP0; break; - case MDP_COMP_ISP_IMGI: - j = mdp_get_mutex_idx(data, MDP_PIPE_IMGI); - mutex_id = data->pipe_info[j].mutex_id; + case MDP_COMP_COLOR0: + subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; break; - case MDP_COMP_WPEI: - j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI); - mutex_id = data->pipe_info[j].mutex_id; + case MDP_COMP_OVL0: subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; break; - case MDP_COMP_WPEI2: - j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI2); - mutex_id = data->pipe_info[j].mutex_id; + case MDP_COMP_PAD0: + subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_TCC0: + subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_CCORR0: + subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_WDMA: + subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; + subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WDMA; + break; + case MDP_COMP_WROT0: + subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; + subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WROT0; + break; + case MDP_COMP_SPLIT: + j = mdp_get_mutex_idx(data, MDP_PIPE_SPLIT); + mutex2_id = data->pipe_info[j].mutex_id; + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_SPLIT; + mutex2_sof = data->pipe_info[j].sof; + break; + case MDP_COMP_SPLIT2: + j = mdp_get_mutex_idx(data, MDP_PIPE_SPLIT2); + mutex2_id = data->pipe_info[j].mutex_id; + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_SPLIT2; + mutex2_sof = data->pipe_info[j].sof; + break; + case MDP_COMP_RDMA1: + j = mdp_get_mutex_idx(data, MDP_PIPE_RDMA1); + mutex2_id = data->pipe_info[j].mutex_id; + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_RDMA1; + break; + case MDP_COMP_RDMA2: + j = mdp_get_mutex_idx(data, MDP_PIPE_RDMA2); + mutex2_id = data->pipe_info[j].mutex_id; + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_RDMA2; + break; + case MDP_COMP_RDMA3: + j = mdp_get_mutex_idx(data, MDP_PIPE_RDMA3); + mutex2_id = data->pipe_info[j].mutex_id; + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_RDMA3; + break; + case MDP_COMP_VPP0_SOUT: + j = mdp_get_mutex_idx(data, MDP_PIPE_VPP0_SOUT); + mutex2_id = data->pipe_info[j].mutex_id; subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; + subfrm->mutex2_mod2 |= data->comp_data[ctx->comp->id].mutex.mod2; + break; + case MDP_COMP_TCC1: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_FG1: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_FG2: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_FG3: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_HDR1: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_HDR2: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_HDR3: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_AAL1: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_AAL2: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_AAL3: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_RSZ1: + if (data->comp_data[ctx->comp->id].mutex.mmsys_id) { + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_RSZ1; + } else { + subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod; + subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RSZ1; + } + break; + case MDP_COMP_RSZ2: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_RSZ2; + break; + case MDP_COMP_RSZ3: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_RSZ3; + break; + case MDP_COMP_TDSHP1: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_TDSHP1; + break; + case MDP_COMP_TDSHP2: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_TDSHP2; + break; + case MDP_COMP_TDSHP3: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_TDSHP3; + break; + case MDP_COMP_COLOR1: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_COLOR2: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_COLOR3: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_OVL1: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_PAD1: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_PAD2: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_PAD3: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + break; + case MDP_COMP_WROT1: + subfrm->mutex2_mod |= data->comp_data[ctx->comp->id].mutex.mod; + subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_WROT1; + break; + case MDP_COMP_WROT2: + subfrm->mutex2_mod2 |= data->comp_data[ctx->comp->id].mutex.mod2; + subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_WROT2; + break; + case MDP_COMP_WROT3: + subfrm->mutex2_mod2 |= data->comp_data[ctx->comp->id].mutex.mod2; + subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_WROT3; + break; + case MDP_COMP_VDO0DL0: + subfrm->mutex2_mod2 |= data->comp_data[ctx->comp->id].mutex.mod2; + break; + case MDP_COMP_VDO1DL0: + subfrm->mutex2_mod2 |= data->comp_data[ctx->comp->id].mutex.mod2; + break; + case MDP_COMP_VDO0DL1: + subfrm->mutex2_mod2 |= data->comp_data[ctx->comp->id].mutex.mod2; + break; + case MDP_COMP_VDO1DL1: + subfrm->mutex2_mod2 |= data->comp_data[ctx->comp->id].mutex.mod2; break; default: break; @@ -142,17 +323,23 @@ static int mdp_path_subfrm_require(struct mdp_path_subfrm *subfrm, } subfrm->mutex_id = mutex_id; - if (-1 == mutex_id) { + subfrm->mutex2_id = mutex2_id; + + if ((-1 == mutex_id) && (-1 == mutex2_id)) { dev_err(dev, "No mutex assigned"); return -EINVAL; } /* Set mutex modules */ - if (subfrm->mutex_mod) { + if (subfrm->mutex_mod || subfrm->mutex_mod2) { mtk_mutex_add_mdp_mod(mutex[mutex_id], subfrm->mutex_mod, - 0, mutex_sof, cmd); + subfrm->mutex_mod2, mutex_sof, cmd); } + if (subfrm->mutex2_mod || subfrm->mutex2_mod2) { + mtk_mutex_add_mdp_mod(mutex2[mutex2_id], subfrm->mutex2_mod, + subfrm->mutex2_mod2, mutex2_sof, cmd); + } return 0; } @@ -162,14 +349,16 @@ static int mdp_path_subfrm_run(const struct mdp_path_subfrm *subfrm, { struct device *dev = &path->mdp_dev->pdev->dev; struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex; + struct mtk_mutex **mutex2 = path->mdp_dev->mdp_mutex2; s32 mutex_id = subfrm->mutex_id; + s32 mutex2_id = subfrm->mutex2_id; - if (-1 == mutex_id) { + if ((-1 == mutex_id) && (-1 == mutex2_id)) { dev_err(dev, "Incorrect mutex id"); return -EINVAL; } - if (subfrm->mutex_mod) { + if (subfrm->mutex_mod || subfrm->mutex_mod2) { int index, evt; /* Wait WROT SRAM shared to DISP RDMA */ @@ -234,6 +423,71 @@ static int mdp_path_subfrm_run(const struct mdp_path_subfrm *subfrm, MM_REG_WAIT(cmd, evt); } } + + if (subfrm->mutex2_mod || subfrm->mutex2_mod2) { + int index, evt; + + /* Clear SOF event for each engine */ + for (index = 0; index < subfrm->num_sof2s; index++) { + switch (subfrm->sof2s[index]) { + case MDP_COMP_RDMA1: + evt = mdp_get_event_idx(path->mdp_dev, RDMA1_SOF); + break; + case MDP_COMP_RDMA2: + evt = mdp_get_event_idx(path->mdp_dev, RDMA2_SOF); + break; + case MDP_COMP_RDMA3: + evt = mdp_get_event_idx(path->mdp_dev, RDMA3_SOF); + break; + case MDP_COMP_WROT1: + evt = mdp_get_event_idx(path->mdp_dev, WROT1_SOF); + break; + case MDP_COMP_WROT2: + evt = mdp_get_event_idx(path->mdp_dev, WROT2_SOF); + break; + case MDP_COMP_WROT3: + evt = mdp_get_event_idx(path->mdp_dev, WROT3_SOF); + break; + default: + evt = -1; + break; + } + if (evt > 0) + MM_REG_CLEAR(cmd, evt); + } + + /* Enable the mutex */ + mtk_mutex_enable_by_cmdq(mutex2[mutex2_id], cmd); + + /* Wait SOF events and clear mutex modules (optional) */ + for (index = 0; index < subfrm->num_sof2s; index++) { + switch (subfrm->sof2s[index]) { + case MDP_COMP_RDMA1: + evt = mdp_get_event_idx(path->mdp_dev, RDMA1_SOF); + break; + case MDP_COMP_RDMA2: + evt = mdp_get_event_idx(path->mdp_dev, RDMA2_SOF); + break; + case MDP_COMP_RDMA3: + evt = mdp_get_event_idx(path->mdp_dev, RDMA3_SOF); + break; + case MDP_COMP_WROT1: + evt = mdp_get_event_idx(path->mdp_dev, WROT1_SOF); + break; + case MDP_COMP_WROT2: + evt = mdp_get_event_idx(path->mdp_dev, WROT2_SOF); + break; + case MDP_COMP_WROT3: + evt = mdp_get_event_idx(path->mdp_dev, WROT3_SOF); + break; + default: + evt = -1; + break; + } + if (evt > 0) + MM_REG_WAIT(cmd, evt); + } + } return 0; } @@ -246,9 +500,12 @@ static int mdp_path_ctx_init(struct mdp_dev *mdp, struct mdp_path *path) return -EINVAL; for (index = 0; index < config->num_components; index++) { + if (is_dummy_engine(mdp, config->components[index].type)) + continue; + ret = mdp_comp_ctx_init(mdp, &path->comps[index], - &config->components[index], - path->param); + &config->components[index], + path->param); if (ret) return ret; } @@ -261,10 +518,12 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd, { struct mdp_path_subfrm subfrm; const struct img_config *config = path->config; - struct device *mmsys_dev = path->mdp_dev->mdp_mmsys; const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data; + struct device *mmsys_dev = path->mdp_dev->mdp_mmsys; + struct device *mmsys2_dev = path->mdp_dev->mdp_mmsys2; struct mdp_comp_ctx *ctx; enum mdp_comp_id cur, next; + enum mtk_mdp_comp_id mtk_cur, mtk_next; int index, ret; /* Acquire components */ @@ -273,15 +532,29 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd, return ret; /* Enable mux settings */ for (index = 0; index < (config->num_components - 1); index++) { - cur = path->comps[index].comp->id; - next = path->comps[index + 1].comp->id; - mtk_mmsys_mdp_connect(mmsys_dev, cmd, - data->comp_data[cur].match.public_id, - data->comp_data[next].match.public_id); + if (is_dummy_engine(path->mdp_dev, config->components[index].type)) + cur = config->components[index].type; + else + cur = path->comps[index].comp->id; + + if (is_dummy_engine(path->mdp_dev, config->components[index + 1].type)) + next = config->components[index + 1].type; + else + next = path->comps[index + 1].comp->id; + + mtk_cur = data->comp_data[cur].match.public_id; + mtk_next = data->comp_data[next].match.public_id; + if (data->comp_data[cur].mutex.mmsys_id != 0) + mtk_mmsys_mdp_connect(mmsys2_dev, cmd, mtk_cur, mtk_next); + else + mtk_mmsys_mdp_connect(mmsys_dev, cmd, mtk_cur, mtk_next); } /* Config sub-frame information */ for (index = (config->num_components - 1); index >= 0; index--) { + if (is_dummy_engine(path->mdp_dev, config->components[index].type)) + continue; + ctx = &path->comps[index]; if (is_output_disable(ctx->param, count)) continue; @@ -295,6 +568,9 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd, return ret; /* Wait components done */ for (index = 0; index < config->num_components; index++) { + if (is_dummy_engine(path->mdp_dev, config->components[index].type)) + continue; + ctx = &path->comps[index]; if (is_output_disable(ctx->param, count)) continue; @@ -304,6 +580,9 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd, } /* Advance to the next sub-frame */ for (index = 0; index < config->num_components; index++) { + if (is_dummy_engine(path->mdp_dev, config->components[index].type)) + continue; + ctx = &path->comps[index]; ret = call_op(ctx, advance_subfrm, cmd, count); if (ret) @@ -311,11 +590,22 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd, } /* Disable mux settings */ for (index = 0; index < (config->num_components - 1); index++) { - cur = path->comps[index].comp->id; - next = path->comps[index + 1].comp->id; - mtk_mmsys_mdp_disconnect(mmsys_dev, cmd, - data->comp_data[cur].match.public_id, - data->comp_data[next].match.public_id); + if (is_dummy_engine(path->mdp_dev, config->components[index].type)) + cur = config->components[index].type; + else + cur = path->comps[index].comp->id; + + if (is_dummy_engine(path->mdp_dev, config->components[index + 1].type)) + next = config->components[index + 1].type; + else + next = path->comps[index + 1].comp->id; + + mtk_cur = data->comp_data[cur].match.public_id; + mtk_next = data->comp_data[next].match.public_id; + if (data->comp_data[cur].mutex.mmsys_id != 0) + mtk_mmsys_mdp_disconnect(mmsys2_dev, cmd, mtk_cur, mtk_next); + else + mtk_mmsys_mdp_disconnect(mmsys_dev, cmd, mtk_cur, mtk_next); } return 0; @@ -331,6 +621,9 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd, /* Config path frame */ /* Reset components */ for (index = 0; index < config->num_components; index++) { + if (is_dummy_engine(mdp, config->components[index].type)) + continue; + ctx = &path->comps[index]; ret = call_op(ctx, init_comp, cmd); if (ret) @@ -341,6 +634,9 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd, const struct v4l2_rect *compose = path->composes[ctx->param->outputs[0]]; + if (is_dummy_engine(mdp, config->components[index].type)) + continue; + ctx = &path->comps[index]; ret = call_op(ctx, config_frame, cmd, compose); if (ret) @@ -355,6 +651,9 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd, } /* Post processing information */ for (index = 0; index < config->num_components; index++) { + if (is_dummy_engine(mdp, config->components[index].type)) + continue; + ctx = &path->comps[index]; ret = call_op(ctx, post_process, cmd); if (ret) @@ -363,6 +662,72 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd, return 0; } +static int mdp_hyfbc_config(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd, + struct mdp_path *path, struct mdp_cmdq_param *param) +{ +#define BYTE_PER_MB_Y (4) +#define BYTE_PER_MB_C (2) + +#define CEIL(a, b) (((a) % (b) == 0) ? ((a) / (b)) : ((a) / (b) + 1)) +#define ALIGN_UP(val, a) \ +({ \ + typeof(val) _a = (a); \ + (_a == 0) ? val : ((val + (_a - 1)) / (_a) * (_a)); \ +}) + +#define is_rdma(id) \ + (mdp->mdp_data->comp_data[id].match.type == MDP_COMP_TYPE_RDMA) + + struct device *dev = &mdp->pdev->dev; + const struct img_config *config = path->config; + struct mdp_m2m_ctx *ctx; + struct mdp_comp_ctx *comp_ctx = &path->comps[0]; + const struct mdp_rdma_data *rdma = &comp_ctx->param->rdma; + struct hyfbc_patch_info hyfbc; + struct mdp_frame *frame; + enum mdp_comp_id wrot_id; + int ret = 0; + + ctx = (struct mdp_m2m_ctx *)param->mdp_ctx; + frame = &ctx->curr_param.output; + + if (!MDP_COLOR_IS_HYFBC_COMPRESS(frame->mdp_fmt->mdp_color) || + frame->format.fmt.pix_mp.width % 32 == 0) + goto exit; + + // First engine should be rdma engine + if (!is_rdma(config->components[0].type)) { + dev_info(dev, "Not RDMA engine (id), end patch.", config->components[0].type); + goto exit; + } + + wrot_id = config->components[(config->num_components - 1)].type; + + hyfbc.is10b = (MDP_COLOR_IS_10BIT(frame->mdp_fmt->mdp_color)); + hyfbc.width_in_mb = CEIL(frame->format.fmt.pix_mp.width, 16); + hyfbc.height_in_mb = CEIL(frame->format.fmt.pix_mp.height, 16); + hyfbc.w_stride_in_mb = CEIL(ALIGN_UP(frame->stride.width, 32), 16); + hyfbc.h_stride_in_mb = CEIL(ALIGN_UP(frame->stride.height, 32), 16); + hyfbc.byte_per_mb = BYTE_PER_MB_Y; + hyfbc.pa_base = rdma->ufo_dec_y; + + ret = mdp_hyfbc_patch(mdp, cmd, &hyfbc, wrot_id); + if (ret) { + dev_info(dev, "mdp_hyfbc_patch: y patch fail."); + goto exit; + } + + hyfbc.byte_per_mb = BYTE_PER_MB_C; + hyfbc.pa_base = rdma->ufo_dec_c; + + ret = mdp_hyfbc_patch(mdp, cmd, &hyfbc, wrot_id); + if (ret) + dev_info(dev, "mdp_hyfbc_patch: c patch fail."); + +exit: + return ret; +} + static void mdp_auto_release_work(struct work_struct *work) { struct mdp_cmdq_cb_param *cb_param; @@ -375,6 +740,11 @@ static void mdp_auto_release_work(struct work_struct *work) i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0); mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]); + + i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1); + if (i >= 0) + mtk_mutex_unprepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]); + mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps, cb_param->num_comps); @@ -393,7 +763,6 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data) int i; if (!data.data) { - pr_info("%s:no callback data\n", __func__); return; } @@ -418,6 +787,11 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data) dev_err(dev, "%s:queue_work fail!\n", __func__); i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0); mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]); + + i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1); + if (i >= 0) + mtk_mutex_unprepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]); + mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps, cb_param->num_comps); @@ -467,19 +841,34 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) ret = mdp_path_ctx_init(mdp, &path); if (ret) { - pr_info("%s mdp_path_ctx_init error\n", __func__); + dev_info(dev, "%s mdp_path_ctx_init error\n", __func__); goto err_destroy_pkt; } i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0); mtk_mutex_prepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]); - for (i = 0; i < param->config->num_components; i++) + i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1); + if (i >= 0) + mtk_mutex_prepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]); + + for (i = 0; i < param->config->num_components; i++) { + if (is_dummy_engine(mdp, path.config->components[i].type)) + continue; + mdp_comp_clock_on(&mdp->pdev->dev, path.comps[i].comp); + } + + if (mdp->mdp_data->mdp_cfg->version == MTK_MDP_VERSION_8195) { + /* HYFBC Patch */ + ret = mdp_hyfbc_config(mdp, &cmd, &path, param); + if (ret) + dev_info(dev, "%s:mdp_hyfbc_config fail!\n", __func__); + } ret = mdp_path_config(mdp, &cmd, &path); if (ret) { - pr_info("%s mdp_path_config error\n", __func__); + dev_info(dev, "%s mdp_path_config error\n", __func__); goto err_destroy_pkt; } @@ -496,9 +885,13 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) goto err_destroy_pkt; } - for (i = 0; i < param->config->num_components; i++) + for (i = 0; i < param->config->num_components; i++) { + if (is_dummy_engine(mdp, path.config->components[i].type)) + continue; + memcpy(&comps[i], path.comps[i].comp, sizeof(struct mdp_comp)); + } cb_param->mdp = mdp; cb_param->user_cmdq_cb = param->cmdq_cb; cb_param->user_cb_data = param->cb_data; @@ -512,7 +905,7 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) mdp_handle_cmdq_callback, (void *)cb_param); if (ret) { - dev_err(dev, "cmdq_pkt_flush_async fail!\n"); + dev_info(dev, "cmdq_pkt_flush_async fail!\n"); goto err_clock_off; } return 0; @@ -520,6 +913,11 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) err_clock_off: i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0); mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]); + + i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1); + if (i >= 0) + mtk_mutex_unprepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]); + mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps, cb_param->num_comps); err_destroy_pkt: diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c index f690502ee42b..12d6c88c68d2 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c @@ -15,6 +15,14 @@ #include "mdp_reg_rdma.h" #include "mdp_reg_ccorr.h" #include "mdp_reg_rsz.h" +#include "mdp_reg_fg.h" +#include "mdp_reg_aal.h" +#include "mdp_reg_tdshp.h" +#include "mdp_reg_hdr.h" +#include "mdp_reg_color.h" +#include "mdp_reg_ovl.h" +#include "mdp_reg_pad.h" +#include "mdp_reg_merge.h" #include "mdp_reg_wrot.h" #include "mdp_reg_wdma.h" #include "mdp_reg_isp.h" @@ -76,7 +84,7 @@ static int init_rdma(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; - if (mdp_cfg && mdp_cfg->rdma_support_10bit) { + if (mdp_cfg && mdp_cfg->rdma_rsz1_sram_sharing) { struct mdp_comp *prz1 = ctx->comp->mdp_dev->comp[MDP_RSZ1]; /* Disable RSZ1 */ @@ -101,23 +109,15 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, { const struct mdp_rdma_data *rdma = &ctx->param->rdma; const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); + u32 width = ctx->input->buffer.format.width; + u32 height = ctx->input->buffer.format.height; u32 colorformat = ctx->input->buffer.format.colorformat; + u32 write_mask = 0; bool block10bit = MDP_COLOR_IS_10BIT_PACKED(colorformat); bool en_ufo = MDP_COLOR_IS_UFP(colorformat); phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; - if (mdp_cfg && mdp_cfg->rdma_support_10bit) { - if (block10bit) - MM_REG_WRITE(cmd, subsys_id, base, - MDP_RDMA_RESV_DUMMY_0, - 0x00000007, 0x00000007); - else - MM_REG_WRITE(cmd, subsys_id, base, - MDP_RDMA_RESV_DUMMY_0, - 0x00000000, 0x00000007); - } - /* Setup smi control */ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_GMCIF_CON, (1 << 0) + @@ -129,7 +129,19 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_CON, rdma->src_ctrl, 0x03C8FE0F); - if (mdp_cfg) + if (mdp_cfg) { + if (mdp_cfg->rdma_support_10bit) { + if (block10bit) { + MM_REG_WRITE(cmd, subsys_id, base, + MDP_RDMA_RESV_DUMMY_0, + 0x00000007, 0x00000007); + } else { + MM_REG_WRITE(cmd, subsys_id, base, + MDP_RDMA_RESV_DUMMY_0, + 0x00000000, 0x00000007); + } + } + if (mdp_cfg->rdma_support_10bit && en_ufo) { /* Setup source buffer base */ MM_REG_WRITE(cmd, subsys_id, @@ -145,15 +157,74 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, rdma->mf_bkgd_in_pxl, 0x001FFFFF); } - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_CON, rdma->control, - 0x00001110); + if (mdp_cfg->rdma_support_extend_ufo) + write_mask |= 0xB0000000; + + if (mdp_cfg->rdma_support_afbc) + write_mask |= 0x0603000; + + if (mdp_cfg->rdma_support_hyfbc && + (MDP_COLOR_IS_HYFBC_COMPRESS(colorformat))) { + /* Setup source buffer base */ + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_UFO_DEC_LENGTH_BASE_Y, + rdma->ufo_dec_y, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_UFO_DEC_LENGTH_BASE_C, + rdma->ufo_dec_c, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_PXL, + ((width + 31) >> 5) << 5, 0x001FFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_H_SIZE_IN_PXL, + ((height + 7) >> 3) << 3, 0x001FFFFF); + + /* Setup Compression Control */ + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_COMP_CON, + rdma->comp_ctrl, write_mask); + } + + if (mdp_cfg->rdma_support_afbc && + (MDP_COLOR_IS_COMPRESS(colorformat))) { + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_PXL, + ((width + 31) >> 5) << 5, 0x001FFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_H_SIZE_IN_PXL, + ((height + 7) >> 3) << 3, 0x001FFFFF); + + /* Setup Compression Control */ + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_COMP_CON, + rdma->comp_ctrl, write_mask); + } + + if (mdp_cfg->rdma_esl_setting) { + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_0, + rdma->dmabuf_con0, 0x0FFF00FF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_0, + rdma->ultra_th_high_con0, 0x3FFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_0, + rdma->ultra_th_low_con0, 0x3FFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_1, + rdma->dmabuf_con1, 0x0F7F007F); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_1, + rdma->ultra_th_high_con1, 0x3FFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_1, + rdma->ultra_th_low_con1, 0x3FFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_2, + rdma->dmabuf_con2, 0x0F3F003F); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_2, + rdma->ultra_th_high_con2, 0x3FFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_2, + rdma->ultra_th_low_con2, 0x3FFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_3, + rdma->dmabuf_con3, 0x0F3F003F); + } + } + + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_CON, + rdma->control, 0x00001130); /* Setup source buffer base */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, rdma->iova[0], - 0xFFFFFFFF); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_1, rdma->iova[1], - 0xFFFFFFFF); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_2, rdma->iova[2], - 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, + rdma->iova[0], 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_1, + rdma->iova[1], 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_2, + rdma->iova[2], 0xFFFFFFFF); /* Setup source buffer end */ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_0, rdma->iova_end[0], 0xFFFFFFFF); @@ -169,7 +240,6 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, /* Setup color transform */ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_TRANSFORM_0, rdma->transform, 0x0F110000); - return 0; } @@ -186,19 +256,32 @@ static int config_rdma_subfrm(struct mdp_comp_ctx *ctx, u8 subsys_id = ctx->comp->subsys_id; /* Enable RDMA */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, 0x00000001, - 0x00000001); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_EN, + 0x00000001, 0x00000001); + + if (mdp_cfg->rdma_support_afbc || + mdp_cfg->rdma_support_hyfbc) { + if (MDP_COLOR_IS_COMPRESS(colorformat) || + MDP_COLOR_IS_HYFBC_COMPRESS(colorformat)) { + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0_P, + subfrm->in_tile_xleft, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_HP, + subfrm->in_tile_ytop, 0xFFFFFFFF); + } + } /* Set Y pixel offset */ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0, subfrm->offset[0], 0xFFFFFFFF); /* Set 10bit UFO mode */ - if (mdp_cfg) - if (mdp_cfg->rdma_support_10bit && block10bit && en_ufo) + if (mdp_cfg) { + if (mdp_cfg->rdma_support_10bit && block10bit && en_ufo) { MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0_P, subfrm->offset_0_p, 0xFFFFFFFF); + } + } /* Set U pixel offset */ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_1, @@ -216,31 +299,46 @@ static int config_rdma_subfrm(struct mdp_comp_ctx *ctx, MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_OFFSET_1, subfrm->clip_ofst, 0x003F001F); - if (mdp_cfg && mdp_cfg->rdma_upsample_repeat_only) - if ((csf->in.right - csf->in.left + 1) > 320) + if (mdp_cfg && mdp_cfg->rdma_upsample_repeat_only) { + if ((csf->in.right - csf->in.left + 1) > 320) { MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_RESV_DUMMY_0, 0x00000004, 0x00000004); + } + } return 0; } static int wait_rdma_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) { + struct device *dev = &ctx->comp->mdp_dev->pdev->dev; phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; int evt = -1; - if (ctx->comp->alias_id == 0) + switch (ctx->comp->alias_id) { + case 0: evt = mdp_get_event_idx(ctx->comp->mdp_dev, RDMA0_DONE); - else - pr_err("Do not support RDMA1_DONE event\n"); + break; + case 1: + evt = mdp_get_event_idx(ctx->comp->mdp_dev, RDMA1_FRAME_DONE); + break; + case 2: + evt = mdp_get_event_idx(ctx->comp->mdp_dev, RDMA2_FRAME_DONE); + break; + case 3: + evt = mdp_get_event_idx(ctx->comp->mdp_dev, RDMA3_FRAME_DONE); + break; + default: + dev_err(dev, "Invalid Engine!\n"); + } if (evt > 0) MM_REG_WAIT(cmd, evt); /* Disable RDMA */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, 0x00000000, - 0x00000001); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_EN, 0x00000000, + 0x00000001); return 0; } @@ -249,17 +347,122 @@ static const struct mdp_comp_ops rdma_ops = { .init_comp = init_rdma, .config_frame = config_rdma_frame, .config_subfrm = config_rdma_subfrm, - /* .reconfig_frame = reconfig_rdma_frame, */ - /* .reconfig_subfrms = reconfig_rdma_subfrms, */ .wait_comp_event = wait_rdma_event, .advance_subfrm = NULL, .post_process = NULL, }; +static int init_split(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) +{ + return 0; +} + +static int config_split_frame(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + return 0; +} + +static int config_split_subfrm(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, u32 index) +{ + return 0; +} + +static const struct mdp_comp_ops split_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_split, + .config_frame = config_split_frame, + .config_subfrm = config_split_subfrm, + .wait_comp_event = NULL, + .advance_subfrm = NULL, + .post_process = NULL, +}; + +static int init_stitch(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) +{ + return 0; +} + +static int config_stitch_frame(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + return 0; +} + +static int config_stitch_subfrm(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, u32 index) +{ + return 0; +} + +static const struct mdp_comp_ops stitch_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_stitch, + .config_frame = config_stitch_frame, + .config_subfrm = config_stitch_subfrm, + .wait_comp_event = NULL, + .advance_subfrm = NULL, + .post_process = NULL, +}; + +static int init_fg(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TRIGGER, + (0x00000001 << 2), 0x00000004); + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TRIGGER, + 0x00000000, 0x00000004); + + return 0; +} + +static int config_fg_frame(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + const struct mdp_fg_data *fg = &ctx->param->fg; + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CTRL_0, fg->ctrl_0, 0x1); + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CK_EN, fg->ck_en, 0x7); + return 0; +} + +static int config_fg_subfrm(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, u32 index) +{ + const struct mdp_fg_subfrm *subfrm = &ctx->param->fg.subfrms[index]; + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_0, subfrm->info_0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_1, subfrm->info_1, 0xFFFFFFFF); + + return 0; +} + +static const struct mdp_comp_ops fg_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_fg, + .config_frame = config_fg_frame, + .config_subfrm = config_fg_subfrm, + .wait_comp_event = NULL, + .advance_subfrm = NULL, + .post_process = NULL, +}; + static int init_rsz(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) { + const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 value = 0, mask = 0, alias_id = 0; /* Reset RSZ */ MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x00010000, @@ -269,6 +472,32 @@ static int init_rsz(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) /* Enable RSZ */ MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x00000001, 0x00000001); + + if (mdp_cfg && mdp_cfg->version == MTK_MDP_VERSION_8195) { + enum mdp_comp_id id = ctx->comp->id; + const struct mtk_mdp_driver_data *data = ctx->comp->mdp_dev->mdp_data; + + value = (1 << 25); + mask = (1 << 25); + alias_id = data->config_table[CONFIG_VPP1_HW_DCM_1ST_DIS0]; + mtk_mmsys_write_reg(ctx->comp->mdp_dev->mdp_mmsys2, + cmd, alias_id, value, mask); + + alias_id = data->config_table[CONFIG_VPP1_HW_DCM_2ND_DIS0]; + mtk_mmsys_write_reg(ctx->comp->mdp_dev->mdp_mmsys2, + cmd, alias_id, value, mask); + + value = (1 << 4 | 1 << 5); + mask = (1 << 4 | 1 << 5); + alias_id = data->config_table[CONFIG_VPP1_HW_DCM_1ST_DIS1]; + mtk_mmsys_write_reg(ctx->comp->mdp_dev->mdp_mmsys2, + cmd, alias_id, value, mask); + + alias_id = data->config_table[CONFIG_VPP1_HW_DCM_2ND_DIS1]; + mtk_mmsys_write_reg(ctx->comp->mdp_dev->mdp_mmsys2, + cmd, alias_id, value, mask); + } + return 0; } @@ -277,9 +506,13 @@ static int config_rsz_frame(struct mdp_comp_ctx *ctx, const struct v4l2_rect *compose) { const struct mdp_rsz_data *rsz = &ctx->param->rsz; + const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + if (mdp_cfg && mdp_cfg->rsz_etc_control) + MM_REG_WRITE(cmd, subsys_id, base, RSZ_ETC_CONTROL, 0x0, 0xFFFFFFFF); + if (ctx->param->frame.bypass) { /* Disable RSZ */ MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x00000000, @@ -320,23 +553,58 @@ static int config_rsz_subfrm(struct mdp_comp_ctx *ctx, MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET, csf->luma.left, 0x0000FFFF); - MM_REG_WRITE(cmd, subsys_id, - base, PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET, + MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET, csf->luma.left_subpix, 0x001FFFFF); MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_INTEGER_OFFSET, csf->luma.top, 0x0000FFFF); MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET, csf->luma.top_subpix, 0x001FFFFF); - MM_REG_WRITE(cmd, subsys_id, - base, PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET, + MM_REG_WRITE(cmd, subsys_id, base, PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET, csf->chroma.left, 0x0000FFFF); - MM_REG_WRITE(cmd, subsys_id, - base, PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET, + MM_REG_WRITE(cmd, subsys_id, base, PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET, csf->chroma.left_subpix, 0x001FFFFF); MM_REG_WRITE(cmd, subsys_id, base, PRZ_OUTPUT_IMAGE, subfrm->clip, 0xFFFFFFFF); + if (mdp_cfg && mdp_cfg->version == MTK_MDP_VERSION_8195) { + struct mdp_comp *merge; + const struct mtk_mdp_driver_data *data = ctx->comp->mdp_dev->mdp_data; + enum mtk_mdp_comp_id id = data->comp_data[ctx->comp->id].match.public_id; + u32 alias_id = 0; + + if (id == MDP_COMP_RSZ2) { + merge = ctx->comp->mdp_dev->comp[MDP_MERGE2]; + + alias_id = data->config_table[CONFIG_SVPP2_BUF_BF_RSZ_SWITCH]; + mtk_mmsys_write_reg(ctx->comp->mdp_dev->mdp_mmsys2, cmd, + alias_id, subfrm->rsz_switch, 0xFFFFFFFF); + } else if (id == MDP_COMP_RSZ3) { + merge = ctx->comp->mdp_dev->comp[MDP_MERGE3]; + + alias_id = data->config_table[CONFIG_SVPP3_BUF_BF_RSZ_SWITCH]; + mtk_mmsys_write_reg(ctx->comp->mdp_dev->mdp_mmsys2, cmd, + alias_id, subfrm->rsz_switch, 0xFFFFFFFF); + } else { + goto subfrm_done; + } + + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, + VPP_MERGE_CFG_0, subfrm->merge_cfg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, + VPP_MERGE_CFG_4, subfrm->merge_cfg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, + VPP_MERGE_CFG_24, subfrm->merge_cfg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, + VPP_MERGE_CFG_25, subfrm->merge_cfg, 0xFFFFFFFF); + + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, + VPP_MERGE_CFG_12, 0x1, 0xFFFFFFFF); // bypass mode + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, + VPP_MERGE_ENABLE, 0x1, 0xFFFFFFFF); + } + +subfrm_done: return 0; } @@ -363,13 +631,476 @@ static const struct mdp_comp_ops rsz_ops = { .init_comp = init_rsz, .config_frame = config_rsz_frame, .config_subfrm = config_rsz_subfrm, - /* .reconfig_frame = NULL, */ - /* .reconfig_subfrms = NULL, */ .wait_comp_event = NULL, .advance_subfrm = advance_rsz_subfrm, .post_process = NULL, }; +static int init_aal(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + // Always set MDP_AAL enable to 1 + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_EN, 0x1, 0x1); + + return 0; +} + +static int config_aal_frame(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + const struct mdp_aal_data *aal = &ctx->param->aal; + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_CFG_MAIN, aal->cfg_main, 0x80); + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_CFG, aal->cfg, 0x1); + + return 0; +} + +static int config_aal_subfrm(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, u32 index) +{ + const struct mdp_aal_subfrm *subfrm = &ctx->param->aal.subfrms[index]; + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_SIZE, + subfrm->src, MDP_AAL_SIZE_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_OFFSET, + subfrm->clip_ofst, 0x00FF00FF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_SIZE, + subfrm->clip, MDP_AAL_OUTPUT_SIZE_MASK); + + return 0; +} + +static const struct mdp_comp_ops aal_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_aal, + .config_frame = config_aal_frame, + .config_subfrm = config_aal_subfrm, + .wait_comp_event = NULL, + .advance_subfrm = NULL, + .post_process = NULL, +}; + +static int init_hdr(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + // Always set MDP_HDR enable to 1 + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, 1, 0x1); + + return 0; +} + +static int config_hdr_frame(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + const struct mdp_hdr_data *hdr = &ctx->param->hdr; + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, + hdr->top, 0x30000000); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_RELAY, + hdr->relay, 0x1); + + return 0; +} + +static int config_hdr_subfrm(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, u32 index) +{ + const struct mdp_hdr_subfrm *subfrm = &ctx->param->hdr.subfrms[index]; + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TILE_POS, + subfrm->win_size, MDP_HDR_TILE_POS_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_0, + subfrm->src, 0x1FFF1FFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_1, + subfrm->clip_ofst0, 0x1FFF1FFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_2, + subfrm->clip_ofst1, 0x1FFF1FFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_0, + subfrm->hist_ctrl_0, 0x00003FFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_1, + subfrm->hist_ctrl_1, 0x00003FFF); + + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, + subfrm->hdr_top, 0x00000060); + // enable hist_clr_en + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_ADDR, + subfrm->hist_addr, 0x00000200); + + return 0; +} + +static const struct mdp_comp_ops hdr_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_hdr, + .config_frame = config_hdr_frame, + .config_subfrm = config_hdr_subfrm, + .wait_comp_event = NULL, + .advance_subfrm = NULL, + .post_process = NULL, +}; + +void reset_luma_hist(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) +{ + const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + // reset LUMA HIST + MM_REG_WRITE(cmd, subsys_id, base, + MDP_LUMA_HIST_INIT_00, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_LUMA_HIST_INIT_01, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_LUMA_HIST_INIT_02, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_LUMA_HIST_INIT_03, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_LUMA_HIST_INIT_04, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_LUMA_HIST_INIT_05, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_LUMA_HIST_INIT_06, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_LUMA_HIST_INIT_07, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_LUMA_HIST_INIT_08, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_LUMA_HIST_INIT_09, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_LUMA_HIST_INIT_10, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_LUMA_HIST_INIT_11, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_LUMA_HIST_INIT_12, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_LUMA_HIST_INIT_13, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_LUMA_HIST_INIT_14, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_LUMA_HIST_INIT_15, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_LUMA_HIST_INIT_16, 0, 0xFFFFFFFF); + + if (mdp_cfg && mdp_cfg->tdshp_1_1 == 2) { + MM_REG_WRITE(cmd, subsys_id, base, + MDP_LUMA_SUM_INIT, 0, 0xFFFFFFFF); + } + + if (mdp_cfg && mdp_cfg->tdshp_dyn_contrast_version == 2) { + MM_REG_WRITE(cmd, subsys_id, base, + MDP_CONTOUR_HIST_INIT_00, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_CONTOUR_HIST_INIT_01, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_CONTOUR_HIST_INIT_02, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_CONTOUR_HIST_INIT_03, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_CONTOUR_HIST_INIT_04, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_CONTOUR_HIST_INIT_05, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_CONTOUR_HIST_INIT_06, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_CONTOUR_HIST_INIT_07, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_CONTOUR_HIST_INIT_08, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_CONTOUR_HIST_INIT_09, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_CONTOUR_HIST_INIT_10, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_CONTOUR_HIST_INIT_11, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_CONTOUR_HIST_INIT_12, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_CONTOUR_HIST_INIT_13, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_CONTOUR_HIST_INIT_14, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_CONTOUR_HIST_INIT_15, 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_CONTOUR_HIST_INIT_16, 0, 0xFFFFFFFF); + } +} + +static int init_tdshp(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CTRL, 0x00000001, + 0x00000001); + // Enable fifo + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CFG, 0x00000002, + 0x00000002); + reset_luma_hist(ctx, cmd); + + return 0; +} + +static int config_tdshp_frame(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + const struct mdp_tdshp_data *tdshp = &ctx->param->tdshp; + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CFG, tdshp->cfg, 0x00000001); + + return 0; +} + +static int config_tdshp_subfrm(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, u32 index) +{ + const struct mdp_tdshp_subfrm *subfrm = &ctx->param->tdshp.subfrms[index]; + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_INPUT_SIZE, + subfrm->src, MDP_TDSHP_INPUT_SIZE_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_OFFSET, + subfrm->clip_ofst, 0x00FF00FF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_SIZE, + subfrm->clip, MDP_TDSHP_OUTPUT_SIZE_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_00, + subfrm->hist_cfg_0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_01, + subfrm->hist_cfg_1, 0xFFFFFFFF); + + return 0; +} + +static const struct mdp_comp_ops tdshp_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_tdshp, + .config_frame = config_tdshp_frame, + .config_subfrm = config_tdshp_subfrm, + .wait_comp_event = NULL, + .advance_subfrm = NULL, + .post_process = NULL, +}; + +static int init_color(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, + DISP_COLOR_START, 0x1, 0x3); + MM_REG_WRITE(cmd, subsys_id, base, + DISP_COLOR_WIN_X_MAIN, 0xFFFF0000, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + DISP_COLOR_WIN_Y_MAIN, 0xFFFF0000, 0xFFFFFFFF); + + // R2Y/Y2R are disabled in MDP + MM_REG_WRITE(cmd, subsys_id, base, + DISP_COLOR_CM1_EN, 0x0, 0x1); + MM_REG_WRITE(cmd, subsys_id, base, + DISP_COLOR_CM2_EN, 0x0, 0x1); + + //enable interrupt + MM_REG_WRITE(cmd, subsys_id, base, + DISP_COLOR_INTEN, 0x00000007, 0x00000007); + + //Set 10bit->8bit Rounding + MM_REG_WRITE(cmd, subsys_id, base, + DISP_COLOR_OUT_SEL, 0x333, 0x333); + + return 0; +} + +static int config_color_frame(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + const struct mdp_color_data *color = &ctx->param->color; + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, + DISP_COLOR_START, color->start, DISP_COLOR_START_MASK); + + return 0; +} + +static int config_color_subfrm(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, u32 index) +{ + const struct mdp_color_subfrm *subfrm = &ctx->param->color.subfrms[index]; + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, DISP_COLOR_INTERNAL_IP_WIDTH, + subfrm->in_hsize, 0x00003FFF); + MM_REG_WRITE(cmd, subsys_id, base, DISP_COLOR_INTERNAL_IP_HEIGHT, + subfrm->in_vsize, 0x00003FFF); + + return 0; +} + +static const struct mdp_comp_ops color_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_color, + .config_frame = config_color_frame, + .config_subfrm = config_color_subfrm, + .wait_comp_event = NULL, + .advance_subfrm = NULL, + .post_process = NULL, +}; + +static int init_ovl(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, OVL_EN, + 0x1, OVL_EN_MASK); + //Relay Mode + MM_REG_WRITE(cmd, subsys_id, base, OVL_SRC_CON, + 0x200, OVL_SRC_CON_MASK); + //Connect OVL, enable smi_id mode + MM_REG_WRITE(cmd, subsys_id, base, OVL_DATAPATH_CON, + 0x1, OVL_DATAPATH_CON_MASK); + + return 0; +} + +static int config_ovl_frame(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + const struct mdp_ovl_data *ovl = &ctx->param->ovl; + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + //Layer0 for PQ-direct-in + MM_REG_WRITE(cmd, subsys_id, base, OVL_L0_CON, + ovl->L0_con, 0x30000000); + //Enable Layer0 + MM_REG_WRITE(cmd, subsys_id, base, OVL_SRC_CON, + ovl->src_con, 0x1); + + return 0; +} + +static int config_ovl_subfrm(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, u32 index) +{ + const struct mdp_ovl_subfrm *subfrm = &ctx->param->ovl.subfrms[index]; + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + //Setup Layer0 source size + MM_REG_WRITE(cmd, subsys_id, base, OVL_L0_SRC_SIZE, + subfrm->L0_src_size, OVL_L0_SRC_SIZE_MASK); + //Setup ROI size (output size) + MM_REG_WRITE(cmd, subsys_id, base, OVL_ROI_SIZE, + subfrm->roi_size, OVL_ROI_SIZE_MASK); + + return 0; +} + +static const struct mdp_comp_ops ovl_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_ovl, + .config_frame = config_ovl_frame, + .config_subfrm = config_ovl_subfrm, + .wait_comp_event = NULL, + .advance_subfrm = NULL, + .post_process = NULL, +}; + +static int init_pad(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, VPP_PADDING0_PADDING_CON, + 0x2, VPP_PADDING0_PADDING_CON_MASK); + //Clear padding area + MM_REG_WRITE(cmd, subsys_id, base, VPP_PADDING0_W_PADDING_SIZE, + 0x0, VPP_PADDING0_W_PADDING_SIZE_MASK); + MM_REG_WRITE(cmd, subsys_id, base, VPP_PADDING0_H_PADDING_SIZE, + 0x0, VPP_PADDING0_H_PADDING_SIZE_MASK); + + return 0; +} + +static int config_pad_frame(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + return 0; +} + +static int config_pad_subfrm(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, u32 index) +{ + const struct mdp_pad_subfrm *subfrm = &ctx->param->pad.subfrms[index]; + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, VPP_PADDING0_PADDING_PIC_SIZE, + subfrm->pic_size, VPP_PADDING0_PADDING_CON_MASK); + + return 0; +} + +static const struct mdp_comp_ops pad_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_pad, + .config_frame = config_pad_frame, + .config_subfrm = config_pad_subfrm, + .wait_comp_event = NULL, + .advance_subfrm = NULL, + .post_process = NULL, +}; + +static int init_tcc(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) +{ + return 0; +} + +static int config_tcc_frame(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + return 0; +} + +static int config_tcc_subfrm(struct mdp_comp_ctx *ctx, + struct mmsys_cmdq_cmd *cmd, u32 index) +{ + return 0; +} + +static const struct mdp_comp_ops tcc_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_tcc, + .config_frame = config_tcc_frame, + .config_subfrm = config_tcc_subfrm, + .wait_comp_event = NULL, + .advance_subfrm = NULL, + .post_process = NULL, +}; static int init_wrot(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) { phys_addr_t base = ctx->comp->reg_base; @@ -379,6 +1110,8 @@ static int init_wrot(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, 0x01, 0x00000001); MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, 0x01, 0x00000001); + /* Reset setting */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, 0x0, 0xFFFFFFFF); MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, 0x00, 0x00000001); MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, 0x00, 0x00000001); @@ -391,8 +1124,12 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx, { const struct mdp_wrot_data *wrot = &ctx->param->wrot; const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); + const struct mtk_mdp_driver_data *data = ctx->comp->mdp_dev->mdp_data; phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + bool comp = 0; + u32 colorformat = ctx->outputs[0]->buffer.format.colorformat; + u32 alias_id = 0; /* Write frame base address */ MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, wrot->iova[0], @@ -401,9 +1138,43 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx, 0xFFFFFFFF); MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, wrot->iova[2], 0xFFFFFFFF); + + if (mdp_cfg) { + if (mdp_cfg->wrot_support_afbc) { + comp = MDP_COLOR_IS_COMPRESS(colorformat); + if (comp) { + MM_REG_WRITE(cmd, subsys_id, base, VIDO_FRAME_SIZE, + wrot->framesize, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_AFBC_YUVTRANS, + wrot->afbc_yuvtrans, 0x1); + } + MM_REG_WRITE(cmd, subsys_id, base, VIDO_PVRIC, wrot->pvric, 0x03); + } + + if (mdp_cfg->wrot_support_10bit) { + MM_REG_WRITE(cmd, subsys_id, base, VIDO_SCAN_10BIT, + wrot->scan_10bit, 0x0000000F); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_PENDING_ZERO, + wrot->pending_zero, 0x04000000); + } + if (mdp_cfg->version == MTK_MDP_VERSION_8195) + MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL_2, + wrot->bit_number, 0x00000007); + + /* Filter enable */ + if (mdp_cfg->wrot_filter_constraint) + MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, + wrot->filter, 0x00000077); + } + /* Write frame related registers */ MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, wrot->control, 0xF131510F); + + /* Write pre-ultra threshold */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_DMA_PREULTRA, wrot->pre_ultra, + 0x00FFFFFF); + /* Write frame Y pitch */ MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE, wrot->stride[0], 0x0000FFFF); @@ -426,10 +1197,25 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx, if (wrot->fifo_test != 0) MM_REG_WRITE(cmd, subsys_id, base, VIDO_FIFO_TEST, wrot->fifo_test, 0x00000FFF); - /* Filter enable */ - if (mdp_cfg && mdp_cfg->wrot_filter_constraint) - MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, - wrot->filter, 0x00000077); + + /* Turn off WROT dma dcm */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, + (0x1 << 23) + (0x1 << 20), 0x00900000); + + if (wrot->vpp02vpp1) { + // Disable DCM (VPP02VPP1_RELAY) + alias_id = data->config_table[CONFIG_VPP0_HW_DCM_1ST_DIS0]; + mtk_mmsys_write_reg(ctx->comp->mdp_dev->mdp_mmsys, cmd, + alias_id, 0x4000, 0xFFFFFFFF); + // Set default size + alias_id = data->config_table[CONFIG_VPP0_DL_IRELAY_WR]; + mtk_mmsys_write_reg(ctx->comp->mdp_dev->mdp_mmsys2, cmd, + alias_id, 0x0, 0xFFFFFFFF); + } else { + alias_id = data->config_table[CONFIG_VPP0_HW_DCM_1ST_DIS0]; + mtk_mmsys_write_reg(ctx->comp->mdp_dev->mdp_mmsys, cmd, + alias_id, 0x0, 0xFFFFFFFF); + } return 0; } @@ -459,6 +1245,9 @@ static int config_wrot_subfrm(struct mdp_comp_ctx *ctx, MM_REG_WRITE(cmd, subsys_id, base, VIDO_CROP_OFST, subfrm->clip_ofst, 0x1FFF1FFF); + // Set wrot interrupt bit for debug, this bit will clear to 0 after wrot done. + MM_REG_WRITE(cmd, subsys_id, base, VIDO_INT, 0x1, VIDO_INT_MASK); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, subfrm->main_buf, 0x1FFF7F00); @@ -471,15 +1260,27 @@ static int config_wrot_subfrm(struct mdp_comp_ctx *ctx, static int wait_wrot_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd) { const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); + struct device *dev = &ctx->comp->mdp_dev->pdev->dev; phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; int evt = -1; - if (ctx->comp->alias_id == 0) + switch (ctx->comp->alias_id) { + case 0: evt = mdp_get_event_idx(ctx->comp->mdp_dev, WROT0_DONE); - else - pr_err("Do not support WROT1_DONE event\n"); - + break; + case 1: + evt = mdp_get_event_idx(ctx->comp->mdp_dev, WROT1_FRAME_DONE); + break; + case 2: + evt = mdp_get_event_idx(ctx->comp->mdp_dev, WROT2_FRAME_DONE); + break; + case 3: + evt = mdp_get_event_idx(ctx->comp->mdp_dev, WROT3_FRAME_DONE); + break; + default: + dev_err(dev, "Invalid Engine!\n"); + } if (evt > 0) MM_REG_WAIT(cmd, evt); @@ -498,8 +1299,6 @@ static const struct mdp_comp_ops wrot_ops = { .init_comp = init_wrot, .config_frame = config_wrot_frame, .config_subfrm = config_wrot_subfrm, - /* .reconfig_frame = reconfig_wrot_frame, */ - /* .reconfig_subfrms = reconfig_wrot_subfrms, */ .wait_comp_event = wait_wrot_event, .advance_subfrm = NULL, .post_process = NULL, @@ -648,8 +1447,6 @@ static const struct mdp_comp_ops ccorr_ops = { .init_comp = init_ccorr, .config_frame = config_ccorr_frame, .config_subfrm = config_ccorr_subfrm, - /* .reconfig_frame = NULL, */ - /* .reconfig_subfrms = NULL, */ .wait_comp_event = NULL, .advance_subfrm = NULL, .post_process = NULL, @@ -865,8 +1662,6 @@ static const struct mdp_comp_ops imgi_ops = { .init_comp = init_isp, .config_frame = config_isp_frame, .config_subfrm = config_isp_subfrm, - /* .reconfig_frame = reconfig_isp_frame, */ - /* .reconfig_subfrms = reconfig_isp_subfrms, */ .wait_comp_event = wait_isp_event, .advance_subfrm = NULL, .post_process = NULL, @@ -898,25 +1693,36 @@ static const struct mdp_comp_ops camin_ops = { .init_comp = NULL, .config_frame = NULL, .config_subfrm = config_camin_subfrm, - /* .reconfig_frame = NULL, */ - /* .reconfig_subfrms = NULL, */ .wait_comp_event = NULL, .advance_subfrm = NULL, .post_process = NULL, }; static const struct mdp_comp_ops *mdp_comp_ops[MDP_COMP_TYPE_COUNT] = { - [MDP_COMP_TYPE_RDMA] = &rdma_ops, - [MDP_COMP_TYPE_RSZ] = &rsz_ops, - [MDP_COMP_TYPE_WROT] = &wrot_ops, - [MDP_COMP_TYPE_WDMA] = &wdma_ops, - [MDP_COMP_TYPE_PATH1] = NULL, - [MDP_COMP_TYPE_PATH2] = NULL, - [MDP_COMP_TYPE_CCORR] = &ccorr_ops, - [MDP_COMP_TYPE_IMGI] = &imgi_ops, - [MDP_COMP_TYPE_EXTO] = NULL, - [MDP_COMP_TYPE_DL_PATH1] = &camin_ops, - [MDP_COMP_TYPE_DL_PATH2] = &camin_ops, + [MDP_COMP_TYPE_WPEI] = &camin_ops, + [MDP_COMP_TYPE_SPLIT] = &split_ops, + [MDP_COMP_TYPE_STITCH] = &stitch_ops, + [MDP_COMP_TYPE_RDMA] = &rdma_ops, + [MDP_COMP_TYPE_FG] = &fg_ops, + [MDP_COMP_TYPE_HDR] = &hdr_ops, + [MDP_COMP_TYPE_AAL] = &aal_ops, + [MDP_COMP_TYPE_RSZ] = &rsz_ops, + [MDP_COMP_TYPE_TDSHP] = &tdshp_ops, + [MDP_COMP_TYPE_COLOR] = &color_ops, + [MDP_COMP_TYPE_OVL] = &ovl_ops, + [MDP_COMP_TYPE_PAD] = &pad_ops, + [MDP_COMP_TYPE_TCC] = &tcc_ops, + [MDP_COMP_TYPE_WROT] = &wrot_ops, + [MDP_COMP_TYPE_WDMA] = &wdma_ops, + [MDP_COMP_TYPE_MERGE] = NULL, + [MDP_COMP_TYPE_PATH1] = NULL, + [MDP_COMP_TYPE_PATH2] = NULL, + [MDP_COMP_TYPE_CCORR] = &ccorr_ops, + [MDP_COMP_TYPE_IMGI] = &imgi_ops, + [MDP_COMP_TYPE_EXTO] = NULL, + [MDP_COMP_TYPE_DL_PATH1] = &camin_ops, + [MDP_COMP_TYPE_DL_PATH2] = &camin_ops, + [MDP_COMP_TYPE_DUMMY] = NULL, }; static const struct of_device_id mdp_comp_dt_ids[] = { @@ -935,6 +1741,39 @@ static const struct of_device_id mdp_comp_dt_ids[] = { }, { .compatible = "mediatek,mt8183-mdp3-wdma", .data = (void *)MDP_COMP_TYPE_WDMA, + }, { + .compatible = "mediatek,mt8195-mdp3-split", + .data = (void *)MDP_COMP_TYPE_SPLIT, + }, { + .compatible = "mediatek,mt8195-mdp3-stitch", + .data = (void *)MDP_COMP_TYPE_STITCH, + }, { + .compatible = "mediatek,mt8195-mdp3-fg", + .data = (void *)MDP_COMP_TYPE_FG, + }, { + .compatible = "mediatek,mt8195-mdp3-hdr", + .data = (void *)MDP_COMP_TYPE_HDR, + }, { + .compatible = "mediatek,mt8195-mdp3-aal", + .data = (void *)MDP_COMP_TYPE_AAL, + }, { + .compatible = "mediatek,mt8195-mdp3-merge", + .data = (void *)MDP_COMP_TYPE_MERGE, + }, { + .compatible = "mediatek,mt8195-mdp3-tdshp", + .data = (void *)MDP_COMP_TYPE_TDSHP, + }, { + .compatible = "mediatek,mt8195-mdp3-color", + .data = (void *)MDP_COMP_TYPE_COLOR, + }, { + .compatible = "mediatek,mt8195-mdp3-ovl", + .data = (void *)MDP_COMP_TYPE_OVL, + }, { + .compatible = "mediatek,mt8195-mdp3-pad", + .data = (void *)MDP_COMP_TYPE_PAD, + }, { + .compatible = "mediatek,mt8195-mdp3-tcc", + .data = (void *)MDP_COMP_TYPE_TCC, }, {} }; @@ -952,12 +1791,36 @@ static const struct of_device_id mdp_sub_comp_dt_ids[] = { }, { .compatible = "mediatek,mt8183-mdp3-exto", .data = (void *)MDP_COMP_TYPE_EXTO, + }, { + .compatible = "mediatek,mt8195-mdp3-path1", + .data = (void *)MDP_COMP_TYPE_PATH1, + }, { + .compatible = "mediatek,mt8195-mdp3-path2", + .data = (void *)MDP_COMP_TYPE_PATH2, }, { .compatible = "mediatek,mt8183-mdp3-dl1", .data = (void *)MDP_COMP_TYPE_DL_PATH1, }, { .compatible = "mediatek,mt8183-mdp3-dl2", .data = (void *)MDP_COMP_TYPE_DL_PATH2, + }, { + .compatible = "mediatek,mt8195-mdp3-dl1", + .data = (void *)MDP_COMP_TYPE_DL_PATH1, + }, { + .compatible = "mediatek,mt8195-mdp3-dl2", + .data = (void *)MDP_COMP_TYPE_DL_PATH2, + }, { + .compatible = "mediatek,mt8195-mdp3-dl3", + .data = (void *)MDP_COMP_TYPE_DL_PATH3, + }, { + .compatible = "mediatek,mt8195-mdp3-dl4", + .data = (void *)MDP_COMP_TYPE_DL_PATH4, + }, { + .compatible = "mediatek,mt8195-mdp3-dl5", + .data = (void *)MDP_COMP_TYPE_DL_PATH5, + }, { + .compatible = "mediatek,mt8195-mdp3-dl6", + .data = (void *)MDP_COMP_TYPE_DL_PATH6, }, {} }; @@ -1304,3 +2167,198 @@ int mdp_comp_ctx_init(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx, ctx->outputs[i] = &frame->outputs[param->outputs[i]]; return 0; } + +int mdp_hyfbc_patch(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd, + struct hyfbc_patch_info *hyfbc, enum mdp_comp_id wrot) +{ +#define is_wrot(id) \ + ((mdp)->mdp_data->comp_data[id].match.type == MDP_COMP_TYPE_WROT) + +#define byte2pixel(byte) ((byte) / 2) + + struct mtk_mutex **mutex = mdp->mdp_mutex; + struct mtk_mutex **mutex2 = mdp->mdp_mutex2; + enum mtk_mdp_comp_id mtk_wrot = MDP_COMP_NONE; + phys_addr_t base; + u16 subsys_id; + u32 offset; + u32 mutex_id; + u32 mutex2_id; + u32 alias_id; + int evt; + + if (!is_wrot(wrot)) { + dev_info(&mdp->pdev->dev, "Invalid wrot id %d", wrot); + return -EINVAL; + } + + base = mdp->comp[wrot]->reg_base; + subsys_id = mdp->comp[wrot]->subsys_id; + offset = hyfbc->width_in_mb * hyfbc->byte_per_mb; + + /* Reset WROT */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, + 0x01, 0x00000001); + MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, + 0x01, 0x00000001); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, + 0x00, 0x00000001); + MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, + 0x00, 0x00000001); + + /* Write frame base address */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, + (hyfbc->pa_base + offset), 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_C, + 0x0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, + 0x0, 0xFFFFFFFF); + + /* Write frame related registers */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, + 0x5020, 0xF131512F); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_BKGD, + ((hyfbc->is10b) ? 0xC8E438 : 0x18f4f8), 0xFFFFFFFF); + + MM_REG_WRITE(cmd, subsys_id, base, VIDO_SCAN_10BIT, + 0x0, 0x0000000F); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_PENDING_ZERO, + 0x0, 0x04000000); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL_2, + 0x0, 0x00000007); + + MM_REG_WRITE(cmd, subsys_id, base, VIDO_PVRIC, + 0x0, 0x03); + /* Write pre-ultra threshold */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_DMA_PREULTRA, + 0x8804c, 0x00FFFFFF); + /* Write frame Y pitch */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE, + (hyfbc->w_stride_in_mb * hyfbc->byte_per_mb), 0x0000FFFF); + /* Write frame UV pitch */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_C, + 0x0, 0x0000FFFF); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_V, + 0x0, 0x0000FFFF); + /* Write matrix control */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAT_CTRL, + 0x60, 0x000000F3); + + /* Set the fixed ALPHA as 0xFF */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_DITHER, + 0xFF000000, 0xFF000000); + /* Set VIDO_EOL_SEL */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_RSV_1, + 0x80000000, 0x80000000); + /* Set VIDO_FIFO_TEST */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_FIFO_TEST, + 0x200, 0x00000FFF); + + /* Filter enable */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, + 0x0, 0x00000077); + + /* Turn off WROT dma dcm */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, + (0x1 << 23) + (0x1 << 20), 0x00900000); + + alias_id = mdp->mdp_data->config_table[CONFIG_VPP0_HW_DCM_1ST_DIS0]; + mtk_mmsys_write_reg(mdp->mdp_mmsys, cmd, + alias_id, 0x0, 0xFFFFFFFF); + + mtk_wrot = mdp->mdp_data->comp_data[wrot].match.public_id; + /* Set mutex modules */ + switch (mtk_wrot) { + case MDP_COMP_WROT0: + mutex_id = 2; + mtk_mutex_add_mdp_mod(mutex[mutex_id], + 0x800, 0x0, 0x0, cmd); + break; + case MDP_COMP_WROT1: + mutex2_id = 1; + mtk_mutex_add_mdp_mod(mutex2[mutex2_id], + 0x80000000, 0x0, 0x0, cmd); + break; + case MDP_COMP_WROT2: + mutex2_id = 2; + mtk_mutex_add_mdp_mod(mutex2[mutex2_id], + 0x0, 0x1, 0x0, cmd); + break; + case MDP_COMP_WROT3: + mutex2_id = 3; + mtk_mutex_add_mdp_mod(mutex2[mutex2_id], + 0x0, 0x2, 0x0, cmd); + break; + default: + break; + } + + /* Write Y pixel offset */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR, + 0x0, 0x0FFFFFFF); + /* Write U pixel offset */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_C, + 0x0, 0x0FFFFFFF); + /* Write V pixel offset */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_V, + 0x0, 0x0FFFFFFF); + /* Write source size */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_IN_SIZE, + (hyfbc->height_in_mb << 16) | byte2pixel(hyfbc->byte_per_mb), 0xFFFFFFFF); + /* Write target size */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_TAR_SIZE, + (hyfbc->height_in_mb << 16) | byte2pixel(hyfbc->byte_per_mb), 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_CROP_OFST, 0x0, + 0xFFFFFFFF); + + MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, + ((byte2pixel(hyfbc->byte_per_mb) << 16) | 0x400), 0xFFFF7F00); + + // Set wrot interrupt bit for debug, this bit will clear to 0 after wrot done. + MM_REG_WRITE(cmd, subsys_id, base, VIDO_INT, 0x1, VIDO_INT_MASK); + + /* Enable WROT */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, 0x01, 0x00000001); + + switch (mtk_wrot) { + case MDP_COMP_WROT0: + evt = mdp_get_event_idx(mdp, WROT0_SOF); + MM_REG_CLEAR(cmd, evt); + mtk_mutex_enable_by_cmdq(mutex[mutex_id], cmd); + MM_REG_WAIT(cmd, evt); + evt = mdp_get_event_idx(mdp, WROT0_DONE); + MM_REG_WAIT(cmd, evt); + break; + case MDP_COMP_WROT1: + evt = mdp_get_event_idx(mdp, WROT1_SOF); + MM_REG_CLEAR(cmd, evt); + mtk_mutex_enable_by_cmdq(mutex2[mutex2_id], cmd); + MM_REG_WAIT(cmd, evt); + evt = mdp_get_event_idx(mdp, WROT1_FRAME_DONE); + MM_REG_WAIT(cmd, evt); + break; + case MDP_COMP_WROT2: + evt = mdp_get_event_idx(mdp, WROT2_SOF); + MM_REG_CLEAR(cmd, evt); + mtk_mutex_enable_by_cmdq(mutex2[mutex2_id], cmd); + MM_REG_WAIT(cmd, evt); + evt = mdp_get_event_idx(mdp, WROT2_FRAME_DONE); + MM_REG_WAIT(cmd, evt); + break; + case MDP_COMP_WROT3: + evt = mdp_get_event_idx(mdp, WROT3_SOF); + MM_REG_CLEAR(cmd, evt); + mtk_mutex_enable_by_cmdq(mutex2[mutex2_id], cmd); + MM_REG_WAIT(cmd, evt); + evt = mdp_get_event_idx(mdp, WROT3_FRAME_DONE); + MM_REG_WAIT(cmd, evt); + break; + default: + break; + } + + /* Disable WROT */ + MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, 0x00, 0x00000001); + + return 0; +} diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h index 02957abd12d0..41833ecd6752 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h @@ -123,6 +123,76 @@ enum mdp_comp_id { MT8183_MDP_COMP_WROT1, /* 25 */ MT8183_MDP_MAX_COMP_COUNT, + /* MT8195 Comp id */ + /* ISP */ + MT8195_MDP_COMP_WPEI = 0, + MT8195_MDP_COMP_WPEO, /* 1 */ + MT8195_MDP_COMP_WPEI2, /* 2 */ + MT8195_MDP_COMP_WPEO2, /* 3 */ + + /* MDP */ + MT8195_MDP_COMP_CAMIN, /* 4 */ + MT8195_MDP_COMP_CAMIN2, /* 5 */ + MT8195_MDP_COMP_SPLIT, /* 6 */ + MT8195_MDP_COMP_SPLIT2, /* 7 */ + MT8195_MDP_COMP_RDMA0, /* 8 */ + MT8195_MDP_COMP_RDMA1, /* 9 */ + MT8195_MDP_COMP_RDMA2, /* 10 */ + MT8195_MDP_COMP_RDMA3, /* 11 */ + MT8195_MDP_COMP_STITCH, /* 12 */ + MT8195_MDP_COMP_FG0, /* 13 */ + MT8195_MDP_COMP_FG1, /* 14 */ + MT8195_MDP_COMP_FG2, /* 15 */ + MT8195_MDP_COMP_FG3, /* 16 */ + MT8195_MDP_COMP_TO_SVPP2MOUT, /* 17 */ + MT8195_MDP_COMP_TO_SVPP3MOUT, /* 18 */ + MT8195_MDP_COMP_TO_WARP0MOUT, /* 19 */ + MT8195_MDP_COMP_TO_WARP1MOUT, /* 20 */ + MT8195_MDP_COMP_VPP0_SOUT, /* 21 */ + MT8195_MDP_COMP_VPP1_SOUT, /* 22 */ + MT8195_MDP_COMP_PQ0_SOUT, /* 23 */ + MT8195_MDP_COMP_PQ1_SOUT, /* 24 */ + MT8195_MDP_COMP_HDR0, /* 25 */ + MT8195_MDP_COMP_HDR1, /* 26 */ + MT8195_MDP_COMP_HDR2, /* 27 */ + MT8195_MDP_COMP_HDR3, /* 28 */ + MT8195_MDP_COMP_AAL0, /* 29 */ + MT8195_MDP_COMP_AAL1, /* 30 */ + MT8195_MDP_COMP_AAL2, /* 31 */ + MT8195_MDP_COMP_AAL3, /* 32 */ + MT8195_MDP_COMP_RSZ0, /* 33 */ + MT8195_MDP_COMP_RSZ1, /* 34 */ + MT8195_MDP_COMP_RSZ2, /* 35 */ + MT8195_MDP_COMP_RSZ3, /* 36 */ + MT8195_MDP_COMP_TDSHP0, /* 37 */ + MT8195_MDP_COMP_TDSHP1, /* 38 */ + MT8195_MDP_COMP_TDSHP2, /* 39 */ + MT8195_MDP_COMP_TDSHP3, /* 40 */ + MT8195_MDP_COMP_COLOR0, /* 41 */ + MT8195_MDP_COMP_COLOR1, /* 42 */ + MT8195_MDP_COMP_COLOR2, /* 43 */ + MT8195_MDP_COMP_COLOR3, /* 44 */ + MT8195_MDP_COMP_OVL0, /* 45 */ + MT8195_MDP_COMP_OVL1, /* 46 */ + MT8195_MDP_COMP_PAD0, /* 47 */ + MT8195_MDP_COMP_PAD1, /* 48 */ + MT8195_MDP_COMP_PAD2, /* 49 */ + MT8195_MDP_COMP_PAD3, /* 50 */ + MT8195_MDP_COMP_TCC0, /* 51 */ + MT8195_MDP_COMP_TCC1, /* 52 */ + MT8195_MDP_COMP_WROT0, /* 53 */ + MT8195_MDP_COMP_WROT1, /* 54 */ + MT8195_MDP_COMP_WROT2, /* 55 */ + MT8195_MDP_COMP_WROT3, /* 56 */ + MT8195_MDP_COMP_MERGE2, /* 57 */ + MT8195_MDP_COMP_MERGE3, /* 58 */ + + MT8195_MDP_COMP_VDO0DL0, /* 59 */ + MT8195_MDP_COMP_VDO1DL0, /* 60 */ + MT8195_MDP_COMP_VDO0DL1, /* 61 */ + MT8195_MDP_COMP_VDO1DL1, /* 62 */ + MT8195_MDP_MAX_COMP_COUNT, + MDP_MAX_COMP /* ALWAYS keep at the end */ }; @@ -269,6 +339,16 @@ struct mdp_comp_info { u32 dts_reg_ofst; }; +struct hyfbc_patch_info { + bool is10b; + u32 width_in_mb; + u32 height_in_mb; + u32 w_stride_in_mb; + u32 h_stride_in_mb; + u32 byte_per_mb; + u32 pa_base; +}; + struct mdp_comp_ops; struct mdp_comp { @@ -328,7 +408,8 @@ void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num); int mdp_comp_ctx_init(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx, const struct img_compparam *param, const struct img_ipi_frameparam *frame); - +int mdp_hyfbc_patch(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd, + struct hyfbc_patch_info *hyfbc, enum mdp_comp_id wrot); int mdp_get_event_idx(struct mdp_dev *mdp, enum mdp_comp_event event); #endif /* __MTK_MDP3_COMP_H__ */ diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c index 4f7d8bc1bf24..524c852e584b 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c @@ -18,12 +18,30 @@ /* MDP debug log level (0-3). 3 shows all the logs. */ static const struct mdp_platform_config mt8183_plat_cfg = { - .rdma_support_10bit = true, - .rdma_rsz1_sram_sharing = true, - .rdma_upsample_repeat_only = true, - .rsz_disable_dcm_small_sample = false, - .wrot_filter_constraint = false, - .gce_event_offset = 0, + .rdma_support_10bit = true, + .rdma_rsz1_sram_sharing = true, + .rdma_upsample_repeat_only = true, + .rsz_disable_dcm_small_sample = false, + .wrot_filter_constraint = false, + .gce_event_offset = 0, + .version = MTK_MDP_VERSION_8183, +}; + +static const struct mdp_platform_config mt8195_plat_cfg = { + .rdma_support_10bit = true, + .rdma_support_extend_ufo = true, + .rdma_support_hyfbc = true, + .rdma_support_afbc = true, + .rdma_esl_setting = true, + .rdma_rsz1_sram_sharing = false, + .rdma_upsample_repeat_only = true, + .rsz_disable_dcm_small_sample = false, + .rsz_etc_control = true, + .wrot_filter_constraint = false, + .tdshp_1_1 = true, + .tdshp_dyn_contrast_version = 2, + .gce_event_offset = 0, + .version = MTK_MDP_VERSION_8195, }; static const struct mdp_comp_list mt8183_comp_list = { @@ -88,6 +106,68 @@ static const struct mdp_comp_list mt8183_comp_list = { .path1_sout = MT8183_MDP_COMP_PATH1_SOUT, }; +static const struct mdp_comp_list mt8195_comp_list = { + .wpei = MT8195_MDP_COMP_WPEI, + .wpeo = MT8195_MDP_COMP_WPEO, + .wpei2 = MT8195_MDP_COMP_WPEI2, + .wpeo2 = MT8195_MDP_COMP_WPEO2, + .camin = MT8195_MDP_COMP_CAMIN, + .camin2 = MT8195_MDP_COMP_CAMIN2, + .split = MT8195_MDP_COMP_SPLIT, + .split2 = MT8195_MDP_COMP_SPLIT2, + .rdma0 = MT8195_MDP_COMP_RDMA0, + .rdma1 = MT8195_MDP_COMP_RDMA1, + .rdma2 = MT8195_MDP_COMP_RDMA2, + .rdma3 = MT8195_MDP_COMP_RDMA3, + .stitch = MT8195_MDP_COMP_STITCH, + .fg0 = MT8195_MDP_COMP_FG0, + .fg1 = MT8195_MDP_COMP_FG1, + .fg2 = MT8195_MDP_COMP_FG2, + .fg3 = MT8195_MDP_COMP_FG3, + .hdr0 = MT8195_MDP_COMP_HDR0, + .hdr1 = MT8195_MDP_COMP_HDR1, + .hdr2 = MT8195_MDP_COMP_HDR2, + .hdr3 = MT8195_MDP_COMP_HDR3, + .aal0 = MT8195_MDP_COMP_AAL0, + .aal1 = MT8195_MDP_COMP_AAL1, + .aal2 = MT8195_MDP_COMP_AAL2, + .aal3 = MT8195_MDP_COMP_AAL3, + .rsz0 = MT8195_MDP_COMP_RSZ0, + .rsz1 = MT8195_MDP_COMP_RSZ1, + .rsz2 = MT8195_MDP_COMP_RSZ2, + .rsz3 = MT8195_MDP_COMP_RSZ3, + .tdshp0 = MT8195_MDP_COMP_TDSHP0, + .tdshp1 = MT8195_MDP_COMP_TDSHP1, + .tdshp2 = MT8195_MDP_COMP_TDSHP2, + .tdshp3 = MT8195_MDP_COMP_TDSHP3, + .color0 = MT8195_MDP_COMP_COLOR0, + .color1 = MT8195_MDP_COMP_COLOR1, + .color2 = MT8195_MDP_COMP_COLOR2, + .color3 = MT8195_MDP_COMP_COLOR3, + .ccorr0 = MDP_COMP_INVALID, + .ovl0 = MT8195_MDP_COMP_OVL0, + .ovl1 = MT8195_MDP_COMP_OVL1, + .pad0 = MT8195_MDP_COMP_PAD0, + .pad1 = MT8195_MDP_COMP_PAD1, + .pad2 = MT8195_MDP_COMP_PAD2, + .pad3 = MT8195_MDP_COMP_PAD3, + .tcc0 = MT8195_MDP_COMP_TCC0, + .tcc1 = MT8195_MDP_COMP_TCC1, + .wrot0 = MT8195_MDP_COMP_WROT0, + .wrot1 = MT8195_MDP_COMP_WROT1, + .wrot2 = MT8195_MDP_COMP_WROT2, + .wrot3 = MT8195_MDP_COMP_WROT3, + .merge2 = MT8195_MDP_COMP_MERGE2, + .merge3 = MT8195_MDP_COMP_MERGE3, + .wdma = MDP_COMP_INVALID, + .vdo0dl0 = MT8195_MDP_COMP_VDO0DL0, + .vdo1dl0 = MT8195_MDP_COMP_VDO1DL0, + .vdo0dl1 = MT8195_MDP_COMP_VDO0DL1, + .vdo1dl1 = MT8195_MDP_COMP_VDO1DL1, + .path0_sout = MDP_COMP_INVALID, + .path1_sout = MDP_COMP_INVALID, +}; + static const struct mdp_comp_data mt8183_mdp_comp_data[MT8183_MDP_MAX_COMP_COUNT] = { [MT8183_MDP_COMP_WPEI] = { {MDP_COMP_TYPE_WPEI, 0, MDP_COMP_WPEI}, {0, 0, 0} }, [MT8183_MDP_COMP_WPEO] = { {MDP_COMP_TYPE_EXTO, 2, MDP_COMP_WPEO}, {0, 0, 0} }, @@ -111,6 +191,261 @@ static const struct mdp_comp_data mt8183_mdp_comp_data[MT8183_MDP_MAX_COMP_COUNT [MT8183_MDP_COMP_WDMA] = { {MDP_COMP_TYPE_WDMA, 0, MDP_COMP_WDMA}, {0, BIT(8), 0} }, }; +static const struct mdp_comp_data mt8195_mdp_comp_data[MT8195_MDP_MAX_COMP_COUNT] = { + [MT8195_MDP_COMP_WPEI] = { + {MDP_COMP_TYPE_WPEI, 0, MDP_COMP_WPEI}, + {0, BIT(13), 0} + }, + [MT8195_MDP_COMP_WPEO] = { + {MDP_COMP_TYPE_EXTO, 2, MDP_COMP_WPEO}, + {0, 0, 0} + }, + [MT8195_MDP_COMP_WPEI2] = { + {MDP_COMP_TYPE_WPEI, 1, MDP_COMP_WPEI2}, + {0, BIT(14), 0} + }, + [MT8195_MDP_COMP_WPEO2] = { + {MDP_COMP_TYPE_EXTO, 3, MDP_COMP_WPEO2}, + {0, 0, 0} + }, + [MT8195_MDP_COMP_CAMIN] = { + {MDP_COMP_TYPE_DL_PATH1, 0, MDP_COMP_CAMIN}, + {0, 0, 0} + }, + [MT8195_MDP_COMP_CAMIN2] = { + {MDP_COMP_TYPE_DL_PATH2, 1, MDP_COMP_CAMIN2}, + {0, 0, 0} + }, + [MT8195_MDP_COMP_SPLIT] = { + {MDP_COMP_TYPE_SPLIT, 0, MDP_COMP_SPLIT}, + {1, 0, BIT(2)} + }, + [MT8195_MDP_COMP_SPLIT2] = { + {MDP_COMP_TYPE_SPLIT, 1, MDP_COMP_SPLIT2}, + {1, BIT(2), 0} + }, + [MT8195_MDP_COMP_RDMA0] = { + {MDP_COMP_TYPE_RDMA, 0, MDP_COMP_RDMA0}, + {0, BIT(0), 0} + }, + [MT8195_MDP_COMP_RDMA1] = { + {MDP_COMP_TYPE_RDMA, 1, MDP_COMP_RDMA1}, + {1, BIT(4), 0} + }, + [MT8195_MDP_COMP_RDMA2] = { + {MDP_COMP_TYPE_RDMA, 2, MDP_COMP_RDMA2}, + {1, BIT(5), 0} + }, + [MT8195_MDP_COMP_RDMA3] = { + {MDP_COMP_TYPE_RDMA, 3, MDP_COMP_RDMA3}, + {1, BIT(6), 0} + }, + [MT8195_MDP_COMP_STITCH] = { + {MDP_COMP_TYPE_STITCH, 0, MDP_COMP_STITCH}, + {0, BIT(2), 0} + }, + [MT8195_MDP_COMP_FG0] = { + {MDP_COMP_TYPE_FG, 0, MDP_COMP_FG0}, + {0, BIT(1), 0} + }, + [MT8195_MDP_COMP_FG1] = { + {MDP_COMP_TYPE_FG, 1, MDP_COMP_FG1}, + {1, BIT(7), 0} + }, + [MT8195_MDP_COMP_FG2] = { + {MDP_COMP_TYPE_FG, 2, MDP_COMP_FG2}, + {1, BIT(8), 0} + }, + [MT8195_MDP_COMP_FG3] = { + {MDP_COMP_TYPE_FG, 3, MDP_COMP_FG3}, + {1, BIT(9), 0} + }, + [MT8195_MDP_COMP_HDR0] = { + {MDP_COMP_TYPE_HDR, 0, MDP_COMP_HDR0}, + {0, BIT(3), 0} + }, + [MT8195_MDP_COMP_HDR1] = { + {MDP_COMP_TYPE_HDR, 1, MDP_COMP_HDR1}, + {1, BIT(10), 0} + }, + [MT8195_MDP_COMP_HDR2] = { + {MDP_COMP_TYPE_HDR, 2, MDP_COMP_HDR2}, + {1, BIT(11), 0} + }, + [MT8195_MDP_COMP_HDR3] = { + {MDP_COMP_TYPE_HDR, 3, MDP_COMP_HDR3}, + {1, BIT(12), 0} + }, + [MT8195_MDP_COMP_AAL0] = { + {MDP_COMP_TYPE_AAL, 0, MDP_COMP_AAL0}, + {0, BIT(4), 0} + }, + [MT8195_MDP_COMP_AAL1] = { + {MDP_COMP_TYPE_AAL, 1, MDP_COMP_AAL1}, + {1, BIT(13), 0} + }, + [MT8195_MDP_COMP_AAL2] = { + {MDP_COMP_TYPE_AAL, 2, MDP_COMP_AAL2}, + {1, BIT(14), 0} + }, + [MT8195_MDP_COMP_AAL3] = { + {MDP_COMP_TYPE_AAL, 3, MDP_COMP_AAL3}, + {1, BIT(15), 0} + }, + [MT8195_MDP_COMP_RSZ0] = { + {MDP_COMP_TYPE_RSZ, 0, MDP_COMP_RSZ0}, + {0, BIT(5), 0} + }, + [MT8195_MDP_COMP_RSZ1] = { + {MDP_COMP_TYPE_RSZ, 1, MDP_COMP_RSZ1}, + {1, BIT(16), 0} + }, + [MT8195_MDP_COMP_RSZ2] = { + {MDP_COMP_TYPE_RSZ, 2, MDP_COMP_RSZ2}, + {1, BIT(17) | BIT(22), 0} + }, + [MT8195_MDP_COMP_RSZ3] = { + {MDP_COMP_TYPE_RSZ, 3, MDP_COMP_RSZ3}, + {1, BIT(18) | BIT(23), 0} + }, + [MT8195_MDP_COMP_TDSHP0] = { + {MDP_COMP_TYPE_TDSHP, 0, MDP_COMP_TDSHP0}, + {0, BIT(6), 0} + }, + [MT8195_MDP_COMP_TDSHP1] = { + {MDP_COMP_TYPE_TDSHP, 1, MDP_COMP_TDSHP1}, + {1, BIT(19), 0} + }, + [MT8195_MDP_COMP_TDSHP2] = { + {MDP_COMP_TYPE_TDSHP, 2, MDP_COMP_TDSHP2}, + {1, BIT(20), 0} + }, + [MT8195_MDP_COMP_TDSHP3] = { + {MDP_COMP_TYPE_TDSHP, 3, MDP_COMP_TDSHP3}, + {1, BIT(21), 0} + }, + [MT8195_MDP_COMP_COLOR0] = { + {MDP_COMP_TYPE_COLOR, 0, MDP_COMP_COLOR0}, + {0, BIT(7), 0} + }, + [MT8195_MDP_COMP_COLOR1] = { + {MDP_COMP_TYPE_COLOR, 1, MDP_COMP_COLOR1}, + {1, BIT(24), 0} + }, + [MT8195_MDP_COMP_COLOR2] = { + {MDP_COMP_TYPE_COLOR, 2, MDP_COMP_COLOR2}, + {1, BIT(25), 0} + }, + [MT8195_MDP_COMP_COLOR3] = { + {MDP_COMP_TYPE_COLOR, 3, MDP_COMP_COLOR3}, + {1, BIT(26), 0} + }, + [MT8195_MDP_COMP_OVL0] = { + {MDP_COMP_TYPE_OVL, 0, MDP_COMP_OVL0}, + {0, BIT(8), 0} + }, + [MT8195_MDP_COMP_OVL1] = { + {MDP_COMP_TYPE_OVL, 1, MDP_COMP_OVL1}, + {1, BIT(27), 0} + }, + [MT8195_MDP_COMP_PAD0] = { + {MDP_COMP_TYPE_PAD, 0, MDP_COMP_PAD0}, + {0, BIT(9), 0} + }, + [MT8195_MDP_COMP_PAD1] = { + {MDP_COMP_TYPE_PAD, 1, MDP_COMP_PAD1}, + {1, BIT(28), 0} + }, + [MT8195_MDP_COMP_PAD2] = { + {MDP_COMP_TYPE_PAD, 2, MDP_COMP_PAD2}, + {1, BIT(29), 0} + }, + [MT8195_MDP_COMP_PAD3] = { + {MDP_COMP_TYPE_PAD, 3, MDP_COMP_PAD3}, + {1, BIT(30), 0} + }, + [MT8195_MDP_COMP_TCC0] = { + {MDP_COMP_TYPE_TCC, 0, MDP_COMP_TCC0}, + {0, BIT(10), 0} + }, + [MT8195_MDP_COMP_TCC1] = { + {MDP_COMP_TYPE_TCC, 1, MDP_COMP_TCC1}, + {1, BIT(3), 0} + }, + [MT8195_MDP_COMP_WROT0] = { + {MDP_COMP_TYPE_WROT, 0, MDP_COMP_WROT0}, + {0, BIT(11), 0} + }, + [MT8195_MDP_COMP_WROT1] = { + {MDP_COMP_TYPE_WROT, 1, MDP_COMP_WROT1}, + {1, BIT(31), 0} + }, + [MT8195_MDP_COMP_WROT2] = { + {MDP_COMP_TYPE_WROT, 2, MDP_COMP_WROT2}, + {1, 0, BIT(0)} + }, + [MT8195_MDP_COMP_WROT3] = { + {MDP_COMP_TYPE_WROT, 3, MDP_COMP_WROT3}, + {1, 0, BIT(1)} + }, + [MT8195_MDP_COMP_MERGE2] = { + {MDP_COMP_TYPE_MERGE, 2, MDP_COMP_MERGE2}, + {1, 0, 0} + }, + [MT8195_MDP_COMP_MERGE3] = { + {MDP_COMP_TYPE_MERGE, 3, MDP_COMP_MERGE2}, + {1, 0, 0} + }, + [MT8195_MDP_COMP_PQ0_SOUT] = { + {MDP_COMP_TYPE_DUMMY, 0, MDP_COMP_PQ0_SOUT}, + {0, 0, 0} + }, + [MT8195_MDP_COMP_PQ1_SOUT] = { + {MDP_COMP_TYPE_DUMMY, 1, MDP_COMP_PQ1_SOUT}, + {1, 0, 0} + }, + [MT8195_MDP_COMP_TO_WARP0MOUT] = { + {MDP_COMP_TYPE_DUMMY, 2, MDP_COMP_TO_WARP0MOUT}, + {0, 0, 0} + }, + [MT8195_MDP_COMP_TO_WARP1MOUT] = { + {MDP_COMP_TYPE_DUMMY, 3, MDP_COMP_TO_WARP1MOUT}, + {0, 0, 0} + }, + [MT8195_MDP_COMP_TO_SVPP2MOUT] = { + {MDP_COMP_TYPE_DUMMY, 4, MDP_COMP_TO_SVPP2MOUT}, + {1, 0, 0} + }, + [MT8195_MDP_COMP_TO_SVPP3MOUT] = { + {MDP_COMP_TYPE_DUMMY, 5, MDP_COMP_TO_SVPP3MOUT}, + {1, 0, 0} + }, + [MT8195_MDP_COMP_VPP0_SOUT] = { + {MDP_COMP_TYPE_PATH1, 0, MDP_COMP_VPP0_SOUT}, + {0, BIT(15), BIT(2)} + }, + [MT8195_MDP_COMP_VPP1_SOUT] = { + {MDP_COMP_TYPE_PATH2, 1, MDP_COMP_VPP1_SOUT}, + {1, BIT(16), BIT(3)} + }, + [MT8195_MDP_COMP_VDO0DL0] = { + {MDP_COMP_TYPE_DL_PATH3, 0, MDP_COMP_VDO0DL0}, + {1, 0, BIT(4)} + }, + [MT8195_MDP_COMP_VDO1DL0] = { + {MDP_COMP_TYPE_DL_PATH4, 0, MDP_COMP_VDO1DL0}, + {1, 0, BIT(6)} + }, + [MT8195_MDP_COMP_VDO0DL1] = { + {MDP_COMP_TYPE_DL_PATH5, 0, MDP_COMP_VDO0DL1}, + {1, 0, BIT(5)} + }, + [MT8195_MDP_COMP_VDO1DL1] = { + {MDP_COMP_TYPE_DL_PATH6, 0, MDP_COMP_VDO1DL1}, + {1, 0, BIT(7)} + }, +}; + static const enum mdp_comp_event mt8183_mdp_event[] = { RDMA0_SOF, RDMA0_DONE, @@ -140,6 +475,25 @@ static const enum mdp_comp_event mt8183_mdp_event[] = { WPE_B_DONE }; +static const enum mdp_comp_event mt8195_mdp_event[] = { + RDMA0_SOF, + WROT0_SOF, + RDMA0_DONE, + WROT0_DONE, + RDMA1_SOF, + RDMA2_SOF, + RDMA3_SOF, + WROT1_SOF, + WROT2_SOF, + WROT3_SOF, + RDMA1_FRAME_DONE, + RDMA2_FRAME_DONE, + RDMA3_FRAME_DONE, + WROT1_FRAME_DONE, + WROT2_FRAME_DONE, + WROT3_FRAME_DONE +}; + static const struct mdp_comp_info mt8183_comp_dt_info[] = { [MDP_COMP_TYPE_RDMA] = {2, 0, 0}, [MDP_COMP_TYPE_RSZ] = {1, 0, 0}, @@ -154,6 +508,31 @@ static const struct mdp_comp_info mt8183_comp_dt_info[] = { [MDP_COMP_TYPE_DL_PATH2] = {2, 4, 1}, }; +static const struct mdp_comp_info mt8195_comp_dt_info[] = { + [MDP_COMP_TYPE_SPLIT] = {7, 0, 0}, + [MDP_COMP_TYPE_STITCH] = {1, 0, 0}, + [MDP_COMP_TYPE_RDMA] = {3, 0, 0}, + [MDP_COMP_TYPE_FG] = {1, 0, 0}, + [MDP_COMP_TYPE_HDR] = {1, 0, 0}, + [MDP_COMP_TYPE_AAL] = {1, 0, 0}, + [MDP_COMP_TYPE_RSZ] = {2, 0, 0}, + [MDP_COMP_TYPE_TDSHP] = {1, 0, 0}, + [MDP_COMP_TYPE_COLOR] = {1, 0, 0}, + [MDP_COMP_TYPE_OVL] = {1, 0, 0}, + [MDP_COMP_TYPE_PAD] = {1, 0, 0}, + [MDP_COMP_TYPE_TCC] = {1, 0, 0}, + [MDP_COMP_TYPE_WROT] = {1, 0, 0}, + [MDP_COMP_TYPE_MERGE] = {1, 0, 0}, + [MDP_COMP_TYPE_PATH1] = {4, 9, 0}, + [MDP_COMP_TYPE_PATH2] = {2, 13, 0}, + [MDP_COMP_TYPE_DL_PATH1] = {3, 3, 0}, + [MDP_COMP_TYPE_DL_PATH2] = {3, 6, 0}, + [MDP_COMP_TYPE_DL_PATH3] = {1, 15, 0}, + [MDP_COMP_TYPE_DL_PATH4] = {1, 16, 0}, + [MDP_COMP_TYPE_DL_PATH5] = {1, 17, 0}, + [MDP_COMP_TYPE_DL_PATH6] = {1, 18, 0}, +}; + static const struct mdp_pipe_info mt8183_pipe_info[] = { {MDP_PIPE_IMGI, 0, 0}, {MDP_PIPE_RDMA0, 0, 1}, @@ -161,6 +540,19 @@ static const struct mdp_pipe_info mt8183_pipe_info[] = { {MDP_PIPE_WPEI2, 0, 3} }; +static const struct mdp_pipe_info mt8195_pipe_info[] = { + {MDP_PIPE_WPEI, 0, 0}, + {MDP_PIPE_WPEI2, 0, 1}, + {MDP_PIPE_RDMA0, 0, 2}, + {MDP_PIPE_VPP1_SOUT, 0, 3}, + {MDP_PIPE_SPLIT, 1, 2, 0x387}, + {MDP_PIPE_SPLIT2, 1, 3, 0x387}, + {MDP_PIPE_RDMA1, 1, 1}, + {MDP_PIPE_RDMA2, 1, 2}, + {MDP_PIPE_RDMA3, 1, 3}, + {MDP_PIPE_VPP0_SOUT, 1, 4}, +}; + static const struct mdp_format mt8183_formats[] = { { .pixelformat = V4L2_PIX_FMT_GREY, @@ -382,6 +774,238 @@ static const struct mdp_format mt8183_formats[] = { } }; +static const struct mdp_format mt8195_formats[] = { + { + .pixelformat = V4L2_PIX_FMT_GREY, + .mdp_color = MDP_COLOR_GREY, + .depth = { 8 }, + .row_depth = { 8 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_RGB565X, + .mdp_color = MDP_COLOR_RGB565, + .depth = { 16 }, + .row_depth = { 16 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_RGB565, + .mdp_color = MDP_COLOR_BGR565, + .depth = { 16 }, + .row_depth = { 16 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_RGB24, + .mdp_color = MDP_COLOR_RGB888, + .depth = { 24 }, + .row_depth = { 24 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_BGR24, + .mdp_color = MDP_COLOR_BGR888, + .depth = { 24 }, + .row_depth = { 24 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_ABGR32, + .mdp_color = MDP_COLOR_BGRA8888, + .depth = { 32 }, + .row_depth = { 32 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_ARGB32, + .mdp_color = MDP_COLOR_ARGB8888, + .depth = { 32 }, + .row_depth = { 32 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_UYVY, + .mdp_color = MDP_COLOR_UYVY, + .depth = { 16 }, + .row_depth = { 16 }, + .num_planes = 1, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_VYUY, + .mdp_color = MDP_COLOR_VYUY, + .depth = { 16 }, + .row_depth = { 16 }, + .num_planes = 1, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_YUYV, + .mdp_color = MDP_COLOR_YUYV, + .depth = { 16 }, + .row_depth = { 16 }, + .num_planes = 1, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_YVYU, + .mdp_color = MDP_COLOR_YVYU, + .depth = { 16 }, + .row_depth = { 16 }, + .num_planes = 1, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_YUV420, + .mdp_color = MDP_COLOR_I420, + .depth = { 12 }, + .row_depth = { 8 }, + .num_planes = 1, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_YVU420, + .mdp_color = MDP_COLOR_YV12, + .depth = { 12 }, + .row_depth = { 8 }, + .num_planes = 1, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_NV12, + .mdp_color = MDP_COLOR_NV12, + .depth = { 12 }, + .row_depth = { 8 }, + .num_planes = 1, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_NV21, + .mdp_color = MDP_COLOR_NV21, + .depth = { 12 }, + .row_depth = { 8 }, + .num_planes = 1, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_NV16, + .mdp_color = MDP_COLOR_NV16, + .depth = { 16 }, + .row_depth = { 8 }, + .num_planes = 1, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT, + }, { + .pixelformat = V4L2_PIX_FMT_NV61, + .mdp_color = MDP_COLOR_NV61, + .depth = { 16 }, + .row_depth = { 8 }, + .num_planes = 1, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT, + }, { + .pixelformat = V4L2_PIX_FMT_NV24, + .mdp_color = MDP_COLOR_NV24, + .depth = { 24 }, + .row_depth = { 8 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT, + }, { + .pixelformat = V4L2_PIX_FMT_NV42, + .mdp_color = MDP_COLOR_NV42, + .depth = { 24 }, + .row_depth = { 8 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT, + }, { + .pixelformat = V4L2_PIX_FMT_MT21C, + .mdp_color = MDP_COLOR_NV12_HYFBC, + .depth = { 8, 4 }, + .row_depth = { 8, 8 }, + .num_planes = 1, + .walign = 4, + .halign = 4, + .flags = MDP_FMT_FLAG_OUTPUT, + }, { + .pixelformat = V4L2_PIX_FMT_MM21, + .mdp_color = MDP_COLOR_420_BLKP, + .depth = { 8, 4 }, + .row_depth = { 8, 8 }, + .num_planes = 2, + .walign = 4, + .halign = 5, + .flags = MDP_FMT_FLAG_OUTPUT, + }, { + .pixelformat = V4L2_PIX_FMT_NV12M, + .mdp_color = MDP_COLOR_NV12, + .depth = { 8, 4 }, + .row_depth = { 8, 8 }, + .num_planes = 2, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_NV21M, + .mdp_color = MDP_COLOR_NV21, + .depth = { 8, 4 }, + .row_depth = { 8, 8 }, + .num_planes = 2, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_NV16M, + .mdp_color = MDP_COLOR_NV16, + .depth = { 8, 8 }, + .row_depth = { 8, 8 }, + .num_planes = 2, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT, + }, { + .pixelformat = V4L2_PIX_FMT_NV61M, + .mdp_color = MDP_COLOR_NV61, + .depth = { 8, 8 }, + .row_depth = { 8, 8 }, + .num_planes = 2, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT, + }, { + .pixelformat = V4L2_PIX_FMT_YUV420M, + .mdp_color = MDP_COLOR_I420, + .depth = { 8, 2, 2 }, + .row_depth = { 8, 4, 4 }, + .num_planes = 3, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_YVU420M, + .mdp_color = MDP_COLOR_YV12, + .depth = { 8, 2, 2 }, + .row_depth = { 8, 4, 4 }, + .num_planes = 3, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + } +}; + +static const u32 mt8195_mdp_mmsys_config_table[] = { + [CONFIG_VPP0_HW_DCM_1ST_DIS0] = 0, + [CONFIG_VPP0_DL_IRELAY_WR] = 1, + [CONFIG_VPP1_HW_DCM_1ST_DIS0] = 2, + [CONFIG_VPP1_HW_DCM_1ST_DIS1] = 3, + [CONFIG_VPP1_HW_DCM_2ND_DIS0] = 4, + [CONFIG_VPP1_HW_DCM_2ND_DIS1] = 5, + [CONFIG_SVPP2_BUF_BF_RSZ_SWITCH] = 6, + [CONFIG_SVPP3_BUF_BF_RSZ_SWITCH] = 7, +}; + static const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { .mdp_cfg = &mt8183_plat_cfg, .event = mt8183_mdp_event, @@ -397,10 +1021,29 @@ static const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { .format_len = ARRAY_SIZE(mt8183_formats), }; +static const struct mtk_mdp_driver_data mt8195_mdp_driver_data = { + .mdp_cfg = &mt8195_plat_cfg, + .event = mt8195_mdp_event, + .event_len = ARRAY_SIZE(mt8195_mdp_event), + .comp_list = &mt8195_comp_list, + .comp_data = mt8195_mdp_comp_data, + .comp_data_len = ARRAY_SIZE(mt8195_mdp_comp_data), + .comp_info = mt8195_comp_dt_info, + .comp_info_len = ARRAY_SIZE(mt8195_comp_dt_info), + .pipe_info = mt8195_pipe_info, + .pipe_info_len = ARRAY_SIZE(mt8195_pipe_info), + .format = mt8195_formats, + .format_len = ARRAY_SIZE(mt8195_formats), + .config_table = mt8195_mdp_mmsys_config_table, +}; + static const struct of_device_id mdp_of_ids[] = { { .compatible = "mediatek,mt8183-mdp3", .data = &mt8183_mdp_driver_data, }, + { .compatible = "mediatek,mt8195-mdp3", + .data = &mt8195_mdp_driver_data, + }, {}, }; MODULE_DEVICE_TABLE(of, mdp_of_ids); @@ -484,8 +1127,8 @@ static int mdp_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct mdp_dev *mdp; struct device_node *mdp_node; - struct platform_device *mm_pdev; - u32 i, event_ofst; + struct platform_device *mm_pdev, *mm_pdev2; + u32 event_ofst; int ret, i, mutex_id; mdp = devm_kzalloc(dev, sizeof(*mdp), GFP_KERNEL); @@ -503,6 +1146,12 @@ static int mdp_probe(struct platform_device *pdev) } mdp->mdp_mmsys = &mm_pdev->dev; + mm_pdev2 = __get_pdev_by_name(pdev, "mediatek,mmsys2"); + if (!mm_pdev2) + dev_err(dev, "Failed to get mdp mmsys2\n"); + else + mdp->mdp_mmsys2 = &mm_pdev2->dev; + mdp_node = of_parse_phandle(pdev->dev.of_node, "mediatek,mm-mutex", 0); if (!mdp_node) { ret = -ENODEV; @@ -534,17 +1183,43 @@ static int mdp_probe(struct platform_device *pdev) goto err_return; } + mdp_node = of_parse_phandle(pdev->dev.of_node, "mediatek,mm-mutex2", 0); + if (!mdp_node) { + dev_err(dev, "Failed to get mdp mm-mutex2\n"); + } else { + mm_pdev2 = of_find_device_by_node(mdp_node); + of_node_put(mdp_node); + if (WARN_ON(!mm_pdev2)) { + ret = -ENODEV; + goto err_return; + } + } + for (i = 0; i < mdp->mdp_data->pipe_info_len; i++) { mutex_id = mdp->mdp_data->pipe_info[i].mutex_id; - if (mdp->mdp_mutex[mutex_id]) - continue; - - mdp->mdp_mutex[mutex_id] = - mtk_mutex_mdp_get(&mm_pdev->dev, mdp->mdp_data->pipe_info[i].pipe_id); - if (!mdp->mdp_mutex[mutex_id]) { - ret = -ENODEV; - goto err_return; + if (mdp->mdp_data->pipe_info[i].mmsys_id != 0) { + if (mdp->mdp_mutex2[mutex_id]) + continue; + mdp->mdp_mutex2[mutex_id] = + mtk_mutex_mdp_get(&mm_pdev2->dev, + mdp->mdp_data->pipe_info[i].pipe_id); + + if (!mdp->mdp_mutex2[mutex_id]) { + ret = -ENODEV; + goto err_return; + } + } else { + if (mdp->mdp_mutex[mutex_id]) + continue; + mdp->mdp_mutex[mutex_id] = + mtk_mutex_mdp_get(&mm_pdev->dev, + mdp->mdp_data->pipe_info[i].pipe_id); + + if (!mdp->mdp_mutex[mutex_id]) { + ret = -ENODEV; + goto err_return; + } } } diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h index f6d70af80b3e..055812140366 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h @@ -24,13 +24,30 @@ enum mdp_buffer_usage { MDP_BUFFER_USAGE_WPE, }; +enum mtk_mdp3_version { + MTK_MDP_VERSION_6885, + MTK_MDP_VERSION_8183, + MTK_MDP_VERSION_8195, + MTK_MDP_VERSION_MAX, +}; + struct mdp_platform_config { - bool rdma_support_10bit; - bool rdma_rsz1_sram_sharing; - bool rdma_upsample_repeat_only; - bool rsz_disable_dcm_small_sample; - bool wrot_filter_constraint; - u32 gce_event_offset; + bool rdma_support_10bit; + bool rdma_rsz1_sram_sharing; + bool rdma_upsample_repeat_only; + bool rdma_support_extend_ufo; + bool rdma_support_hyfbc; + bool rdma_support_afbc; + bool rdma_esl_setting; + bool rsz_disable_dcm_small_sample; + bool rsz_etc_control; + bool tdshp_1_1; + bool wrot_filter_constraint; + bool wrot_support_afbc; + bool wrot_support_10bit; + u8 tdshp_dyn_contrast_version; + u32 gce_event_offset; + u32 version; }; struct mtk_mdp_driver_data { @@ -52,7 +69,9 @@ struct mtk_mdp_driver_data { struct mdp_dev { struct platform_device *pdev; struct device *mdp_mmsys; + struct device *mdp_mmsys2; struct mtk_mutex *mdp_mutex[MDP_PIPE_MAX]; + struct mtk_mutex *mdp_mutex2[MDP_PIPE_MAX]; struct mdp_comp *comp[MDP_MAX_COMP_COUNT]; const struct mtk_mdp_driver_data *mdp_data; s32 event[MDP_MAX_EVENT_COUNT]; diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c index 0b81f8ea16a8..1eaeaf58906a 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c @@ -111,6 +111,7 @@ static void mdp_m2m_worker(struct work_struct *work) param.type = ctx->curr_param.type; param.num_inputs = 1; param.num_outputs = 1; + param.frame_change = (ctx->frame_count == 0) ? true : false; frame = ctx_get_frame(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); src_vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx); @@ -353,6 +354,9 @@ static int mdp_m2m_s_fmt_mplane(struct file *file, void *fh, ctx->curr_param.ycbcr_enc = f->fmt.pix_mp.ycbcr_enc; ctx->curr_param.quant = f->fmt.pix_mp.quantization; ctx->curr_param.xfer_func = f->fmt.pix_mp.xfer_func; + + frame->stride.width = ((f->fmt.pix_mp.width + 63) >> 6) << 6; + frame->stride.height = ((f->fmt.pix_mp.height + 31) >> 5) << 5; } else { capture->compose.left = 0; capture->compose.top = 0; diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c index 50fd5430a565..7d26c5d8df7f 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c @@ -149,6 +149,45 @@ int mdp_enum_fmt_mplane(struct mdp_dev *mdp, struct v4l2_fmtdesc *f) return 0; } +static u32 mdp_fmt_get_hyfbc_plane_size(u32 width, u32 height, u32 color) +{ + u32 y_data_size = 0; + u32 c_data_size = 0; + u32 y_header_size = 0; + u32 c_header_size = 0; + u32 y_data_ofst = 0; + u32 y_header_ofst = 0; + u32 c_data_ofst = 0; + u32 c_header_ofst = 0; + + y_data_size = (((width + 63) >> 6) << 6) * (((height + 63) >> 6) << 6); + y_header_size = y_data_size >> 6; + if (MDP_COLOR_IS_10BIT_PACKED(color)) + y_data_size = (y_data_size * 6) >> 2; + + c_data_size = y_data_size >> 1; + c_header_size = (((y_header_size >> 1) + 63) >> 6) << 6; + + // Setup source buffer base + y_data_ofst = ((y_header_size + 4095) >> 12) << 12; // align 4k + y_header_ofst = y_data_ofst - y_header_size; + c_data_ofst = ((y_data_ofst + y_data_size + c_header_size + 4095) >> 12) << 12; // align 4k + c_header_ofst = c_data_ofst - c_header_size; + + return (c_data_ofst + c_data_size); +} + +static u32 mdp_fmt_get_afbc_plane_size(u32 width, u32 height, u32 color) +{ + u32 align_w = ((width + 31) >> 5) << 5; + u32 align_h = ((height + 31) >> 5) << 5; + + if (MDP_COLOR_IS_10BIT_PACKED(color)) + return ((align_w >> 4) * (align_h >> 4) * (16 + 512)); + else + return ((align_w >> 4) * (align_h >> 4) * (16 + 384)); +} + const struct mdp_format *mdp_try_fmt_mplane(struct mdp_dev *mdp, struct v4l2_format *f, struct mdp_frameparam *param, @@ -157,8 +196,11 @@ const struct mdp_format *mdp_try_fmt_mplane(struct mdp_dev *mdp, struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; const struct mdp_format *fmt; const struct mdp_pix_limit *pix_limit; + struct device *dev = &mdp->pdev->dev; u32 wmin, wmax, hmin, hmax, org_w, org_h; unsigned int i; + u32 ysize; + u32 exsize; if (!V4L2_TYPE_IS_MULTIPLANAR(f->type)) return NULL; @@ -167,11 +209,11 @@ const struct mdp_format *mdp_try_fmt_mplane(struct mdp_dev *mdp, if (!fmt) fmt = mdp_find_fmt_by_index(mdp->mdp_data, 0, f->type); if (!fmt) { - pr_err("[%s:%d] pixelformat %c%c%c%c invalid", __func__, ctx_id, - (pix_mp->pixelformat & 0xff), - (pix_mp->pixelformat >> 8) & 0xff, - (pix_mp->pixelformat >> 16) & 0xff, - (pix_mp->pixelformat >> 24) & 0xff); + dev_err(dev, "[%s:%d] pixelformat %c%c%c%c invalid", __func__, ctx_id, + (pix_mp->pixelformat & 0xff), + (pix_mp->pixelformat >> 8) & 0xff, + (pix_mp->pixelformat >> 16) & 0xff, + (pix_mp->pixelformat >> 24) & 0xff); return NULL; } @@ -198,13 +240,7 @@ const struct mdp_format *mdp_try_fmt_mplane(struct mdp_dev *mdp, mdp_bound_align_image(&pix_mp->width, wmin, wmax, fmt->walign, &pix_mp->height, hmin, hmax, fmt->halign, fmt->salign); - if (org_w != pix_mp->width || org_h != pix_mp->height) - pr_err("[%s:%d] size change: %ux%u to %ux%u", __func__, ctx_id, - org_w, org_h, pix_mp->width, pix_mp->height); - if (pix_mp->num_planes && pix_mp->num_planes != fmt->num_planes) - pr_err("[%s:%d] num of planes change: %u to %u", __func__, - ctx_id, pix_mp->num_planes, fmt->num_planes); pix_mp->num_planes = fmt->num_planes; for (i = 0; i < pix_mp->num_planes; ++i) { @@ -216,14 +252,31 @@ const struct mdp_format *mdp_try_fmt_mplane(struct mdp_dev *mdp, bpl = min_bpl; si = (bpl * pix_mp->height * fmt->depth[i]) / fmt->row_depth[i]; + if (MDP_COLOR_IS_HYFBC_COMPRESS(fmt->mdp_color)) { + si = mdp_fmt_get_hyfbc_plane_size(pix_mp->width, + pix_mp->height, fmt->mdp_color); + } else if (MDP_COLOR_IS_COMPRESS(fmt->mdp_color)) { + si = mdp_fmt_get_afbc_plane_size(pix_mp->width, + pix_mp->height, fmt->mdp_color); + } else if (MDP_COLOR_IS_UFP(fmt->mdp_color)) { + if (i == 0) + ysize = si; + + exsize = (((ysize + 255) >> 8) + 128); + exsize = ((exsize + 63) >> 6) << 6; + + if (i == 1) { + exsize = exsize / 2 + 128; + exsize = ((exsize + 15) >> 4) << 4; + } + si += exsize; + } + pix_mp->plane_fmt[i].bytesperline = bpl; if (pix_mp->plane_fmt[i].sizeimage < si) pix_mp->plane_fmt[i].sizeimage = si; memset(pix_mp->plane_fmt[i].reserved, 0, sizeof(pix_mp->plane_fmt[i].reserved)); - pr_info("[%s:%d] p%u, bpl:%u (%u), sizeimage:%u (%u)", __func__, - ctx_id, i, bpl, min_bpl, pix_mp->plane_fmt[i].sizeimage, - si); } return fmt; @@ -256,9 +309,6 @@ int mdp_try_crop(struct v4l2_rect *r, const struct v4l2_selection *s, u32 framew, frameh, walign, halign; int ret; - pr_info("[%s:%d] target:%d, set:(%d,%d) %ux%u", __func__, ctx_id, - s->target, s->r.left, s->r.top, s->r.width, s->r.height); - left = s->r.left; top = s->r.top; right = s->r.left + s->r.width; @@ -274,9 +324,6 @@ int mdp_try_crop(struct v4l2_rect *r, const struct v4l2_selection *s, halign = frame->mdp_fmt->halign; } - pr_info("[%s:%d] align:%u,%u, bound:%ux%u", __func__, ctx_id, - walign, halign, framew, frameh); - ret = mdp_clamp_start(&left, 0, right, walign, s->flags); if (ret) return ret; @@ -295,8 +342,6 @@ int mdp_try_crop(struct v4l2_rect *r, const struct v4l2_selection *s, r->width = right - left; r->height = bottom - top; - pr_info("[%s:%d] crop:(%d,%d) %ux%u", __func__, ctx_id, - r->left, r->top, r->width, r->height); return 0; } @@ -331,8 +376,14 @@ static u32 mdp_fmt_get_stride(const struct mdp_format *fmt, enum mdp_color c = fmt->mdp_color; u32 stride; - stride = (bytesperline * MDP_COLOR_BITS_PER_PIXEL(c)) - / fmt->row_depth[0]; + if (MDP_COLOR_IS_COMPRESS(c)) { + bytesperline = ((bytesperline + 31) >> 5) << 5; + stride = (bytesperline * MDP_COLOR_BITS_PER_PIXEL(c)) + / fmt->row_depth[0]; + } else { + stride = (bytesperline * MDP_COLOR_BITS_PER_PIXEL(c)) + / fmt->row_depth[0]; + } if (plane == 0) return stride; if (plane < MDP_COLOR_GET_PLANE_COUNT(c)) { @@ -386,6 +437,7 @@ static void mdp_prepare_buffer(struct img_image_buffer *b, { struct v4l2_pix_format_mplane *pix_mp = &frame->format.fmt.pix_mp; unsigned int i; + u32 exsize; b->format.colorformat = frame->mdp_fmt->mdp_color; b->format.ycbcr_prof = frame->ycbcr_prof; @@ -405,6 +457,28 @@ static void mdp_prepare_buffer(struct img_image_buffer *b, mdp_fmt_get_plane_size(frame->mdp_fmt, stride, pix_mp->height, i) - vb->planes[i].data_offset; + + if (MDP_COLOR_IS_HYFBC_COMPRESS(b->format.colorformat)) { + b->format.plane_fmt[i].size = + mdp_fmt_get_hyfbc_plane_size(pix_mp->width, + pix_mp->height, + b->format.colorformat); + } else if (MDP_COLOR_IS_COMPRESS(b->format.colorformat)) { + b->format.plane_fmt[i].size = + mdp_fmt_get_afbc_plane_size(pix_mp->width, + pix_mp->height, + b->format.colorformat); + } else if (MDP_COLOR_IS_UFP(b->format.colorformat)) { + exsize = (((b->format.plane_fmt[0].size + 255) >> 8) + 128); + exsize = ((exsize + 63) >> 6) << 6; + + if (i == 1) { + exsize = exsize / 2 + 128; + exsize = ((exsize + 15) >> 4) << 4; + } + b->format.plane_fmt[i].size += exsize; + } + b->iova[i] = vb2_dma_contig_plane_dma_addr(vb, i) + vb->planes[i].data_offset; } @@ -416,6 +490,27 @@ static void mdp_prepare_buffer(struct img_image_buffer *b, b->format.plane_fmt[i].size = mdp_fmt_get_plane_size(frame->mdp_fmt, stride, pix_mp->height, i); + + if (MDP_COLOR_IS_HYFBC_COMPRESS(b->format.colorformat)) { + b->format.plane_fmt[i].size = + mdp_fmt_get_hyfbc_plane_size(pix_mp->width, + pix_mp->height, + b->format.colorformat); + } else if (MDP_COLOR_IS_COMPRESS(b->format.colorformat)) { + b->format.plane_fmt[i].size = + mdp_fmt_get_afbc_plane_size(pix_mp->width, + pix_mp->height, + b->format.colorformat); + } else if (MDP_COLOR_IS_UFP(b->format.colorformat)) { + exsize = (((b->format.plane_fmt[0].size + 255) >> 8) + 128); + exsize = ((exsize + 63) >> 6) << 6; + + if (i == 1) { + exsize = exsize / 2 + 128; + exsize = ((exsize + 15) >> 4) << 4; + } + b->format.plane_fmt[i].size += exsize; + } b->iova[i] = b->iova[i - 1] + b->format.plane_fmt[i - 1].size; } b->usage = frame->usage; diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h index 4b6afaaa8645..8a3d430dca36 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h @@ -288,6 +288,8 @@ struct mdp_frame { u32 dre:1; u32 sharpness:1; u32 dither:1; + /* H and V stride, only for HYFBC format */ + struct v4l2_rect stride; }; static inline bool mdp_target_is_crop(u32 target) From patchwork Wed Oct 20 07:14:48 2021 Content-Type: text/plain; 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mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1md5p1-003Y6z-Qn; Wed, 20 Oct 2021 07:15:45 +0000 X-UUID: aa0c0d9b68504c6287bb19c12271a89c-20211020 X-UUID: aa0c0d9b68504c6287bb19c12271a89c-20211020 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 227577448; Wed, 20 Oct 2021 00:15:30 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Oct 2021 00:15:29 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Oct 2021 15:15:28 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Oct 2021 15:15:27 +0800 From: roy-cw.yeh To: Rob Herring , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Kuang Hu CC: Mauro Carvalho Chehab , Fabien Parent , "Roy-CW . Yeh" , "jason-jh . lin" , daoyuan huang , Ping-Hsun Wu , Moudy Ho , "river . cheng" , Enric Balletbo i Serra , Yongqiang Niu , , , , , Subject: [PATCH v2 9/9] media: platform: mtk-mdp3: Add dual pipe feature support Date: Wed, 20 Oct 2021 15:14:48 +0800 Message-ID: <20211020071448.14187-10-roy-cw.yeh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211020071448.14187-1-roy-cw.yeh@mediatek.com> References: <20211020071448.14187-1-roy-cw.yeh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211020_001535_932103_A4CB64C4 X-CRM114-Status: GOOD ( 23.89 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: "Roy-CW.Yeh" Add dual pipe feature which uses two svpp to execute dma Signed-off-by: Roy-CW.Yeh Acked-by: AngeloGioacchino Del Regno --- .../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 191 ++++++++++++++---- .../media/platform/mtk-mdp3/mtk-mdp3-cmdq.h | 1 + .../media/platform/mtk-mdp3/mtk-mdp3-core.c | 11 +- .../media/platform/mtk-mdp3/mtk-mdp3-core.h | 3 + .../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 4 + .../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 18 ++ .../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 4 + 7 files changed, 189 insertions(+), 43 deletions(-) diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c index afa114fe9817..37bd7c4b9ded 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c @@ -10,7 +10,10 @@ #include "mtk-mdp3-core.h" #include "mtk-mdp3-m2m.h" -#define MDP_PATH_MAX_COMPS IMG_MAX_COMPONENTS +#define PATH_0 0 +#define PATH_1 1 +#define MDP_DUAL_PIPE 2 +#define MDP_PATH_MAX_COMPS IMG_MAX_COMPONENTS struct mdp_path { struct mdp_dev *mdp_dev; @@ -30,6 +33,9 @@ struct mdp_path { #define is_dummy_engine(mdp, id) \ ((mdp)->mdp_data->comp_data[id].match.type == MDP_COMP_TYPE_DUMMY) +#define is_dual_pipe(scenario) \ + ((scenario) == MDP_STREAM_TYPE_DUAL_BITBLT) + struct mdp_path_subfrm { s32 mutex_id; u32 mutex_mod; @@ -733,26 +739,31 @@ static void mdp_auto_release_work(struct work_struct *work) struct mdp_cmdq_cb_param *cb_param; struct mdp_dev *mdp; int i; + bool finalize; cb_param = container_of(work, struct mdp_cmdq_cb_param, auto_release_work); mdp = cb_param->mdp; + finalize = cb_param->finalize; - i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0); - mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]); - - i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1); - if (i >= 0) - mtk_mutex_unprepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]); + if (finalize) { + i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0); + mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]); + i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1); + if (i >= 0) + mtk_mutex_unprepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]); + } mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps, cb_param->num_comps); kfree(cb_param->comps); kfree(cb_param); - atomic_dec(&mdp->job_count); - wake_up(&mdp->callback_wq); + if (finalize) { + atomic_dec(&mdp->job_count); + wake_up(&mdp->callback_wq); + } } static void mdp_handle_cmdq_callback(struct cmdq_cb_data data) @@ -770,7 +781,9 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data) mdp = cb_param->mdp; dev = &mdp->pdev->dev; - if (cb_param->mdp_ctx) + cb_param->finalize = (atomic_dec_and_test(&mdp->cmdq_count)); + + if (cb_param->finalize && cb_param->mdp_ctx) mdp_m2m_job_finish(cb_param->mdp_ctx); if (cb_param->user_cmdq_cb) { @@ -805,12 +818,15 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data) int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) { - struct mmsys_cmdq_cmd cmd; - struct mdp_path path; + struct mmsys_cmdq_cmd cmd, cmd_d; + static struct mdp_path path[MDP_DUAL_PIPE]; struct mdp_cmdq_cb_param *cb_param = NULL; + struct mdp_cmdq_cb_param *cb_param_d = NULL; struct mdp_comp *comps = NULL; + struct mdp_comp *comps_d = NULL; struct device *dev = &mdp->pdev->dev; - int i, ret; + enum mdp_stream_type scenario = param->param->type; + int i, ret, path_id; if (atomic_read(&mdp->suspended)) return -ECANCELED; @@ -825,24 +841,39 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) } cmd.event = &mdp->event[0]; - path.mdp_dev = mdp; - path.config = param->config; - path.param = param->param; - for (i = 0; i < param->param->num_outputs; i++) { - path.bounds[i].left = 0; - path.bounds[i].top = 0; - path.bounds[i].width = - param->param->outputs[i].buffer.format.width; - path.bounds[i].height = - param->param->outputs[i].buffer.format.height; - path.composes[i] = param->composes[i] ? - param->composes[i] : &path.bounds[i]; - } - - ret = mdp_path_ctx_init(mdp, &path); - if (ret) { - dev_info(dev, "%s mdp_path_ctx_init error\n", __func__); - goto err_destroy_pkt; + if (is_dual_pipe(scenario)) { + cmd_d.pkt = cmdq_pkt_create(mdp->cmdq_d_clt, SZ_16K); + if (IS_ERR(cmd_d.pkt)) { + atomic_dec(&mdp->job_count); + wake_up(&mdp->callback_wq); + return PTR_ERR(cmd_d.pkt); + } + cmd_d.event = &mdp->event[0]; + } + + for (path_id = 0; path_id < MDP_DUAL_PIPE; path_id++) { + if (path_id != 0 && (!is_dual_pipe(scenario))) + break; + + path[path_id].mdp_dev = mdp; + path[path_id].config = ¶m->config[path_id]; + path[path_id].param = param->param; + for (i = 0; i < param->param->num_outputs; i++) { + path[path_id].bounds[i].left = 0; + path[path_id].bounds[i].top = 0; + path[path_id].bounds[i].width = + param->param->outputs[i].buffer.format.width; + path[path_id].bounds[i].height = + param->param->outputs[i].buffer.format.height; + path[path_id].composes[i] = param->composes[i] ? + param->composes[i] : &path[path_id].bounds[i]; + } + + ret = mdp_path_ctx_init(mdp, &path[path_id]); + if (ret) { + dev_info(dev, "%s mdp_path_ctx_init error at path %d\n", __func__, path_id); + goto err_destroy_pkt; + } } i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0); @@ -852,44 +883,61 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) if (i >= 0) mtk_mutex_prepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]); - for (i = 0; i < param->config->num_components; i++) { - if (is_dummy_engine(mdp, path.config->components[i].type)) + for (i = 0; i < param->config[PATH_0].num_components; i++) { + if (is_dummy_engine(mdp, path[PATH_0].config->components[i].type)) continue; - mdp_comp_clock_on(&mdp->pdev->dev, path.comps[i].comp); + mdp_comp_clock_on(&mdp->pdev->dev, path[PATH_0].comps[i].comp); + } + + if (is_dual_pipe(scenario)) { + for (i = 0; i < param->config[PATH_1].num_components; i++) { + if (is_dummy_engine(mdp, path[PATH_1].config->components[i].type)) + continue; + + mdp_comp_clock_on(&mdp->pdev->dev, path[PATH_1].comps[i].comp); + } } if (mdp->mdp_data->mdp_cfg->version == MTK_MDP_VERSION_8195) { /* HYFBC Patch */ - ret = mdp_hyfbc_config(mdp, &cmd, &path, param); + ret = mdp_hyfbc_config(mdp, &cmd, &path[PATH_0], param); if (ret) dev_info(dev, "%s:mdp_hyfbc_config fail!\n", __func__); } - ret = mdp_path_config(mdp, &cmd, &path); + ret = mdp_path_config(mdp, &cmd, &path[PATH_0]); if (ret) { - dev_info(dev, "%s mdp_path_config error\n", __func__); + dev_info(dev, "%s path 0 mdp_path_config error\n", __func__); goto err_destroy_pkt; } + if (is_dual_pipe(scenario)) { + ret = mdp_path_config(mdp, &cmd_d, &path[PATH_1]); + if (ret) { + pr_info("%s path 1 mdp_path_config error\n", __func__); + goto err_destroy_pkt; + } + } + cb_param = kzalloc(sizeof(*cb_param), GFP_KERNEL); if (!cb_param) { ret = -ENOMEM; goto err_destroy_pkt; } - comps = kcalloc(param->config->num_components, sizeof(*comps), + comps = kcalloc(param->config[PATH_0].num_components, sizeof(*comps), GFP_KERNEL); if (!comps) { ret = -ENOMEM; goto err_destroy_pkt; } - for (i = 0; i < param->config->num_components; i++) { - if (is_dummy_engine(mdp, path.config->components[i].type)) + for (i = 0; i < param->config[PATH_0].num_components; i++) { + if (is_dummy_engine(mdp, path[PATH_0].config->components[i].type)) continue; - memcpy(&comps[i], path.comps[i].comp, + memcpy(&comps[i], path[PATH_0].comps[i].comp, sizeof(struct mdp_comp)); } cb_param->mdp = mdp; @@ -897,10 +945,49 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) cb_param->user_cb_data = param->cb_data; cb_param->pkt = cmd.pkt; cb_param->comps = comps; - cb_param->num_comps = param->config->num_components; + cb_param->num_comps = param->config[PATH_0].num_components; cb_param->mdp_ctx = param->mdp_ctx; + if (is_dual_pipe(scenario)) { + cb_param_d = kzalloc(sizeof(*cb_param_d), GFP_KERNEL); + if (!cb_param_d) { + ret = -ENOMEM; + goto err_destroy_pkt; + } + comps_d = kcalloc(param->config[PATH_1].num_components, sizeof(*comps_d), + GFP_KERNEL); + if (!comps_d) { + ret = -ENOMEM; + goto err_destroy_pkt; + } + + for (i = 0; i < param->config[PATH_1].num_components; i++) { + if (is_dummy_engine(mdp, path[PATH_1].config->components[i].type)) + continue; + + memcpy(&comps_d[i], path[PATH_1].comps[i].comp, + sizeof(struct mdp_comp)); + } + cb_param_d->mdp = mdp; + cb_param_d->user_cmdq_cb = param->cmdq_cb; + cb_param_d->user_cb_data = param->cb_data; + cb_param_d->pkt = cmd_d.pkt; + cb_param_d->comps = comps_d; + cb_param_d->num_comps = param->config[PATH_1].num_components; + cb_param_d->mdp_ctx = param->mdp_ctx; + } + + if (atomic_read(&mdp->cmdq_count)) + pr_info("%s: Warning: cmdq_count:%d !\n", __func__, atomic_read(&mdp->cmdq_count)); + cmdq_pkt_finalize(cmd.pkt); + atomic_inc(&mdp->cmdq_count); + + if (is_dual_pipe(scenario)) { + cmdq_pkt_finalize(cmd_d.pkt); + atomic_inc(&mdp->cmdq_count); + } + ret = cmdq_pkt_flush_async(cmd.pkt, mdp_handle_cmdq_callback, (void *)cb_param); @@ -908,6 +995,16 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) dev_info(dev, "cmdq_pkt_flush_async fail!\n"); goto err_clock_off; } + + if (is_dual_pipe(scenario)) { + ret = cmdq_pkt_flush_async(cmd_d.pkt, + mdp_handle_cmdq_callback, + (void *)cb_param_d); + if (ret) { + dev_err(dev, "cmdq_dual_pkt_flush_async fail!\n"); + goto err_clock_off; + } + } return 0; err_clock_off: @@ -920,12 +1017,22 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps, cb_param->num_comps); + if (cb_param_d) + mdp_comp_clocks_off(&mdp->pdev->dev, cb_param_d->comps, + cb_param_d->num_comps); err_destroy_pkt: cmdq_pkt_destroy(cmd.pkt); + if (is_dual_pipe(scenario)) { + cmdq_pkt_destroy(cmd_d.pkt); + atomic_inc(&mdp->cmdq_count); + } atomic_dec(&mdp->job_count); + atomic_dec(&mdp->cmdq_count); wake_up(&mdp->callback_wq); kfree(comps); + kfree(comps_d); kfree(cb_param); + kfree(cb_param_d); return ret; } diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h index 16933507333b..0a0e88cef6b5 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h @@ -37,6 +37,7 @@ struct mdp_cmdq_cb_param { struct mdp_comp *comps; u8 num_comps; void *mdp_ctx; + bool finalize; }; struct mdp_dev; diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c index 524c852e584b..1c8baa33ecc6 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c @@ -40,6 +40,7 @@ static const struct mdp_platform_config mt8195_plat_cfg = { .wrot_filter_constraint = false, .tdshp_1_1 = true, .tdshp_dyn_contrast_version = 2, + .support_dual_pipe = true, .gce_event_offset = 0, .version = MTK_MDP_VERSION_8195, }; @@ -1263,6 +1264,12 @@ static int mdp_probe(struct platform_device *pdev) goto err_put_scp; } + mdp->cmdq_d_clt = cmdq_mbox_create(dev, 1); + if (IS_ERR(mdp->cmdq_d_clt)) { + ret = PTR_ERR(mdp->cmdq_d_clt); + goto err_mbox_destroy; + } + init_waitqueue_head(&mdp->callback_wq); ida_init(&mdp->mdp_ida); platform_set_drvdata(pdev, mdp); @@ -1273,7 +1280,7 @@ static int mdp_probe(struct platform_device *pdev) if (ret) { dev_err(dev, "Failed to register v4l2 device\n"); ret = -EINVAL; - goto err_mbox_destroy; + goto err_dual_mbox_destroy; } ret = mdp_m2m_device_register(mdp); @@ -1287,6 +1294,8 @@ static int mdp_probe(struct platform_device *pdev) err_unregister_device: v4l2_device_unregister(&mdp->v4l2_dev); +err_dual_mbox_destroy: + cmdq_mbox_destroy(mdp->cmdq_d_clt); err_mbox_destroy: cmdq_mbox_destroy(mdp->cmdq_clt); err_put_scp: diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h index 055812140366..5091fdacc5c6 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h @@ -45,6 +45,7 @@ struct mdp_platform_config { bool wrot_filter_constraint; bool wrot_support_afbc; bool wrot_support_10bit; + bool support_dual_pipe; u8 tdshp_dyn_contrast_version; u32 gce_event_offset; u32 version; @@ -87,6 +88,7 @@ struct mdp_dev { u32 id_count; struct ida mdp_ida; struct cmdq_client *cmdq_clt; + struct cmdq_client *cmdq_d_clt; wait_queue_head_t callback_wq; struct v4l2_device v4l2_dev; @@ -96,6 +98,7 @@ struct mdp_dev { struct mutex m2m_lock; atomic_t suspended; atomic_t job_count; + atomic_t cmdq_count; }; struct mdp_pipe_info { diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c index 1eaeaf58906a..55384bb812cf 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c @@ -116,6 +116,10 @@ static void mdp_m2m_worker(struct work_struct *work) frame = ctx_get_frame(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); src_vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx); mdp_set_src_config(¶m.inputs[0], frame, &src_vb->vb2_buf); + mdp_set_scenario(ctx->mdp_dev, ¶m, frame); + if (param.frame_change) + dev_info(&ctx->mdp_dev->pdev->dev, + "MDP Scenario: %d\n", param.type); frame = ctx_get_frame(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); dst_vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx); diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c index 7d26c5d8df7f..92f337077411 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c @@ -10,6 +10,8 @@ #include "mtk-mdp3-core.h" #include "mtk-mdp3-regs.h" +#define QHD (2560 * 1440) + static const struct mdp_limit mdp_def_limit = { .out_limit = { .wmin = 16, @@ -432,6 +434,22 @@ static u32 mdp_fmt_get_plane_size(const struct mdp_format *fmt, return 0; } +void mdp_set_scenario(struct mdp_dev *mdp, + struct img_ipi_frameparam *param, + struct mdp_frame *frame) +{ + u32 width = frame->format.fmt.pix_mp.width; + u32 height = frame->format.fmt.pix_mp.height; + + if (!mdp) + return; + + if (mdp->mdp_data->mdp_cfg->support_dual_pipe) { + if ((width * height) >= QHD) + param->type = MDP_STREAM_TYPE_DUAL_BITBLT; + } +} + static void mdp_prepare_buffer(struct img_image_buffer *b, struct mdp_frame *frame, struct vb2_buffer *vb) { diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h index 8a3d430dca36..7979ad60ab87 100644 --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h @@ -10,6 +10,7 @@ #include #include #include "mtk-img-ipi.h" +#include "mtk-mdp3-cmdq.h" /* * MDP native color code @@ -340,6 +341,9 @@ int mdp_try_crop(struct v4l2_rect *r, const struct v4l2_selection *s, int mdp_check_scaling_ratio(const struct v4l2_rect *crop, const struct v4l2_rect *compose, s32 rotation, const struct mdp_limit *limit); +void mdp_set_scenario(struct mdp_dev *mdp, + struct img_ipi_frameparam *param, + struct mdp_frame *frame); void mdp_set_src_config(struct img_input *in, struct mdp_frame *frame, struct vb2_buffer *vb); void mdp_set_dst_config(struct img_output *out,