From patchwork Wed Oct 20 18:48:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12573057 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3005BC433EF for ; Wed, 20 Oct 2021 18:50:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 008DB61212 for ; Wed, 20 Oct 2021 18:50:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230076AbhJTSwr (ORCPT ); Wed, 20 Oct 2021 14:52:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231331AbhJTSwp (ORCPT ); Wed, 20 Oct 2021 14:52:45 -0400 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A38E5C06161C; Wed, 20 Oct 2021 11:50:30 -0700 (PDT) Received: by mail-pj1-x102f.google.com with SMTP id u6-20020a17090a3fc600b001a00250584aso1202788pjm.4; Wed, 20 Oct 2021 11:50:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=znmARRiQVkqC85lKLifIrCv0U2JcIdQKNsLQ6jRH+xY=; b=AFQnxzJBoUJOr2jrRbs0eEL5JnHsokQL0/MSRypi9D3z2Cnb8e6xsjRopqx6kJsXzb 3/vfQ6JU1JWPLsYjesBk7L/viivaf+fmLAuv0k57UJd9S1S1isaQ5VdSnW7UInl4ZY8P rBgeG6ObrlPtOxQDgf/DY8ycdY2jKZIdzE6uPE71NVJg/xSZZ3g6XbATqHaYp18feDtZ oDZFWqiIkqhN1HgD+r20lHH0I87xBle9pCQD6g8yQwQN159mi92ouY7m9/RzbkaR1xmB NCCFB38R+ZCnmoFDrkL01g4gf5dou78VIXg61tr86Xq6zpZRXiXCduGeA9dsoxplsBCC spvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=znmARRiQVkqC85lKLifIrCv0U2JcIdQKNsLQ6jRH+xY=; b=eycjACs3dRxZDbezOA8t4YQjo6N0V2H5nVcR+x1ZwI1h7GvyPd1oqnmBYwc81XeNF2 QwauCBVU5FH3Lvw0lmvEsRpRE3VrtQLjyPcytjGVhtrIzSYnyHZvc1UbHKtEP+Syxdbj B4WWtd7e1L3cMxAaeYEXqZxtHCwGV0I5k8/sXqV17gP1x0bEBlQzv8ht+ixm9xzqeSx0 Efih1bjFCQ/2EogNOpKaUVB/QS60kBs5oe8YBrLW57l7sxeeS4g4xX7vsqA2CCY9jKhU jGUdDohW7G3VldBY4Gix5pidKjFw5S4+/bpX0ByvfoNF24qwdZQxNOcQLCtSBd4sCM9p rgWA== X-Gm-Message-State: AOAM532NCY/SZKJPJ2XLf32jvzPsK9LcAwVcBOkJQYGSjhG8IVBTMU5j pQvB0fK6xw4p66i+m6L8IOKoU3XQhKs= X-Google-Smtp-Source: ABdhPJz2zVU2zmA1USXKi8K+wWLy6wjyOoeBBh9yjG0hpBbXJb53QVX7O+TpCZLJPzXBxUCjv3wZSg== X-Received: by 2002:a17:90b:3ecb:: with SMTP id rm11mr886865pjb.110.1634755829860; Wed, 20 Oct 2021 11:50:29 -0700 (PDT) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id o127sm3267863pfb.216.2021.10.20.11.50.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Oct 2021 11:50:29 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Thomas Gleixner , Thomas Bogendoerfer , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...), Russell King , Catalin Marinas , Will Deacon , Marc Zyngier , Rob Herring , Frank Rowand , linux-arm-kernel@lists.infradead.org (moderated list:ARM SUB-ARCHITECTURES), linux-mips@vger.kernel.org (open list:MIPS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE) Subject: [PATCH v6 01/13] MIPS: BMIPS: Remove use of irq_cpu_offline Date: Wed, 20 Oct 2021 11:48:47 -0700 Message-Id: <20211020184859.2705451-2-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020184859.2705451-1-f.fainelli@gmail.com> References: <20211020184859.2705451-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org irq_cpu_offline() is only used by MIPS and we should instead use irq_migrate_all_off_this_cpu(). This will be helpful in order to remove drivers/irqchip/irq-bcm7038-l1.c irq_cpu_offline callback which would have got in the way of making this driver modular. Suggested-by: Thomas Gleixner Acked-by: Thomas Bogendoerfer Signed-off-by: Florian Fainelli --- arch/mips/Kconfig | 1 + arch/mips/kernel/smp-bmips.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 771ca53af06d..2c03b27cec02 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1782,6 +1782,7 @@ config CPU_BMIPS select CPU_HAS_PREFETCH select CPU_SUPPORTS_CPUFREQ select MIPS_EXTERNAL_TIMER + select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU help Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors. diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index b6ef5f7312cf..f5d7bfa3472a 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -373,7 +374,7 @@ static int bmips_cpu_disable(void) set_cpu_online(cpu, false); calculate_cpu_foreign_map(); - irq_cpu_offline(); + irq_migrate_all_off_this_cpu(); clear_c0_status(IE_IRQ5); local_flush_tlb_all(); From patchwork Wed Oct 20 18:48:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12573059 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CC2EC4332F for ; Wed, 20 Oct 2021 18:50:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 42C37610D0 for ; Wed, 20 Oct 2021 18:50:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231352AbhJTSws (ORCPT ); Wed, 20 Oct 2021 14:52:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231344AbhJTSwr (ORCPT ); Wed, 20 Oct 2021 14:52:47 -0400 Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C3ABC061753; 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Wed, 20 Oct 2021 11:50:31 -0700 (PDT) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id o127sm3267863pfb.216.2021.10.20.11.50.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Oct 2021 11:50:30 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...), Russell King , Catalin Marinas , Will Deacon , Thomas Bogendoerfer , Thomas Gleixner , Marc Zyngier , Rob Herring , Frank Rowand , linux-arm-kernel@lists.infradead.org (moderated list:ARM SUB-ARCHITECTURES), linux-mips@vger.kernel.org (open list:MIPS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE) Subject: [PATCH v6 02/13] irqchip/irq-bcm7038-l1: Remove .irq_cpu_offline() Date: Wed, 20 Oct 2021 11:48:48 -0700 Message-Id: <20211020184859.2705451-3-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020184859.2705451-1-f.fainelli@gmail.com> References: <20211020184859.2705451-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org With arch/mips/kernel/smp-bmips.c having been migrated away from irq_cpu_offline() and use irq_migrate_all_off_this_cpu() instead, we no longer need to implement an .irq_cpu_offline() callback. This is a necessary change to facilitate the building of this driver as a module. Signed-off-by: Florian Fainelli --- drivers/irqchip/irq-bcm7038-l1.c | 30 ------------------------------ 1 file changed, 30 deletions(-) diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c index a035c385ca7a..750156217c82 100644 --- a/drivers/irqchip/irq-bcm7038-l1.c +++ b/drivers/irqchip/irq-bcm7038-l1.c @@ -221,33 +221,6 @@ static int bcm7038_l1_set_affinity(struct irq_data *d, return 0; } -#ifdef CONFIG_SMP -static void bcm7038_l1_cpu_offline(struct irq_data *d) -{ - struct cpumask *mask = irq_data_get_affinity_mask(d); - int cpu = smp_processor_id(); - cpumask_t new_affinity; - - /* This CPU was not on the affinity mask */ - if (!cpumask_test_cpu(cpu, mask)) - return; - - if (cpumask_weight(mask) > 1) { - /* - * Multiple CPU affinity, remove this CPU from the affinity - * mask - */ - cpumask_copy(&new_affinity, mask); - cpumask_clear_cpu(cpu, &new_affinity); - } else { - /* Only CPU, put on the lowest online CPU */ - cpumask_clear(&new_affinity); - cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity); - } - irq_set_affinity_locked(d, &new_affinity, false); -} -#endif - static int __init bcm7038_l1_init_one(struct device_node *dn, unsigned int idx, struct bcm7038_l1_chip *intc) @@ -396,9 +369,6 @@ static struct irq_chip bcm7038_l1_irq_chip = { .irq_mask = bcm7038_l1_mask, .irq_unmask = bcm7038_l1_unmask, .irq_set_affinity = bcm7038_l1_set_affinity, -#ifdef CONFIG_SMP - .irq_cpu_offline = bcm7038_l1_cpu_offline, -#endif #ifdef CONFIG_PM_SLEEP .irq_set_wake = bcm7038_l1_set_wake, #endif From patchwork Wed Oct 20 18:48:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12573061 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60055C4332F for ; Wed, 20 Oct 2021 18:50:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 463BC6138B for ; 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Wed, 20 Oct 2021 11:50:32 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...), Russell King , Catalin Marinas , Will Deacon , Thomas Bogendoerfer , Thomas Gleixner , Marc Zyngier , Rob Herring , Frank Rowand , linux-arm-kernel@lists.infradead.org (moderated list:ARM SUB-ARCHITECTURES), linux-mips@vger.kernel.org (open list:MIPS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE) Subject: [PATCH v6 03/13] irqchip/irq-bcm7038-l1: Use irq_get_irq_data() Date: Wed, 20 Oct 2021 11:48:49 -0700 Message-Id: <20211020184859.2705451-4-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020184859.2705451-1-f.fainelli@gmail.com> References: <20211020184859.2705451-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Using irq_desc_get_irq_data(irq_to_desc()) to retrieve the irq_data structure from a virtual interrupt number is going to be problematic to make irq-bcm7038-l1 a module because irq_to_desc() is not exported, and there is no intent to export it to modules, see 64a1b95bb9fe ("genirq: Restrict export of irq_to_desc()"). Signed-off-by: Florian Fainelli --- drivers/irqchip/irq-bcm7038-l1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c index 750156217c82..14caf32dc23e 100644 --- a/drivers/irqchip/irq-bcm7038-l1.c +++ b/drivers/irqchip/irq-bcm7038-l1.c @@ -386,7 +386,7 @@ static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq, irq_set_chip_and_handler(virq, &bcm7038_l1_irq_chip, handle_level_irq); irq_set_chip_data(virq, d->host_data); - irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq))); + irqd_set_single_target(irq_get_irq_data(virq)); return 0; } From patchwork Wed Oct 20 18:48:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12573063 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB9C1C433F5 for ; Wed, 20 Oct 2021 18:50:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 965B161038 for ; Wed, 20 Oct 2021 18:50:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231450AbhJTSwv (ORCPT ); Wed, 20 Oct 2021 14:52:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231397AbhJTSwt (ORCPT ); Wed, 20 Oct 2021 14:52:49 -0400 Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2238FC06161C; Wed, 20 Oct 2021 11:50:35 -0700 (PDT) Received: by mail-pg1-x536.google.com with SMTP id c4so16278356pgv.11; Wed, 20 Oct 2021 11:50:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G1RiT4GRKPcXSkOjyrks/jOWZL3DTQpMJtRhCsgVjY8=; b=hEsPXiTNsHEKrv7LrTxImma40UBastHpzRHkCpg1UyvZaIZUem+ieQzNA9xZ4dh7Yl bTBNV8ixGN9/BjYTtrdhRxfCu/4LZAczT1Kixt1lWMUtF//kUIZ+lYJIu9x73XGL6Ma+ wN92PvdzevimIS28e6BanTaolgM4RuwDPLbENV/WcYm8zhdj0OD95KUSlKarCrVxVXPE 9FrGXJTua/ydZn9xrhej+AsMzNnn1B6+bAnHKUKVpdxYIyT778CWElDRkj+8S+6gT6ef cvomTzR5OjtuqDbTHYem5Mm0IB7+TNjBwu5LW2QZ4R6DyrsERCSiHhb08EdwueYOcFeY U49w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G1RiT4GRKPcXSkOjyrks/jOWZL3DTQpMJtRhCsgVjY8=; b=mCLqPkaP0U2hYIKlqlcKXX4/2sDTXI8xOr3VEUfgFn6RK53f0m/12MrzwImpG/InT1 sPsxA6lKwhlVWOWrWoZv4I/RdB+2rtUArpR6Wld6ezNEMTMmwxmQhscaDTv6rByTwgIh eoRPk02squgCE4iMmmuhQuC4ItmCwyKr3SLa1gogMecxC9ft611YR4m5ShYdpaBZ60VI oytgfCyBovOnBJbbf2daLs7lBPL9+DlQeFUkWFsSTrfE3S0lfHEhVxxB8UoHnQFVlU4z qn5jF/kNvEM2oXbOnT+Oc59PCmJzcovbA9WESEcfc4T/Nhuv0O5qiYvsrdVcsZbM4NOV vozQ== X-Gm-Message-State: AOAM532BfjghHXeG7VbHsmG+EO5nwlEAPsVMIAHe/HM0n+vFUF+GD27B PGPPY/4styh+TymjRc16o2oF0rsr6xo= X-Google-Smtp-Source: ABdhPJwbzWHKin126tbJWWzQImBYaNKIeFtG9nT98+ylY4/8HfKntmcN0jXAbn859i8BkSEAZ414gA== X-Received: by 2002:a63:b909:: with SMTP id z9mr809070pge.140.1634755834115; Wed, 20 Oct 2021 11:50:34 -0700 (PDT) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id o127sm3267863pfb.216.2021.10.20.11.50.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Oct 2021 11:50:33 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...), Russell King , Catalin Marinas , Will Deacon , Thomas Bogendoerfer , Thomas Gleixner , Marc Zyngier , Rob Herring , Frank Rowand , linux-arm-kernel@lists.infradead.org (moderated list:ARM SUB-ARCHITECTURES), linux-mips@vger.kernel.org (open list:MIPS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE) Subject: [PATCH v6 04/13] irqchip/irq-bcm7038-l1: Gate use of CPU logical map to MIPS Date: Wed, 20 Oct 2021 11:48:50 -0700 Message-Id: <20211020184859.2705451-5-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020184859.2705451-1-f.fainelli@gmail.com> References: <20211020184859.2705451-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The use of the cpu_logical_map[] array is only relevant for MIPS based platform where this driver is used as a first level interrupt controller and contains multiple register groups to map with an associated CPU. On ARM/ARM64 based systems this interrupt controller is present and used as a second level interrupt controller hanging off the ARM GIC. That copy of the interrupt controller contains a single group, resulting in the intc->cpus[] array to be of size 1. Things happened to work in that case because we install that interrupt controller as a chained handler which does not allow it to be affine to any CPU but the boot CPU which happens to be 0, therefore we never de-reference past intc->cpus[] but with the current code in place, we do leave a chance of de-referencing the array past its bounds. Signed-off-by: Florian Fainelli --- drivers/irqchip/irq-bcm7038-l1.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c index 14caf32dc23e..3c4e348c661e 100644 --- a/drivers/irqchip/irq-bcm7038-l1.c +++ b/drivers/irqchip/irq-bcm7038-l1.c @@ -28,9 +28,6 @@ #include #include #include -#ifdef CONFIG_ARM -#include -#endif #define IRQS_PER_WORD 32 #define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 4) @@ -127,7 +124,7 @@ static void bcm7038_l1_irq_handle(struct irq_desc *desc) struct irq_chip *chip = irq_desc_get_chip(desc); unsigned int idx; -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && defined(CONFIG_MIPS) cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; #else cpu = intc->cpus[0]; @@ -301,7 +298,7 @@ static int bcm7038_l1_suspend(void) u32 val; /* Wakeup interrupt should only come from the boot cpu */ -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && defined(CONFIG_MIPS) boot_cpu = cpu_logical_map(0); #else boot_cpu = 0; @@ -325,7 +322,7 @@ static void bcm7038_l1_resume(void) struct bcm7038_l1_chip *intc; int boot_cpu, word; -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && defined(CONFIG_MIPS) boot_cpu = cpu_logical_map(0); #else boot_cpu = 0; From patchwork Wed Oct 20 18:48:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12573065 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECA85C4332F for ; Wed, 20 Oct 2021 18:50:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DA6086121E for ; Wed, 20 Oct 2021 18:50:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231405AbhJTSww (ORCPT ); Wed, 20 Oct 2021 14:52:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231431AbhJTSwv (ORCPT ); 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Wed, 20 Oct 2021 11:50:35 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...), Russell King , Catalin Marinas , Will Deacon , Thomas Bogendoerfer , Thomas Gleixner , Marc Zyngier , Rob Herring , Frank Rowand , linux-arm-kernel@lists.infradead.org (moderated list:ARM SUB-ARCHITECTURES), linux-mips@vger.kernel.org (open list:MIPS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE) Subject: [PATCH v6 05/13] irqchip/irq-bcm7038-l1: Restrict affinity setting to MIPS Date: Wed, 20 Oct 2021 11:48:51 -0700 Message-Id: <20211020184859.2705451-6-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020184859.2705451-1-f.fainelli@gmail.com> References: <20211020184859.2705451-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Only MIPS based platforms using this interrupt controller as first level interrupt controller can actually change the affinity of interrupts by re-programming the affinity mask of the interrupt controller and use another word group to have another CPU process the interrupt. When this interrupt is used as a second level interrupt controller on ARM/ARM64 there is no way to change the interrupt affinity. This fixes a NULL pointer de-reference while trying to change the affinity since there is only a single word group in that case, and we would have been overruning the intc->cpus[] array. Signed-off-by: Florian Fainelli --- drivers/irqchip/irq-bcm7038-l1.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c index 3c4e348c661e..357570dd8780 100644 --- a/drivers/irqchip/irq-bcm7038-l1.c +++ b/drivers/irqchip/irq-bcm7038-l1.c @@ -191,6 +191,7 @@ static void bcm7038_l1_mask(struct irq_data *d) raw_spin_unlock_irqrestore(&intc->lock, flags); } +#if defined(CONFIG_MIPS) && defined(CONFIG_SMP) static int bcm7038_l1_set_affinity(struct irq_data *d, const struct cpumask *dest, bool force) @@ -217,6 +218,7 @@ static int bcm7038_l1_set_affinity(struct irq_data *d, return 0; } +#endif static int __init bcm7038_l1_init_one(struct device_node *dn, unsigned int idx, @@ -365,7 +367,9 @@ static struct irq_chip bcm7038_l1_irq_chip = { .name = "bcm7038-l1", .irq_mask = bcm7038_l1_mask, .irq_unmask = bcm7038_l1_unmask, +#if defined(CONFIG_SMP) && defined(CONFIG_MIPS) .irq_set_affinity = bcm7038_l1_set_affinity, +#endif #ifdef CONFIG_PM_SLEEP .irq_set_wake = bcm7038_l1_set_wake, #endif From patchwork Wed Oct 20 18:48:52 2021 Content-Type: text/plain; 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Wed, 20 Oct 2021 11:50:36 -0700 (PDT) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id o127sm3267863pfb.216.2021.10.20.11.50.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Oct 2021 11:50:36 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...), Russell King , Catalin Marinas , Will Deacon , Thomas Bogendoerfer , Thomas Gleixner , Marc Zyngier , Rob Herring , Frank Rowand , linux-arm-kernel@lists.infradead.org (moderated list:ARM SUB-ARCHITECTURES), linux-mips@vger.kernel.org (open list:MIPS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE) Subject: [PATCH v6 06/13] irqchip/irq-bcm7038-l1: Switch to IRQCHIP_PLATFORM_DRIVER Date: Wed, 20 Oct 2021 11:48:52 -0700 Message-Id: <20211020184859.2705451-7-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020184859.2705451-1-f.fainelli@gmail.com> References: <20211020184859.2705451-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Allow the user selection and building of this interrupt controller driver as a module since it is used on ARM/ARM64 based systems as a second level interrupt controller hanging off the ARM GIC and is therefore loadable during boot. Signed-off-by: Florian Fainelli --- drivers/irqchip/Kconfig | 4 +++- drivers/irqchip/irq-bcm7038-l1.c | 6 +++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 4d5924e9f766..3022f6137096 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -115,7 +115,9 @@ config BCM6345_L1_IRQ select GENERIC_IRQ_EFFECTIVE_AFF_MASK config BCM7038_L1_IRQ - bool + tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" + depends on ARCH_BRCMSTB || BMIPS_GENERIC + default ARCH_BRCMSTB || BMIPS_GENERIC select GENERIC_IRQ_CHIP select IRQ_DOMAIN select GENERIC_IRQ_EFFECTIVE_AFF_MASK diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c index 357570dd8780..a62b96237b82 100644 --- a/drivers/irqchip/irq-bcm7038-l1.c +++ b/drivers/irqchip/irq-bcm7038-l1.c @@ -455,4 +455,8 @@ static int __init bcm7038_l1_of_init(struct device_node *dn, return ret; } -IRQCHIP_DECLARE(bcm7038_l1, "brcm,bcm7038-l1-intc", bcm7038_l1_of_init); +IRQCHIP_PLATFORM_DRIVER_BEGIN(bcm7038_l1) +IRQCHIP_MATCH("brcm,bcm7038-l1-intc", bcm7038_l1_of_init) +IRQCHIP_PLATFORM_DRIVER_END(bcm7038_l1) +MODULE_DESCRIPTION("Broadcom STB 7038-style L1/L2 interrupt controller"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Oct 20 18:48:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12573069 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFA86C4321E for ; Wed, 20 Oct 2021 18:50:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C883861212 for ; Wed, 20 Oct 2021 18:50:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231490AbhJTSw7 (ORCPT ); Wed, 20 Oct 2021 14:52:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231365AbhJTSwx (ORCPT ); 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Wed, 20 Oct 2021 11:50:37 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...), Russell King , Catalin Marinas , Will Deacon , Thomas Bogendoerfer , Thomas Gleixner , Marc Zyngier , Rob Herring , Frank Rowand , linux-arm-kernel@lists.infradead.org (moderated list:ARM SUB-ARCHITECTURES), linux-mips@vger.kernel.org (open list:MIPS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE) Subject: [PATCH v6 07/13] genirq: Export irq_gc_{unmask_enable,mask_disable}_reg Date: Wed, 20 Oct 2021 11:48:53 -0700 Message-Id: <20211020184859.2705451-8-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020184859.2705451-1-f.fainelli@gmail.com> References: <20211020184859.2705451-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org In order to allow drivers/irqchip/irq-brcmstb-l2.c to be built as a module we need to export: irq_gc_unmask_enable_reg() and irq_gc_mask_disable_reg(). Signed-off-by: Florian Fainelli --- kernel/irq/generic-chip.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index cc7cdd26e23e..4c011c21bb1a 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -44,6 +44,7 @@ void irq_gc_mask_disable_reg(struct irq_data *d) *ct->mask_cache &= ~mask; irq_gc_unlock(gc); } +EXPORT_SYMBOL_GPL(irq_gc_mask_disable_reg); /** * irq_gc_mask_set_bit - Mask chip via setting bit in mask register @@ -103,6 +104,7 @@ void irq_gc_unmask_enable_reg(struct irq_data *d) *ct->mask_cache |= mask; irq_gc_unlock(gc); } +EXPORT_SYMBOL_GPL(irq_gc_unmask_enable_reg); /** * irq_gc_ack_set_bit - Ack pending interrupt via setting bit From patchwork Wed Oct 20 18:48:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12573071 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D4BCC4332F for ; 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Wed, 20 Oct 2021 11:50:39 -0700 (PDT) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id o127sm3267863pfb.216.2021.10.20.11.50.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Oct 2021 11:50:39 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...), Russell King , Catalin Marinas , Will Deacon , Thomas Bogendoerfer , Thomas Gleixner , Marc Zyngier , Rob Herring , Frank Rowand , linux-arm-kernel@lists.infradead.org (moderated list:ARM SUB-ARCHITECTURES), linux-mips@vger.kernel.org (open list:MIPS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE) Subject: [PATCH v6 08/13] irqchip/irq-brcmstb-l2: Switch to IRQCHIP_PLATFORM_DRIVER Date: Wed, 20 Oct 2021 11:48:54 -0700 Message-Id: <20211020184859.2705451-9-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020184859.2705451-1-f.fainelli@gmail.com> References: <20211020184859.2705451-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Allow the user selection and building of this interrupt controller driver as a module since it is used on ARM/ARM64 based systems as a second level interrupt controller hanging off the ARM GIC and is therefore loadable during boot. Signed-off-by: Florian Fainelli --- drivers/irqchip/Kconfig | 4 +++- drivers/irqchip/irq-brcmstb-l2.c | 16 +++++++++------- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 3022f6137096..dfe54bf9b35f 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -128,7 +128,9 @@ config BCM7120_L2_IRQ select IRQ_DOMAIN config BRCMSTB_L2_IRQ - bool + tristate "Broadcom STB generic L2 interrupt controller driver" + depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC + default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC select GENERIC_IRQ_CHIP select IRQ_DOMAIN diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c index 8e0911561f2d..e4efc08ac594 100644 --- a/drivers/irqchip/irq-brcmstb-l2.c +++ b/drivers/irqchip/irq-brcmstb-l2.c @@ -275,16 +275,18 @@ static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np, { return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init); } -IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init); -IRQCHIP_DECLARE(brcmstb_hif_spi_l2_intc, "brcm,hif-spi-l2-intc", - brcmstb_l2_edge_intc_of_init); -IRQCHIP_DECLARE(brcmstb_upg_aux_aon_l2_intc, "brcm,upg-aux-aon-l2-intc", - brcmstb_l2_edge_intc_of_init); static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np, struct device_node *parent) { return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init); } -IRQCHIP_DECLARE(bcm7271_l2_intc, "brcm,bcm7271-l2-intc", - brcmstb_l2_lvl_intc_of_init); + +IRQCHIP_PLATFORM_DRIVER_BEGIN(brcmstb_l2) +IRQCHIP_MATCH("brcm,l2-intc", brcmstb_l2_edge_intc_of_init) +IRQCHIP_MATCH("brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_of_init) +IRQCHIP_MATCH("brcm,upg-aux-aon-l2-intc", brcmstb_l2_edge_intc_of_init) +IRQCHIP_MATCH("brcm,bcm7271-l2-intc", brcmstb_l2_lvl_intc_of_init) +IRQCHIP_PLATFORM_DRIVER_END(brcmstb_l2) +MODULE_DESCRIPTION("Broadcom STB generic L2 interrupt controller"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Oct 20 18:48:55 2021 Content-Type: text/plain; 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Signed-off-by: Florian Fainelli --- kernel/irq/generic-chip.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index 4c011c21bb1a..6f29bf4c8515 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -25,6 +25,7 @@ static DEFINE_RAW_SPINLOCK(gc_lock); void irq_gc_noop(struct irq_data *d) { } +EXPORT_SYMBOL_GPL(irq_gc_noop); /** * irq_gc_mask_disable_reg - Mask chip via disable register From patchwork Wed Oct 20 18:48:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12573075 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49961C433EF for ; Wed, 20 Oct 2021 18:50:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3483B6115B for ; Wed, 20 Oct 2021 18:50:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231603AbhJTSxI (ORCPT ); Wed, 20 Oct 2021 14:53:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231352AbhJTSw6 (ORCPT ); Wed, 20 Oct 2021 14:52:58 -0400 Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37388C061769; Wed, 20 Oct 2021 11:50:43 -0700 (PDT) Received: by mail-pg1-x531.google.com with SMTP id 75so23349863pga.3; Wed, 20 Oct 2021 11:50:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DgNlnw/X0eZIQ1orBNwNN4B1FWjS3NXzL3tygL/Zpc0=; b=nclhbtnO1d3VUqCjuO6fbVBLJwRCFzgkiQCrv3xYB3HM5GTyWvBhu6RljQKGdK2pK5 FR176iIdQqTr2RIJHZjvYaiVc8DtqG8Kbl30nEEs5hFoUAMhNRAedi+tAgyIhIw2qHbY Ah6th4TjmsOMkzx1p9m/a9z00gKcRY1FsArZ5GN/5oDFODb5uFWozEanMBUoZ6aKDxiG zWu1j9qJbrdumFiOrnH9tMw8uQWqPs5UYM+hatVgL/rBcTBxkszxKOv81hdZ38ezJL2R KPmZAnmi7K4LCsVXzYCCrxAcf2u+tMkzemWMSxWNfVLCrJrwvyHXKpP1nTOWgsGza8/k DSuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DgNlnw/X0eZIQ1orBNwNN4B1FWjS3NXzL3tygL/Zpc0=; b=LO2Er46BJlHPvKRrzLFe47v+6kjjbImxjxRqvPi3g1Wv1GrWBPsZpJ+ofu5FTLVYh+ 4PiS8wV+LueSx08FoHVO3kEf5Om3OuvzeLjOFvFaT5sGkJcpGeUKt6AFMKTwm7rk9M9F b3Rup9a6AQe4axqxvQpOC8Okq6SwZMkn0p1RAdoENDa9H7AIDZdkfvv7+Skxo7q1Pupu fWT7l9JEh4of84Z3vmO2zUMRGPxXPN48MoQQnS3uKG5Mju5/J7R16/VleK16YicHzbMK S6V+hOs0cIJF0MJXsf5PeV+5aqOFHhaj/mQl/h8u1VQRqnio4Lfmw4Pwh4puLz1OHpLH /nGA== X-Gm-Message-State: AOAM531Thiqca4vaeZzKc8K8wMMm0xjkDALVvxVccN0rzrfA/k5ewIDa SwlIxXaWXi68D60qTa+8K7QxK4MH4KQ= X-Google-Smtp-Source: ABdhPJxxYfaTpM34yX+EnA7h6FN0DD/aOb+FRn6t5KRFu0Tua/JQSghv55UaM3L5Rms0kPaDPlsd8A== X-Received: by 2002:a05:6a00:2389:b0:44d:6d57:a38e with SMTP id f9-20020a056a00238900b0044d6d57a38emr1053648pfc.50.1634755842459; Wed, 20 Oct 2021 11:50:42 -0700 (PDT) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id o127sm3267863pfb.216.2021.10.20.11.50.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Oct 2021 11:50:41 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...), Russell King , Catalin Marinas , Will Deacon , Thomas Bogendoerfer , Thomas Gleixner , Marc Zyngier , Rob Herring , Frank Rowand , linux-arm-kernel@lists.infradead.org (moderated list:ARM SUB-ARCHITECTURES), linux-mips@vger.kernel.org (open list:MIPS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE) Subject: [PATCH v6 10/13] irqchip/irq-bcm7120-l2: Switch to IRQCHIP_PLATFORM_DRIVER Date: Wed, 20 Oct 2021 11:48:56 -0700 Message-Id: <20211020184859.2705451-11-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020184859.2705451-1-f.fainelli@gmail.com> References: <20211020184859.2705451-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Allow the user selection and building of this interrupt controller driver as a module since it is used on ARM/ARM64 based systems as a second level interrupt controller hanging off the ARM GIC and is therefore loadable during boot. To avoid using of_irq_count() which is not exported towards module, switch the driver to use the platform_device provided by the irqchip platform driver code and resolve the number of interrupts using platform_irq_count(). Signed-off-by: Florian Fainelli --- drivers/irqchip/Kconfig | 4 +++- drivers/irqchip/irq-bcm7120-l2.c | 21 +++++++++++++++------ 2 files changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index dfe54bf9b35f..c7320bed5668 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -123,7 +123,9 @@ config BCM7038_L1_IRQ select GENERIC_IRQ_EFFECTIVE_AFF_MASK config BCM7120_L2_IRQ - bool + tristate "Broadcom STB 7120-style L2 interrupt controller driver" + depends on ARCH_BRCMSTB || BMIPS_GENERIC + default ARCH_BRCMSTB || BMIPS_GENERIC select GENERIC_IRQ_CHIP select IRQ_DOMAIN diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchip/irq-bcm7120-l2.c index f23d7651ea84..d80e67a6aad2 100644 --- a/drivers/irqchip/irq-bcm7120-l2.c +++ b/drivers/irqchip/irq-bcm7120-l2.c @@ -220,6 +220,7 @@ static int __init bcm7120_l2_intc_probe(struct device_node *dn, { unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; struct bcm7120_l2_intc_data *data; + struct platform_device *pdev; struct irq_chip_generic *gc; struct irq_chip_type *ct; int ret = 0; @@ -230,7 +231,13 @@ static int __init bcm7120_l2_intc_probe(struct device_node *dn, if (!data) return -ENOMEM; - data->num_parent_irqs = of_irq_count(dn); + pdev = of_find_device_by_node(dn); + if (!pdev) { + ret = -ENODEV; + goto out_free_data; + } + + data->num_parent_irqs = platform_irq_count(pdev); if (data->num_parent_irqs <= 0) { pr_err("invalid number of parent interrupts\n"); ret = -ENOMEM; @@ -329,6 +336,7 @@ static int __init bcm7120_l2_intc_probe(struct device_node *dn, if (data->map_base[idx]) iounmap(data->map_base[idx]); } +out_free_data: kfree(data); return ret; } @@ -347,8 +355,9 @@ static int __init bcm7120_l2_intc_probe_3380(struct device_node *dn, "BCM3380 L2"); } -IRQCHIP_DECLARE(bcm7120_l2_intc, "brcm,bcm7120-l2-intc", - bcm7120_l2_intc_probe_7120); - -IRQCHIP_DECLARE(bcm3380_l2_intc, "brcm,bcm3380-l2-intc", - bcm7120_l2_intc_probe_3380); +IRQCHIP_PLATFORM_DRIVER_BEGIN(bcm7120_l2) +IRQCHIP_MATCH("brcm,bcm7120-l2-intc", bcm7120_l2_intc_probe_7120) +IRQCHIP_MATCH("brcm,bcm3380-l2-intc", bcm7120_l2_intc_probe_3380) +IRQCHIP_PLATFORM_DRIVER_END(bcm7120_l2) +MODULE_DESCRIPTION("Broadcom STB 7120-style L2 interrupt controller driver"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Oct 20 18:48:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12573077 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAA50C43219 for ; Wed, 20 Oct 2021 18:50:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C676561038 for ; Wed, 20 Oct 2021 18:50:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231488AbhJTSxI (ORCPT ); Wed, 20 Oct 2021 14:53:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231515AbhJTSw7 (ORCPT ); Wed, 20 Oct 2021 14:52:59 -0400 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92577C06176C; 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Signed-off-by: Florian Fainelli --- arch/arm64/Kconfig.platforms | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index b0ce18d4cc98..2e9440f2da22 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -44,7 +44,6 @@ config ARCH_BCM2835 select ARM_AMBA select ARM_GIC select ARM_TIMER_SP804 - select BRCMSTB_L2_IRQ help This enables support for the Broadcom BCM2837 and BCM2711 SoC. These SoCs are used in the Raspberry Pi 3 and 4 devices. @@ -82,8 +81,6 @@ config ARCH_BITMAIN config ARCH_BRCMSTB bool "Broadcom Set-Top-Box SoCs" select ARCH_HAS_RESET_CONTROLLER - select BCM7038_L1_IRQ - select BRCMSTB_L2_IRQ select GENERIC_IRQ_CHIP select PINCTRL help From patchwork Wed Oct 20 18:48:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12573079 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F06AC433EF for ; Wed, 20 Oct 2021 18:51:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 19DA3610D0 for ; Wed, 20 Oct 2021 18:51:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231703AbhJTSxO (ORCPT ); Wed, 20 Oct 2021 14:53:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231529AbhJTSxA (ORCPT ); Wed, 20 Oct 2021 14:53:00 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2CF6BC06161C; Wed, 20 Oct 2021 11:50:46 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id k26so3730795pfi.5; Wed, 20 Oct 2021 11:50:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cvv2iZxij6FWrFEEKivGkcFAPGtCwuGKeJ0S/lB+6EU=; b=qohmFo7HSTuJiAuIg8jC9flJcI1Tz+q6TCYy7uEX1gXUDQ9oekWlTqYalK8iWW+mbk MT8LiO+KjgBDe7X2n6d5Zxa2thuN2px4LR/56XUbp3kkFs8AWOqvdx2h50r62Z3fvyvl MLop1X59Rk4uXj5ceRKB9legRu4YYKtqE50RTblCBy5ARZd/JKKra7VppZDKjvi5Ot/R AsMQX6Pg1fc2uLmopGB8v6jS38aB7B38NSgSMYHfXMV43dAOZmLtVGiZE8AAMnnOtggm MgJdPYPEhnUSAtN5sppUN+A9Q4imzs4EFaQJSGAY9wiFTrhu1Y7tN3qGszVBlTuTdrUO /uWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cvv2iZxij6FWrFEEKivGkcFAPGtCwuGKeJ0S/lB+6EU=; b=MlHM0DhG+QtLmk9mZdO2oTGuEBGo/IjloeXoPyGaExfZV3BV36PYKsa46pXOs02IUJ GpHWumw/Gc3Ft7VuXorqzQ4sWGckoZFfhQCtI9f5hSTC/WGQUxZpFI3Z84x2i3tztoNs pvht8UQmIxU2kpS9wg+GaNWyLxYo7Yie5Zu7NBAn3+dgJXUvQcx/oqqj9tOlvfKVzTZv 8t9foawvKPwbLJ+fVqxD//m8Rvl5PL7sqmCGqqgqveQuCP4ZrcR02mtFQeeihz5nNFFp hhOVB7jz6Gkc1IdUTGvWUarzpbxaKLE9EB9aDpC3CJ/nNjZB7CVpKqeLxlG7xS2F+sbr ZTWQ== X-Gm-Message-State: AOAM530ddkWcT+NN6Pa3/vR/hBWCr8E7UbRpLt0REyFZMdVCZa3CI7VW +axQdNquQPPQSQ3YqdW82S58Jv9uZWs= X-Google-Smtp-Source: ABdhPJyq0DSVNz71EBMdhA5txyFDLR2UKlGDUpXfcZZbCJzNwUZ45gyW393A5LrdSIZpv8Cpckh+bw== X-Received: by 2002:a05:6a00:d63:b0:44d:186d:c4c0 with SMTP id n35-20020a056a000d6300b0044d186dc4c0mr608662pfv.47.1634755845385; Wed, 20 Oct 2021 11:50:45 -0700 (PDT) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id o127sm3267863pfb.216.2021.10.20.11.50.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Oct 2021 11:50:44 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...), Russell King , Catalin Marinas , Will Deacon , Thomas Bogendoerfer , Thomas Gleixner , Marc Zyngier , Rob Herring , Frank Rowand , linux-arm-kernel@lists.infradead.org (moderated list:ARM SUB-ARCHITECTURES), linux-mips@vger.kernel.org (open list:MIPS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE) Subject: [PATCH v6 12/13] ARM: bcm: Removed forced select of interrupt controllers Date: Wed, 20 Oct 2021 11:48:58 -0700 Message-Id: <20211020184859.2705451-13-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020184859.2705451-1-f.fainelli@gmail.com> References: <20211020184859.2705451-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Now that the various second level interrupt controllers have been moved to IRQCHIP_PLATFORM_DRIVER and they do default to ARCH_BRCMSTB and ARCH_BCM2835 where relevant, remove their forced selection from the machine entry to allow an user to build them as modules. Signed-off-by: Florian Fainelli --- arch/arm/mach-bcm/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 2890e61b2b46..bd3f82788ebc 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -161,7 +161,6 @@ config ARCH_BCM2835 select ARM_TIMER_SP804 select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7 select BCM2835_TIMER - select BRCMSTB_L2_IRQ select PINCTRL select PINCTRL_BCM2835 select MFD_CORE @@ -209,9 +208,6 @@ config ARCH_BRCMSTB select ARM_GIC select ARM_ERRATA_798181 if SMP select HAVE_ARM_ARCH_TIMER - select BCM7038_L1_IRQ - select BRCMSTB_L2_IRQ - select BCM7120_L2_IRQ select ZONE_DMA if ARM_LPAE select SOC_BRCMSTB select SOC_BUS From patchwork Wed Oct 20 18:48:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12573081 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A129BC433F5 for ; Wed, 20 Oct 2021 18:51:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8CE9E61284 for ; Wed, 20 Oct 2021 18:51:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231732AbhJTSxQ (ORCPT ); Wed, 20 Oct 2021 14:53:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231546AbhJTSxC (ORCPT ); Wed, 20 Oct 2021 14:53:02 -0400 Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9383DC061760; Wed, 20 Oct 2021 11:50:47 -0700 (PDT) Received: by mail-pf1-x435.google.com with SMTP id d9so3742621pfl.6; Wed, 20 Oct 2021 11:50:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2G1kdri23kWnlj1enPufIZN1leyxpMasJ2EyRU0acfw=; b=GwRLeZAgQyhWzXBve39ZZ8disRmnwjqnXMZrtjJMr8p4bDJiS2ak5weMfmJWh4MMF1 cq1/VRmUkqMvbTD+bm9Xg5RJbYvwNbf/h5GWAXSuTwfUG9m3yZqFj3kLughJlaEwbCbq WFX0GhuK3476jKxhv3jTzDHrHCShNSSIOsFVIF9Ndy3E6htLHlNHaieXIAa7pZXzOu9h 69dpFXdbwAua8TZBAHkSUtNyZPHrdjbLLUeZnFIYjQ6fQCZpPWLg3mSMikvXWH/LX7pd NYI+WYr37cWoONmgtB2i+Am1E6mVnAcBpx7SXwWfVvOmXo2YcV4MxuNwZwMpskTePTFG RaKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2G1kdri23kWnlj1enPufIZN1leyxpMasJ2EyRU0acfw=; b=lIHQll+5u0v/L4z5CM8pZBbOre9X+ksZ9hNmz27iBdEEORQKqMl+yA15D46HM+nJ/q QQZMewyuhX30+ygUf2XiZLIigE85LL6Rofpsknk8xil3qV/uJoaJcB+/Pk+HxKqlgRV5 HwN3TA5zHh2t41U71X6a1qM2r8kF3v90QpQT03bxodAg/KBmkpv8MkJzIdHGaBmUemue 1jV2U6O0lYaZmI872E0Ok85UqY20UU4jLYTLSVO9reP4O9cl1J5vSFy5KadRJZQbKNKY lvO/GnFyJ9Yv0DY53xlQTbpxV/5JzEB/XbdQ4xmlBf1g00VzGsI4vMiGzHNUr1PbSSk0 obYw== X-Gm-Message-State: AOAM531K0f3ZRofskxbBWD2PYvEw/MJv0PQRz3zZaV7Et5cUHzOlWQRd wm982YFdfSUeYGFWVi3Pw/wGYZeXbyY= X-Google-Smtp-Source: ABdhPJzTBKlnu/SAxrtzo9ELZ3GXRd222mBb2VFjfNED53MAdRSpGCiwjE3SxrYBR4O4pWV+SP/xyg== X-Received: by 2002:a63:8c19:: with SMTP id m25mr794397pgd.164.1634755846750; Wed, 20 Oct 2021 11:50:46 -0700 (PDT) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id o127sm3267863pfb.216.2021.10.20.11.50.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Oct 2021 11:50:46 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...), Russell King , Catalin Marinas , Will Deacon , Thomas Bogendoerfer , Thomas Gleixner , Marc Zyngier , Rob Herring , Frank Rowand , linux-arm-kernel@lists.infradead.org (moderated list:ARM SUB-ARCHITECTURES), linux-mips@vger.kernel.org (open list:MIPS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE) Subject: [PATCH v6 13/13] irqchip: Fix kernel-doc parameter typo for IRQCHIP_DECLARE Date: Wed, 20 Oct 2021 11:48:59 -0700 Message-Id: <20211020184859.2705451-14-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020184859.2705451-1-f.fainelli@gmail.com> References: <20211020184859.2705451-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The documentation refers to "compstr" when we have the parameter named "compat", fix the typo. Signed-off-by: Florian Fainelli --- include/linux/irqchip.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/irqchip.h b/include/linux/irqchip.h index 67351aac65ef..ccf32758ea85 100644 --- a/include/linux/irqchip.h +++ b/include/linux/irqchip.h @@ -23,7 +23,7 @@ * * @name: name that must be unique across all IRQCHIP_DECLARE of the * same file. - * @compstr: compatible string of the irqchip driver + * @compat: compatible string of the irqchip driver * @fn: initialization function */ #define IRQCHIP_DECLARE(name, compat, fn) OF_DECLARE_2(irqchip, name, compat, fn)