From patchwork Fri Oct 22 07:52:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25555C433F5 for ; Fri, 22 Oct 2021 07:53:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 076EF60FC1 for ; Fri, 22 Oct 2021 07:53:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232249AbhJVH4F (ORCPT ); Fri, 22 Oct 2021 03:56:05 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:55648 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232223AbhJVH4E (ORCPT ); Fri, 22 Oct 2021 03:56:04 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889227; x=1666425227; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JCeKmhJWxbf+RcCJcIJfFnVB9AI8YV+GSaNqCjDMXX4=; b=eZUpEJErzWlH/x/UOXeE/+KkmPQOfXn8Zci2AiVnIDrlkRgV1lEuMA9x eu3LeXGLnX8NHefJn0K74ukgwOX5zFerTL55zIAnRypVw/p9jfin+xOh3 lyDSX5rKAYyJkdDaQxFZi0T6uHmVdVpXyqstxr2sfj95IVXK5koiaddxb XdJbrSr5Ck2dSlZejyicElrI+jzRqunOBM35/TcZzgeflVX274zYSqkzm Oak/UvcYrJNBkeEwWR0r19Z446wKdFWT7pNkoiAvkgAXS3+IundGMrvTY NIn8tABjz90o5vAwE5fb+GVC3eVd1skwUx+pMOLgNbT6OYppnBa/yMOMe w==; IronPort-SDR: 2cISAF1DdtTbo4weyyW0yKrwm+zoT9mYmysUSs6euBZfpGfhNrDW6VS2KkkA2JAoP0Z9KxcruA 0HcZiqFhd6940mtlq0nUkg+/pSLRcUPXcBKseOoHmPfrEm6x535St0VyD4k4RXVeiBvPjoa5r7 SGvKP7vVfpaSSwfC0VqW8H53Md6EqpcV+Y+UmJHJp0bubNDSWKViHdBjC3WGofc/OYG2NCcxdj txBQiqXJ7U3xqv72WBht4DiCsFX5r9sbtvGc3hHusVxf19nuxqArTnLkrdRP64YYJT4aZluUAY eTBlzk5gv72AdtZ99i6g7Q66 X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="149141115" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:53:46 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:53:46 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:53:42 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 01/21] MAINTAINERS: add microchip csi2dc Date: Fri, 22 Oct 2021 10:52:27 +0300 Message-ID: <20211022075247.518880-2-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add Microchip CSI2DC driver in the list. Signed-off-by: Eugen Hristev --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 186cfab07504..dab338f424db 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12252,6 +12252,13 @@ L: alsa-devel@alsa-project.org (moderated for non-subscribers) S: Supported F: sound/soc/atmel +MICROCHIP CSI2DC DRIVER +M: Eugen Hristev +L: linux-media@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/media/microchip,csi2dc.yaml +F: drivers/media/platform/atmel/microchip-csi2dc.c + MICROCHIP ECC DRIVER M: Tudor Ambarus L: linux-crypto@vger.kernel.org From patchwork Fri Oct 22 07:52:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7604C4332F for ; Fri, 22 Oct 2021 07:53:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 91DD46112D for ; Fri, 22 Oct 2021 07:53:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232290AbhJVH4I (ORCPT ); Fri, 22 Oct 2021 03:56:08 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:22711 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232279AbhJVH4H (ORCPT ); Fri, 22 Oct 2021 03:56:07 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889230; x=1666425230; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7j8Vm5cahPULNyteL3wTTU/YYgHhNg+Xi3C1+HJ/vuc=; b=ZBePsHE1FIM7ASxgauuS3ApmMk3lQkRmb3T0CA/fid8HDt6EX5G0fs18 Yli/RabfTUxoff5CZKCk4BpeGK/0UtJh3m6Ze0C6mh5Bhevp1qUzX0j80 7LOpNn4OP254k1LOd1Ityz2+cMbW97N0K5njP+KSLLUuIIAoewfuwVH85 8dDiHn0mhdlWhqkvNJVSVXGdpnx56z6D0VGMhN2CSHjEqnASsO8GP8YRQ eClPtA59tDyize7utGtXxYbetlEn4eqcEXhJ7PFZsjHiar39HjSMYjLQw Lf9yygq30BvrJJ3PNe0+H+UwqGOjk1WstObEjSdJy1nJk8YZR+dEU2NgE g==; IronPort-SDR: sFnqktDCZOPLJPNQHDHM+oCUTWHzAID1pPNEiQ2E2Xh0YdoZncM9ocYizeXkzYO/hCyC2h6F5d IXIZOaFQym1B9MFGmRBZnKvXaNS8XQESbVJifey26kx1JFh4t7TPK9ml4vQ2g6JesmcVWTFIyM hUuSKiN4B/4R4c+SEKSlY0WEZqIGDwpkPdgL1ZKMK9XBzhHuvcg12kPcIzITPDy2D9MA7bRjZT JqdfAKs4FKQ0cnb6nO+YUTjvDJaMv4hJzK6aSliPMEHpgYChnoyyl2Cm8Uf3TNPNOkm6B8RGZC v7m0QXuJECq4D1hPQIY8TNG0 X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="73928948" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:53:49 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:53:49 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:53:46 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 02/21] dt-bindings: media: atmel: csi2dc: add bindings for microchip csi2dc Date: Fri, 22 Oct 2021 10:52:28 +0300 Message-ID: <20211022075247.518880-3-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add bindings documentation for Microchip CSI2 Demultiplexer controller. CSI2DC is a demultiplexer from Synopsys IDI interface specification to parallel interface connection or direct memory access. Signed-off-by: Eugen Hristev --- Changes in this version : - fixed 'sink' name to be actually source. - added dma properties and example with dma Previous change log: Changes in v5: - modified bindings as per Rob Herring review Changes in v4: - Removed property for inter-line-delay and for clock continuous/non-continuous - Removed virtual channel by reg for second endpoint Changes in v3: - Removed some text from description, as it was explained in the schema - fixed other things as per Rob's review - moved some text inside the schema, like the clock description Changes in v2: - fixed warnings reported by dt_binding_check .../bindings/media/microchip,csi2dc.yaml | 149 ++++++++++++++++++ 1 file changed, 149 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/microchip,csi2dc.yaml diff --git a/Documentation/devicetree/bindings/media/microchip,csi2dc.yaml b/Documentation/devicetree/bindings/media/microchip,csi2dc.yaml new file mode 100644 index 000000000000..d317478908d0 --- /dev/null +++ b/Documentation/devicetree/bindings/media/microchip,csi2dc.yaml @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/microchip,csi2dc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip CSI2 Demux Controller (CSI2DC) + +maintainers: + - Eugen Hristev + +description: + CSI2DC - Camera Serial Interface 2 Demux Controller + + CSI2DC is a hardware block that receives incoming data from an IDI interface + and filters packets based on their data type and virtual channel identifier, + then converts the byte stream into a cross clock domain to a pixel stream + to a parallel interface that can be read by a sensor controller. + IDI interface is Synopsys proprietary. + + CSI2DC provides two pipes, one video pipe and one data pipe. Video pipe + is connected to a sensor controller and the data pipe is accessible + as a DMA slave port to a DMA controller. + + CSI2DC supports a single 'port' node as a sink port with Synopsys 32-bit + IDI interface. The connected endpoint must be a IDI interface compatible + device , that can provide 32-bit IDI interface connection as source port. + For graph video endpoints please refer to the bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + This port is mandatory. + + CSI2DC supports one 'port' node as source port with parallel interface. + This is called video pipe. + This port has an 'endpoint' that can be connected to a sink port of another + controller (next in pipeline). + Please refer to the bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + CSI2DC also supports direct access to the data through AHB, via DMA channel, + called data pipe. + Because of this, the source 'port' child node (second) is not mandatory. + If the source 'port' child node is missing, only data pipe is available. + For data pipe to be available, a dma controller must be referenced. + +properties: + compatible: + const: microchip,sama7g5-csi2dc + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + description: + CSI2DC must have two clocks to function correctly. One clock is the + peripheral clock for the inside functionality of the hardware block. + This is named 'pclk'. The second clock must be the cross domain clock, + in which CSI2DC will perform clock crossing. This clock must be fed + by the next controller in pipeline, which usually is a sensor controller. + Normally this clock should be given by this sensor controller who + is also a clock source. This clock is named 'scck', sensor controller clock. + items: + - const: pclk + - const: scck + + dmas: + maxItems: 1 + + dma-names: + const: rx + + ports: + type: object + description: + List of ports + + properties: + port@0: + type: object + description: + Input port node, single endpoint describing the input port. + port@1: + type: object + description: + Output port node, single endpoint, describing the output port. + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - ports + +examples: + # Example for connecting to a parallel sensor controller block + - | + csi2dc@e1404000 { + compatible = "microchip,sama7g5-csi2dc"; + reg = <0xe1404000 0x500>; + clocks = <&pclk>, <&scck>; + clock-names = "pclk", "scck"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; /* must be 0, first child port */ + csi2dc_in: endpoint { /* input from IDI interface */ + remote-endpoint = <&csi2host_out>; + }; + }; + + port@1 { + reg = <1>; /* must be 1, second child port */ + csi2dc_out: endpoint { + remote-endpoint = <&xisc_in>; /* output to sensor controller */ + }; + }; + }; + }; + + # Example for connecting to a DMA master as an AHB slave + - | + #include + csi2dc@e1404000 { + compatible = "microchip,sama7g5-csi2dc"; + reg = <0xe1404000 0x500>; + clocks = <&pclk>, <&scck>; + clock-names = "pclk", "scck"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>; + dma-names = "rx"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; /* must be 0, first child port */ + csi2dc_input: endpoint { /* input from IDI interface */ + remote-endpoint = <&csi2host_out>; + }; + }; + }; + }; + +... From patchwork Fri Oct 22 07:52:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D20FC433F5 for ; Fri, 22 Oct 2021 07:53:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6F17560FC3 for ; Fri, 22 Oct 2021 07:53:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232310AbhJVH4M (ORCPT ); Fri, 22 Oct 2021 03:56:12 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:17393 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232331AbhJVH4L (ORCPT ); Fri, 22 Oct 2021 03:56:11 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889234; x=1666425234; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ma+dKAX2pWoOewfmPmJTzXpxvEKF4oMdIqtmrE7Tbn4=; b=ZOddMYZDCJ74riY3dyTn10EjYQD9EGe3hVkMhT6BhYtIB4P/leoBqsqD WvpwiKsXVfzHOqrhkNrlINyTh/tyxPrsMQ3OnP5AVbGQlO9CUYc6K4rRZ uh6itQIJFvJES2MScvIOtEO1hIJPik4xaAywwHFbwYLvB599KDrI90IAS KT0b58OXhacWKFDK5FTuV4c87JHCdyw76CXwKiWWsd/aZRYW0SYwPrrDA 1ut0Lo/hot9WxeJ1M1OgTloGQGE/lB6ehXaGEUNT8V5BFnrYyZ3vwMvLz 7CMs3rEf04aoOukVj559vRZwJMNQztPc/UtpIgTkEAbd78Zn89MDZvtyw Q==; IronPort-SDR: vAV8ebsp5hN6aY9V5G7CCBK457C6rJ4vBI65rR+DZKHhKis9dn4JFODWS9sVPVpHXyfDFZsabt 3B0uTGbxCQl6X333zpEMwnZycY8Fd01RPgORwdcy7P2Tj3/1rydw0vetX1CFyTM+agpGIyV8ax preQrlIEz/lfO1aahW74FyoAwT3H2Rg9+ySJB8cW2ZzixG4SQQ8Y1TYU+5alWAxS0dI07iX5gc F/aTdRI9Te1ii9CsxgwMbFbq9v5FfLmVHtfG8H5pO1Q0+dGWRMQpFzi9PebdWUTJAp4FM9GFsy IOxHDZL0qAoRYEjFDFLAciDk X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="136538040" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:53:54 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:53:53 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:53:49 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 03/21] media: atmel: introduce microchip csi2dc driver Date: Fri, 22 Oct 2021 10:52:29 +0300 Message-ID: <20211022075247.518880-4-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Microchip CSI2DC (CSI2 Demultiplexer Controller) is a misc bridge device that converts a byte stream in IDI Synopsys format (coming from a CSI2HOST) to a pixel stream that can be captured by a sensor controller. Signed-off-by: Eugen Hristev --- Changes in this revision: - addressed comments by Jacopo and Laurent as in this thread: https://www.spinics.net/lists/linux-media/msg181044.html Previous change log : Changes in v5: - only in bindings Changes in v4: - now using get_mbus_config ops to get data from the subdevice, like the virtual channel id, and the clock type. - now having possibility to select any of the RAW10 data modes - at completion time, select which formats are also available in the subdevice, and move to the dynamic list accordingly - changed the pipeline integration, do not advertise subdev ready at probe time. wait until completion is done, and then start a workqueue that will register this device as a subdevice for the next element in pipeline. - moved the s_power code into a different function called now csi2dc_power that is called with CONFIG_PM functions. This is also called at completion, to have the device ready in case CONFIG_PM is not selected on the platform. - merged try_fmt into set_fmt - driver cleanup, wrapped lines over 80 characters Changes in v2: - moved driver to platform/atmel - fixed minor things as per Sakari's review - still some things from v2 review are not yet addressed, to be followed up drivers/media/platform/atmel/Kconfig | 15 + drivers/media/platform/atmel/Makefile | 1 + .../media/platform/atmel/microchip-csi2dc.c | 700 ++++++++++++++++++ 3 files changed, 716 insertions(+) create mode 100644 drivers/media/platform/atmel/microchip-csi2dc.c diff --git a/drivers/media/platform/atmel/Kconfig b/drivers/media/platform/atmel/Kconfig index dda2f27da317..f83bee373d82 100644 --- a/drivers/media/platform/atmel/Kconfig +++ b/drivers/media/platform/atmel/Kconfig @@ -40,3 +40,18 @@ config VIDEO_ATMEL_ISI help This module makes the ATMEL Image Sensor Interface available as a v4l2 device. + +config VIDEO_MICROCHIP_CSI2DC + tristate "Microchip CSI2 Demux Controller" + depends on VIDEO_V4L2 && COMMON_CLK && OF + depends on ARCH_AT91 || COMPILE_TEST + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + CSI2 Demux Controller driver. CSI2DC is a helper chip + that converts IDI interface byte stream to a parallel pixel stream. + It supports various RAW formats as input. + + To compile this driver as a module, choose M here: the + module will be called microchip-csi2dc. diff --git a/drivers/media/platform/atmel/Makefile b/drivers/media/platform/atmel/Makefile index 46d264ab7948..39f0a7eba702 100644 --- a/drivers/media/platform/atmel/Makefile +++ b/drivers/media/platform/atmel/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o obj-$(CONFIG_VIDEO_ATMEL_ISC_BASE) += atmel-isc-base.o obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel-isc.o obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel-xisc.o +obj-$(CONFIG_VIDEO_MICROCHIP_CSI2DC) += microchip-csi2dc.o diff --git a/drivers/media/platform/atmel/microchip-csi2dc.c b/drivers/media/platform/atmel/microchip-csi2dc.c new file mode 100644 index 000000000000..277b86988eee --- /dev/null +++ b/drivers/media/platform/atmel/microchip-csi2dc.c @@ -0,0 +1,700 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Microchip CSI2 Demux Controller (CSI2DC) driver + * + * Copyright (C) 2018 Microchip Technology, Inc. + * + * Author: Eugen Hristev + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* Global configuration register */ +#define CSI2DC_GCFG 0x0 + +/* MIPI sensor pixel clock is free running */ +#define CSI2DC_GCFG_MIPIFRN BIT(0) +/* Output waveform inter-line minimum delay */ +#define CSI2DC_GCFG_HLC(v) ((v) << 4) +#define CSI2DC_GCFG_HLC_MASK GENMASK(7, 4) +/* SAMA7G5 requires a HLC delay of 15 */ +#define SAMA7G5_HLC (15) + +/* Global control register */ +#define CSI2DC_GCTLR 0x04 +#define CSI2DC_GCTLR_SWRST BIT(0) + +/* Global status register */ +#define CSI2DC_GS 0x08 + +/* SSP interrupt status register */ +#define CSI2DC_SSPIS 0x28 +/* Pipe update register */ +#define CSI2DC_PU 0xC0 +/* Video pipe attributes update */ +#define CSI2DC_PU_VP BIT(0) + +/* Pipe update status register */ +#define CSI2DC_PUS 0xC4 + +/* Video pipeline enable register */ +#define CSI2DC_VPE 0xF8 +#define CSI2DC_VPE_ENABLE BIT(0) + +/* Video pipeline configuration register */ +#define CSI2DC_VPCFG 0xFC +/* Data type */ +#define CSI2DC_VPCFG_DT(v) ((v) << 0) +#define CSI2DC_VPCFG_DT_MASK GENMASK(5, 0) +/* Virtual channel identifier */ +#define CSI2DC_VPCFG_VC(v) ((v) << 6) +#define CSI2DC_VPCFG_VC_MASK GENMASK(7, 6) +/* Decompression enable */ +#define CSI2DC_VPCFG_DE BIT(8) +/* Decoder mode */ +#define CSI2DC_VPCFG_DM(v) ((v) << 9) +#define CSI2DC_VPCFG_DM_DECODER8TO12 0 +/* Decoder predictor 2 selection */ +#define CSI2DC_VPCFG_DP2 BIT(12) +/* Recommended memory storage */ +#define CSI2DC_VPCFG_RMS BIT(13) +/* Post adjustment */ +#define CSI2DC_VPCFG_PA BIT(14) + +/* Video pipeline column register */ +#define CSI2DC_VPCOL 0x100 +/* Column number */ +#define CSI2DC_VPCOL_COL(v) ((v) << 0) +#define CSI2DC_VPCOL_COL_MASK GENMASK(15, 0) + +/* Video pipeline row register */ +#define CSI2DC_VPROW 0x104 +/* Row number */ +#define CSI2DC_VPROW_ROW(v) ((v) << 0) +#define CSI2DC_VPROW_ROW_MASK GENMASK(15, 0) + +/* Version register */ +#define CSI2DC_VERSION 0x1FC + +/* register read/write helpers */ +#define csi2dc_readl(st, reg) readl_relaxed((st)->base + (reg)) +#define csi2dc_writel(st, reg, val) writel_relaxed((val), \ + (st)->base + (reg)) + +/* supported RAW data types */ +#define CSI2DC_DT_RAW6 0x28 +#define CSI2DC_DT_RAW7 0x29 +#define CSI2DC_DT_RAW8 0x2A +#define CSI2DC_DT_RAW10 0x2B +#define CSI2DC_DT_RAW12 0x2C +#define CSI2DC_DT_RAW14 0x2D + +/* + * struct csi2dc_format - CSI2DC format type struct + * @mbus_code: Media bus code for the format + * @dt: Data type constant for this format + */ +struct csi2dc_format { + u32 mbus_code; + u32 dt; +}; + +static const struct csi2dc_format csi2dc_formats[] = { + { + .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, + .dt = CSI2DC_DT_RAW10, + }, { + .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, + .dt = CSI2DC_DT_RAW10, + }, { + .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, + .dt = CSI2DC_DT_RAW10, + }, { + .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, + .dt = CSI2DC_DT_RAW10, + }, +}; + +enum mipi_csi_pads { + CSI2DC_PAD_SINK = 0, + CSI2DC_PAD_SOURCE = 1, + CSI2DC_PADS_NUM = 2, +}; + +/* + * struct csi2dc_device - CSI2DC device driver data/config struct + * @base: Register map base address + * @csi2dc_sd: v4l2 subdevice for the csi2dc device + * This is the subdevice that the csi2dc device itself + * registers in v4l2 subsystem + * @dev: struct device for this csi2dc device + * @pclk: Peripheral clock reference + * Input clock that clocks the hardware block internal + * logic + * @scck: Sensor Controller clock reference + * Input clock that is used to generate the pixel clock + * @format: Current saved format used in g/s fmt + * @cur_fmt: Current state format + * @try_fmt: Try format that is being tried + * @pads: Media entity pads for the csi2dc subdevice + * @clk_gated: Whether the clock is gated or free running + * @video_pipe: Whether video pipeline is configured + * @vc: Current set virtual channel + * @asd: Async subdevice for async bound of the underlying subdev + * @notifier: Async notifier that is used to bound the underlying + * subdevice to the csi2dc subdevice + * @input_sd: Reference to the underlying subdevice bound to the + * csi2dc subdevice + * @remote_pad: Pad number of the underlying subdevice that is linked + * to the csi2dc subdevice sink pad. + */ +struct csi2dc_device { + void __iomem *base; + struct v4l2_subdev csi2dc_sd; + struct device *dev; + struct clk *pclk; + struct clk *scck; + + struct v4l2_mbus_framefmt format; + + const struct csi2dc_format *cur_fmt; + const struct csi2dc_format *try_fmt; + + struct media_pad pads[CSI2DC_PADS_NUM]; + + bool clk_gated; + bool video_pipe; + u32 vc; + + struct v4l2_async_subdev *asd; + struct v4l2_async_notifier notifier; + + struct v4l2_subdev *input_sd; + + u32 remote_pad; +}; + +static void csi2dc_vp_update(struct csi2dc_device *csi2dc) +{ + u32 vp; + + if (!csi2dc->cur_fmt) { + dev_err(csi2dc->dev, "format must be configured first\n"); + return; + } + + if (!csi2dc->video_pipe) { + dev_err(csi2dc->dev, "video pipeline unavailable\n"); + return; + } + + vp = CSI2DC_VPCFG_DT(csi2dc->cur_fmt->dt) & CSI2DC_VPCFG_DT_MASK; + vp |= CSI2DC_VPCFG_VC(csi2dc->vc) & CSI2DC_VPCFG_VC_MASK; + vp &= ~CSI2DC_VPCFG_DE; + vp |= CSI2DC_VPCFG_DM(CSI2DC_VPCFG_DM_DECODER8TO12); + vp &= ~CSI2DC_VPCFG_DP2; + vp &= ~CSI2DC_VPCFG_RMS; + vp |= CSI2DC_VPCFG_PA; + + csi2dc_writel(csi2dc, CSI2DC_VPCFG, vp); + csi2dc_writel(csi2dc, CSI2DC_VPE, CSI2DC_VPE_ENABLE); + csi2dc_writel(csi2dc, CSI2DC_PU, CSI2DC_PU_VP); +} + +static inline struct csi2dc_device * +csi2dc_sd_to_csi2dc_device(struct v4l2_subdev *csi2dc_sd) +{ + return container_of(csi2dc_sd, struct csi2dc_device, csi2dc_sd); +} + +static int csi2dc_enum_mbus_code(struct v4l2_subdev *csi2dc_sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= ARRAY_SIZE(csi2dc_formats)) + return -EINVAL; + + code->code = csi2dc_formats[code->index].mbus_code; + + return 0; +} + +static int csi2dc_get_fmt(struct v4l2_subdev *csi2dc_sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + struct csi2dc_device *csi2dc = csi2dc_sd_to_csi2dc_device(csi2dc_sd); + + format->format = csi2dc->format; + + return 0; +} + +static int csi2dc_set_fmt(struct v4l2_subdev *csi2dc_sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *req_fmt) +{ + struct csi2dc_device *csi2dc = csi2dc_sd_to_csi2dc_device(csi2dc_sd); + const struct csi2dc_format *fmt; + int i; + + for (i = 0; i < ARRAY_SIZE(csi2dc_formats); i++) { + fmt = &csi2dc_formats[i]; + if (req_fmt->format.code == fmt->mbus_code) + csi2dc->try_fmt = fmt; + fmt++; + } + + /* in case we could not find the desired format, default to something */ + if (!csi2dc->try_fmt || + req_fmt->format.code != csi2dc->try_fmt->mbus_code) { + csi2dc->try_fmt = &csi2dc_formats[0]; + + dev_dbg(csi2dc->dev, + "CSI2DC unsupported format 0x%x, defaulting to 0x%x\n", + req_fmt->format.code, csi2dc_formats[0].mbus_code); + + req_fmt->format.code = csi2dc_formats[0].mbus_code; + } + + req_fmt->format.colorspace = V4L2_COLORSPACE_SRGB; + req_fmt->format.field = V4L2_FIELD_NONE; + + /* save the format for later requests */ + csi2dc->format = req_fmt->format; + + /* if we are just trying, we are done */ + if (req_fmt->which == V4L2_SUBDEV_FORMAT_TRY) + return 0; + + csi2dc->cur_fmt = csi2dc->try_fmt; + + dev_dbg(csi2dc->dev, "new format set: 0x%x\n", req_fmt->format.code); + + return 0; +} + +static int csi2dc_power(struct csi2dc_device *csi2dc, int on) +{ + int ret = 0; + + if (on) { + ret = clk_prepare_enable(csi2dc->pclk); + if (ret) { + dev_err(csi2dc->dev, "failed to enable pclk: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(csi2dc->scck); + if (ret) + dev_err(csi2dc->dev, + "failed to enable scck: %d\n", ret); + + /* if powering up, deassert reset line */ + csi2dc_writel(csi2dc, CSI2DC_GCTLR, CSI2DC_GCTLR_SWRST); + } else { + clk_disable_unprepare(csi2dc->scck); + + /* if powering down, assert reset line */ + csi2dc_writel(csi2dc, CSI2DC_GCTLR, !CSI2DC_GCTLR_SWRST); + + clk_disable_unprepare(csi2dc->pclk); + } + + return ret; +} + +static int csi2dc_s_stream(struct v4l2_subdev *csi2dc_sd, int enable) +{ + struct csi2dc_device *csi2dc = csi2dc_sd_to_csi2dc_device(csi2dc_sd); + int ret; + + if (enable) { + ret = pm_runtime_resume_and_get(csi2dc->dev); + if (ret < 0) + return ret; + csi2dc_vp_update(csi2dc); + } else { + pm_runtime_put_sync(csi2dc->dev); + } + + return v4l2_subdev_call(csi2dc->input_sd, video, s_stream, enable); +} + +static const struct v4l2_subdev_pad_ops csi2dc_pad_ops = { + .enum_mbus_code = csi2dc_enum_mbus_code, + .set_fmt = csi2dc_set_fmt, + .get_fmt = csi2dc_get_fmt, +}; + +static const struct v4l2_subdev_video_ops csi2dc_video_ops = { + .s_stream = csi2dc_s_stream, +}; + +static const struct v4l2_subdev_ops csi2dc_subdev_ops = { + .pad = &csi2dc_pad_ops, + .video = &csi2dc_video_ops, +}; + +static int csi2dc_get_mbus_config(struct csi2dc_device *csi2dc) +{ + struct v4l2_mbus_config mbus_config = { 0 }; + int ret; + + ret = v4l2_subdev_call(csi2dc->input_sd, pad, get_mbus_config, + csi2dc->remote_pad, &mbus_config); + if (ret == -ENOIOCTLCMD) { + dev_dbg(csi2dc->dev, + "no remote mbus configuration available\n"); + goto csi2dc_get_mbus_config_defaults; + } + + if (ret) { + dev_err(csi2dc->dev, + "failed to get remote mbus configuration\n"); + goto csi2dc_get_mbus_config_defaults; + } + + if (mbus_config.flags & V4L2_MBUS_CSI2_CHANNEL_0) + csi2dc->vc = 0; + else if (mbus_config.flags & V4L2_MBUS_CSI2_CHANNEL_1) + csi2dc->vc = 1; + else if (mbus_config.flags & V4L2_MBUS_CSI2_CHANNEL_2) + csi2dc->vc = 2; + else if (mbus_config.flags & V4L2_MBUS_CSI2_CHANNEL_3) + csi2dc->vc = 3; + + dev_dbg(csi2dc->dev, "subdev sending on channel %d\n", csi2dc->vc); + + csi2dc->clk_gated = mbus_config.flags & + V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK; + + dev_dbg(csi2dc->dev, "%s clock\n", + csi2dc->clk_gated ? "gated" : "free running"); + + return 0; + +csi2dc_get_mbus_config_defaults: + csi2dc->vc = 0; /* Virtual ID 0 by default */ + csi2dc->clk_gated = false; /* Free running clock by default */ + + return 0; +} + +static int csi2dc_async_bound(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *subdev, + struct v4l2_async_subdev *asd) +{ + struct csi2dc_device *csi2dc = container_of(notifier, + struct csi2dc_device, notifier); + int pad; + int ret; + + csi2dc->input_sd = subdev; + + pad = media_entity_get_fwnode_pad(&subdev->entity, + asd->match.fwnode, + MEDIA_PAD_FL_SOURCE); + if (pad < 0) { + dev_err(csi2dc->dev, "Failed to find pad for %s\n", + subdev->name); + return pad; + } + + csi2dc->remote_pad = pad; + + csi2dc_get_mbus_config(csi2dc); + + ret = media_create_pad_link(&csi2dc->input_sd->entity, + csi2dc->remote_pad, + &csi2dc->csi2dc_sd.entity, 0, + MEDIA_LNK_FL_ENABLED); + if (ret < 0) { + dev_err(csi2dc->dev, + "Failed to create pad link: %s to %s\n", + csi2dc->input_sd->entity.name, + csi2dc->csi2dc_sd.entity.name); + return ret; + } + + dev_dbg(csi2dc->dev, "link with %s pad: %d\n", + csi2dc->input_sd->name, csi2dc->remote_pad); + + ret = pm_runtime_resume_and_get(csi2dc->dev); + if (ret < 0) + return ret; + + csi2dc_writel(csi2dc, CSI2DC_GCFG, + (SAMA7G5_HLC & CSI2DC_GCFG_HLC_MASK) | + (csi2dc->clk_gated ? 0 : CSI2DC_GCFG_MIPIFRN)); + + csi2dc_writel(csi2dc, CSI2DC_VPCOL, + CSI2DC_VPCOL_COL(0xFFF) & CSI2DC_VPCOL_COL_MASK); + csi2dc_writel(csi2dc, CSI2DC_VPROW, + CSI2DC_VPROW_ROW(0xFFF) & CSI2DC_VPROW_ROW_MASK); + + pm_runtime_put_sync(csi2dc->dev); + + return ret; +} + +static const struct v4l2_async_notifier_operations csi2dc_async_ops = { + .bound = csi2dc_async_bound, +}; + +static void csi2dc_cleanup_notifier(struct csi2dc_device *csi2dc) +{ + v4l2_async_notifier_unregister(&csi2dc->notifier); + v4l2_async_notifier_cleanup(&csi2dc->notifier); +} + +static int csi2dc_prepare_notifier(struct csi2dc_device *csi2dc, + struct device_node *input_node) +{ + int ret = 0; + + v4l2_async_notifier_init(&csi2dc->notifier); + + csi2dc->asd = v4l2_async_notifier_add_fwnode_remote_subdev + (&csi2dc->notifier, of_fwnode_handle(input_node), + struct v4l2_async_subdev); + + of_node_put(input_node); + + if (IS_ERR(csi2dc->asd)) { + ret = PTR_ERR(csi2dc->asd); + dev_err(csi2dc->dev, + "failed to add async notifier for node %pOF: %d\n", + input_node, ret); + v4l2_async_notifier_cleanup(&csi2dc->notifier); + return ret; + } + + csi2dc->notifier.ops = &csi2dc_async_ops; + + ret = v4l2_async_subdev_notifier_register(&csi2dc->csi2dc_sd, + &csi2dc->notifier); + + if (ret) { + dev_err(csi2dc->dev, "fail to register async notifier: %d\n", + ret); + v4l2_async_notifier_cleanup(&csi2dc->notifier); + } + + return ret; +} + +static int csi2dc_of_parse(struct csi2dc_device *csi2dc, + struct device_node *of_node) +{ + struct device_node *input_node, *output_node; + struct v4l2_fwnode_endpoint input_endpoint = { 0 }, + output_endpoint = { 0 }; + int ret; + + output_endpoint.bus_type = V4L2_MBUS_PARALLEL; + + input_node = of_graph_get_next_endpoint(of_node, NULL); + + if (!input_node) { + dev_err(csi2dc->dev, + "missing port node at %pOF, input node is mandatory.\n", + of_node); + return -EINVAL; + } + + ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(input_node), + &input_endpoint); + + if (ret) { + dev_err(csi2dc->dev, "endpoint not defined at %pOF\n", of_node); + return ret; + } + + output_node = of_graph_get_next_endpoint(of_node, input_node); + + if (output_node) + ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(output_node), + &output_endpoint); + + if (!output_node || ret) { + dev_info(csi2dc->dev, + "missing output node at %pOF, data pipe available only.\n", + of_node); + } else { + csi2dc->video_pipe = true; + + dev_dbg(csi2dc->dev, "block %pOF %d.%d->%d.%d video pipeline\n", + of_node, input_endpoint.base.port, + input_endpoint.base.id, output_endpoint.base.port, + output_endpoint.base.id); + } + + of_node_put(output_node); + of_node_put(input_node); + + /* prepare async notifier for subdevice completion */ + return csi2dc_prepare_notifier(csi2dc, input_node); +} + +static int csi2dc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct csi2dc_device *csi2dc; + struct resource *res = NULL; + int ret = 0; + u32 ver; + + csi2dc = devm_kzalloc(dev, sizeof(*csi2dc), GFP_KERNEL); + if (!csi2dc) + return -ENOMEM; + + csi2dc->dev = dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + csi2dc->base = devm_ioremap_resource(dev, res); + if (IS_ERR(csi2dc->base)) { + dev_err(dev, "base address not set\n"); + return PTR_ERR(csi2dc->base); + } + + csi2dc->pclk = devm_clk_get(dev, "pclk"); + if (IS_ERR(csi2dc->pclk)) { + ret = PTR_ERR(csi2dc->pclk); + dev_err(dev, "failed to get pclk: %d\n", ret); + return ret; + } + + csi2dc->scck = devm_clk_get(dev, "scck"); + if (IS_ERR(csi2dc->scck)) { + ret = PTR_ERR(csi2dc->scck); + dev_err(dev, "failed to get scck: %d\n", ret); + return ret; + } + + v4l2_subdev_init(&csi2dc->csi2dc_sd, &csi2dc_subdev_ops); + + csi2dc->csi2dc_sd.owner = THIS_MODULE; + csi2dc->csi2dc_sd.dev = dev; + snprintf(csi2dc->csi2dc_sd.name, sizeof(csi2dc->csi2dc_sd.name), + "csi2dc"); + + csi2dc->csi2dc_sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + csi2dc->csi2dc_sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; + v4l2_set_subdevdata(&csi2dc->csi2dc_sd, pdev); + + platform_set_drvdata(pdev, csi2dc); + + ret = csi2dc_of_parse(csi2dc, dev->of_node); + if (ret) + goto csi2dc_probe_cleanup_entity; + + csi2dc->pads[CSI2DC_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + if (csi2dc->video_pipe) + csi2dc->pads[CSI2DC_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + + ret = media_entity_pads_init(&csi2dc->csi2dc_sd.entity, + csi2dc->video_pipe ? CSI2DC_PADS_NUM : 1, + csi2dc->pads); + if (ret < 0) { + dev_err(dev, "media entity init failed\n"); + goto csi2dc_probe_cleanup_entity; + } + + /* turn power on to validate capabilities */ + ret = csi2dc_power(csi2dc, true); + if (ret < 0) + goto csi2dc_probe_cleanup_entity; + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + ver = csi2dc_readl(csi2dc, CSI2DC_VERSION); + pm_request_idle(dev); + + /* + * we must register the subdev after PM runtime has been requested, + * otherwise we might bound immediately and request pm_runtime_resume + * before runtime_enable. + */ + ret = v4l2_async_register_subdev(&csi2dc->csi2dc_sd); + if (ret) { + dev_err(csi2dc->dev, "failed to register the subdevice\n"); + goto csi2dc_probe_cleanup_entity; + } + + dev_info(dev, "Microchip CSI2DC version %x\n", ver); + + return 0; + +csi2dc_probe_cleanup_entity: + media_entity_cleanup(&csi2dc->csi2dc_sd.entity); + + return ret; +} + +static int csi2dc_remove(struct platform_device *pdev) +{ + struct csi2dc_device *csi2dc = platform_get_drvdata(pdev); + + pm_runtime_disable(&pdev->dev); + + v4l2_async_unregister_subdev(&csi2dc->csi2dc_sd); + csi2dc_cleanup_notifier(csi2dc); + media_entity_cleanup(&csi2dc->csi2dc_sd.entity); + + return 0; +} + +static int __maybe_unused csi2dc_runtime_suspend(struct device *dev) +{ + struct csi2dc_device *csi2dc = dev_get_drvdata(dev); + + return csi2dc_power(csi2dc, false); +} + +static int __maybe_unused csi2dc_runtime_resume(struct device *dev) +{ + struct csi2dc_device *csi2dc = dev_get_drvdata(dev); + + return csi2dc_power(csi2dc, true); +} + +static const struct dev_pm_ops csi2dc_dev_pm_ops = { + SET_RUNTIME_PM_OPS(csi2dc_runtime_suspend, csi2dc_runtime_resume, NULL) +}; + +static const struct of_device_id csi2dc_of_match[] = { + { .compatible = "microchip,sama7g5-csi2dc" }, + { } +}; + +MODULE_DEVICE_TABLE(of, csi2dc_of_match); + +static struct platform_driver csi2dc_driver = { + .probe = csi2dc_probe, + .remove = csi2dc_remove, + .driver = { + .name = "microchip-csi2dc", + .pm = &csi2dc_dev_pm_ops, + .of_match_table = of_match_ptr(csi2dc_of_match), + }, +}; + +module_platform_driver(csi2dc_driver); + +MODULE_AUTHOR("Eugen Hristev "); +MODULE_DESCRIPTION("Microchip CSI2 Demux Controller driver"); +MODULE_LICENSE("GPL v2"); From patchwork Fri Oct 22 07:52:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577299 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C47C0C433FE for ; Fri, 22 Oct 2021 07:54:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A9548610C8 for ; Fri, 22 Oct 2021 07:54:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232404AbhJVH4Y (ORCPT ); Fri, 22 Oct 2021 03:56:24 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:22728 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232324AbhJVH4Q (ORCPT ); Fri, 22 Oct 2021 03:56:16 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889239; x=1666425239; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XEDYPt5D/N3RVUcKR9/1kimB4x9GpFaJKFi+qV15Yrg=; b=iyMc94ieMuNUsTAIwe/IvcVViW3ik8+eg3+P2CcA/8up1RPu+pWGW3+t 3+i7mqlH5RT68W8po7KswoA0DRFhnzBsIWDO+tsduF/iXXEU4DLc51if1 yWM3ML5DA4SJuXIwfeT/bKZEmakNfbBPkMCxtw46eOcb9bkXQ5LXOmbEX 5/U/4+A+bNiphH/KozOqtF0XhRZh0yaEzZ5ZYfZ3wbbILWPSuIXmqELNm CHRgzGd5egQtOVvsayETbodjcrYRv5rJcmFK17CgYvPbhriyEV81qoiJ7 5UK2+RMmzRd+KmR1X3+jbzjYl3jhM0yXaJpyvJaSTs2nSImyMwW1/eiL0 g==; IronPort-SDR: K+cFbPjU3jloI+pAo075LzbTT3GZFx10RMyyIt4dbdTl8SGND4M6yR7vLqAHlq1pHZ4oiv2PMD NUnSl70CjNgbkCrbQYxMnKjXM+9egoP/YLzvvbnxI4Sn9MY10bwHs/7AR0xh0J9x8WU94kjOPm hDM04ibFnYhEFiy0yIwEg6fFrSRxHF7s0PZMsrbYKSbAatslNXSVUhDMn1RAnlQVPRTMr6ZY1b APwCXgCvCc2uUkAHa1Bzc6K7DQLBnBPglnhfMgrZnaK/Zw7vV6+a3teCKtvC9tv3Shgpatp4cS 13SNCbY3aMEWrZi3SrH08kr0 X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="73928959" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:53:58 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:53:57 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:53:54 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 04/21] MAINTAINERS: atmel-isc: add new file atmel-isc-clk.c Date: Fri, 22 Oct 2021 10:52:30 +0300 Message-ID: <20211022075247.518880-5-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add new file atmel-isc-clk.c to MAINTAINERS entry. Signed-off-by: Eugen Hristev --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index dab338f424db..e151716c8d1e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12279,6 +12279,7 @@ S: Supported F: Documentation/devicetree/bindings/media/atmel,isc.yaml F: Documentation/devicetree/bindings/media/microchip,xisc.yaml F: drivers/media/platform/atmel/atmel-isc-base.c +F: drivers/media/platform/atmel/atmel-isc-clk.c F: drivers/media/platform/atmel/atmel-isc-regs.h F: drivers/media/platform/atmel/atmel-isc.h F: drivers/media/platform/atmel/atmel-sama5d2-isc.c From patchwork Fri Oct 22 07:52:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577301 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DFC3C433F5 for ; Fri, 22 Oct 2021 07:54:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 050FC610C8 for ; Fri, 22 Oct 2021 07:54:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232377AbhJVH40 (ORCPT ); Fri, 22 Oct 2021 03:56:26 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:55127 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232382AbhJVH4T (ORCPT ); Fri, 22 Oct 2021 03:56:19 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889242; x=1666425242; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9AEfk4Ejtyle8LNhVaGLs0EoD420ZJuqh72yczV22pU=; b=HWHfPGyXrkSn+3eK87RTPpK7jgnYF8O2ha9aBo10z9g79FsV2xJrobd7 YeRIBscmyLMCkoMxtNi9QpV2V5cQxTaksuSGCA6woZ/1IrJNG4eMrR6FL hKyu/ZAYNCiHZwX5WZeLxot5kgNq8K+h4AszSEA0Ijg2y8i9pA9tgqBWs z0IFnjbGjl17r1VFmveROHyniKrMf9eEmqTwgSnGfbm4vLmCNhnN34VQ2 eS9jiCqLtBKBCkycKyKyDO6VNj34+/AFTgZISVPAYF5t2IUk0KySpGQor V7uSltb2PosSruUFFJQXKGShNrPhrv4QuaHwZN9esnOSIqaBf+NBvT2lU A==; IronPort-SDR: eZ3SVDXYda8Pkor056Yqhx4z8RqWfohHzN7IQ7kHx051DV4H48kIe/SAxTo+gI8ZEDXym3TbgT Vl2L8ZZ+WLEIw520cVoEKpun4KXMv4RbVRTqNL1VMAf3JLPz7AbeShi0VypzTCovP7Mm+0IBgb L6tiUCh0c5KY8ULcTLUTqBc6lLkApUFlJOULpNS80LP11jsO6e2ZFeiY60XwPk/NPEnWvzvhMh GGSbUfcA24ZUpHKQgAfLENYtN9ZTmhg24Y+sRIcWUB8N8OIgcmSVOeYQOzrDEzA1XLMBQhqsrB pQpi9vkubN1ZeORmLQ8cfpCv X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="134007190" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:54:01 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:54:01 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:53:58 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 05/21] media: atmel: atmel-isc: split the clock code into separate source file Date: Fri, 22 Oct 2021 10:52:31 +0300 Message-ID: <20211022075247.518880-6-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The atmel-isc-base is getting crowded. Split the clock functions into atmel-isc-clk.c. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/Makefile | 2 +- drivers/media/platform/atmel/atmel-isc-base.c | 294 ---------------- drivers/media/platform/atmel/atmel-isc-clk.c | 316 ++++++++++++++++++ 3 files changed, 317 insertions(+), 295 deletions(-) create mode 100644 drivers/media/platform/atmel/atmel-isc-clk.c diff --git a/drivers/media/platform/atmel/Makefile b/drivers/media/platform/atmel/Makefile index 39f0a7eba702..1f6fe7427769 100644 --- a/drivers/media/platform/atmel/Makefile +++ b/drivers/media/platform/atmel/Makefile @@ -3,7 +3,7 @@ atmel-isc-objs = atmel-sama5d2-isc.o atmel-xisc-objs = atmel-sama7g5-isc.o obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o -obj-$(CONFIG_VIDEO_ATMEL_ISC_BASE) += atmel-isc-base.o +obj-$(CONFIG_VIDEO_ATMEL_ISC_BASE) += atmel-isc-base.o atmel-isc-clk.o obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel-isc.o obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel-xisc.o obj-$(CONFIG_VIDEO_MICROCHIP_CSI2DC) += microchip-csi2dc.o diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index ebf264b980f9..f532fd03e807 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -8,9 +8,6 @@ * Author: Eugen Hristev * */ - -#include -#include #include #include #include @@ -100,297 +97,6 @@ static inline void isc_reset_awb_ctrls(struct isc_device *isc) } } -static int isc_wait_clk_stable(struct clk_hw *hw) -{ - struct isc_clk *isc_clk = to_isc_clk(hw); - struct regmap *regmap = isc_clk->regmap; - unsigned long timeout = jiffies + usecs_to_jiffies(1000); - unsigned int status; - - while (time_before(jiffies, timeout)) { - regmap_read(regmap, ISC_CLKSR, &status); - if (!(status & ISC_CLKSR_SIP)) - return 0; - - usleep_range(10, 250); - } - - return -ETIMEDOUT; -} - -static int isc_clk_prepare(struct clk_hw *hw) -{ - struct isc_clk *isc_clk = to_isc_clk(hw); - int ret; - - ret = pm_runtime_resume_and_get(isc_clk->dev); - if (ret < 0) - return ret; - - return isc_wait_clk_stable(hw); -} - -static void isc_clk_unprepare(struct clk_hw *hw) -{ - struct isc_clk *isc_clk = to_isc_clk(hw); - - isc_wait_clk_stable(hw); - - pm_runtime_put_sync(isc_clk->dev); -} - -static int isc_clk_enable(struct clk_hw *hw) -{ - struct isc_clk *isc_clk = to_isc_clk(hw); - u32 id = isc_clk->id; - struct regmap *regmap = isc_clk->regmap; - unsigned long flags; - unsigned int status; - - dev_dbg(isc_clk->dev, "ISC CLK: %s, id = %d, div = %d, parent id = %d\n", - __func__, id, isc_clk->div, isc_clk->parent_id); - - spin_lock_irqsave(&isc_clk->lock, flags); - regmap_update_bits(regmap, ISC_CLKCFG, - ISC_CLKCFG_DIV_MASK(id) | ISC_CLKCFG_SEL_MASK(id), - (isc_clk->div << ISC_CLKCFG_DIV_SHIFT(id)) | - (isc_clk->parent_id << ISC_CLKCFG_SEL_SHIFT(id))); - - regmap_write(regmap, ISC_CLKEN, ISC_CLK(id)); - spin_unlock_irqrestore(&isc_clk->lock, flags); - - regmap_read(regmap, ISC_CLKSR, &status); - if (status & ISC_CLK(id)) - return 0; - else - return -EINVAL; -} - -static void isc_clk_disable(struct clk_hw *hw) -{ - struct isc_clk *isc_clk = to_isc_clk(hw); - u32 id = isc_clk->id; - unsigned long flags; - - spin_lock_irqsave(&isc_clk->lock, flags); - regmap_write(isc_clk->regmap, ISC_CLKDIS, ISC_CLK(id)); - spin_unlock_irqrestore(&isc_clk->lock, flags); -} - -static int isc_clk_is_enabled(struct clk_hw *hw) -{ - struct isc_clk *isc_clk = to_isc_clk(hw); - u32 status; - int ret; - - ret = pm_runtime_resume_and_get(isc_clk->dev); - if (ret < 0) - return 0; - - regmap_read(isc_clk->regmap, ISC_CLKSR, &status); - - pm_runtime_put_sync(isc_clk->dev); - - return status & ISC_CLK(isc_clk->id) ? 1 : 0; -} - -static unsigned long -isc_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) -{ - struct isc_clk *isc_clk = to_isc_clk(hw); - - return DIV_ROUND_CLOSEST(parent_rate, isc_clk->div + 1); -} - -static int isc_clk_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - struct isc_clk *isc_clk = to_isc_clk(hw); - long best_rate = -EINVAL; - int best_diff = -1; - unsigned int i, div; - - for (i = 0; i < clk_hw_get_num_parents(hw); i++) { - struct clk_hw *parent; - unsigned long parent_rate; - - parent = clk_hw_get_parent_by_index(hw, i); - if (!parent) - continue; - - parent_rate = clk_hw_get_rate(parent); - if (!parent_rate) - continue; - - for (div = 1; div < ISC_CLK_MAX_DIV + 2; div++) { - unsigned long rate; - int diff; - - rate = DIV_ROUND_CLOSEST(parent_rate, div); - diff = abs(req->rate - rate); - - if (best_diff < 0 || best_diff > diff) { - best_rate = rate; - best_diff = diff; - req->best_parent_rate = parent_rate; - req->best_parent_hw = parent; - } - - if (!best_diff || rate < req->rate) - break; - } - - if (!best_diff) - break; - } - - dev_dbg(isc_clk->dev, - "ISC CLK: %s, best_rate = %ld, parent clk: %s @ %ld\n", - __func__, best_rate, - __clk_get_name((req->best_parent_hw)->clk), - req->best_parent_rate); - - if (best_rate < 0) - return best_rate; - - req->rate = best_rate; - - return 0; -} - -static int isc_clk_set_parent(struct clk_hw *hw, u8 index) -{ - struct isc_clk *isc_clk = to_isc_clk(hw); - - if (index >= clk_hw_get_num_parents(hw)) - return -EINVAL; - - isc_clk->parent_id = index; - - return 0; -} - -static u8 isc_clk_get_parent(struct clk_hw *hw) -{ - struct isc_clk *isc_clk = to_isc_clk(hw); - - return isc_clk->parent_id; -} - -static int isc_clk_set_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long parent_rate) -{ - struct isc_clk *isc_clk = to_isc_clk(hw); - u32 div; - - if (!rate) - return -EINVAL; - - div = DIV_ROUND_CLOSEST(parent_rate, rate); - if (div > (ISC_CLK_MAX_DIV + 1) || !div) - return -EINVAL; - - isc_clk->div = div - 1; - - return 0; -} - -static const struct clk_ops isc_clk_ops = { - .prepare = isc_clk_prepare, - .unprepare = isc_clk_unprepare, - .enable = isc_clk_enable, - .disable = isc_clk_disable, - .is_enabled = isc_clk_is_enabled, - .recalc_rate = isc_clk_recalc_rate, - .determine_rate = isc_clk_determine_rate, - .set_parent = isc_clk_set_parent, - .get_parent = isc_clk_get_parent, - .set_rate = isc_clk_set_rate, -}; - -static int isc_clk_register(struct isc_device *isc, unsigned int id) -{ - struct regmap *regmap = isc->regmap; - struct device_node *np = isc->dev->of_node; - struct isc_clk *isc_clk; - struct clk_init_data init; - const char *clk_name = np->name; - const char *parent_names[3]; - int num_parents; - - if (id == ISC_ISPCK && !isc->ispck_required) - return 0; - - num_parents = of_clk_get_parent_count(np); - if (num_parents < 1 || num_parents > 3) - return -EINVAL; - - if (num_parents > 2 && id == ISC_ISPCK) - num_parents = 2; - - of_clk_parent_fill(np, parent_names, num_parents); - - if (id == ISC_MCK) - of_property_read_string(np, "clock-output-names", &clk_name); - else - clk_name = "isc-ispck"; - - init.parent_names = parent_names; - init.num_parents = num_parents; - init.name = clk_name; - init.ops = &isc_clk_ops; - init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; - - isc_clk = &isc->isc_clks[id]; - isc_clk->hw.init = &init; - isc_clk->regmap = regmap; - isc_clk->id = id; - isc_clk->dev = isc->dev; - spin_lock_init(&isc_clk->lock); - - isc_clk->clk = clk_register(isc->dev, &isc_clk->hw); - if (IS_ERR(isc_clk->clk)) { - dev_err(isc->dev, "%s: clock register fail\n", clk_name); - return PTR_ERR(isc_clk->clk); - } else if (id == ISC_MCK) - of_clk_add_provider(np, of_clk_src_simple_get, isc_clk->clk); - - return 0; -} - -int isc_clk_init(struct isc_device *isc) -{ - unsigned int i; - int ret; - - for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) - isc->isc_clks[i].clk = ERR_PTR(-EINVAL); - - for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) { - ret = isc_clk_register(isc, i); - if (ret) - return ret; - } - - return 0; -} -EXPORT_SYMBOL_GPL(isc_clk_init); - -void isc_clk_cleanup(struct isc_device *isc) -{ - unsigned int i; - - of_clk_del_provider(isc->dev->of_node); - - for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) { - struct isc_clk *isc_clk = &isc->isc_clks[i]; - - if (!IS_ERR(isc_clk->clk)) - clk_unregister(isc_clk->clk); - } -} -EXPORT_SYMBOL_GPL(isc_clk_cleanup); static int isc_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers, unsigned int *nplanes, diff --git a/drivers/media/platform/atmel/atmel-isc-clk.c b/drivers/media/platform/atmel/atmel-isc-clk.c new file mode 100644 index 000000000000..d650caade396 --- /dev/null +++ b/drivers/media/platform/atmel/atmel-isc-clk.c @@ -0,0 +1,316 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Microchip Image Sensor Controller (ISC) common clock driver setup + * + * Copyright (C) 2016-2019 Microchip Technology, Inc. + * + * Author: Songjun Wu + * Author: Eugen Hristev + * + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "atmel-isc-regs.h" +#include "atmel-isc.h" + +static int isc_wait_clk_stable(struct clk_hw *hw) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + struct regmap *regmap = isc_clk->regmap; + unsigned long timeout = jiffies + usecs_to_jiffies(1000); + unsigned int status; + + while (time_before(jiffies, timeout)) { + regmap_read(regmap, ISC_CLKSR, &status); + if (!(status & ISC_CLKSR_SIP)) + return 0; + + usleep_range(10, 250); + } + + return -ETIMEDOUT; +} + +static int isc_clk_prepare(struct clk_hw *hw) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + int ret; + + ret = pm_runtime_resume_and_get(isc_clk->dev); + if (ret < 0) + return ret; + + return isc_wait_clk_stable(hw); +} + +static void isc_clk_unprepare(struct clk_hw *hw) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + + isc_wait_clk_stable(hw); + + pm_runtime_put_sync(isc_clk->dev); +} + +static int isc_clk_enable(struct clk_hw *hw) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + u32 id = isc_clk->id; + struct regmap *regmap = isc_clk->regmap; + unsigned long flags; + unsigned int status; + + dev_dbg(isc_clk->dev, "ISC CLK: %s, id = %d, div = %d, parent id = %d\n", + __func__, id, isc_clk->div, isc_clk->parent_id); + + spin_lock_irqsave(&isc_clk->lock, flags); + regmap_update_bits(regmap, ISC_CLKCFG, + ISC_CLKCFG_DIV_MASK(id) | ISC_CLKCFG_SEL_MASK(id), + (isc_clk->div << ISC_CLKCFG_DIV_SHIFT(id)) | + (isc_clk->parent_id << ISC_CLKCFG_SEL_SHIFT(id))); + + regmap_write(regmap, ISC_CLKEN, ISC_CLK(id)); + spin_unlock_irqrestore(&isc_clk->lock, flags); + + regmap_read(regmap, ISC_CLKSR, &status); + if (status & ISC_CLK(id)) + return 0; + else + return -EINVAL; +} + +static void isc_clk_disable(struct clk_hw *hw) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + u32 id = isc_clk->id; + unsigned long flags; + + spin_lock_irqsave(&isc_clk->lock, flags); + regmap_write(isc_clk->regmap, ISC_CLKDIS, ISC_CLK(id)); + spin_unlock_irqrestore(&isc_clk->lock, flags); +} + +static int isc_clk_is_enabled(struct clk_hw *hw) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + u32 status; + int ret; + + ret = pm_runtime_resume_and_get(isc_clk->dev); + if (ret < 0) + return 0; + + regmap_read(isc_clk->regmap, ISC_CLKSR, &status); + + pm_runtime_put_sync(isc_clk->dev); + + return status & ISC_CLK(isc_clk->id) ? 1 : 0; +} + +static unsigned long +isc_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + + return DIV_ROUND_CLOSEST(parent_rate, isc_clk->div + 1); +} + +static int isc_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + long best_rate = -EINVAL; + int best_diff = -1; + unsigned int i, div; + + for (i = 0; i < clk_hw_get_num_parents(hw); i++) { + struct clk_hw *parent; + unsigned long parent_rate; + + parent = clk_hw_get_parent_by_index(hw, i); + if (!parent) + continue; + + parent_rate = clk_hw_get_rate(parent); + if (!parent_rate) + continue; + + for (div = 1; div < ISC_CLK_MAX_DIV + 2; div++) { + unsigned long rate; + int diff; + + rate = DIV_ROUND_CLOSEST(parent_rate, div); + diff = abs(req->rate - rate); + + if (best_diff < 0 || best_diff > diff) { + best_rate = rate; + best_diff = diff; + req->best_parent_rate = parent_rate; + req->best_parent_hw = parent; + } + + if (!best_diff || rate < req->rate) + break; + } + + if (!best_diff) + break; + } + + dev_dbg(isc_clk->dev, + "ISC CLK: %s, best_rate = %ld, parent clk: %s @ %ld\n", + __func__, best_rate, + __clk_get_name((req->best_parent_hw)->clk), + req->best_parent_rate); + + if (best_rate < 0) + return best_rate; + + req->rate = best_rate; + + return 0; +} + +static int isc_clk_set_parent(struct clk_hw *hw, u8 index) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + + if (index >= clk_hw_get_num_parents(hw)) + return -EINVAL; + + isc_clk->parent_id = index; + + return 0; +} + +static u8 isc_clk_get_parent(struct clk_hw *hw) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + + return isc_clk->parent_id; +} + +static int isc_clk_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + u32 div; + + if (!rate) + return -EINVAL; + + div = DIV_ROUND_CLOSEST(parent_rate, rate); + if (div > (ISC_CLK_MAX_DIV + 1) || !div) + return -EINVAL; + + isc_clk->div = div - 1; + + return 0; +} + +static const struct clk_ops isc_clk_ops = { + .prepare = isc_clk_prepare, + .unprepare = isc_clk_unprepare, + .enable = isc_clk_enable, + .disable = isc_clk_disable, + .is_enabled = isc_clk_is_enabled, + .recalc_rate = isc_clk_recalc_rate, + .determine_rate = isc_clk_determine_rate, + .set_parent = isc_clk_set_parent, + .get_parent = isc_clk_get_parent, + .set_rate = isc_clk_set_rate, +}; + +static int isc_clk_register(struct isc_device *isc, unsigned int id) +{ + struct regmap *regmap = isc->regmap; + struct device_node *np = isc->dev->of_node; + struct isc_clk *isc_clk; + struct clk_init_data init; + const char *clk_name = np->name; + const char *parent_names[3]; + int num_parents; + + if (id == ISC_ISPCK && !isc->ispck_required) + return 0; + + num_parents = of_clk_get_parent_count(np); + if (num_parents < 1 || num_parents > 3) + return -EINVAL; + + if (num_parents > 2 && id == ISC_ISPCK) + num_parents = 2; + + of_clk_parent_fill(np, parent_names, num_parents); + + if (id == ISC_MCK) + of_property_read_string(np, "clock-output-names", &clk_name); + else + clk_name = "isc-ispck"; + + init.parent_names = parent_names; + init.num_parents = num_parents; + init.name = clk_name; + init.ops = &isc_clk_ops; + init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; + + isc_clk = &isc->isc_clks[id]; + isc_clk->hw.init = &init; + isc_clk->regmap = regmap; + isc_clk->id = id; + isc_clk->dev = isc->dev; + spin_lock_init(&isc_clk->lock); + + isc_clk->clk = clk_register(isc->dev, &isc_clk->hw); + if (IS_ERR(isc_clk->clk)) { + dev_err(isc->dev, "%s: clock register fail\n", clk_name); + return PTR_ERR(isc_clk->clk); + } else if (id == ISC_MCK) { + of_clk_add_provider(np, of_clk_src_simple_get, isc_clk->clk); + } + + return 0; +} + +int isc_clk_init(struct isc_device *isc) +{ + unsigned int i; + int ret; + + for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) + isc->isc_clks[i].clk = ERR_PTR(-EINVAL); + + for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) { + ret = isc_clk_register(isc, i); + if (ret) + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(isc_clk_init); + +void isc_clk_cleanup(struct isc_device *isc) +{ + unsigned int i; + + of_clk_del_provider(isc->dev->of_node); + + for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) { + struct isc_clk *isc_clk = &isc->isc_clks[i]; + + if (!IS_ERR(isc_clk->clk)) + clk_unregister(isc_clk->clk); + } +} +EXPORT_SYMBOL_GPL(isc_clk_cleanup); From patchwork Fri Oct 22 07:52:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E83D0C433FE for ; Fri, 22 Oct 2021 07:54:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D53BC610EA for ; Fri, 22 Oct 2021 07:54:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232471AbhJVH4f (ORCPT ); Fri, 22 Oct 2021 03:56:35 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:55701 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232403AbhJVH4X (ORCPT ); Fri, 22 Oct 2021 03:56:23 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889246; x=1666425246; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6BOv8t6XXiIv6cggJ4nA8XW7gOqf6UXOIahF6kB4/v4=; b=qcCb2TQ+GWAp1s7NXwQ1ZxETtc48AwNJix+1DWNiuYCy5O8T9wvZq+l4 v95KWC6ovI0X/6m+uqnd3SRV5s6GR0wdCvP5O85ae7H7faEDBH4z3iFsF SgENHDyVkuwZgW90T9xx2jF2lDWHpoFiJDoO4rgzup78K4jJHHMBnFPjX 82HINy3JevuWiw9QR2KMjRs0NjerOE/V2k8qX5v4C4k0650IlDPDjwRIz U1NQpHFJCRV2vGIoLh3qFrJZyfgMc4Hh4JXB7Eu2nuxTquwCd9hgNNUAZ c4TzwX3Vl4d2nUvE9nRF413cHytzTfbeUoqkaJY8p8mxkTJVWOZKgHu7I g==; IronPort-SDR: OlS2KaopDJCX//rpSBhrtdHebAKks669tV0QOW9GSDw8ZNyqYaX4FgcXYlH5MLAidr6wKfSv2Y Ce7csUHW21y2p19P5hYthSO4OMnr7kyuepcQNSD933DTaB/s6hwt22EhpYYvnJunxhvKEcDmqn ZqleZ0L1Y4QqG7nNiURg5OqzbWTtS3hUtk8Lq7/3vmoRikTAnlQl4sxCXIcv5YDhivVA7hNlRC 8Wxg6w3aq50ZxULfoFQ2KVcNNCLuYyHpb5odyrLwnhLhFh1gVCJBMxl+vyh27f5vrSjcwrluea cdayXOuo0JebuajjX/Sz7nHR X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="149141186" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:54:05 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:54:05 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:54:02 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 06/21] media: atmel: atmel-isc: replace video device name with module name Date: Fri, 22 Oct 2021 10:52:32 +0300 Message-ID: <20211022075247.518880-7-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org To have consistency with future media controller development, replace the video device name with KBUILD_MODNAME. Signed-off-by: Eugen Hristev Reviewed-by: Jacopo Mondi --- drivers/media/platform/atmel/atmel-isc-base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index f532fd03e807..f3e89a892373 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -1887,7 +1887,7 @@ static int isc_async_complete(struct v4l2_async_notifier *notifier) } /* Register video device */ - strscpy(vdev->name, "microchip-isc", sizeof(vdev->name)); + strscpy(vdev->name, KBUILD_MODNAME, sizeof(vdev->name)); vdev->release = video_device_release_empty; vdev->fops = &isc_fops; vdev->ioctl_ops = &isc_ioctl_ops; From patchwork Fri Oct 22 07:52:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC792C433EF for ; Fri, 22 Oct 2021 07:54:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B122660FC3 for ; Fri, 22 Oct 2021 07:54:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232385AbhJVH4e (ORCPT ); Fri, 22 Oct 2021 03:56:34 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:22728 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232420AbhJVH41 (ORCPT ); Fri, 22 Oct 2021 03:56:27 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889250; x=1666425250; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zC/S5JoxrW9wPWNFUwF6hzlwSc6G6XtCvAP06ceXI7o=; b=f0f4Tnp5bwZ8Nfg32vs61ac8YRiTk+VMOleK6zmdTSGo0mQBfBrQngAQ x5q7MyyDC/zuu/1SLAA2mwam+tPI38LV+huYm1sZEth6D+8EU6HYP3WZ9 kHTrxpdvgyFlaVDty+t5ZSDDOOVOR9UqY6CMTk55j8kz1KiMjTDmHsR+P l2pd7sP9hV2x5TLTLwyhofZOdEvVsPphbOZS8DLfxz9FxgTHtBRI2BZM/ QGAEwMRkjbLm2ec/HBm49wKf9vx7+7NMVQFng57nwln7oZ5yRfvQUyQtL hpvwkNxf6+EaYZOVQfHGjBhZJde5rnuChcZVgMuTL4TBmI3OomRylTErX A==; IronPort-SDR: k8PMjQVSTLoRMhMIGkQr5BiLO9WMvyA0T9uIIfbKDXSMtl/rfZUs606yO0z6hOKDel3lXs7A2d WimB01KxiUtKnibyN5JLlIs7dKrP7mEB/WrXDCvkIVJeDIBl7p2pJVoKWr4PD1au3qstz6Ow2k 3db3UgGRZgWEgGT+IDlM/0taS1xsAjnvYHgFxe5dclQJjkVNS6DW3kK43Uwm5jCkc/+ixhDV/z BQIf6EDNY7uLV10nwIiZiX3tw+ZQUyabE3L+1WJv0v34JZpGjah88qRPMc2ICNg/sre92TjI4R ec/yvmxc/N84S3xq/rDp4Qog X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="73928984" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:54:09 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:54:09 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:54:06 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 07/21] media: atmel: atmel-sama7g5-isc: fix ispck leftover Date: Fri, 22 Oct 2021 10:52:33 +0300 Message-ID: <20211022075247.518880-8-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The ispck is not used for sama7g5 variant of the ISC. Calls to ispck have to be removed also from module insert/removal. Fixes: d7f26849ed7c ("media: atmel: fix the ispck initialization") Signed-off-by: Eugen Hristev Reviewed-by: Jacopo Mondi --- drivers/media/platform/atmel/atmel-sama7g5-isc.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-sama7g5-isc.c b/drivers/media/platform/atmel/atmel-sama7g5-isc.c index 9c05acafd072..6a5d3f7ce75e 100644 --- a/drivers/media/platform/atmel/atmel-sama7g5-isc.c +++ b/drivers/media/platform/atmel/atmel-sama7g5-isc.c @@ -555,7 +555,6 @@ static int microchip_xisc_remove(struct platform_device *pdev) v4l2_device_unregister(&isc->v4l2_dev); - clk_disable_unprepare(isc->ispck); clk_disable_unprepare(isc->hclock); isc_clk_cleanup(isc); @@ -567,7 +566,6 @@ static int __maybe_unused xisc_runtime_suspend(struct device *dev) { struct isc_device *isc = dev_get_drvdata(dev); - clk_disable_unprepare(isc->ispck); clk_disable_unprepare(isc->hclock); return 0; @@ -582,10 +580,6 @@ static int __maybe_unused xisc_runtime_resume(struct device *dev) if (ret) return ret; - ret = clk_prepare_enable(isc->ispck); - if (ret) - clk_disable_unprepare(isc->hclock); - return ret; } From patchwork Fri Oct 22 07:52:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577303 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86722C433FE for ; Fri, 22 Oct 2021 07:54:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 72FC1610EA for ; Fri, 22 Oct 2021 07:54:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232452AbhJVH4d (ORCPT ); Fri, 22 Oct 2021 03:56:33 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:55701 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232445AbhJVH4b (ORCPT ); Fri, 22 Oct 2021 03:56:31 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889254; x=1666425254; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Gcb+lnpjPb51M6Oj/PPqswwgdjHYl153vJF1lo5rimE=; b=rlP71XSEiNPbp1yGWkJriJms5LKiq1SW+M6JLLUAbzp36vh9jxLTsY/7 79zSJYU/c9KgIbtgJ/rtNTdJ9zyRkmVbCoyHbS6+EcM6dghZHntoEfweg JP/xxEDqw39Cyli4U2MfYgrNA+IKS/+w0Jpx/6rh0QoYEdaDXah8jUkIH cd/5+yKuV1HMb2g+75WwtJHV+h/OD49CyZXhhEh5GYHtSk30k6a3F6GX1 k6344Iil1Y4U1A+WDDJAaEmlFg9cdiLcxtc8paJOzqwSzRtDHjfmcEakL AnPVln/RZJWR8PcLdv/EH4J/xJ3JsL99lq35r3I+ki1enk3z/fx57tadM Q==; IronPort-SDR: biDkLlip17oxnkF2jKE70Mfk0IlDOq8R3NLj8ilE2cQRdNS4Bq24W0uxAPUCL9psuWLR3458Rt D7QrP4ljohElJa79uRoZFTd1gCA/aWlIIpBRQfLfGJDsaS645SStzD/KGCvW1na04dbClcs6s4 Lplk5sqyvn5xWtHNgNiFJNMRjsFlEmyyUb0tCWz5tc6Y+swLsA7TAYPvErNgNOVhJ4+W4lYo1J P52aT3d3aadhHBz8FWi3E8aWEpuPEMXhFoahW7+DQaMzHra3paIYm5MTFdjE+6JKhFFZ2k16Pc rbbL4+SX16zZ1FBKsuzx9DwM X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="149141211" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:54:13 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:54:13 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:54:09 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 08/21] media: atmel: atmel-isc-base: use streaming status when queueing buffers Date: Fri, 22 Oct 2021 10:52:34 +0300 Message-ID: <20211022075247.518880-9-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org During experiments with libcamera, it looks like vb2_is_streaming returns true before our start streaming is called. Order of operations is streamon -> queue -> start_streaming ISC would have started the DMA immediately when a buffer is being added to the vbqueue if the queue is streaming. It is more safe to start the DMA after the start streaming of the driver is called. Thus, even if vb2queue is streaming, add the buffer to the dma queue of the driver instead of actually starting the DMA process, if the start streaming has not been called yet. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index f3e89a892373..6f14cc549543 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -442,12 +442,14 @@ static void isc_buffer_queue(struct vb2_buffer *vb) unsigned long flags; spin_lock_irqsave(&isc->dma_queue_lock, flags); - if (!isc->cur_frm && list_empty(&isc->dma_queue) && - vb2_is_streaming(vb->vb2_queue)) { + + if (!isc->cur_frm && list_empty(&isc->dma_queue) && !isc->stop) { isc->cur_frm = buf; isc_start_dma(isc); - } else + } else { list_add_tail(&buf->list, &isc->dma_queue); + } + spin_unlock_irqrestore(&isc->dma_queue_lock, flags); } @@ -1015,7 +1017,7 @@ static int isc_s_fmt_vid_cap(struct file *file, void *priv, { struct isc_device *isc = video_drvdata(file); - if (vb2_is_streaming(&isc->vb2_vidq)) + if (!isc->stop) return -EBUSY; return isc_set_fmt(isc, f); @@ -1537,7 +1539,7 @@ static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl) isc_update_awb_ctrls(isc); - if (vb2_is_streaming(&isc->vb2_vidq)) { + if (!isc->stop) { /* * If we are streaming, we can update profile to * have the new settings in place. @@ -1553,8 +1555,7 @@ static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl) } /* if we have autowhitebalance on, start histogram procedure */ - if (ctrls->awb == ISC_WB_AUTO && - vb2_is_streaming(&isc->vb2_vidq) && + if (ctrls->awb == ISC_WB_AUTO && !isc->stop && ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) isc_set_histogram(isc, true); @@ -1830,6 +1831,8 @@ static int isc_async_complete(struct v4l2_async_notifier *notifier) struct vb2_queue *q = &isc->vb2_vidq; int ret = 0; + isc->stop = true; + INIT_WORK(&isc->awb_work, isc_awb_work); ret = v4l2_device_register_subdev_nodes(&isc->v4l2_dev); From patchwork Fri Oct 22 07:52:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3677EC433FE for ; Fri, 22 Oct 2021 07:54:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2058A6115B for ; Fri, 22 Oct 2021 07:54:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232486AbhJVH4i (ORCPT ); Fri, 22 Oct 2021 03:56:38 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:55701 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232467AbhJVH4e (ORCPT ); Fri, 22 Oct 2021 03:56:34 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889257; x=1666425257; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DbOQBIZ8qsZGKgcWsohY/wLUvD2T4nyMI7qgesmvHIQ=; b=eq8Z9gmeAwK+zP0Vs33xVAVfsHGcxZzKQw879r9vDQdqrm6flQGj23O9 yadkh4/+2m6I/rhRRPAIF8mayjLf5ada8oFOQRWEUQN8aPCuTuentS6jp xklqSBmSBUF51fYn6ReL4Oz7zQryR1E5gNE7M5mNQGn5D1IGRtowqc/T5 rRhiuh588oHkMXpAiqpe8StRmbvBV5ls25g+SaxFOt0QH2T2qTMdmxf5m yuKS/nnlJtJw2BwwiYM0lOZZH+4mHZ3TC9AlOg+rDNQSb5WRBQDgN44HM 6DRExB0lfO8HZ3i3Ggo+ISwX4xYLQ31BlOUIjV7QyGzs7HBP6sCOdu3j8 A==; IronPort-SDR: o7hltVifFjqISO99iUYKb5mEi5BOqiirlMBNhcr15YZhId2kUAOIA03nbPwuxvA3HME4eE29vA 82/yV3nXi6K626/ecxGfNauKXWptkaQ5FsxwVjZAtg9wsrp1TCwuDyn4s85cJWFuVRpuyx3rbY SGTWZL9Euk/++aH/laJDmgJLKd4JVvCU6e4GKDo+M35cdNatcTQQePXfDoOZaqphDrV7ZhTE7/ 6i1BfDa1NZRm7+4fgds0Dl3w+/eJ0mocweLC3Z2oM0LFc7GvdzTFsxa0bP9O1TV98UhkaAVDb/ 8QqCjFgqHFnn896+5eu1ZjSi X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="149141228" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:54:17 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:54:16 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:54:13 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 09/21] media: atmel: atmel-isc-base: remove frameintervals VIDIOC Date: Fri, 22 Oct 2021 10:52:35 +0300 Message-ID: <20211022075247.518880-10-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org VIDIOC_ENUM_FRAMEINTERVALS is not recommended for a top video driver. The frame rate is defined by the sensor subdevice, thus it can be queried directly by anyone interested in the frame intervals. Signed-off-by: Eugen Hristev Reviewed-by: Jacopo Mondi --- drivers/media/platform/atmel/atmel-isc-base.c | 37 ------------------- 1 file changed, 37 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 6f14cc549543..8537ad73d160 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -1108,42 +1108,6 @@ static int isc_enum_framesizes(struct file *file, void *fh, return 0; } -static int isc_enum_frameintervals(struct file *file, void *fh, - struct v4l2_frmivalenum *fival) -{ - struct isc_device *isc = video_drvdata(file); - struct v4l2_subdev_frame_interval_enum fie = { - .code = isc->config.sd_format->mbus_code, - .index = fival->index, - .width = fival->width, - .height = fival->height, - .which = V4L2_SUBDEV_FORMAT_ACTIVE, - }; - int ret = -EINVAL; - unsigned int i; - - for (i = 0; i < isc->num_user_formats; i++) - if (isc->user_formats[i]->fourcc == fival->pixel_format) - ret = 0; - - for (i = 0; i < isc->controller_formats_size; i++) - if (isc->controller_formats[i].fourcc == fival->pixel_format) - ret = 0; - - if (ret) - return ret; - - ret = v4l2_subdev_call(isc->current_subdev->sd, pad, - enum_frame_interval, NULL, &fie); - if (ret) - return ret; - - fival->type = V4L2_FRMIVAL_TYPE_DISCRETE; - fival->discrete = fie.interval; - - return 0; -} - static const struct v4l2_ioctl_ops isc_ioctl_ops = { .vidioc_querycap = isc_querycap, .vidioc_enum_fmt_vid_cap = isc_enum_fmt_vid_cap, @@ -1168,7 +1132,6 @@ static const struct v4l2_ioctl_ops isc_ioctl_ops = { .vidioc_g_parm = isc_g_parm, .vidioc_s_parm = isc_s_parm, .vidioc_enum_framesizes = isc_enum_framesizes, - .vidioc_enum_frameintervals = isc_enum_frameintervals, .vidioc_log_status = v4l2_ctrl_log_status, .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, From patchwork Fri Oct 22 07:52:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577311 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33707C433EF for ; Fri, 22 Oct 2021 07:54:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 205CB60231 for ; Fri, 22 Oct 2021 07:54:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232511AbhJVH4n (ORCPT ); Fri, 22 Oct 2021 03:56:43 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:55701 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232488AbhJVH4i (ORCPT ); Fri, 22 Oct 2021 03:56:38 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889261; x=1666425261; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=REZFzzAUOglb7K1RDabqAKzlGAFNSmzLTlTDD6DNu20=; b=GASC9XHlsZALlmo2eq4DitIfiiuBBG0KMnc75tTcELmJNVC+6ZOguZuD X0kq91/jf2CnXjV4LEDcqDms9OkxZZLFzgOS0Vr4UeX22nnmSLEgf6snV 7acpISCzLbQ/tG9V+/XRYKLJ5wpy+Pk6A3VJJa3myxo1uioFw3rrDwsde 46XY5iwItbjUzMfR6N7nYkhXlUKYoaHf+EgE9IwANkOYhCM3YBF8EK0Cp Zz+uxEDsp0c7zgWb6ZMs0up5pK4GUmW/6qJsIEUt75u+/ixONlDuLlvnq df/e/zQvN2FwN7jfHw7kxBFEL09WnOmlb2Pc1OZmjZO138TSRXAD2gpSM w==; IronPort-SDR: AjDl8UDo1XWgESJKb05p6S4cISZnEXYMUMtDLVbDmrgHAhSxatZEJ/AAUqCdRoxUnK4LRBDyaA eoMdA4RN09/5vCcaiS500z7NNdifSAGKq6CxLfJgmUiJg9L6SO1Yuw7w/NUMR1qS0WzO8T8D6r xmvaaT1DzhtxQMx7V8hee7qyy34jxaBJ2FCt4x1qdTFplJv8p0ekGuRkth6egKBgR9GfjYEms5 hMeOQTQvd0DgpMWGhDTOLOMLiDuR0A8MyMCtLwtZ3F7AOVa7dwUmSfRrG+ZvnFjSV6cG0xqgY7 v4h/tw+ZbjxjIJcPEljdtbVl X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="149141234" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:54:20 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:54:20 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:54:17 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 10/21] media: atmel: atmel-isc-base: report frame sizes as full supported range Date: Fri, 22 Oct 2021 10:52:36 +0300 Message-ID: <20211022075247.518880-11-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The ISC supports a full broad range of frame sizes. Until now, the subdevice was queried for possible frame sizes and these were reported to the user space. However, the ISC should not care about which frame sizes the subdev supports, as long as this frame size is supported. Thus, report a continuous range from smallest frame size up to the max resolution. Signed-off-by: Eugen Hristev Reviewed-by: Jacopo Mondi --- drivers/media/platform/atmel/atmel-isc-base.c | 22 +++++++++---------- 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 8537ad73d160..2dd2511c7be1 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -1077,14 +1077,12 @@ static int isc_enum_framesizes(struct file *file, void *fh, struct v4l2_frmsizeenum *fsize) { struct isc_device *isc = video_drvdata(file); - struct v4l2_subdev_frame_size_enum fse = { - .code = isc->config.sd_format->mbus_code, - .index = fsize->index, - .which = V4L2_SUBDEV_FORMAT_ACTIVE, - }; int ret = -EINVAL; int i; + if (fsize->index) + return -EINVAL; + for (i = 0; i < isc->num_user_formats; i++) if (isc->user_formats[i]->fourcc == fsize->pixel_format) ret = 0; @@ -1096,14 +1094,14 @@ static int isc_enum_framesizes(struct file *file, void *fh, if (ret) return ret; - ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size, - NULL, &fse); - if (ret) - return ret; + fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; - fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; - fsize->discrete.width = fse.max_width; - fsize->discrete.height = fse.max_height; + fsize->stepwise.min_width = 16; + fsize->stepwise.max_width = isc->max_width; + fsize->stepwise.min_height = 16; + fsize->stepwise.max_height = isc->max_height; + fsize->stepwise.step_width = 1; + fsize->stepwise.step_height = 1; return 0; } From patchwork Fri Oct 22 07:52:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22724C433F5 for ; Fri, 22 Oct 2021 07:54:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0AD7D6112F for ; Fri, 22 Oct 2021 07:54:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232502AbhJVH4r (ORCPT ); Fri, 22 Oct 2021 03:56:47 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:55701 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232460AbhJVH4m (ORCPT ); Fri, 22 Oct 2021 03:56:42 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889265; x=1666425265; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7uj+t4rQfdpIRquvDPiGpVBIISkD5ZZAW2R+pnACNe8=; b=x3Kpx3GdN7ZnyaE+cH6jj5x+B0tjoOJCtD1IRw+qZzlpWwdiHa6diX8l k2A1uHmRxw/XyMwADc6X6kjxv0W49wLhmWvB+YNz4W3UykfIkl/8U4iKi td345p7xteVciRFJ7vM+fNo+tYY+4pxn7HEaZ8koHLTBebMd07J6dIOZg p8PrhwAU6UKz/7VLb1Zw4gKfKOO3i6I2mTudcks1stbxPL6pY9fJLPsCp mAHeUx0O+N7XWSl0po5eEGGlD6gGJWIzCfIzvH5SNGVYdX4iPpfE9sMbL VJ/8tXkv4ZdLe6KRA3s6rnA2e2oHfTdkBYIwGTcLlwjZHRH3/Ke+A0PSg w==; IronPort-SDR: CETVNPj6N1MOxLiGeHvXinNHvxsJWWfqZEjFkysTBKXDN3szl3JHaLZkM/tbtEepa0mDWVjAsc SdoBUDtpPKRomly2WyKL7+PMjV+HRFRihfpTqonzO8UGW7CqgBTQckMDzPaVyMXK0nhAV2Rx5Z tmS5r/A7K4NQfq0iwCwiSpkFGKuxbGabyt2yiGjBKG6c0UFc5twbXF7HoGEpGi0xDQVCKKOFNX 0TnpHHI1UeWQ/boMgCJloqyG1iENjQ7a33kUCP4lgqWD5itCbKJMSJJgV8eITXsz7jZy7NDrAX e4DQ86/7OgfayC0LkUTUp0Fz X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="149141246" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:54:25 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:54:24 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:54:21 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 11/21] media: atmel: atmel-isc-base: implement mbus_code support in enumfmt Date: Fri, 22 Oct 2021 10:52:37 +0300 Message-ID: <20211022075247.518880-12-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org If enumfmt is called with an mbus_code, the enumfmt handler should only return the formats that are supported for this mbus_code. To make it more easy to understand the formats, changed the report order to report first the native formats, and after that the formats that the ISC can convert to. Signed-off-by: Eugen Hristev Reviewed-by: Jacopo Mondi --- drivers/media/platform/atmel/atmel-isc-base.c | 51 ++++++++++++++++--- 1 file changed, 43 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 2dd2511c7be1..1f7fbe5e4d79 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -499,21 +499,56 @@ static int isc_enum_fmt_vid_cap(struct file *file, void *priv, u32 index = f->index; u32 i, supported_index; - if (index < isc->controller_formats_size) { - f->pixelformat = isc->controller_formats[index].fourcc; - return 0; + supported_index = 0; + + for (i = 0; i < isc->formats_list_size; i++) { + if (!isc->formats_list[i].sd_support) + continue; + /* + * If specific mbus_code is requested, provide only + * supported formats with this mbus code + */ + if (f->mbus_code && f->mbus_code != + isc->formats_list[i].mbus_code) + continue; + if (supported_index == index) { + f->pixelformat = isc->formats_list[i].fourcc; + return 0; + } + supported_index++; } - index -= isc->controller_formats_size; + /* + * If the sensor does not support this mbus_code whatsoever, + * there is no reason to advertise any of our output formats + */ + if (supported_index == 0) + return -EINVAL; + + /* + * If the sensor uses a format that is not raw, then we cannot + * convert it to any of the formats that we usually can with a + * RAW sensor. Thus, do not advertise them. + */ + if (!isc->config.sd_format || + !ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) + return -EINVAL; + /* + * Iterate again through the formats that we can convert to. + * However, to avoid duplicates, skip the formats that + * the sensor already supports directly + */ + index -= supported_index; supported_index = 0; - for (i = 0; i < isc->formats_list_size; i++) { - if (!ISC_IS_FORMAT_RAW(isc->formats_list[i].mbus_code) || - !isc->formats_list[i].sd_support) + for (i = 0; i < isc->controller_formats_size; i++) { + /* if this format is already supported by sensor, skip it */ + if (find_format_by_fourcc(isc, isc->controller_formats[i].fourcc)) continue; if (supported_index == index) { - f->pixelformat = isc->formats_list[i].fourcc; + f->pixelformat = + isc->controller_formats[i].fourcc; return 0; } supported_index++; From patchwork Fri Oct 22 07:52:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2854C433F5 for ; Fri, 22 Oct 2021 07:54:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 93BFF60FC1 for ; Fri, 22 Oct 2021 07:54:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232533AbhJVH4x (ORCPT ); Fri, 22 Oct 2021 03:56:53 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:17436 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232476AbhJVH4q (ORCPT ); Fri, 22 Oct 2021 03:56:46 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889270; x=1666425270; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YophVPqSKDOhZAeaX0zq7lMCw+/S9NtNX5xE+8ZrvMo=; b=xRqGcM8W21xQUKcqP4FpGgC+gLwJyDVB+5wu95sfONT8qN6Fy57xl6Uo jbVJLGdwdb7NirNoduk9aest0YiQzFMZYKWkZee8fiPcdM/AKLcoaffLR 8qBsWMT9w/K9k670r1+R4TVucymTqGPaAvjlGj6wcApCQcl4QBSf23Ut+ XrbGycLc88gkdiMbjLnvVPu8xYKTgK/N9hUYyQm0Yp14ZnDd+6uT+xf/F BUiFoShXj24idJw8Tj3ww56A6dBbde4qRMYmKMDRC3UW/ibqqSIviK9X0 OKuWBvvqz46FpzvhNMNac/8PkW/oTO6VAxafLlMECgkgx5GkaPd21ap+i A==; IronPort-SDR: xtWR+VxUGXkaS/4HzDYnrNhrrEoXi/BI5Vb1eaBgimoIz+wrvPragc6+S75PGg/MoaIld1kzkB 5sJlNyWo+KlmYzxTctVR9D4MnBK07ezy/kKM8cRYgb6HLVxT/UhQDXPIL5Ev7bUd2IvX742m7S kVXwbaZ1YpyNCfNGNav4i9tMFj9y3DOsF6YZSgU1JaAWiyC/zEDbNf7JSCUjEOgEPN6sXYWhj+ tZLEr45+L09XvLy1lqzJMsIjbl5oauPt4+EpsRQeNpJFRJkcWe+s9+xWZXnk10qVPH0Uw4FRHx Cm/Ouag6WGAQBuW2UEPfE4kH X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="136538099" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:54:29 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:54:28 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:54:25 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 12/21] media: atmel: atmel-isc-base: fix bytesperline value for planar formats Date: Fri, 22 Oct 2021 10:52:38 +0300 Message-ID: <20211022075247.518880-13-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The bytesperline field of the pixfmt should be only for the first plane in case of planar formats like YUV420 or YUV422. The bytesperline is used by the driver to compute the framesize. We have to report a different bpp (bytes per pixel) to v4l2 in bytesperline than the actual bpp. For example for YUV420, the real bpp is 12, but the first plane has only 8 bpp. Thus we report a bytesperline 8*width instead of 12*width. However, for real framezise we have to compute 12*width*height. Hence added a new variable to hold this information and to correctly compute the frame size. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 19 +++++++++++++++++-- drivers/media/platform/atmel/atmel-isc.h | 4 ++++ 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 1f7fbe5e4d79..f782a9c0c07d 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -655,6 +655,7 @@ static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump) isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8; isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; isc->try_config.bpp = 8; + isc->try_config.bpp_v4l2 = 8; break; case V4L2_PIX_FMT_SBGGR10: case V4L2_PIX_FMT_SGBRG10: @@ -664,6 +665,7 @@ static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump) isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 16; break; case V4L2_PIX_FMT_SBGGR12: case V4L2_PIX_FMT_SGBRG12: @@ -673,24 +675,28 @@ static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump) isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 16; break; case V4L2_PIX_FMT_RGB565: isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_RGB565; isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 16; break; case V4L2_PIX_FMT_ARGB444: isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB444; isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 16; break; case V4L2_PIX_FMT_ARGB555: isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB555; isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 16; break; case V4L2_PIX_FMT_ABGR32: case V4L2_PIX_FMT_XBGR32: @@ -698,42 +704,49 @@ static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump) isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; isc->try_config.bpp = 32; + isc->try_config.bpp_v4l2 = 32; break; case V4L2_PIX_FMT_YUV420: isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC; isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC420P; isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR; isc->try_config.bpp = 12; + isc->try_config.bpp_v4l2 = 8; /* only first plane */ break; case V4L2_PIX_FMT_YUV422P: isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC; isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC422P; isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR; isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 8; /* only first plane */ break; case V4L2_PIX_FMT_YUYV: isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV; isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 16; break; case V4L2_PIX_FMT_UYVY: isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY; isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 16; break; case V4L2_PIX_FMT_VYUY: isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY; isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 16; break; case V4L2_PIX_FMT_GREY: isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY8; isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8; isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; isc->try_config.bpp = 8; + isc->try_config.bpp_v4l2 = 8; break; case V4L2_PIX_FMT_Y16: isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH; @@ -743,6 +756,7 @@ static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump) isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 16; break; default: return -EINVAL; @@ -991,8 +1005,9 @@ static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f, pixfmt->height = isc->max_height; pixfmt->field = V4L2_FIELD_NONE; - pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3; - pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height; + pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp_v4l2) >> 3; + pixfmt->sizeimage = ((pixfmt->width * isc->try_config.bpp) >> 3) * + pixfmt->height; if (code) *code = mbus_code; diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index 2bfcb135ef13..dd45e9ca22a9 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -95,6 +95,9 @@ struct isc_format { configuration. * @fourcc: Fourcc code for this format. * @bpp: Bytes per pixel in the current format. + * @bpp_v4l2: Bytes per pixel in the current format, for v4l2. + This differs from 'bpp' in the sense that in planar + formats, it refers only to the first plane. * @rlp_cfg_mode: Configuration of the RLP (rounding, limiting packaging) * @dcfg_imode: Configuration of the input of the DMA module * @dctrl_dview: Configuration of the output of the DMA module @@ -105,6 +108,7 @@ struct fmt_config { u32 fourcc; u8 bpp; + u8 bpp_v4l2; u32 rlp_cfg_mode; u32 dcfg_imode; From patchwork Fri Oct 22 07:52:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3AA9C433EF for ; Fri, 22 Oct 2021 07:54:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C19116112F for ; Fri, 22 Oct 2021 07:54:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232515AbhJVH4z (ORCPT ); Fri, 22 Oct 2021 03:56:55 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:55701 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232521AbhJVH4t (ORCPT ); Fri, 22 Oct 2021 03:56:49 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889272; x=1666425272; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HpLWhRHVJkMruImhcz3J99RgIOqwGY9UOr7XCdVVWF8=; b=lkHlbIKSU7qzGyKDr8m0XmjAdqpgq4/v9LDJxS97CAzpb0CCm8X3K8NG f0dy6jKdW+IFV93CQoc7K5HhpliFSdVQDtxezOx7HjWyWGHKKGyVmuHBM NHhBPRIXvH4Zjp7Hx4xuMkiY7s2r3rJFTMN/FbLHDUx03hKtod9Lyn9xh EEOc8ue/JJdTybg8jEXS60kAqB2X3ET/KM58d/Uj4HeUw9EmXAOEVcNZE d8BCpt/jX5S2mvdFOeFmBt7ih1xqQm1KGxOgLP21nflIdu5ZGH3UsA+Vl jbj2C3gySMDk4ppct2H+WAT0At7ItE7h3jr4ByZZnX1p0DFVbt0Ih01sY A==; IronPort-SDR: d7sz6h8s3+cDiY2A2PBWaMWxq6uMS5fPnGfLfxMonKZHFZAVzm+NAPuBqgmbFhj7s/U8Zx8WDu pIV7B6bK+9ncuhFWAf7csqcowqOfoZaqAu38axwIaSXi6KxaGe51R5wguB79yFWHcoSaP7BvWz AKnw2WDhTnEkb2SjKYwfX/9cWJhA5PE8Z4h3R4o0WMo/QhkNHiSUtZMfBuifUMQTUaLNqOLeKT PyYSbAvvrgQcnryrESCxfELIzTzcaz9N+xcsx3Rw4Jwkoqmk+ExI6/h4dQNrYNkgE8AEME3oZq 3H5CZYgpIpYcScyIMhHap/5M X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="149141258" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:54:32 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:54:32 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:54:29 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 13/21] MAINTAINERS: atmel-isc: add new file atmel-isc-mc.c Date: Fri, 22 Oct 2021 10:52:39 +0300 Message-ID: <20211022075247.518880-14-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add new file atmel-isc-mc.c to MAINTAINERS entry. Signed-off-by: Eugen Hristev --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index e151716c8d1e..228363d2afe7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12280,6 +12280,7 @@ F: Documentation/devicetree/bindings/media/atmel,isc.yaml F: Documentation/devicetree/bindings/media/microchip,xisc.yaml F: drivers/media/platform/atmel/atmel-isc-base.c F: drivers/media/platform/atmel/atmel-isc-clk.c +F: drivers/media/platform/atmel/atmel-isc-mc.c F: drivers/media/platform/atmel/atmel-isc-regs.h F: drivers/media/platform/atmel/atmel-isc.h F: drivers/media/platform/atmel/atmel-sama5d2-isc.c From patchwork Fri Oct 22 07:52:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8050C433FE for ; Fri, 22 Oct 2021 07:54:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9071D60231 for ; Fri, 22 Oct 2021 07:54:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232564AbhJVH47 (ORCPT ); Fri, 22 Oct 2021 03:56:59 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:17436 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232021AbhJVH4x (ORCPT ); Fri, 22 Oct 2021 03:56:53 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889276; x=1666425276; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ixD6BMudf6IYcKYrLkBMIKtHCcNCXzIxfXYr4uC2V80=; b=HHJYS5xRTESoDxhPHgFfRtn3WhRLtUcHIW0H5AUgpyCheJN/X+WRUzvy qUQMPKcLoVr4QpKwa2CdpYAGOtwTHqS+apkbTpW+AsRGFq513gqe+iGzQ hHnYJPOxm1SpixcuBnI0gpMNmXBB1S/ITZvFhClIZSofmL56SZ0BMccY3 NeH2Hfe+k470h+Ke3PsqG7a+v4U2sjhXXld7zaEbjKqOtF9aOD+QYKl4q HLgP7Nz9ebtJbBFm3QupSFtDjEEc5cDOOdO2Tipn808UB+4bPaaONVGOD SUfLUry6XLF0UrYMMZ5NHV7j3mgy0Z4Hf3eItDe6UkCWd9rhpSnnb5y7r Q==; IronPort-SDR: P0Ti7Dz2K/kJGe2hJuwL1ipx4Ctd0Q18SI2YCPAlG4w40z2ShnC2A5sCvRI9oJ9TO1LyyRg5aO O1PyaIsz6FlbzJJuNn9hJi2nyHrz93UZBOaUy9bcCIvC2N3wvMe5E/QPEaBigVr5jhIVvVakhD asZWGU6bg4v2UgIu9F9UuGOiZx5bH0x/wX74kJKz7E4FUrXi0ELmKl7G1QUV5ZKZnZaLJS81/c aLhVorfuWI+VNjIBXSBVy+GGH3RGqRSOhNQ43Xu0aajT9yidYzUgBIoY7OmUjPMzgLpIYFzri6 PjuXKByd8qyHAen2y3XQJ4L9 X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="136538115" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:54:35 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:54:34 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:54:32 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 14/21] media: atmel: atmel-isc: implement media controller Date: Fri, 22 Oct 2021 10:52:40 +0300 Message-ID: <20211022075247.518880-15-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Implement the support for media-controller. This means that the capabilities of the driver have changed and now it also advertises the IO_MC . The driver will register it's media device, and add the video entity to this media device. The subdevices are registered to the same media device. The ISC will have a base entity which is auto-detected as atmel_isc_base. It will also register a subdevice that allows cropping of the incoming frame to the maximum frame size supported by the ISC. The ISC will create a link between the subdevice that is asynchronously registered and the atmel_isc_scaler entity. Then, the atmel_isc_scaler and atmel_isc_base are connected through another link. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/Makefile | 2 +- drivers/media/platform/atmel/atmel-isc-base.c | 20 +- drivers/media/platform/atmel/atmel-isc-mc.c | 235 ++++++++++++++++++ drivers/media/platform/atmel/atmel-isc.h | 28 +++ .../media/platform/atmel/atmel-sama5d2-isc.c | 14 +- .../media/platform/atmel/atmel-sama7g5-isc.c | 12 +- 6 files changed, 306 insertions(+), 5 deletions(-) create mode 100644 drivers/media/platform/atmel/atmel-isc-mc.c diff --git a/drivers/media/platform/atmel/Makefile b/drivers/media/platform/atmel/Makefile index 1f6fe7427769..90220eaefa20 100644 --- a/drivers/media/platform/atmel/Makefile +++ b/drivers/media/platform/atmel/Makefile @@ -3,7 +3,7 @@ atmel-isc-objs = atmel-sama5d2-isc.o atmel-xisc-objs = atmel-sama7g5-isc.o obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o -obj-$(CONFIG_VIDEO_ATMEL_ISC_BASE) += atmel-isc-base.o atmel-isc-clk.o +obj-$(CONFIG_VIDEO_ATMEL_ISC_BASE) += atmel-isc-base.o atmel-isc-clk.o atmel-isc-mc.o obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel-isc.o obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel-xisc.o obj-$(CONFIG_VIDEO_MICROCHIP_CSI2DC) += microchip-csi2dc.o diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index f782a9c0c07d..a0e4bc75d1a2 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -1727,6 +1727,7 @@ static int isc_async_bound(struct v4l2_async_notifier *notifier, struct isc_device, v4l2_dev); struct isc_subdev_entity *subdev_entity = container_of(notifier, struct isc_subdev_entity, notifier); + int pad; if (video_is_registered(&isc->video_dev)) { v4l2_err(&isc->v4l2_dev, "only supports one sub-device.\n"); @@ -1735,6 +1736,16 @@ static int isc_async_bound(struct v4l2_async_notifier *notifier, subdev_entity->sd = subdev; + pad = media_entity_get_fwnode_pad(&subdev->entity, asd->match.fwnode, + MEDIA_PAD_FL_SOURCE); + if (pad < 0) { + v4l2_err(&isc->v4l2_dev, "failed to find pad for %s\n", + subdev->name); + return pad; + } + + isc->remote_pad = pad; + return 0; } @@ -1910,7 +1921,8 @@ static int isc_async_complete(struct v4l2_async_notifier *notifier) vdev->queue = q; vdev->lock = &isc->lock; vdev->ctrl_handler = &isc->ctrls.handler; - vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE; + vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE | + V4L2_CAP_IO_MC; video_set_drvdata(vdev, isc); ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); @@ -1920,8 +1932,14 @@ static int isc_async_complete(struct v4l2_async_notifier *notifier) goto isc_async_complete_err; } + ret = isc_mc_register(isc); + if (ret < 0) + goto isc_async_complete_unregister_device; return 0; +isc_async_complete_unregister_device: + video_unregister_device(vdev); + isc_async_complete_err: mutex_destroy(&isc->lock); return ret; diff --git a/drivers/media/platform/atmel/atmel-isc-mc.c b/drivers/media/platform/atmel/atmel-isc-mc.c new file mode 100644 index 000000000000..fe9ebb46e270 --- /dev/null +++ b/drivers/media/platform/atmel/atmel-isc-mc.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Microchip Image Sensor Controller (ISC) Media Controller support + * + * Copyright (C) 2021 Microchip Technology, Inc. + * + * Author: Eugen Hristev + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "atmel-isc-regs.h" +#include "atmel-isc.h" + +static const struct media_device_ops isc_media_ops = { +}; + +static int isc_scaler_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + struct isc_device *isc = container_of(sd, struct isc_device, scaler_sd); + + format->format = isc->scaler_format; + + if (format->pad == 1) { + if (format->format.height > isc->max_height) + format->format.height = isc->max_height; + if (format->format.width > isc->max_width) + format->format.width = isc->max_width; + } + + return 0; +} + +static int isc_scaler_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *req_fmt) +{ + struct isc_device *isc = container_of(sd, struct isc_device, scaler_sd); + + if (req_fmt->pad == 1) { + if (req_fmt->format.height > isc->max_height) + req_fmt->format.height = isc->max_height; + if (req_fmt->format.width > isc->max_width) + req_fmt->format.width = isc->max_width; + } + + isc->scaler_format = req_fmt->format; + + return 0; +} + +static int isc_scaler_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct isc_device *isc = container_of(sd, struct isc_device, scaler_sd); + int supported_index = 0; + int i; + + for (i = 0; i < isc->formats_list_size; i++) { + if (!isc->formats_list[i].sd_support) + continue; + if (supported_index == code->index) { + code->code = isc->formats_list[i].mbus_code; + return 0; + } + supported_index++; + } + + return -EINVAL; +} + +static int isc_scaler_g_sel(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_selection *sel) +{ + struct isc_device *isc = container_of(sd, struct isc_device, scaler_sd); + + if (sel->pad == ISC_SCALER_PAD_SOURCE) + return -EINVAL; + + if (sel->target != V4L2_SEL_TGT_CROP_BOUNDS && + sel->target != V4L2_SEL_TGT_CROP) + return -EINVAL; + + sel->r.height = isc->max_height; + sel->r.width = isc->max_width; + + sel->r.left = 0; + sel->r.top = 0; + + return 0; +} + +static const struct v4l2_subdev_pad_ops isc_scaler_pad_ops = { + .enum_mbus_code = isc_scaler_enum_mbus_code, + .set_fmt = isc_scaler_set_fmt, + .get_fmt = isc_scaler_get_fmt, + .get_selection = isc_scaler_g_sel, +}; + +static const struct v4l2_subdev_ops xisc_scaler_subdev_ops = { + .pad = &isc_scaler_pad_ops, +}; + +static int isc_init_own_sd(struct isc_device *isc) +{ + int ret; + + v4l2_subdev_init(&isc->scaler_sd, &xisc_scaler_subdev_ops); + + isc->scaler_sd.owner = THIS_MODULE; + isc->scaler_sd.dev = isc->dev; + snprintf(isc->scaler_sd.name, sizeof(isc->scaler_sd.name), + "atmel_isc_scaler"); + + isc->scaler_sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + isc->scaler_sd.entity.function = MEDIA_ENT_F_PROC_VIDEO_SCALER; + isc->scaler_pads[ISC_SCALER_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + isc->scaler_pads[ISC_SCALER_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + + isc->scaler_format.height = isc->max_height; + isc->scaler_format.width = isc->max_width; + + ret = media_entity_pads_init(&isc->scaler_sd.entity, + ISC_SCALER_PADS_NUM, + isc->scaler_pads); + if (ret < 0) { + dev_err(isc->dev, "scaler sd media entity init failed\n"); + return ret; + } + ret = v4l2_device_register_subdev(&isc->v4l2_dev, &isc->scaler_sd); + if (ret < 0) { + dev_err(isc->dev, "scaler sd failed to register subdev\n"); + return ret; + } + + return ret; +} + +int isc_mc_init(struct isc_device *isc, u32 ver) +{ + const struct of_device_id *match; + int ret; + + isc->video_dev.entity.function = MEDIA_ENT_F_IO_V4L; + isc->video_dev.entity.flags = MEDIA_ENT_FL_DEFAULT; + isc->pads[ISC_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + + ret = media_entity_pads_init(&isc->video_dev.entity, ISC_PADS_NUM, + isc->pads); + if (ret < 0) { + dev_err(isc->dev, "media entity init failed\n"); + return ret; + } + + isc->mdev.dev = isc->dev; + isc->mdev.ops = &isc_media_ops; + + match = of_match_node(isc->dev->driver->of_match_table, + isc->dev->of_node); + + strscpy(isc->mdev.driver_name, KBUILD_MODNAME, + sizeof(isc->mdev.driver_name)); + strscpy(isc->mdev.model, match->compatible, sizeof(isc->mdev.model)); + snprintf(isc->mdev.bus_info, sizeof(isc->mdev.bus_info), "platform:%s", + isc->v4l2_dev.name); + isc->mdev.hw_revision = ver; + + media_device_init(&isc->mdev); + + isc->v4l2_dev.mdev = &isc->mdev; + + return isc_init_own_sd(isc); +} + +int isc_mc_register(struct isc_device *isc) +{ + int ret; + + ret = media_create_pad_link(&isc->current_subdev->sd->entity, + isc->remote_pad, &isc->scaler_sd.entity, + ISC_SCALER_PAD_SINK, + MEDIA_LNK_FL_ENABLED | + MEDIA_LNK_FL_IMMUTABLE); + + if (ret < 0) { + v4l2_err(&isc->v4l2_dev, + "Failed to create pad link: %s to %s\n", + isc->current_subdev->sd->entity.name, + isc->scaler_sd.entity.name); + return ret; + } + + dev_dbg(isc->dev, "link with %s pad: %d\n", + isc->current_subdev->sd->name, isc->remote_pad); + + ret = media_create_pad_link(&isc->scaler_sd.entity, + ISC_SCALER_PAD_SOURCE, + &isc->video_dev.entity, ISC_PAD_SINK, + MEDIA_LNK_FL_ENABLED | + MEDIA_LNK_FL_IMMUTABLE); + + if (ret < 0) { + v4l2_err(&isc->v4l2_dev, + "Failed to create pad link: %s to %s\n", + isc->scaler_sd.entity.name, + isc->video_dev.entity.name); + return ret; + } + + dev_dbg(isc->dev, "link with %s pad: %d\n", isc->scaler_sd.name, + ISC_SCALER_PAD_SOURCE); + + return media_device_register(&isc->mdev); +} + +void isc_mc_cleanup(struct isc_device *isc) +{ + media_entity_cleanup(&isc->video_dev.entity); +} diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index dd45e9ca22a9..27292c50915e 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -176,6 +176,17 @@ struct isc_reg_offsets { u32 his_entry; }; +enum isc_mc_pads { + ISC_PAD_SINK = 0, + ISC_PADS_NUM = 1, +}; + +enum isc_scaler_pads { + ISC_SCALER_PAD_SINK = 0, + ISC_SCALER_PAD_SOURCE = 1, + ISC_SCALER_PADS_NUM = 2, +}; + /* * struct isc_device - ISC device driver data/config struct * @regmap: Register map @@ -339,6 +350,19 @@ struct isc_device { struct isc_format *formats_list; u32 controller_formats_size; u32 formats_list_size; + + struct { + struct media_pad pads[ISC_PADS_NUM]; + struct media_device mdev; + + u32 remote_pad; + }; + + struct { + struct v4l2_subdev scaler_sd; + struct media_pad scaler_pads[ISC_SCALER_PADS_NUM]; + struct v4l2_mbus_framefmt scaler_format; + }; }; extern const struct regmap_config isc_regmap_config; @@ -350,4 +374,8 @@ int isc_clk_init(struct isc_device *isc); void isc_subdev_cleanup(struct isc_device *isc); void isc_clk_cleanup(struct isc_device *isc); +int isc_mc_init(struct isc_device *isc, u32 ver); +int isc_mc_register(struct isc_device *isc); +void isc_mc_cleanup(struct isc_device *isc); + #endif diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index e29a9193bac8..8c088ad899ea 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -528,6 +528,12 @@ static int atmel_isc_probe(struct platform_device *pdev) break; } + regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver); + + ret = isc_mc_init(isc, ver); + if (ret < 0) + goto isc_probe_mc_init_err; + pm_runtime_set_active(dev); pm_runtime_enable(dev); pm_request_idle(dev); @@ -537,7 +543,7 @@ static int atmel_isc_probe(struct platform_device *pdev) ret = clk_prepare_enable(isc->ispck); if (ret) { dev_err(dev, "failed to enable ispck: %d\n", ret); - goto cleanup_subdev; + goto isc_probe_mc_init_err; } /* ispck should be greater or equal to hclock */ @@ -547,7 +553,6 @@ static int atmel_isc_probe(struct platform_device *pdev) goto unprepare_clk; } - regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver); dev_info(dev, "Microchip ISC version %x\n", ver); return 0; @@ -555,6 +560,9 @@ static int atmel_isc_probe(struct platform_device *pdev) unprepare_clk: clk_disable_unprepare(isc->ispck); +isc_probe_mc_init_err: + isc_mc_cleanup(isc); + cleanup_subdev: isc_subdev_cleanup(isc); @@ -575,6 +583,8 @@ static int atmel_isc_remove(struct platform_device *pdev) pm_runtime_disable(&pdev->dev); + isc_mc_cleanup(isc); + isc_subdev_cleanup(isc); v4l2_device_unregister(&isc->v4l2_dev); diff --git a/drivers/media/platform/atmel/atmel-sama7g5-isc.c b/drivers/media/platform/atmel/atmel-sama7g5-isc.c index 6a5d3f7ce75e..3484971ff9be 100644 --- a/drivers/media/platform/atmel/atmel-sama7g5-isc.c +++ b/drivers/media/platform/atmel/atmel-sama7g5-isc.c @@ -522,15 +522,23 @@ static int microchip_xisc_probe(struct platform_device *pdev) break; } + regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver); + + ret = isc_mc_init(isc, ver); + if (ret < 0) + goto isc_probe_mc_init_err; + pm_runtime_set_active(dev); pm_runtime_enable(dev); pm_request_idle(dev); - regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver); dev_info(dev, "Microchip XISC version %x\n", ver); return 0; +isc_probe_mc_init_err: + isc_mc_cleanup(isc); + cleanup_subdev: isc_subdev_cleanup(isc); @@ -551,6 +559,8 @@ static int microchip_xisc_remove(struct platform_device *pdev) pm_runtime_disable(&pdev->dev); + isc_mc_cleanup(isc); + isc_subdev_cleanup(isc); v4l2_device_unregister(&isc->v4l2_dev); From patchwork Fri Oct 22 07:52:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C835C433FE for ; Fri, 22 Oct 2021 07:55:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 659F860FC3 for ; Fri, 22 Oct 2021 07:55:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232584AbhJVH5Q (ORCPT ); Fri, 22 Oct 2021 03:57:16 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:17446 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232586AbhJVH44 (ORCPT ); Fri, 22 Oct 2021 03:56:56 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889280; x=1666425280; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mGXSulOcLd/+pEdw+DTE5v6o3xipo1H1wT+9aSReL8M=; b=OkIEw3lKSEKvDtXtKHYQdpF7MHRZto+L1nWWB2+gjRD9gBxzaeYxBIPc TmoUkP7D8J4tfIcLJtV0HWofXm3loFm+06h9f5cjYg41sbe4mud4gnXPh uI8AVGXiTNUdNp2HP0cShY/27ewgh+CFuCB/Wdgsni5p6FcCUTDn7pk1k K1e1Cx2q4AJ0KUN2hk2Ii+o+4S1YcC0EAp5Xt00Ds6GUslGjYvDaVMtR7 cmY7QYVi2EE9u4eSK22xKsw3uNSgic6ZV1vkjDH4WyshPGX4Y8g5Tu2yI 2oU3mrRvFR6vyHxba630lkmrVxmcY3aBd/k2+FgwsVIYbjFlvPkWXZ30/ A==; IronPort-SDR: Nz/rmn6Caqi6ikJ75pwzOgC07QYIe7d2MhtiXUsQ2z3co3d1tRDalwK8z/qE9HVTkgvhbtDYdh C3PwljrQp71yh0Z29fI7y715kZ8n7Aqm/j7B+rId3LaO+PDiWtpwTxB/4BFJe15s0UXWksaFkV 7pb+avWIhhLHFZ1tUDWSFmo4TsTDunh7JyTjQf/nh4omih9r9tCyfxFIhf7lHNesd41jmx/e2n TCD9Yk98kiwT8Q0ggXKM7oSLtgcgUFTmZEgsju8x4dRj5fVsZkuogcAQ8ZwAb8+HjR9IS9aQDa sd8PXoSZAI/C/OkOCbI538nV X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="136538127" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:54:39 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:54:38 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:54:35 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 15/21] ARM: dts: at91: sama7g5: add nodes for video capture Date: Fri, 22 Oct 2021 10:52:41 +0300 Message-ID: <20211022075247.518880-16-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add node for the XISC (eXtended Image Sensor Controller) and CSI2DC (csi2 demux controller). These nodes represent the top level of the video capture hardware pipeline and are directly connected in hardware. Signed-off-by: Eugen Hristev --- arch/arm/boot/dts/sama7g5.dtsi | 49 ++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index 6c58c151c6d9..a8dda38ff18b 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -203,6 +203,55 @@ sdmmc2: mmc@e120c000 { status = "disabled"; }; + csi2dc: csi2dc@e1404000 { + compatible = "microchip,sama7g5-csi2dc"; + reg = <0xe1404000 0x500>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&xisc>; + clock-names = "pclk", "scck"; + assigned-clocks = <&xisc>; + assigned-clock-rates = <266000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csi2dc_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + csi2dc_out: endpoint { + bus-width = <12>; + hsync-active = <1>; + vsync-active = <1>; + remote-endpoint = <&xisc_in>; + }; + }; + }; + }; + + xisc: xisc@e1408000 { + compatible = "microchip,sama7g5-isc"; + reg = <0xe1408000 0x2000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; + clock-names = "hclock"; + #clock-cells = <0>; + clock-output-names = "isc-mck"; + + port { + xisc_in: endpoint { + bus-type = <5>; /* Parallel */ + bus-width = <12>; + hsync-active = <1>; + vsync-active = <1>; + remote-endpoint = <&csi2dc_out>; + }; + }; + }; + pwm: pwm@e1604000 { compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; reg = <0xe1604000 0x4000>; From patchwork Fri Oct 22 07:52:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7300C433EF for ; Fri, 22 Oct 2021 07:55:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AE3DA60FC1 for ; Fri, 22 Oct 2021 07:55:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232624AbhJVH5W (ORCPT ); Fri, 22 Oct 2021 03:57:22 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:13639 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232615AbhJVH5A (ORCPT ); Fri, 22 Oct 2021 03:57:00 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889283; x=1666425283; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3aLq+6t34WawSD7x49jHw5NnHLDsUbXrYRwccy4TZv0=; b=MLlqq7AzKZTRuOiHtMixZ0b6ATjA/CNY7vtgNaAMzy3Lq7/4ePvaJXaU erCUhe25D51raQIwg0pxSuxkwVu1Ggn1dDzj/w/4Z6F4/kecdcEhzzJco 374W7i8C7CRFHc/ChooI6d0htPq/JGtpPaS5tQCaTnfDE1TaZPMVF5WBN tg65ZBcW2gvZU9vb0oAfzivWHcGHZLbw8HIUYfz1j8w1gyX3N4Yi5y6Wn GVcn8E5TNptSjunLFt6VmswBlQg6cPk3IP0o1cvHvD3cIWt8f2isD8n1y fBQr5lS4W+9iUfXl7em5dH92+MdfWi4dyu1FpEbS9lP7QGP2KlLi0Gurz Q==; IronPort-SDR: H/EP0NVZkOR+SpcDtUhy70BhjWOBpL9EibPOBD1uVBeXvh1+W8x4OdK9cvdH1iO4vWSXPsnrz0 xTP1wygDqDsGOpIDuGuWJJ7xvVZZuRJkxFVmxPjMBaPeMolojBTeISynPL2LTkrWEfYoNl/2Ry U94ej0E1UDhkece5em7PsCCpal65XdxRfWhy20P99E15Lt9HdlI+ZGo1rp1vnH0vSgIsyELvvj y7+b2/61mzBfL7rGlEozK33FC++OeEej8QCPEonKs8g374mj11X/8oNak9zNTBfa4a6m7+y7PQ f+tzkdu+Rcjt4GGmaJvzti8n X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="141320555" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:54:43 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:54:42 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:54:39 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 16/21] ARM: configs: at91: sama7: add xisc and csi2dc Date: Fri, 22 Oct 2021 10:52:42 +0300 Message-ID: <20211022075247.518880-17-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Enable XISC and CSI2DC drivers. Signed-off-by: Eugen Hristev --- arch/arm/configs/sama7_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defconfig index 938aae4bd80b..15978f2ab4ea 100644 --- a/arch/arm/configs/sama7_defconfig +++ b/arch/arm/configs/sama7_defconfig @@ -126,6 +126,8 @@ CONFIG_MEDIA_SUPPORT_FILTER=y CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_PLATFORM_SUPPORT=y CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_ATMEL_XISC=y +CONFIG_VIDEO_MICROCHIP_CSI2DC=y CONFIG_VIDEO_IMX219=m CONFIG_VIDEO_IMX274=m CONFIG_VIDEO_OV5647=m From patchwork Fri Oct 22 07:52:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B15D8C433FE for ; Fri, 22 Oct 2021 07:55:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9D3556112D for ; Fri, 22 Oct 2021 07:55:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232213AbhJVH5X (ORCPT ); Fri, 22 Oct 2021 03:57:23 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:17462 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232573AbhJVH5F (ORCPT ); Fri, 22 Oct 2021 03:57:05 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889288; x=1666425288; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QSPFjxfXba29mpcA0AuoqTxyv540cTpqNP1ZdHCYLbU=; b=DYMhi9kE0TBLIqvmO+TTddzgjMH2iSaUij85UitYFrdAHkeX6lQR8w1W XFFUhcBE0U6I7VFOrcU30/xun2oJ8ZK4bcpmDWDiUvEHMmIycPvN7kS6C Y2+6kbotp2CqCBH4Hc0SIKEknvJl/Iw2Q00sH6R19A3cY24Sgz3COEYsZ I0xaT7hCi88dsU/gu1hcplpT10MRiLjDBmPTKYpcGqeBumU9AIMz91OYh 94Hzzia+H/ecoZcwN6izU0PL8tdUE6lyzaEZtlFDfbScoqA5h6K5AgRtG Yu0ymIvpSbz/4pk2yorynV0hHGbFM0xQ4O0h3derP16pmvFg33B2DpIZY g==; IronPort-SDR: vRkuhleayvIZc0sRRD/1oc8Uzy9QiwYq/IMnaKvs9mfFFJ/Fwz1KjGdM1mSV5uRZfGNzCpsLja +Ud+pNMmYjEgoEpdLpwCqE1p7p46AZr0YokcGtvbMWSI8PQPUznkAKGNYvU4DKMYH3QyTFRk+8 BFFnMmMPD1h4MIgy+oA8FfUbGMsxxCLAYBt6Np78GDGrwoU/eTLaC5zGgqTWRGJ2sEV6Gd5eaw eaDmIZdwObb8K0UkYmi/jmbjDL4GVKiftdDKTzRoURsXUGwAAXpzRIIftgoBClMQDg4eUx7gQE rZKtOMeGgkZ24ujY8GPEDjkw X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="136538145" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:54:47 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:54:46 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:54:43 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 17/21] ARM: multi_v7_defconfig: add atmel video pipeline modules Date: Fri, 22 Oct 2021 10:52:43 +0300 Message-ID: <20211022075247.518880-18-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add drivers for the atmel video capture pipeline: atmel isc, xisc and microchip csi2dc. Signed-off-by: Eugen Hristev --- arch/arm/configs/multi_v7_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index b4f74454f20f..03ea4d0ca242 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -654,7 +654,10 @@ CONFIG_VIDEO_S5P_MIPI_CSIS=m CONFIG_VIDEO_EXYNOS_FIMC_LITE=m CONFIG_VIDEO_EXYNOS4_FIMC_IS=m CONFIG_VIDEO_RCAR_VIN=m +CONFIG_VIDEO_ATMEL_ISC=m +CONFIG_VIDEO_ATMEL_XISC=m CONFIG_VIDEO_ATMEL_ISI=m +CONFIG_VIDEO_MICROCHIP_CSI2DC=m CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m CONFIG_VIDEO_SAMSUNG_S5P_MFC=m From patchwork Fri Oct 22 07:52:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577327 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47D8FC433F5 for ; Fri, 22 Oct 2021 07:55:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 32A8360231 for ; Fri, 22 Oct 2021 07:55:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232615AbhJVH5Y (ORCPT ); Fri, 22 Oct 2021 03:57:24 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:47680 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232663AbhJVH5I (ORCPT ); Fri, 22 Oct 2021 03:57:08 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889291; x=1666425291; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=D0ieQhGQKRttt8Quef04SMrFGlqdtCHyoWYWeCfMDGk=; b=j5ywe2B79kAL8/06eutj2WJYe+fbw/DH70oUL4cgUVqkHiMrt8gX4TIA I8A1zeZgDejD+P4SwDpKGwGhxKvfWg8FyqIMYR6CiUZhyO4S8qkTI1AEi CjG9uefCH1gE10cN6fT/xm7jy+z45QSW6Ui1fmjEZkupNszjV4+LUYa1F hihRjGv1WoBuFrhax0AcjjWjv+w0y85mrFfg18EpS03GdZ4wYViPHyPs4 Y9Vg5Ej8H+OxX1YBKFr1qhErUlnHpRnS/V8IsFYQPfeA5lFd0mvXrXW8B vWXeCLxCGbzN7rnwdmmWXIzG/k5nJYOL+vP+E+vPN6ZM6B8vVRlYWv/fI A==; IronPort-SDR: YHOphYOD3Hes4fbLfCeCzTP158oEPByAbT/aC+ooqTu6zMPxpa/GuRvA/883Rl3Agc7hcrmnLX 7u1uiSzGXTlyiXCag9R4wcv5BwI65XEDFbiUoU6Ni2ABFw0dnPYSz7qBZro1ydFdWCY4nPRcuF dsT3oou+7Hb3qbqzCWESmf8s6KcyN4CYs3/KEJmikScSFcTyRe4Xo7yOJHw+gRXJxRKSgsliFF kvW9mgLEmcRkujkWaVsFcD4OGd3BbyvlWFfk0AUs4nMVIMRNTufVSthBT5uBWIEGok36l3/3Zz VaeGt6YLMoXZtzKxl9M9di2x X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="134007238" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:54:50 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:54:50 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:54:47 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 18/21] media: atmel: atmel-sama5d2-isc: fix wrong mask in YUYV format check Date: Fri, 22 Oct 2021 10:52:44 +0300 Message-ID: <20211022075247.518880-19-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org While this does not happen in production, this check should be done versus the mask, as checking with the YCYC value may not include some bits that may be set. Is it correct and safe to check the whole mask. Fixes: 123aaf816b95 ("media: atmel: atmel-sama5d2-isc: fix YUYV format") Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-sama5d2-isc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index 8c088ad899ea..6c9c5fb041d7 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -267,7 +267,7 @@ static void isc_sama5d2_config_rlp(struct isc_device *isc) * Thus, if the YCYC mode is selected, replace it with the * sama5d2-compliant mode which is YYCC . */ - if ((rlp_mode & ISC_RLP_CFG_MODE_YCYC) == ISC_RLP_CFG_MODE_YCYC) { + if ((rlp_mode & ISC_RLP_CFG_MODE_MASK) == ISC_RLP_CFG_MODE_YCYC) { rlp_mode &= ~ISC_RLP_CFG_MODE_MASK; rlp_mode |= ISC_RLP_CFG_MODE_YYCC; } From patchwork Fri Oct 22 07:52:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6158C433FE for ; Fri, 22 Oct 2021 07:55:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B8409610C8 for ; Fri, 22 Oct 2021 07:55:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232523AbhJVH5e (ORCPT ); Fri, 22 Oct 2021 03:57:34 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:13668 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232344AbhJVH5M (ORCPT ); Fri, 22 Oct 2021 03:57:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889295; x=1666425295; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1GT8uqsv1PvTE+w2q+eOd1uaZzWC5KHZ8sqS85toEos=; b=UErz2OkU8Ezsya7ozGYmTkd/UdgkpN/wn/REv00ASMGOvZCTz0gjbiwz zgftbAYf7ChnXXbGcB0ui9XHWZctPUzLumktl9NGAtthOySGbh/D/B10/ idawFj3kDFl4JOu+g6474ZnO4UqQRXHiA95hqZYc6bTfYixPRymNWL7Wg 3+vuiHJ8dv3XksMqETPLJI/gogVwLmIPpPN0JcwXwZ+gLm9DqRChwNv0/ R8sttzuARICrw1xxPifNnxSVNCAMH9Mqk7qg2Y0F9tyFKVH//t+5DuK88 re1fpIV0FUEbLx0YbTvz6+Z7wIHRb80yKc84q5ve1V62exEyzLeurK9mm A==; IronPort-SDR: GjcNflvWfkh5na0E2ZC3jyHo3m+dK+n/f/FFivCstzNKx8s89kXKRnPl6zL4Yq7aLtzJ97zX9r +DqbXXrMzQUUfRjwdKxOtEjgxwIv7r7y1iBaHUwGHhFxLQ0avUMr5/4OtPE5ZDWkinX1Vn926c nSbPusXwGBg2UU+ME4y/cAnFuZxn6ITCW8PnKxnLGU3n8nM8b9y/OcYjCk7ncGcuXBw0PuocOK ETwlUMgVTcVmEi92hS3grSCmehDbkjrvrNNFgzqBRJUyTPEWITetAuMSuxVEfMb1PP3j7TrXrY neMq0LDg2GOW/gEGBvYMsYjX X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="141320579" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:54:54 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:54:54 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:54:50 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 19/21] media: atmel: atmel-isc-base: use mutex to lock awb workqueue from streaming Date: Fri, 22 Oct 2021 10:52:45 +0300 Message-ID: <20211022075247.518880-20-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The AWB workqueue runs in a kernel thread and needs to be synchronized w.r.t. the streaming status. It is possible that streaming is stopped while the AWB workq is running. In this case it is likely that the check for isc->stop is done at one point in time, but the AWB computations are done later, including a call to isc_update_profile, which requires streaming to be started. Thus , isc_update_profile will fail if during this operation sequence the streaming was stopped. To solve this issue, a mutex is added, that will serialize the awb work and streaming stopping, with the mention that either streaming is stopped completely including termination of the last frame is done, and after that the AWB work can check stream status and stop; either first AWB work is completed and after that the streaming can stop correctly. The awb spin lock cannot be used since this spinlock is taken in the same context and using it in the stop streaming will result in a recursion BUG. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 31 ++++++++++++++++--- drivers/media/platform/atmel/atmel-isc.h | 1 + 2 files changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index a0e4bc75d1a2..7ebe0a2d130f 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -402,6 +402,7 @@ static void isc_stop_streaming(struct vb2_queue *vq) struct isc_buffer *buf; int ret; + mutex_lock(&isc->awb_mutex); v4l2_ctrl_activate(isc->do_wb_ctrl, false); isc->stop = true; @@ -411,6 +412,8 @@ static void isc_stop_streaming(struct vb2_queue *vq) v4l2_err(&isc->v4l2_dev, "Timeout waiting for end of the capture\n"); + mutex_unlock(&isc->awb_mutex); + /* Disable DMA interrupt */ regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE); @@ -1417,10 +1420,6 @@ static void isc_awb_work(struct work_struct *w) u32 min, max; int ret; - /* streaming is not active anymore */ - if (isc->stop) - return; - if (ctrls->hist_stat != HIST_ENABLED) return; @@ -1471,7 +1470,24 @@ static void isc_awb_work(struct work_struct *w) } regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his, hist_id | baysel | ISC_HIS_CFG_RAR); + + /* + * We have to make sure the streaming has not stopped meanwhile. + * ISC requires a frame to clock the internal profile update. + * To avoid issues, lock the sequence with a mutex + */ + mutex_lock(&isc->awb_mutex); + + /* streaming is not active anymore */ + if (isc->stop) { + mutex_unlock(&isc->awb_mutex); + return; + }; + isc_update_profile(isc); + + mutex_unlock(&isc->awb_mutex); + /* if awb has been disabled, we don't need to start another histogram */ if (ctrls->awb) regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ); @@ -1550,6 +1566,8 @@ static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl) isc_update_awb_ctrls(isc); + mutex_lock(&isc->awb_mutex); + if (!isc->stop) { /* * If we are streaming, we can update profile to @@ -1564,6 +1582,7 @@ static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl) */ v4l2_ctrl_activate(isc->do_wb_ctrl, false); } + mutex_unlock(&isc->awb_mutex); /* if we have autowhitebalance on, start histogram procedure */ if (ctrls->awb == ISC_WB_AUTO && !isc->stop && @@ -1755,6 +1774,7 @@ static void isc_async_unbind(struct v4l2_async_notifier *notifier, { struct isc_device *isc = container_of(notifier->v4l2_dev, struct isc_device, v4l2_dev); + mutex_destroy(&isc->awb_mutex); cancel_work_sync(&isc->awb_work); video_unregister_device(&isc->video_dev); v4l2_ctrl_handler_free(&isc->ctrls.handler); @@ -1866,6 +1886,8 @@ static int isc_async_complete(struct v4l2_async_notifier *notifier) isc->current_subdev = container_of(notifier, struct isc_subdev_entity, notifier); mutex_init(&isc->lock); + mutex_init(&isc->awb_mutex); + init_completion(&isc->comp); /* Initialize videobuf2 queue */ @@ -1941,6 +1963,7 @@ static int isc_async_complete(struct v4l2_async_notifier *notifier) video_unregister_device(vdev); isc_async_complete_err: + mutex_destroy(&isc->awb_mutex); mutex_destroy(&isc->lock); return ret; } diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index 27292c50915e..93ee000279f2 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -294,6 +294,7 @@ struct isc_device { struct work_struct awb_work; struct mutex lock; /* serialize access to file operations */ + struct mutex awb_mutex; /* serialize access to streaming status from awb work queue */ spinlock_t awb_lock; /* serialize access to DMA buffers from awb work queue */ struct regmap_field *pipeline[ISC_PIPE_LINE_NODE_NUM]; From patchwork Fri Oct 22 07:52:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577331 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4A1DC433EF for ; Fri, 22 Oct 2021 07:55:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C5B6361284 for ; Fri, 22 Oct 2021 07:55:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232688AbhJVH5f (ORCPT ); Fri, 22 Oct 2021 03:57:35 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:17446 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232585AbhJVH5Q (ORCPT ); Fri, 22 Oct 2021 03:57:16 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889299; x=1666425299; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nWSLtOBP89ZKPr7pkblnuPZXTqOXvF6+GrCCZxMsTgs=; b=r11jyMlmtUEOkkLKg0fWbYqfiTLkCFmyuuvkqMegDErOUAS6Uriij+76 HkEYl7jF80npS79fGDOr5hCrIWWWFrHDp1X07Rtlc6S76623UE+ky2uz1 Uf1jrMnHjLb9guTSGo62CbItDVqPXovb5Cxo5yN5XdZAqjT0dU3J+uJEv 3F1DzxcJo0Rjwvkoazo5uJjWBqlqDavjia/CahL2Y84Z/EqJDhXf6l75m ir2PSIyo8hReYyqoAahd5PRYuxtbBsTuS+yOuNVYPbNNjZN8sb2Cd2gqx ZyasgKLJ2tkMYBYk11kBZYs2mM/irMfCfs8V/z44HdzNZTeCqMXwORAlS A==; IronPort-SDR: E1PSMpB5xUajAd7LRMEcZlOJKma4QnDaxhDfmJMIQabvI5OzcR2lR9N0Jl1GNHlsIvphgLV2bp 7THor6gDVyfhR6QwPVjOOMrp8n+O7+CCneB5A4U56RJl04Vns4fnDGHyUsNudqJqx/kb8sHfl1 kWAskcDrDiPvESxTfaRBVsD1gYVN4re3w1HV+m4RoK0W+SI0JxWWmGRTnpsJ3IUbZNtMFP3ZFY 4Zb8GVFMm2IMzxqUZzMFQ7LewSatm0UpQ/zFFQCcTvhP/Q1cIPm1Ml4yN9FDMj9GKBn3D7Z9TN 1GxxVsI2KbPfq4OqzN0DK48g X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="136538157" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:54:58 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:54:58 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:54:54 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 20/21] media: atmel: atmel-isc-base: add wb debug messages Date: Fri, 22 Oct 2021 10:52:46 +0300 Message-ID: <20211022075247.518880-21-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add debug messages that make it easier to debug white balance algorithm. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 7ebe0a2d130f..071ac5eec7ec 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -1330,10 +1330,15 @@ static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max) if (!*min) *min = 1; + + v4l2_dbg(1, debug, &isc->v4l2_dev, + "isc wb: hist_id %u, hist_count %u", + ctrls->hist_id, *hist_count); } static void isc_wb_update(struct isc_ctrls *ctrls) { + struct isc_device *isc = container_of(ctrls, struct isc_device, ctrls); u32 *hist_count = &ctrls->hist_count[0]; u32 c, offset[4]; u64 avg = 0; @@ -1350,6 +1355,9 @@ static void isc_wb_update(struct isc_ctrls *ctrls) (u64)hist_count[ISC_HIS_CFG_MODE_GB]; avg >>= 1; + v4l2_dbg(1, debug, &isc->v4l2_dev, + "isc wb: green components average %llu\n", avg); + /* Green histogram is null, nothing to do */ if (!avg) return; @@ -1402,9 +1410,15 @@ static void isc_wb_update(struct isc_ctrls *ctrls) else gw_gain[c] = 1 << 9; + v4l2_dbg(1, debug, &isc->v4l2_dev, + "isc wb: component %d, s_gain %u, gw_gain %u\n", + c, s_gain[c], gw_gain[c]); /* multiply both gains and adjust for decimals */ ctrls->gain[c] = s_gain[c] * gw_gain[c]; ctrls->gain[c] >>= 9; + v4l2_dbg(1, debug, &isc->v4l2_dev, + "isc wb: component %d, final gain %u\n", + c, ctrls->gain[c]); } } @@ -1424,6 +1438,10 @@ static void isc_awb_work(struct work_struct *w) return; isc_hist_count(isc, &min, &max); + + v4l2_dbg(1, debug, &isc->v4l2_dev, + "isc wb mode %d: hist min %u , max %u\n", hist_id, min, max); + ctrls->hist_minmax[hist_id][HIST_MIN_INDEX] = min; ctrls->hist_minmax[hist_id][HIST_MAX_INDEX] = max; From patchwork Fri Oct 22 07:52:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12577333 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DAE1C433FE for ; Fri, 22 Oct 2021 07:55:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8391B6112D for ; Fri, 22 Oct 2021 07:55:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232788AbhJVH5m (ORCPT ); Fri, 22 Oct 2021 03:57:42 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:17502 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232601AbhJVH5U (ORCPT ); Fri, 22 Oct 2021 03:57:20 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634889303; x=1666425303; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wDcAUxy4+J7U+nbdqT4H/qC13HwZeJ4M+KkOlbGfiME=; b=WNKYFIsX6oeMYEYqqdpd7eX4+WsBGHcvme8EvBUy0b8BtnB7EAG5teWn Q53mNfWvjlvrMIihHz/ol9OFp9vJ1Wy7aZImxLKnNDizBT32c8vw434ff vLsZVpv1R95P3ZSH2lT0FMnjF/2PmZ4PiK4GqrRZqtzbvkJ40jFXSMXzM 9JA+qnk3+4KtpO7PDaJ8D9mncGy7KuzE+puWnEVJkJ01m8rZmv7hKbroZ f6KNXN6MQFUbPHSZ0YDItxurG5zrcmi6ikNerOfVJ9MV3CVobLj6DQb4V ZaSpjzvi3jGAyLzYc3NS8PPAN+0tTxIqtNSmzyxYEzNu0ONM7pf7pw9SZ Q==; IronPort-SDR: pQHfuea1n6HvBzLnXY4q2xY5gL5e2sVLtU/XkIjxJXH5IWwVumJOUTKrqIA4G48+f0LYa3v0/N j1O+74QXzZ4BWFHn7fdcWoQBndpZAWNvdleLQwWVktbIRErYMkB3chhmeQGT5oYpk/z8rTXr34 ea5j/qt0GGRdHGZ1j51UXtf9Tmx8kG/30/qqSYLzUN9J+GsKvpv4idcEKe6Z7I9wXNWCD3+LOm T4sR+Y5gjQtpi2VNltRGTo3dp5mFWf0zSyDe9Mh63RxHnW4Kuzni2G/Bj45jdqYTG/POrBDRst c/pzKP+Rd+GTzkMdKxxqGoVD X-IronPort-AV: E=Sophos;i="5.87,172,1631602800"; d="scan'208";a="136538173" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2021 00:55:02 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 22 Oct 2021 00:55:02 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 22 Oct 2021 00:54:58 -0700 From: Eugen Hristev To: , , , CC: , , , , , Eugen Hristev Subject: [PATCH 21/21] media: atmel: atmel-isc-base: clamp wb gain coefficients Date: Fri, 22 Oct 2021 10:52:47 +0300 Message-ID: <20211022075247.518880-22-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022075247.518880-1-eugen.hristev@microchip.com> References: <20211022075247.518880-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org White balance computed gains can overflow above the 13 bits hardware coefficient that can be used, in some specific scenarios like a subexposure from the sensor when the image is mostly black. In this case the computed gain has to be clamped to the maximum value allowed by the hardware. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 071ac5eec7ec..53141de78f67 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -1416,6 +1416,10 @@ static void isc_wb_update(struct isc_ctrls *ctrls) /* multiply both gains and adjust for decimals */ ctrls->gain[c] = s_gain[c] * gw_gain[c]; ctrls->gain[c] >>= 9; + + /* make sure we are not out of range */ + ctrls->gain[c] = clamp_val(ctrls->gain[c], 0, GENMASK(12, 0)); + v4l2_dbg(1, debug, &isc->v4l2_dev, "isc wb: component %d, final gain %u\n", c, ctrls->gain[c]);