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Mon, 25 Oct 2021 05:43:47 -0700 (PDT) From: Rahul Pathak To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, bmeng.cn@gmail.com, Alistair.Francis@wdc.com Subject: [PATCH v2 1/2] target/riscv: Add priv spec 1.12.0 version check Date: Mon, 25 Oct 2021 18:13:18 +0530 Message-Id: <20211025124319.195290-2-rpathak@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211025124319.195290-1-rpathak@ventanamicro.com> References: <20211025124319.195290-1-rpathak@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=rpathak@ventanamicro.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: rpathak@ventanamicro.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Rahul Pathak --- target/riscv/cpu.c | 4 +++- target/riscv/cpu.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 788fa0b11c..83c3814a5a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -405,7 +405,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { + priv_version = PRIV_VERSION_1_12_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { priv_version = PRIV_VERSION_1_11_0; } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { priv_version = PRIV_VERSION_1_10_0; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a33dc30be8..67c52e6f9e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -79,6 +79,7 @@ enum { #define PRIV_VERSION_1_10_0 0x00011000 #define PRIV_VERSION_1_11_0 0x00011100 +#define PRIV_VERSION_1_12_0 0x00011200 #define VEXT_VERSION_0_07_1 0x00000701 From patchwork Mon Oct 25 12:43:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Pathak X-Patchwork-Id: 12581785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62012C433F5 for ; Mon, 25 Oct 2021 12:56:14 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1F60961027 for ; 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Mon, 25 Oct 2021 05:43:54 -0700 (PDT) Received: from localhost.localdomain ([2405:201:6817:c049:7263:28b8:7cdf:c7e4]) by smtp.googlemail.com with ESMTPSA id nn2sm3293461pjb.34.2021.10.25.05.43.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Oct 2021 05:43:54 -0700 (PDT) From: Rahul Pathak To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, bmeng.cn@gmail.com, Alistair.Francis@wdc.com Subject: [PATCH v2 2/2] target/riscv: csr: Implement mconfigptr CSR Date: Mon, 25 Oct 2021 18:13:19 +0530 Message-Id: <20211025124319.195290-3-rpathak@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211025124319.195290-1-rpathak@ventanamicro.com> References: <20211025124319.195290-1-rpathak@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=rpathak@ventanamicro.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: rpathak@ventanamicro.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Rahul Pathak --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 19 +++++++++++++++---- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index cffcd3a5df..e2f154b7c5 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -140,6 +140,7 @@ #define CSR_MARCHID 0xf12 #define CSR_MIMPID 0xf13 #define CSR_MHARTID 0xf14 +#define CSR_MCONFIGPTR 0xf15 /* Machine Trap Setup */ #define CSR_MSTATUS 0x300 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 69e4d65fcd..2d7f608d49 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -209,6 +209,16 @@ static RISCVException epmp(CPURISCVState *env, int csrno) return RISCV_EXCP_ILLEGAL_INST; } + +static RISCVException priv1p12(CPURISCVState *env, int csrno) +{ + if (env->priv_ver >= PRIV_VERSION_1_12_0) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} + #endif /* User Floating-Point CSRs */ @@ -1569,10 +1579,11 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, /* Machine Information Registers */ - [CSR_MVENDORID] = { "mvendorid", any, read_zero }, - [CSR_MARCHID] = { "marchid", any, read_zero }, - [CSR_MIMPID] = { "mimpid", any, read_zero }, - [CSR_MHARTID] = { "mhartid", any, read_mhartid }, + [CSR_MVENDORID] = { "mvendorid", any, read_zero }, + [CSR_MARCHID] = { "marchid", any, read_zero }, + [CSR_MIMPID] = { "mimpid", any, read_zero }, + [CSR_MHARTID] = { "mhartid", any, read_mhartid }, + [CSR_MCONFIGPTR] = {"mconfigptr", priv1p12, read_zero }, /* Machine Trap Setup */ [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus },