From patchwork Fri Dec 14 18:20:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 10731531 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A69F5924 for ; Fri, 14 Dec 2018 18:22:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D039B2D91A for ; Fri, 14 Dec 2018 18:22:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CE8FD2D95D; Fri, 14 Dec 2018 18:22:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5D08B2D949 for ; Fri, 14 Dec 2018 18:22:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 82B716F638; Fri, 14 Dec 2018 18:22:56 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id E59CB6F638 for ; Fri, 14 Dec 2018 18:22:55 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Dec 2018 10:22:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,354,1539673200"; d="scan'208";a="259554833" Received: from pewalla-mobl1.amr.corp.intel.com (HELO ldmartin-desk.jf.intel.com) ([10.251.146.10]) by orsmga004.jf.intel.com with ESMTP; 14 Dec 2018 10:22:55 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Fri, 14 Dec 2018 10:20:18 -0800 Message-Id: <20181214182021.10483-2-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20181214182021.10483-1-lucas.demarchi@intel.com> References: <20181214182021.10483-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 1/4] drm/i915: Simplify MOCS table definition X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anuj Phogat Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Make the defines for LE and L3 caching options to contain the shifts and remove the zeros from the tables as shifting zeros always result in zero. Starting from Ice Lake the MOCS table is defined in the spec and contains all entries. So to simplify checking the table with the values set in code, the value is now part of the macro name. This allows to still give the most used option and sensible name, but also to easily cross check the table from the spec for gen >= 11. By removing the zeros we avoid maintaining a huge table since the one from spec contains many more entries. The new table for Ice Lake will be added by other patches, this only reformats the table. While at it also fix the indentation. Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/intel_mocs.c | 80 +++++++++++-------------------- 1 file changed, 29 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index e976c5ce5479..4fbfb335bc4e 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -36,8 +36,8 @@ struct drm_i915_mocs_table { }; /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */ -#define LE_CACHEABILITY(value) ((value) << 0) -#define LE_TGT_CACHE(value) ((value) << 2) +#define _LE_CACHEABILITY(value) ((value) << 0) +#define _LE_TGT_CACHE(value) ((value) << 2) #define LE_LRUM(value) ((value) << 4) #define LE_AOM(value) ((value) << 6) #define LE_RSC(value) ((value) << 7) @@ -48,28 +48,28 @@ struct drm_i915_mocs_table { /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */ #define L3_ESC(value) ((value) << 0) #define L3_SCC(value) ((value) << 1) -#define L3_CACHEABILITY(value) ((value) << 4) +#define _L3_CACHEABILITY(value) ((value) << 4) /* Helper defines */ #define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */ /* (e)LLC caching options */ -#define LE_PAGETABLE 0 -#define LE_UC 1 -#define LE_WT 2 -#define LE_WB 3 - -/* L3 caching options */ -#define L3_DIRECT 0 -#define L3_UC 1 -#define L3_RESERVED 2 -#define L3_WB 3 +#define LE_0_PAGETABLE _LE_CACHEABILITY(0) +#define LE_1_UC _LE_CACHEABILITY(1) +#define LE_2_WT _LE_CACHEABILITY(2) +#define LE_3_WB _LE_CACHEABILITY(3) /* Target cache */ -#define LE_TC_PAGETABLE 0 -#define LE_TC_LLC 1 -#define LE_TC_LLC_ELLC 2 -#define LE_TC_LLC_ELLC_ALT 3 +#define LE_TC_0_PAGETABLE _LE_TGT_CACHE(0) +#define LE_TC_1_LLC _LE_TGT_CACHE(1) +#define LE_TC_2_LLC_ELLC _LE_TGT_CACHE(2) +#define LE_TC_3_LLC_ELLC_ALT _LE_TGT_CACHE(3) + +/* L3 caching options */ +#define L3_0_DIRECT _L3_CACHEABILITY(0) +#define L3_1_UC _L3_CACHEABILITY(1) +#define L3_2_RESERVED _L3_CACHEABILITY(2) +#define L3_3_WB _L3_CACHEABILITY(3) /* * MOCS tables @@ -99,31 +99,21 @@ struct drm_i915_mocs_table { static const struct drm_i915_mocs_entry skylake_mocs_table[] = { [I915_MOCS_UNCACHED] = { /* 0x00000009 */ - .control_value = LE_CACHEABILITY(LE_UC) | - LE_TGT_CACHE(LE_TC_LLC_ELLC) | - LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | - LE_PFM(0) | LE_SCF(0), - + .control_value = LE_1_UC | LE_TC_2_LLC_ELLC, /* 0x0010 */ - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + .l3cc_value = L3_1_UC, }, [I915_MOCS_PTE] = { /* 0x00000038 */ - .control_value = LE_CACHEABILITY(LE_PAGETABLE) | - LE_TGT_CACHE(LE_TC_LLC_ELLC) | - LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | - LE_PFM(0) | LE_SCF(0), + .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3), /* 0x0030 */ - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + .l3cc_value = L3_3_WB, }, [I915_MOCS_CACHED] = { /* 0x0000003b */ - .control_value = LE_CACHEABILITY(LE_WB) | - LE_TGT_CACHE(LE_TC_LLC_ELLC) | - LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | - LE_PFM(0) | LE_SCF(0), + .control_value = LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3), /* 0x0030 */ - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + .l3cc_value = L3_3_WB, }, }; @@ -131,33 +121,21 @@ static const struct drm_i915_mocs_entry skylake_mocs_table[] = { static const struct drm_i915_mocs_entry broxton_mocs_table[] = { [I915_MOCS_UNCACHED] = { /* 0x00000009 */ - .control_value = LE_CACHEABILITY(LE_UC) | - LE_TGT_CACHE(LE_TC_LLC_ELLC) | - LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | - LE_PFM(0) | LE_SCF(0), - + .control_value = LE_1_UC | LE_TC_2_LLC_ELLC, /* 0x0010 */ - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + .l3cc_value = L3_1_UC, }, [I915_MOCS_PTE] = { /* 0x00000038 */ - .control_value = LE_CACHEABILITY(LE_PAGETABLE) | - LE_TGT_CACHE(LE_TC_LLC_ELLC) | - LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | - LE_PFM(0) | LE_SCF(0), - + .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3), /* 0x0030 */ - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + .l3cc_value = L3_3_WB, }, [I915_MOCS_CACHED] = { /* 0x00000039 */ - .control_value = LE_CACHEABILITY(LE_UC) | - LE_TGT_CACHE(LE_TC_LLC_ELLC) | - LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | - LE_PFM(0) | LE_SCF(0), - + .control_value = LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3), /* 0x0030 */ - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + .l3cc_value = L3_3_WB, }, }; From patchwork Fri Dec 14 18:20:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 10731537 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4D0E813BF for ; Fri, 14 Dec 2018 18:23:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 769162D970 for ; Fri, 14 Dec 2018 18:23:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 752832D975; Fri, 14 Dec 2018 18:23:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 261482D970 for ; Fri, 14 Dec 2018 18:23:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8ADA56F63B; Fri, 14 Dec 2018 18:23:03 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5F0D86F636 for ; Fri, 14 Dec 2018 18:22:56 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Dec 2018 10:22:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,354,1539673200"; d="scan'208";a="259554836" Received: from pewalla-mobl1.amr.corp.intel.com (HELO ldmartin-desk.jf.intel.com) ([10.251.146.10]) by orsmga004.jf.intel.com with ESMTP; 14 Dec 2018 10:22:55 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Fri, 14 Dec 2018 10:20:19 -0800 Message-Id: <20181214182021.10483-3-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20181214182021.10483-1-lucas.demarchi@intel.com> References: <20181214182021.10483-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 2/4] drm/i915/skl: Rework MOCS tables to keep common part in a define X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anuj Phogat Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tomasz Lis The MOCS tables are going to be very similar across platforms. To reduce the amount of copied code, this patch rips the common part and puts it into a definition valid for all gen9 platforms. v2: Made defines for or-ing flags. Renamed macros from MOCS_TABLE to MOCS_ENTRIES. (Joonas) v3 (Lucas): - Fix indentation - Rebase on rework done by additional patch - Remove define for or-ing flags as it made the table more complex by requiring zeroed values to be passed - Do not embed comma in the macro, so to treat that just as another item and please source code formatting tools Signed-off-by: Tomasz Lis Suggested-by: Lucas De Marchi Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/intel_mocs.c | 57 ++++++++++++++----------------- 1 file changed, 25 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index 4fbfb335bc4e..577633cefb8a 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -96,46 +96,39 @@ struct drm_i915_mocs_table { * may only be updated incrementally by adding entries at the * end. */ + +#define GEN9_MOCS_ENTRIES \ + [I915_MOCS_UNCACHED] = { \ + /* 0x00000009 */ \ + .control_value = LE_1_UC | LE_TC_2_LLC_ELLC, \ + /* 0x0010 */ \ + .l3cc_value = L3_1_UC, \ + }, \ + [I915_MOCS_PTE] = { \ + /* 0x00000038 */ \ + .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3), \ + /* 0x0030 */ \ + .l3cc_value = L3_3_WB, \ + } + static const struct drm_i915_mocs_entry skylake_mocs_table[] = { - [I915_MOCS_UNCACHED] = { - /* 0x00000009 */ - .control_value = LE_1_UC | LE_TC_2_LLC_ELLC, - /* 0x0010 */ - .l3cc_value = L3_1_UC, - }, - [I915_MOCS_PTE] = { - /* 0x00000038 */ - .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3), - /* 0x0030 */ - .l3cc_value = L3_3_WB, - }, + GEN9_MOCS_ENTRIES, [I915_MOCS_CACHED] = { - /* 0x0000003b */ - .control_value = LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3), - /* 0x0030 */ - .l3cc_value = L3_3_WB, + /* 0x0000003b */ + .control_value = LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3), + /* 0x0030 */ + .l3cc_value = L3_3_WB, }, }; /* NOTE: the LE_TGT_CACHE is not used on Broxton */ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { - [I915_MOCS_UNCACHED] = { - /* 0x00000009 */ - .control_value = LE_1_UC | LE_TC_2_LLC_ELLC, - /* 0x0010 */ - .l3cc_value = L3_1_UC, - }, - [I915_MOCS_PTE] = { - /* 0x00000038 */ - .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3), - /* 0x0030 */ - .l3cc_value = L3_3_WB, - }, + GEN9_MOCS_ENTRIES, [I915_MOCS_CACHED] = { - /* 0x00000039 */ - .control_value = LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3), - /* 0x0030 */ - .l3cc_value = L3_3_WB, + /* 0x00000039 */ + .control_value = LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3), + /* 0x0030 */ + .l3cc_value = L3_3_WB, }, }; From patchwork Fri Dec 14 18:20:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 10731539 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AA56413BF for ; Fri, 14 Dec 2018 18:23:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D14CF2D963 for ; Fri, 14 Dec 2018 18:23:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CF9312D947; Fri, 14 Dec 2018 18:23:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0FCE52D970 for ; Fri, 14 Dec 2018 18:23:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E05F26F63C; Fri, 14 Dec 2018 18:23:03 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id ED9C16F639 for ; Fri, 14 Dec 2018 18:22:56 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Dec 2018 10:22:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,354,1539673200"; d="scan'208";a="259554840" Received: from pewalla-mobl1.amr.corp.intel.com (HELO ldmartin-desk.jf.intel.com) ([10.251.146.10]) by orsmga004.jf.intel.com with ESMTP; 14 Dec 2018 10:22:56 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Fri, 14 Dec 2018 10:20:20 -0800 Message-Id: <20181214182021.10483-4-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20181214182021.10483-1-lucas.demarchi@intel.com> References: <20181214182021.10483-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 3/4] drm/i915/icl: Define MOCS table for Icelake X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anuj Phogat Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tomasz Lis The table has been unified across OSes to minimize virtualization overhead. The MOCS table is now published as part of bspec, and versioned. Entries are supposed to never be modified, but new ones can be added. Adding entries increases table version. The patch includes version 1 entries. Meaning of each entry is now explained in bspec, and user mode clients are expected to know what each entry means. The 3 entries used for previous platforms are still compatible with their legacy definitions, but that is not guaranteed to be true for future platforms. v2: Fixed SCC values, improved commit comment (Daniele) v3: Improved MOCS table comment (Daniele) v4: Moved new entries below gen9 ones. Put common entries into definition to be used in multiple arrays. (Lucas) v5: Made defines for or-ing flags. Renamed macros from MOCS_TABLE to MOCS_ENTRIES. Switched LE_CoS to upper case. (Joonas) v6: Removed definitions of reserved entries. (Michal) Increased limit of entries sent to the hardware on gen11+. v7: Simplify table as done for previou gens (Lucas) BSpec: 34007 BSpec: 560 Signed-off-by: Tomasz Lis Reviewed-by: Daniele Ceraolo Spurio Reviewed-by: Lucas De Marchi Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/intel_mocs.c | 187 ++++++++++++++++++++++++++---- 1 file changed, 162 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index 577633cefb8a..dfc4edea020f 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -44,6 +44,8 @@ struct drm_i915_mocs_table { #define LE_SCC(value) ((value) << 8) #define LE_PFM(value) ((value) << 11) #define LE_SCF(value) ((value) << 14) +#define LE_COS(value) ((value) << 15) +#define LE_SSE(value) ((value) << 17) /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */ #define L3_ESC(value) ((value) << 0) @@ -52,6 +54,10 @@ struct drm_i915_mocs_table { /* Helper defines */ #define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */ +#define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */ + +#define NUM_MOCS_ENTRIES(i915) \ + (INTEL_GEN(i915) < 11 ? GEN9_NUM_MOCS_ENTRIES : GEN11_NUM_MOCS_ENTRIES) /* (e)LLC caching options */ #define LE_0_PAGETABLE _LE_CACHEABILITY(0) @@ -80,21 +86,21 @@ struct drm_i915_mocs_table { * LNCFCMOCS0 - LNCFCMOCS32 registers. * * These tables are intended to be kept reasonably consistent across - * platforms. However some of the fields are not applicable to all of - * them. + * HW platforms, and for ICL+, be identical across OSes. To achieve + * that, for Icelake and above, list of entries is published as part + * of bspec. * * Entries not part of the following tables are undefined as far as - * userspace is concerned and shouldn't be relied upon. For the time - * being they will be implicitly initialized to the strictest caching - * configuration (uncached) to guarantee forwards compatibility with - * userspace programs written against more recent kernels providing - * additional MOCS entries. + * userspace is concerned and shouldn't be relied upon. + * + * The last two entries are reserved by the hardware. For ICL+ they + * should be initialized according to bspec and never used, for older + * platforms they should never be written to. * - * NOTE: These tables MUST start with being uncached and the length - * MUST be less than 63 as the last two registers are reserved - * by the hardware. These tables are part of the kernel ABI and - * may only be updated incrementally by adding entries at the - * end. + * NOTE: These tables are part of bspec and defined as part of hardware + * interface for ICL+. For older platforms, they are part of kernel + * ABI. It is expected that existing entries will remain constant + * and the tables will only be updated by adding new entries. */ #define GEN9_MOCS_ENTRIES \ @@ -132,6 +138,132 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { }, }; +#define GEN11_MOCS_ENTRIES \ + [0] = { \ + /* Base - Uncached (Deprecated) */ \ + .control_value = LE_1_UC | LE_TC_1_LLC, \ + .l3cc_value = L3_1_UC \ + }, \ + [1] = { \ + /* Base - L3 + LeCC:PAT (Deprecated) */ \ + .control_value = LE_0_PAGETABLE | LE_TC_1_LLC, \ + .l3cc_value = L3_3_WB \ + }, \ + [2] = { \ + /* Base - L3 + LLC */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ + .l3cc_value = L3_3_WB \ + }, \ + [3] = { \ + /* Base - Uncached */ \ + .control_value = LE_1_UC | LE_TC_1_LLC, \ + .l3cc_value = L3_1_UC \ + }, \ + [4] = { \ + /* Base - L3 */ \ + .control_value = LE_1_UC | LE_TC_1_LLC, \ + .l3cc_value = L3_3_WB \ + }, \ + [5] = { \ + /* Base - LLC */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ + .l3cc_value = L3_1_UC \ + }, \ + [6] = { \ + /* Age 0 - LLC */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \ + .l3cc_value = L3_1_UC \ + }, \ + [7] = { \ + /* Age 0 - L3 + LLC */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \ + .l3cc_value = L3_3_WB \ + }, \ + [8] = { \ + /* Age: Don't Chg. - LLC */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \ + .l3cc_value = L3_1_UC \ + }, \ + [9] = { \ + /* Age: Don't Chg. - L3 + LLC */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \ + .l3cc_value = L3_3_WB \ + }, \ + [10] = { \ + /* No AOM - LLC */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \ + .l3cc_value = L3_1_UC \ + }, \ + [11] = { \ + /* No AOM - L3 + LLC */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \ + .l3cc_value = L3_3_WB \ + }, \ + [12] = { \ + /* No AOM; Age 0 - LLC */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \ + .l3cc_value = L3_1_UC \ + }, \ + [13] = { \ + /* No AOM; Age 0 - L3 + LLC */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \ + .l3cc_value = L3_3_WB \ + }, \ + [14] = { \ + /* No AOM; Age:DC - LLC */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \ + .l3cc_value = L3_1_UC \ + }, \ + [15] = { \ + /* No AOM; Age:DC - L3 + LLC */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \ + .l3cc_value = L3_3_WB \ + }, \ + [18] = { \ + /* Self-Snoop - L3 + LLC */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \ + .l3cc_value = L3_3_WB \ + }, \ + [19] = { \ + /* Skip Caching - L3 + LLC(12.5%) */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(7), \ + .l3cc_value = L3_3_WB \ + }, \ + [20] = { \ + /* Skip Caching - L3 + LLC(25%) */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(3), \ + .l3cc_value = L3_3_WB \ + }, \ + [21] = { \ + /* Skip Caching - L3 + LLC(50%) */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(1), \ + .l3cc_value = L3_3_WB \ + }, \ + [22] = { \ + /* Skip Caching - L3 + LLC(75%) */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(3), \ + .l3cc_value = L3_3_WB \ + }, \ + [23] = { \ + /* Skip Caching - L3 + LLC(87.5%) */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \ + .l3cc_value = L3_3_WB \ + }, \ + [62] = { \ + /* HW Reserved - SW program but never use */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ + .l3cc_value = L3_1_UC \ + }, \ + [63] = { \ + /* HW Reserved - SW program but never use */ \ + .control_value = LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ + .l3cc_value = L3_1_UC \ + }, + +static const struct drm_i915_mocs_entry icelake_mocs_table[] = { + GEN11_MOCS_ENTRIES +}; + /** * get_mocs_settings() * @dev_priv: i915 device. @@ -149,8 +281,11 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, { bool result = false; - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) || - IS_ICELAKE(dev_priv)) { + if (IS_ICELAKE(dev_priv)) { + table->size = ARRAY_SIZE(icelake_mocs_table); + table->table = icelake_mocs_table; + result = true; + } else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { table->size = ARRAY_SIZE(skylake_mocs_table); table->table = skylake_mocs_table; result = true; @@ -213,7 +348,7 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine) if (!get_mocs_settings(dev_priv, &table)) return; - GEM_BUG_ON(table.size > GEN9_NUM_MOCS_ENTRIES); + GEM_BUG_ON(table.size > NUM_MOCS_ENTRIES(dev_priv)); for (index = 0; index < table.size; index++) I915_WRITE(mocs_register(engine->id, index), @@ -227,7 +362,7 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine) * Entry 0 in the table is uncached - so we are just writing * that value to all the used entries. */ - for (; index < GEN9_NUM_MOCS_ENTRIES; index++) + for (; index < NUM_MOCS_ENTRIES(dev_priv); index++) I915_WRITE(mocs_register(engine->id, index), table.table[0].control_value); } @@ -245,18 +380,19 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine) static int emit_mocs_control_table(struct i915_request *rq, const struct drm_i915_mocs_table *table) { + struct drm_i915_private *i915 = rq->i915; enum intel_engine_id engine = rq->engine->id; unsigned int index; u32 *cs; - if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES)) + if (WARN_ON(table->size > NUM_MOCS_ENTRIES(i915))) return -ENODEV; - cs = intel_ring_begin(rq, 2 + 2 * GEN9_NUM_MOCS_ENTRIES); + cs = intel_ring_begin(rq, 2 + 2 * NUM_MOCS_ENTRIES(i915)); if (IS_ERR(cs)) return PTR_ERR(cs); - *cs++ = MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES); + *cs++ = MI_LOAD_REGISTER_IMM(NUM_MOCS_ENTRIES(i915)); for (index = 0; index < table->size; index++) { *cs++ = i915_mmio_reg_offset(mocs_register(engine, index)); @@ -271,7 +407,7 @@ static int emit_mocs_control_table(struct i915_request *rq, * Entry 0 in the table is uncached - so we are just writing * that value to all the used entries. */ - for (; index < GEN9_NUM_MOCS_ENTRIES; index++) { + for (; index < NUM_MOCS_ENTRIES(i915); index++) { *cs++ = i915_mmio_reg_offset(mocs_register(engine, index)); *cs++ = table->table[0].control_value; } @@ -304,17 +440,18 @@ static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table, static int emit_mocs_l3cc_table(struct i915_request *rq, const struct drm_i915_mocs_table *table) { + struct drm_i915_private *i915 = rq->i915; unsigned int i; u32 *cs; - if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES)) + if (WARN_ON(table->size > NUM_MOCS_ENTRIES(i915))) return -ENODEV; - cs = intel_ring_begin(rq, 2 + GEN9_NUM_MOCS_ENTRIES); + cs = intel_ring_begin(rq, 2 + NUM_MOCS_ENTRIES(i915)); if (IS_ERR(cs)) return PTR_ERR(cs); - *cs++ = MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2); + *cs++ = MI_LOAD_REGISTER_IMM(NUM_MOCS_ENTRIES(i915) / 2); for (i = 0; i < table->size/2; i++) { *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i)); @@ -333,7 +470,7 @@ static int emit_mocs_l3cc_table(struct i915_request *rq, * this will be uncached. Leave the last pair uninitialised as * they are reserved by the hardware. */ - for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) { + for (; i < NUM_MOCS_ENTRIES(i915) / 2; i++) { *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i)); *cs++ = l3cc_combine(table, 0, 0); } @@ -380,7 +517,7 @@ void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv) * this will be uncached. Leave the last pair as initialised as * they are reserved by the hardware. */ - for (; i < (GEN9_NUM_MOCS_ENTRIES / 2); i++) + for (; i < (NUM_MOCS_ENTRIES(dev_priv) / 2); i++) I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 0, 0)); } From patchwork Fri Dec 14 18:20:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 10731535 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DD116924 for ; Fri, 14 Dec 2018 18:23:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 130D62D951 for ; Fri, 14 Dec 2018 18:23:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1161A2D970; Fri, 14 Dec 2018 18:23:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 93BB12D963 for ; Fri, 14 Dec 2018 18:23:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8AE836F639; Fri, 14 Dec 2018 18:22:59 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7A68C6F636 for ; Fri, 14 Dec 2018 18:22:57 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Dec 2018 10:22:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,354,1539673200"; d="scan'208";a="259554845" Received: from pewalla-mobl1.amr.corp.intel.com (HELO ldmartin-desk.jf.intel.com) ([10.251.146.10]) by orsmga004.jf.intel.com with ESMTP; 14 Dec 2018 10:22:56 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Fri, 14 Dec 2018 10:20:21 -0800 Message-Id: <20181214182021.10483-5-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20181214182021.10483-1-lucas.demarchi@intel.com> References: <20181214182021.10483-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 4/4] drm/i915: cache number of MOCS entries X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anuj Phogat Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Instead of checking the gen number every time we need to know the max number of entries, just save it into the table struct so we don't need extra branches throughout the code. Suggested-by: Tvrtko Ursulin Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/intel_mocs.c | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index dfc4edea020f..22c5f576a3c2 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -32,6 +32,7 @@ struct drm_i915_mocs_entry { struct drm_i915_mocs_table { u32 size; + u32 n_entries; const struct drm_i915_mocs_entry *table; }; @@ -56,9 +57,6 @@ struct drm_i915_mocs_table { #define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */ #define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */ -#define NUM_MOCS_ENTRIES(i915) \ - (INTEL_GEN(i915) < 11 ? GEN9_NUM_MOCS_ENTRIES : GEN11_NUM_MOCS_ENTRIES) - /* (e)LLC caching options */ #define LE_0_PAGETABLE _LE_CACHEABILITY(0) #define LE_1_UC _LE_CACHEABILITY(1) @@ -283,14 +281,17 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, if (IS_ICELAKE(dev_priv)) { table->size = ARRAY_SIZE(icelake_mocs_table); + table->n_entries = GEN11_NUM_MOCS_ENTRIES; table->table = icelake_mocs_table; result = true; } else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { table->size = ARRAY_SIZE(skylake_mocs_table); + table->n_entries = GEN9_NUM_MOCS_ENTRIES; table->table = skylake_mocs_table; result = true; } else if (IS_GEN9_LP(dev_priv)) { table->size = ARRAY_SIZE(broxton_mocs_table); + table->n_entries = GEN9_NUM_MOCS_ENTRIES; table->table = broxton_mocs_table; result = true; } else { @@ -348,8 +349,6 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine) if (!get_mocs_settings(dev_priv, &table)) return; - GEM_BUG_ON(table.size > NUM_MOCS_ENTRIES(dev_priv)); - for (index = 0; index < table.size; index++) I915_WRITE(mocs_register(engine->id, index), table.table[index].control_value); @@ -362,7 +361,7 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine) * Entry 0 in the table is uncached - so we are just writing * that value to all the used entries. */ - for (; index < NUM_MOCS_ENTRIES(dev_priv); index++) + for (; index < table.n_entries; index++) I915_WRITE(mocs_register(engine->id, index), table.table[0].control_value); } @@ -380,19 +379,18 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine) static int emit_mocs_control_table(struct i915_request *rq, const struct drm_i915_mocs_table *table) { - struct drm_i915_private *i915 = rq->i915; enum intel_engine_id engine = rq->engine->id; unsigned int index; u32 *cs; - if (WARN_ON(table->size > NUM_MOCS_ENTRIES(i915))) + if (GEM_WARN_ON(table->size > table->n_entries)) return -ENODEV; - cs = intel_ring_begin(rq, 2 + 2 * NUM_MOCS_ENTRIES(i915)); + cs = intel_ring_begin(rq, 2 + 2 * table->n_entries); if (IS_ERR(cs)) return PTR_ERR(cs); - *cs++ = MI_LOAD_REGISTER_IMM(NUM_MOCS_ENTRIES(i915)); + *cs++ = MI_LOAD_REGISTER_IMM(table->n_entries); for (index = 0; index < table->size; index++) { *cs++ = i915_mmio_reg_offset(mocs_register(engine, index)); @@ -407,7 +405,7 @@ static int emit_mocs_control_table(struct i915_request *rq, * Entry 0 in the table is uncached - so we are just writing * that value to all the used entries. */ - for (; index < NUM_MOCS_ENTRIES(i915); index++) { + for (; index < table->n_entries; index++) { *cs++ = i915_mmio_reg_offset(mocs_register(engine, index)); *cs++ = table->table[0].control_value; } @@ -440,18 +438,17 @@ static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table, static int emit_mocs_l3cc_table(struct i915_request *rq, const struct drm_i915_mocs_table *table) { - struct drm_i915_private *i915 = rq->i915; unsigned int i; u32 *cs; - if (WARN_ON(table->size > NUM_MOCS_ENTRIES(i915))) + if (GEM_WARN_ON(table->size > table->n_entries)) return -ENODEV; - cs = intel_ring_begin(rq, 2 + NUM_MOCS_ENTRIES(i915)); + cs = intel_ring_begin(rq, 2 + table->n_entries); if (IS_ERR(cs)) return PTR_ERR(cs); - *cs++ = MI_LOAD_REGISTER_IMM(NUM_MOCS_ENTRIES(i915) / 2); + *cs++ = MI_LOAD_REGISTER_IMM(table->n_entries / 2); for (i = 0; i < table->size/2; i++) { *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i)); @@ -470,7 +467,7 @@ static int emit_mocs_l3cc_table(struct i915_request *rq, * this will be uncached. Leave the last pair uninitialised as * they are reserved by the hardware. */ - for (; i < NUM_MOCS_ENTRIES(i915) / 2; i++) { + for (; i < table->n_entries / 2; i++) { *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i)); *cs++ = l3cc_combine(table, 0, 0); } @@ -517,7 +514,7 @@ void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv) * this will be uncached. Leave the last pair as initialised as * they are reserved by the hardware. */ - for (; i < (NUM_MOCS_ENTRIES(dev_priv) / 2); i++) + for (; i < table.n_entries / 2; i++) I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 0, 0)); }