From patchwork Wed Oct 27 09:56:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12586921 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 757A3C433EF for ; Wed, 27 Oct 2021 09:58:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5C9F161052 for ; Wed, 27 Oct 2021 09:58:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241280AbhJ0KAY (ORCPT ); Wed, 27 Oct 2021 06:00:24 -0400 Received: from mail-mw2nam10on2047.outbound.protection.outlook.com ([40.107.94.47]:14433 "EHLO NAM10-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S240102AbhJ0KAV (ORCPT ); Wed, 27 Oct 2021 06:00:21 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=nZSu0fuTwffd4wX7Wji32B8lpwP5ldlFnSvNNsxEvLigI+WpdQxzR4jZenmNj7493b9QHkphzcRfgmjiG0zhanpAeFsTKn3VHaf26oQKPynN29FjGSqydqfVotJjpxvQbUUJd4BE6aC7ZvYilyTKopIbtJd/x2AtbS6KhHqa8LHlZrEh7Xh7KMHMwoC3KTFoRa2wtpP0R760w1slV+JZpe/a/Vo/QcjuWLKlQGXojVezqeGwR4wBgx1/xqA9JIT2KtpZDjMzNdx/Btbdk8MgpQBGCXKXM/keRZMhikSertljgyil8uGSjVr2IuwjNKbU8jZn1b6iQnGW3FtZJxfTGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=4WQC7MbzY4SkKjUkPCgiLuU12kLGzfDWQ2BT0ZKYN6s=; b=JUIai4tcx6lprIqCNLScUjFCIP7im/ztk8yNaSTbA5g6t0I7x6nBVy3H1qouqoRaQ1batxOqq5CHTaLoBR5xQ9VDpcFvq5hjdaHzERa1WFTlt/3dt4n7WhgWrtPxxxUhgRySGVwHvOI0wGkJaRWid3pMrE9B/59TRBCprv0Zv8qWwSCsMaL8M/M1wB/ACYbmXReIxtGway8UX9ReZJQfyzbYz7jC185vMwOKbDH1MN19BUZci2ysmvVxvrEL7rYulmfAZCvR5tRZCWuFHLMomwPWX+v9V7pdltrgdU6VpB8J1qHwDv9b8ja7BdMYDFGSOOx4tAEeQJVHusDPOswjkg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.32) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4WQC7MbzY4SkKjUkPCgiLuU12kLGzfDWQ2BT0ZKYN6s=; b=Ch/cyvte/fhwXCo8q1JtBHym2oxcXcXfr5zbDrKCvxXh1L8GOadlDo+v5ws80TNj/dBFVSDWQRaLxkBZ/On3IOgaBEUilcWTJ4rJWOKMUZ4/+CVRoCYvtVVCH+M4FgTKs7Bd59Upf1msfCiyhcbCfrvGpvr6X7k92Y/s/r+hPE4r19y7vMlcxfavln/jSalvZgC7p0jvLjDAQgQwyZzKPkTEmIB7yVZpKTtzZGJwhvvH0AfCmOPSdqUm3DrGsyk07s0OijvaJkQwWh850T3yr8xX3DNBB1EJSRm+gphJnIUdG9HDrxtTb/eQfMTi9tX0aXcDebmusr4IwA/5WAyW/Q== Received: from DS7PR06CA0025.namprd06.prod.outlook.com (2603:10b6:8:54::31) by BL0PR12MB4993.namprd12.prod.outlook.com (2603:10b6:208:17e::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.16; Wed, 27 Oct 2021 09:57:55 +0000 Received: from DM6NAM11FT055.eop-nam11.prod.protection.outlook.com (2603:10b6:8:54:cafe::58) by DS7PR06CA0025.outlook.office365.com (2603:10b6:8:54::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.14 via Frontend Transport; Wed, 27 Oct 2021 09:57:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.32) smtp.mailfrom=nvidia.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.32 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.32; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.32) by DM6NAM11FT055.mail.protection.outlook.com (10.13.173.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4649.14 via Frontend Transport; Wed, 27 Oct 2021 09:57:54 +0000 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 27 Oct 2021 02:57:54 -0700 Received: from vdi.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 27 Oct 2021 09:57:51 +0000 From: Yishai Hadas To: , , , CC: , , , , , , , , Subject: [PATCH V5 mlx5-next 01/13] PCI/IOV: Add pci_iov_vf_id() to get VF index Date: Wed, 27 Oct 2021 12:56:46 +0300 Message-ID: <20211027095658.144468-2-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211027095658.144468-1-yishaih@nvidia.com> References: <20211027095658.144468-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 16d097c2-279e-42d5-30eb-08d999303f51 X-MS-TrafficTypeDiagnostic: BL0PR12MB4993: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: q9yfiEuse/Xqn7sWZziWJ4Ib6IxJJtVgC9XHRU53VndeOj8aGzmkNtZX+jSxL2VTyFX7gzrlEpW9HMQC+2QNTRbiGLhNhxBVJFyG4kZo6gyCsk5Cy/WZbesA97ZY2AGYk3IGvDpEV91bR5lq5QgX7PCrBz1u5eWt9rgtVFsC6hD25HaPGnPf2gYx6CJDVP4oxRwh6cK3rqWpf3Maz8cZEF0R8hps3cB6ZI4jRwv+lSCLoL57T17gzNJoO5vmzFXUdoE5+/8HogzCLYRQPyDcHcuhcGL1h0cnmrlk1QT86mxLmdz2UjfiA8a+MfxlgPAKGOeLFYCk0BGFfou3gx5Sz9iL4UduyX0VjmwEJXjmygHx4WJTtsIkGIELGlBVcBKcCIPdnlxnAIYF4c6vZLIbPjmfvf9HE7sA5/SgBiuzUamzx/OVbiV4NdnF0XKIeQVRyRWE7BzjMRXu73HPXhJdJ/Yu83xkUDOu9w/doi6nL5OKOdEgcjvgBcGxtgC+jcpyXSIV18cXGocjPH0GVdxP/DtG3WTYGI+404WF1uZoUX8JL7W7v2UtoJpGqC+vg9+gc4th09MMDLtjvE4y28z/9X9S6esNg/ta+H6fwMymnHaMxo2BTyrfNleceuZwTodCUhqK2c+Zt7faSc+sjc9iUiOjGQPkB2qNfV95uCA1NVgYzPl1oBlGHlMValblnz6Ik28ocbi+QWIBIELY6BStvA== X-Forefront-Antispam-Report: CIP:216.228.112.32;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid01.nvidia.com;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(2906002)(7696005)(82310400003)(83380400001)(7636003)(1076003)(110136005)(186003)(2616005)(8676002)(4326008)(36860700001)(5660300002)(356005)(6636002)(426003)(26005)(336012)(47076005)(70586007)(86362001)(107886003)(316002)(6666004)(508600001)(36756003)(70206006)(8936002)(54906003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2021 09:57:54.8172 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 16d097c2-279e-42d5-30eb-08d999303f51 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.32];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4993 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Jason Gunthorpe The PCI core uses the VF index internally, often called the vf_id, during the setup of the VF, eg pci_iov_add_virtfn(). This index is needed for device drivers that implement live migration for their internal operations that configure/control their VFs. Specifically, mlx5_vfio_pci driver that is introduced in coming patches from this series needs it and not the bus/device/function which is exposed today. Add pci_iov_vf_id() which computes the vf_id by reversing the math that was used to create the bus/device/function. Signed-off-by: Yishai Hadas Signed-off-by: Jason Gunthorpe Acked-by: Bjorn Helgaas Signed-off-by: Leon Romanovsky --- drivers/pci/iov.c | 14 ++++++++++++++ include/linux/pci.h | 8 +++++++- 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index dafdc652fcd0..e7751fa3fe0b 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -33,6 +33,20 @@ int pci_iov_virtfn_devfn(struct pci_dev *dev, int vf_id) } EXPORT_SYMBOL_GPL(pci_iov_virtfn_devfn); +int pci_iov_vf_id(struct pci_dev *dev) +{ + struct pci_dev *pf; + + if (!dev->is_virtfn) + return -EINVAL; + + pf = pci_physfn(dev); + return (((dev->bus->number << 8) + dev->devfn) - + ((pf->bus->number << 8) + pf->devfn + pf->sriov->offset)) / + pf->sriov->stride; +} +EXPORT_SYMBOL_GPL(pci_iov_vf_id); + /* * Per SR-IOV spec sec 3.3.10 and 3.3.11, First VF Offset and VF Stride may * change when NumVFs changes. diff --git a/include/linux/pci.h b/include/linux/pci.h index cd8aa6fce204..2337512e67f0 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2153,7 +2153,7 @@ void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); #ifdef CONFIG_PCI_IOV int pci_iov_virtfn_bus(struct pci_dev *dev, int id); int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); - +int pci_iov_vf_id(struct pci_dev *dev); int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); void pci_disable_sriov(struct pci_dev *dev); @@ -2181,6 +2181,12 @@ static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) { return -ENOSYS; } + +static inline int pci_iov_vf_id(struct pci_dev *dev) +{ + return -ENOSYS; +} + static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) { return -ENODEV; } From patchwork Wed Oct 27 09:56:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12586923 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C569C433EF for ; Wed, 27 Oct 2021 09:58:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3E410610A3 for ; Wed, 27 Oct 2021 09:58:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241284AbhJ0KAd (ORCPT ); Wed, 27 Oct 2021 06:00:33 -0400 Received: from mail-mw2nam12on2058.outbound.protection.outlook.com ([40.107.244.58]:42159 "EHLO NAM12-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241290AbhJ0KA0 (ORCPT ); Wed, 27 Oct 2021 06:00:26 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ewU+aT3VmqWGb3FecN9qzsrWotUW+liVVNKvxWitaqjob2jUI80/lS/jKkakhi5IiRQfeVzyAUXNtErXRC4pJLCTDYfFMB/PUhGCP4QgW/dHPqFsmYJxPtNVDuMC+Pd7jDR/x5MVZJr8HpqTHmgHVGpzTeFACzp9hY8+HWcsaeSmq/y3CxUOvzTIpJ2TAEOQ31Y9OTlnVSqlhPzq9IrNMdap3EFhexv8syuzBxuI1dYlUIAh0DGjerfi5ByvrwxYxuWJOo/8GcjjpAgOZaKyWu9tR7cBQ3Ula8d4o75A9ynVjU866CQUILcFcf8UhgLmJkcE0eOUPXnFoIUTvcGP0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=eawxF+jFRBAH1P9hWq5BE145QVmYPfYNp1U9MJCuY0E=; b=geb+HRqcCZrN7WBiB0CYW1sKVTzUQ3zDvPJ8BPAGKYF/CouvIfPBdB0tQu3HLpoYnPZgB8E9ZqO3Queu/xT+rZpJcOpI5Em+Jz16j2CSWSLz5rHPvkEqwAhg0hEYpxtP61txSZ7jkH7KH2satmJT0xdbYqgBoLukIehrV1I1pwBtJIydp4vOIMfbuNk20WeUWht7r6AAZ5wImhkBOHnjcmFtVLF8ewybW/cgH8ktxGgBDYjj7h4VQ8HAYObuDtYtJ4big4rDbdMIelSZ0GWBHjZiZUB7cQsGAK2dDM/LIDoVsEF7V5QmQ9ssyVQHAvE7w1Z1O9nidRfOCsjx+OP/3A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=eawxF+jFRBAH1P9hWq5BE145QVmYPfYNp1U9MJCuY0E=; b=WQ/jpE5fU4wWQEHQ9gBoPDU+FpY7LWeVXvgajDpl/sksMi/TJJyXPMhiJjEOVcjlFOK8+8EujLbGH64az3vYhfq2lSVU66BadJbbX//a0eP6ZfRWBTToZZRbm0yuZfTcA9Ii9wKrhEiOAdmwmfrM0+HMqNnWG12pJg+NFFC4x53n6W+OUqMvoGQZGJnxCC3AupDxAzkXkmvGQDRyr+mSQIUuICPdggx5GhGhXhR+mstaZeTDCm9TRWQ7NRaKi8jfHiEbA0/P7UGKnWob+CgiGM/4eiLHVboOtUMwffzNsdoBLuuGEzlBUzOTis/s0x11kp+wKje1vU7MxA834OHHqg== Received: from DM5PR07CA0156.namprd07.prod.outlook.com (2603:10b6:3:ee::22) by MW3PR12MB4571.namprd12.prod.outlook.com (2603:10b6:303:5c::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.15; Wed, 27 Oct 2021 09:58:00 +0000 Received: from DM6NAM11FT054.eop-nam11.prod.protection.outlook.com (2603:10b6:3:ee:cafe::f9) by DM5PR07CA0156.outlook.office365.com (2603:10b6:3:ee::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.13 via Frontend Transport; Wed, 27 Oct 2021 09:57:59 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT054.mail.protection.outlook.com (10.13.173.95) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4649.14 via Frontend Transport; Wed, 27 Oct 2021 09:57:59 +0000 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 27 Oct 2021 09:57:57 +0000 Received: from vdi.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 27 Oct 2021 09:57:54 +0000 From: Yishai Hadas To: , , , CC: , , , , , , , , Subject: [PATCH V5 mlx5-next 02/13] net/mlx5: Reuse exported virtfn index function call Date: Wed, 27 Oct 2021 12:56:47 +0300 Message-ID: <20211027095658.144468-3-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211027095658.144468-1-yishaih@nvidia.com> References: <20211027095658.144468-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ef8d0f48-8ed3-4e25-1af6-08d9993041fa X-MS-TrafficTypeDiagnostic: MW3PR12MB4571: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3826; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HKqrBflGYj/LmTzLsDKDJOOYJwbplTSWc/0Hkth35MRyUC0UjcjSaq7ttJW7e1MXky7eaujC3RkprFCIDg9zEMGarpk9TCN8/lgZiemK8TYyjiWCDF54CBBRRv+t88lmjDYe1xu/IwY9mqNEX0Y0lGWDLl8JH/m7SXtzu4BvpniEMWgu5jcLjIIZRdhnYWmNAeGbEFtUEnVTz1CeqlrpplHmYg8DHc89jI2h17na3widwML//N63Q03v/P/8+6I4NcrFuuWLuEcpf7wtutEXahMmnEJssQ6Dc7oHWIakrFpNljDP+KOAu8wCc8Rp9IvKCheNC+vJLDLO2RRiB8iwQLDPk1KF3heN0p+ASOOL00NP6IlLyT0lzzq449Gbyp4TG7KqVDx86U4VqyZm6a2bRAPde9mcbXA9Xt0pA+Bcmd995RshlJO2KooFF8NZ0Ii4XaKnpdnPL5T6por6nAHVvUgFnEFM78hZkb41gdIZryPwxJCt9Sk4Pl14udUCBtEJLEGHqid4x21eEmVsY1kL/YRFfm3L2VTFQhIU8FKRmONKixqaJ1bkhrU3RghrT1Y3TjH6kIYNR5eRY/pUZ4XbXJNhjUEmE7oiCHK3nOz7Bdh0g21KsxMhkfN+6PrZFnG2adM42Ew6xwrKH++zJOknUEKdZuVe+5ywo66NcAuUiq0iIEh2STdolprpFXZSheyF7b/Tl3cvY5WxHNiMEG6T4Q== X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(8936002)(2906002)(5660300002)(6636002)(47076005)(70586007)(6666004)(70206006)(7696005)(316002)(8676002)(186003)(83380400001)(36756003)(4326008)(110136005)(54906003)(36860700001)(82310400003)(86362001)(7636003)(356005)(1076003)(336012)(508600001)(26005)(2616005)(107886003)(426003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2021 09:57:59.2936 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ef8d0f48-8ed3-4e25-1af6-08d9993041fa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4571 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Leon Romanovsky Instead open-code iteration to compare virtfn internal index, use newly introduced pci_iov_vf_id() call. Signed-off-by: Leon Romanovsky Signed-off-by: Yishai Hadas --- drivers/net/ethernet/mellanox/mlx5/core/sriov.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sriov.c b/drivers/net/ethernet/mellanox/mlx5/core/sriov.c index e8185b69ac6c..24c4b4f05214 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sriov.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/sriov.c @@ -205,19 +205,8 @@ int mlx5_core_sriov_set_msix_vec_count(struct pci_dev *vf, int msix_vec_count) mlx5_get_default_msix_vec_count(dev, pci_num_vf(pf)); sriov = &dev->priv.sriov; - - /* Reversed translation of PCI VF function number to the internal - * function_id, which exists in the name of virtfn symlink. - */ - for (id = 0; id < pci_num_vf(pf); id++) { - if (!sriov->vfs_ctx[id].enabled) - continue; - - if (vf->devfn == pci_iov_virtfn_devfn(pf, id)) - break; - } - - if (id == pci_num_vf(pf) || !sriov->vfs_ctx[id].enabled) + id = pci_iov_vf_id(vf); + if (id < 0 || !sriov->vfs_ctx[id].enabled) return -EINVAL; return mlx5_set_msix_vec_count(dev, id + 1, msix_vec_count); From patchwork Wed Oct 27 09:56:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12586925 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CD56C43219 for ; Wed, 27 Oct 2021 09:58:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 376E9610A3 for ; Wed, 27 Oct 2021 09:58:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241290AbhJ0KAe (ORCPT ); Wed, 27 Oct 2021 06:00:34 -0400 Received: from mail-dm6nam10on2086.outbound.protection.outlook.com ([40.107.93.86]:50912 "EHLO NAM10-DM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241300AbhJ0KA3 (ORCPT ); Wed, 27 Oct 2021 06:00:29 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=C+OwOjn8iEv6aVOuHyh2fA728rtouI9biskqYckhKut2BOWBoTpVSmlxa9NqQNVqUYI6QhZwcNYW6VcruUkf4wc9nkbRo8ZpBzs+kOfwBgbe48fHefb2ody2EH8tRQkzHUoJfbHJt3a1RoNPubnl0c5Tw9KFYS9kXhSM6ja0z3AWVfN5Jg6Z8ZDlf3tIRuPqcoAMBU/GLci222DLYguf+zLx+dfp/pQrV+0ZMu682V1PFZ9NbEeOw73U0vpNLkgJ7zAloZh8ufbb1mz23EOd1FZKyf23hFpobmVNAkkhGv+0xjatJkPUu1MaQk5cO/zezr/E1PNj5l+SqEnBfUYFww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ATQOdGVF4dTjbvMJ1bmmazMNjFwWqMg4M5PKqHqf20k=; b=KBTcXXnUaOcclEnqNb29D6M1WHp5QWYLUJ4jPKT63wCVTgtgCoS/IkPo5mF4L0EbiWehkm9duX4HZgSyb+WpJkRMH9/S5XGeGEJm6/CIdS0pPtIFd/BAWZoYkhFw++WHx1zKvykQzpItRFixn4MFWFmI72SAuKKKspa940ijGwkd/1UvVLKrNvB9cbAuNv9VKC09XxC6LvMykHeb1k3Fi6jzH/1y9sXtIcq2pQ7hNL2T5m4g2w2O89UE4iJNJCievHC2gq2pB6T82iKia6oWNYvkFnciPsTOFEknh2Rr1inPZnd7Ld5H9k2e0Ck6OSYaqmInHG2J9H9oVo8oOuYC4g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.35) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ATQOdGVF4dTjbvMJ1bmmazMNjFwWqMg4M5PKqHqf20k=; b=TAG/Cjw+eJNDFhJMKJfc7WPd0yPrAxhhDsoBO5f4AsPLcjIxfTmYhxZLjK3JeWiVVeselFy3EAp9h5C5LsviilRiQvqmC1lchoZTI0ukqHdgAcCv+ibi9rUuWsYcG2AIHdY+YK30qjCIA5EHcfBt4XJXJ3BpOxNJQ6acAteotmn4XiN6kVTk7vPOFm46/HzAUEdoyI4gYxiiLw+QSGUbxiRa7RIBAlV0cqT4PdKIfSJXypwynBKLRlvFgnXjscs88TfNThA8x5JRbcV7+w3Ky95vkQmjtogmFWnEQa//I2FOR6/nzrEhbChjOLwQjoDfzyezdxcNpYR8O0xuKzwESw== Received: from BN9PR03CA0239.namprd03.prod.outlook.com (2603:10b6:408:f8::34) by BL1PR12MB5380.namprd12.prod.outlook.com (2603:10b6:208:314::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.18; Wed, 27 Oct 2021 09:58:02 +0000 Received: from BN8NAM11FT038.eop-nam11.prod.protection.outlook.com (2603:10b6:408:f8:cafe::4b) by BN9PR03CA0239.outlook.office365.com (2603:10b6:408:f8::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.16 via Frontend Transport; Wed, 27 Oct 2021 09:58:02 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.35) smtp.mailfrom=nvidia.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.35 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.35; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.35) by BN8NAM11FT038.mail.protection.outlook.com (10.13.176.246) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4649.14 via Frontend Transport; Wed, 27 Oct 2021 09:58:02 +0000 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 27 Oct 2021 09:58:01 +0000 Received: from vdi.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 27 Oct 2021 09:57:58 +0000 From: Yishai Hadas To: , , , CC: , , , , , , , , Subject: [PATCH V5 mlx5-next 03/13] net/mlx5: Disable SRIOV before PF removal Date: Wed, 27 Oct 2021 12:56:48 +0300 Message-ID: <20211027095658.144468-4-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211027095658.144468-1-yishaih@nvidia.com> References: <20211027095658.144468-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 74946f44-0a65-427b-5279-08d9993043bc X-MS-TrafficTypeDiagnostic: BL1PR12MB5380: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZqxDxRT7Q4MZzeA+ytdmJHgZN8yWevakJ+Opga+TS9YPgNS6qALu1NfAq3hsJ2wv4D67I5SuHQNWP8vSnV4PT7qZ1iN5Cn2CdJ9JITye5a40R9g87zi2Wv9TV9VoUVJzYuZQYxWR7Lt4MwAcpdvLdGuMJbQpYylTZku91PfdNT2/kIx8UjU4GY62amd9xWcRBxo9I39wdlmabr+zDrofTV+Nfuq61cJ2tE4IjALLEEeKJPfaczpOtMKid3t/eMZvZTJakEiVmDstKpbbJ6IFbc1Is2pbH84/AS2dtB2VLkyM+RNFtReiWhO3uijObvZTrG+HYaHuMJ6Ksj96+m5DmsUiNnWNimv6+zklwjZCmJAWyoCRZSt4VFjtZZbRX0YOgbPj6PkDecjs0GXevt5RXHNp1xn3ZYx9LHcv9yRI8DCUpe26x3/ZyszEnmEq/VV1NwfgegDWNMLzQlVmeSPNEkuV54wnXp7HtuN6p522diqEArp9ZPlhyQVsOpCkVPv7nNvlht2N1lkjkCkpwPYAlH8NSNOR4izI+awFJC8zC0XgKHSptPSkh4TtyJn31mb9n2L9L23z4Wb2AxQJFWD2VfY3FfFPSO0XNKatdk4FiIqL2woTYtH0JJxKhi4gpg1jyRfnLQGstZjs+JjBA/Wjyj7Kg1VwqhtPZfVJyTfzK5qku1HxjIu000r9vVewU0aWxrt7TUnfktNV/BVmL/9NBw== X-Forefront-Antispam-Report: CIP:216.228.112.35;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid04.nvidia.com;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(47076005)(356005)(508600001)(83380400001)(2906002)(70586007)(1076003)(7636003)(70206006)(26005)(107886003)(4326008)(82310400003)(8676002)(8936002)(7696005)(54906003)(36756003)(2616005)(110136005)(316002)(426003)(86362001)(186003)(5660300002)(6636002)(6666004)(336012)(36860700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2021 09:58:02.1872 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 74946f44-0a65-427b-5279-08d9993043bc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.35];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5380 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Virtual functions depend on physical function for device access (for example firmware host PAGE management), so make sure to disable SRIOV once PF is gone. This will prevent also the below warning if PF has gone before disabling SRIOV. "driver left SR-IOV enabled after remove" Next patch from this series will rely on that when the VF may need to access safely the PF 'driver data'. Signed-off-by: Yishai Hadas Signed-off-by: Leon Romanovsky --- drivers/net/ethernet/mellanox/mlx5/core/main.c | 1 + drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h | 1 + drivers/net/ethernet/mellanox/mlx5/core/sriov.c | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index 79482824c64f..0b9a911acfc1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -1558,6 +1558,7 @@ static void remove_one(struct pci_dev *pdev) struct mlx5_core_dev *dev = pci_get_drvdata(pdev); struct devlink *devlink = priv_to_devlink(dev); + mlx5_sriov_disable(pdev); devlink_reload_disable(devlink); mlx5_crdump_disable(dev); mlx5_drain_health_wq(dev); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h index 230eab7e3bc9..f21d64416f7f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -140,6 +140,7 @@ void mlx5_sriov_cleanup(struct mlx5_core_dev *dev); int mlx5_sriov_attach(struct mlx5_core_dev *dev); void mlx5_sriov_detach(struct mlx5_core_dev *dev); int mlx5_core_sriov_configure(struct pci_dev *dev, int num_vfs); +void mlx5_sriov_disable(struct pci_dev *pdev); int mlx5_core_sriov_set_msix_vec_count(struct pci_dev *vf, int msix_vec_count); int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id); int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sriov.c b/drivers/net/ethernet/mellanox/mlx5/core/sriov.c index 24c4b4f05214..887ee0f729d1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sriov.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/sriov.c @@ -161,7 +161,7 @@ static int mlx5_sriov_enable(struct pci_dev *pdev, int num_vfs) return err; } -static void mlx5_sriov_disable(struct pci_dev *pdev) +void mlx5_sriov_disable(struct pci_dev *pdev) { struct mlx5_core_dev *dev = pci_get_drvdata(pdev); int num_vfs = pci_num_vf(dev->pdev); From patchwork Wed Oct 27 09:56:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12586927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DB2DC4332F for ; Wed, 27 Oct 2021 09:58:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5DF96610CB for ; Wed, 27 Oct 2021 09:58:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241308AbhJ0KAg (ORCPT ); Wed, 27 Oct 2021 06:00:36 -0400 Received: from mail-dm6nam10on2070.outbound.protection.outlook.com ([40.107.93.70]:1761 "EHLO NAM10-DM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S237126AbhJ0KAc (ORCPT ); Wed, 27 Oct 2021 06:00:32 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=KsZSGP4K+3GrWz8SfcXHGPMwIaheA2eYTNbtNmNw1Uce1iCQaklkXZBOiol2iixSBFaFAK3Qtbo+F6kU/EFuzTCuS6fIx9jDGmPtszCP/un6IXuoeGoLgsh+H/eeIYnBUXsEMouQoarCzFb+3gW8gRme8jB3VOI41o3N9o7iFp6sf04qIJEO5YUZXOLqQZwI8YB4xWAObq9ezShgQnrta+FkvdWIm5g63E2C6vrj7mUNryH48w+D/D1HLEm9199LhVzoO5QvDTkWkMVUMk6qpjuZIv1ZtSW9AMlB06jWCLvizLrn8PAVNHVvhh8eeUgtkMcSs9ySsz3KYdDWgkzcBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PX8vNibUQ+77tQfzz+YEsNNh/fZeI9f68zyWZiZWxw8=; b=aCsjrCEoA9BYlQaqZbZ2Ua+7srm5X47JDNcLRA1MmQ6/jBPa1SqUGkK91BARhUGXt6knc3DUAbkon7LYCCLJet8TmMSonr2dEfrvFzsl6DAVamMz84sgutP3ydaZkGHR87Uf6cRivWhinxaBKutNHaNVfZn9L8uT8juhBei3n27Q8d0RWurcWsOwDbQZpn2pg0Hg7YWIIF9ySXDcxJCdaenybLumvE1SdJsdQcOPQfkI8ZMyAZ43TI2r12AgY5bSbsmFV5XxE8sizXNphEMmZAqt0BIfWNs1L96NHBqR1F8wiJTY4/NbaTj3avf+Ms0nU4TSgR49YIJpXTF9bQH2DQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PX8vNibUQ+77tQfzz+YEsNNh/fZeI9f68zyWZiZWxw8=; b=cQmGflL3BQI7IT2EwBZGDGjF0GCRL+37ScZkcAGzdIWkradbKIKIFY8B5E/bvWOmCMdNOYZs15sVnODIFeJ3hSjGdTdkEP0b+pzztzAqenJxhFy6GIdzard8MoAbAE3b4XS5yAskw1XYiT4Bec8XHlLzeKShYAIaXiorfV8fW2nWmzsDoXduedCftbYNE8QJ4+Zz6m+eBV7YqxhBCj7UqfmbFjGzCOGzBkHBJzKb82ptuk5Epgnq5vWERJP7TfvxMyY1HjdwrJ2GDjAfibQTNeCPTK1g6EEi/Kenbe7kDwnJBHtQ3we9avRi0q5fuHwksIqWRxRV10UYTc24WSrpGQ== Received: from DM6PR11CA0051.namprd11.prod.outlook.com (2603:10b6:5:14c::28) by PH0PR12MB5497.namprd12.prod.outlook.com (2603:10b6:510:eb::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.18; Wed, 27 Oct 2021 09:58:05 +0000 Received: from DM6NAM11FT044.eop-nam11.prod.protection.outlook.com (2603:10b6:5:14c:cafe::6c) by DM6PR11CA0051.outlook.office365.com (2603:10b6:5:14c::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.14 via Frontend Transport; Wed, 27 Oct 2021 09:58:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT044.mail.protection.outlook.com (10.13.173.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4649.14 via Frontend Transport; Wed, 27 Oct 2021 09:58:05 +0000 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 27 Oct 2021 09:58:04 +0000 Received: from vdi.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 27 Oct 2021 09:58:01 +0000 From: Yishai Hadas To: , , , CC: , , , , , , , , Subject: [PATCH V5 mlx5-next 04/13] PCI/IOV: Add pci_iov_get_pf_drvdata() to allow VF reaching the drvdata of a PF Date: Wed, 27 Oct 2021 12:56:49 +0300 Message-ID: <20211027095658.144468-5-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211027095658.144468-1-yishaih@nvidia.com> References: <20211027095658.144468-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 85387722-f879-4503-6e79-08d99930457a X-MS-TrafficTypeDiagnostic: PH0PR12MB5497: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MpWyJkcnGhJccs/g1BzU27cagWvJt0xLFycQ2LBRTD3FRvl8/1baDVnUR7UX7C0BTukaCglaynT9e+yFoYinCjTqav0/1U9MXJsp6BS/zg1qMt+JlcRRsr/KLsCZZUG0mcWRUQjmjxVpMMHm8O7IBzwqVbMVLRVeM4a9rRmdonoZUn36QzYuxGuVRxBH9pBIkZemLwz0UGj3KSNvCsOxmGf6Z1zAyEdx3PNA7bj11RoLZO5e5evru88xeyPQRyAJ26hxxLRrVWqMTIzfrAa43udV+my9fOtCBpwvb37jxZ5D32RQLLcoHgX1Vd8ZcankfLLCdUxE2VGraqMSuW6JRiqgFcHPH30WLPt0/BT4XNSjmCPrXMpejF2oxmXgE+XgRLbBhM+NYH+7QoYt4tffDEdczl+C+fI/yF63R3CXoSOyQlnEVCamp9b3TugPW3XxIXb8VMGmgsxxJvFIE6ZGkOAz0M9vCYjKpfjyx6gkKhZgv++lO7R6llW6/m9LoWdWCCX1OK/2/BSt2KQc0foVkvewmtmc7os/abq/mG+vReUyYoAAptjn3LnmJWube46rAtcc/uv2LP+xJmkswqa7xsrq6Err5kL0ZjsVRh9nl9cU4tXBNZ1aLtEBJltjC/u1lReY5rEI/S6Lv5PjdBQ1HZLtvLIVDVnxNiFSwZdIj800pxthaWnMkPODTSHlqyJ8SM7qGC94QA/CYxTIwENTdA== X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(86362001)(82310400003)(36756003)(36860700001)(6636002)(110136005)(70206006)(7696005)(54906003)(107886003)(83380400001)(336012)(4326008)(36906005)(186003)(26005)(47076005)(8936002)(1076003)(8676002)(5660300002)(6666004)(426003)(7636003)(356005)(508600001)(2906002)(70586007)(316002)(2616005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2021 09:58:05.1757 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 85387722-f879-4503-6e79-08d99930457a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5497 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Jason Gunthorpe There are some cases where a SR-IOV VF driver will need to reach into and interact with the PF driver. This requires accessing the drvdata of the PF. Provide a function pci_iov_get_pf_drvdata() to return this PF drvdata in a safe way. Normally accessing a drvdata of a foreign struct device would be done using the device_lock() to protect against device driver probe()/remove() races. However, due to the design of pci_enable_sriov() this will result in a ABBA deadlock on the device_lock as the PF's device_lock is held during PF sriov_configure() while calling pci_enable_sriov() which in turn holds the VF's device_lock while calling VF probe(), and similarly for remove. This means the VF driver can never obtain the PF's device_lock. Instead use the implicit locking created by pci_enable/disable_sriov(). A VF driver can access its PF drvdata only while its own driver is attached, and the PF driver can control access to its own drvdata based on when it calls pci_enable/disable_sriov(). To use this API the PF driver will setup the PF drvdata in the probe() function. pci_enable_sriov() is only called from sriov_configure() which cannot happen until probe() completes, ensuring no VF races with drvdata setup. For removal, the PF driver must call pci_disable_sriov() in its remove function before destroying any of the drvdata. This ensures that all VF drivers are unbound before returning, fencing concurrent access to the drvdata. The introduction of a new function to do this access makes clear the special locking scheme and the documents the requirements on the PF/VF drivers using this. Signed-off-by: Jason Gunthorpe Acked-by: Bjorn Helgaas Signed-off-by: Leon Romanovsky Signed-off-by: Yishai Hadas --- drivers/pci/iov.c | 29 +++++++++++++++++++++++++++++ include/linux/pci.h | 7 +++++++ 2 files changed, 36 insertions(+) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index e7751fa3fe0b..8c724bc134c7 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -47,6 +47,35 @@ int pci_iov_vf_id(struct pci_dev *dev) } EXPORT_SYMBOL_GPL(pci_iov_vf_id); +/** + * pci_iov_get_pf_drvdata - Return the drvdata of a PF + * @dev - VF pci_dev + * @pf_driver - Device driver required to own the PF + * + * This must be called from a context that ensures that a VF driver is attached. + * The value returned is invalid once the VF driver completes its remove() + * callback. + * + * Locking is achieved by the driver core. A VF driver cannot be probed until + * pci_enable_sriov() is called and pci_disable_sriov() does not return until + * all VF drivers have completed their remove(). + * + * The PF driver must call pci_disable_sriov() before it begins to destroy the + * drvdata. + */ +void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver) +{ + struct pci_dev *pf_dev; + + if (!dev->is_virtfn) + return ERR_PTR(-EINVAL); + pf_dev = dev->physfn; + if (pf_dev->driver != pf_driver) + return ERR_PTR(-EINVAL); + return pci_get_drvdata(pf_dev); +} +EXPORT_SYMBOL_GPL(pci_iov_get_pf_drvdata); + /* * Per SR-IOV spec sec 3.3.10 and 3.3.11, First VF Offset and VF Stride may * change when NumVFs changes. diff --git a/include/linux/pci.h b/include/linux/pci.h index 2337512e67f0..639a0a239774 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2154,6 +2154,7 @@ void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); int pci_iov_virtfn_bus(struct pci_dev *dev, int id); int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); int pci_iov_vf_id(struct pci_dev *dev); +void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver); int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); void pci_disable_sriov(struct pci_dev *dev); @@ -2187,6 +2188,12 @@ static inline int pci_iov_vf_id(struct pci_dev *dev) return -ENOSYS; } +static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev, + struct pci_driver *pf_driver) +{ + return ERR_PTR(-EINVAL); +} + static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) { return -ENODEV; } From patchwork Wed Oct 27 09:56:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12586929 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EDDDC433EF for ; Wed, 27 Oct 2021 09:58:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F344161052 for ; Wed, 27 Oct 2021 09:58:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241300AbhJ0KAs (ORCPT ); Wed, 27 Oct 2021 06:00:48 -0400 Received: from mail-dm6nam11on2089.outbound.protection.outlook.com ([40.107.223.89]:45624 "EHLO NAM11-DM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241309AbhJ0KAi (ORCPT ); Wed, 27 Oct 2021 06:00:38 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Gq9BjPFZ/8yDm3hmjaMOec4RtH83GvA/mKll6Zv0a+BgCMx3cmfXqOn2iqzp3lw/Hcczqi7N/FWZ3uZrY46rp0vBqcsGWBUFrojAi0Q0nlxv5KuSV3m8Y6ZplXMDaQvDtRLtptvLcXMy3f9WYcrbvLwxRt2Yddu1rLHj/fOFD7FpNK1eVsNbiOUIKiJGJ6lI64HxS9T/VfkUBZA3Zpmt1tixw1lAVm2P+j4izNXaj2iV0/Tkv4jsWcDZ1Kzi/QgKLm3qzMGx3MY04i5WrSb2XMDVmtcwyR0kbyCXXLqVK6chiZZAD6CoUEWFY+YJtszvJ/IdMUA4L4bx5pLwK1F/wg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0Rg93GuPxk5N0KtlMyEKO/efa5SGHQlpbOGoEZBLbxs=; b=WSCow8DFZfy+E2RsnPr/dJ2nIrvxfFc4DF6xCaPzAN8IIub7oBSo63ePQESFHRKuSySl2lbKBucKzBhemoxvH12gEP2AYg/46WQZgopNY598cSFtzIoc+BjoF3JLRSWdAf06qJWmEVCw/0q5+ggTJzGCperiT1WbuYXK9cH6+laMsvhv0Y8MxGhwPJfr0pezMFnbAF1TJTxFZZ6hTQLx5MVgvqnoGtjw5b8BJ7EPojlmPWghlwnIxbzVCC0NJlQolmEAN1j7nws/bZ293Pmw9/MOmUi8leysbsjgIgCvEbhfjfAvUXX9tvnX7TrviDFy4+xRWB+23vGwbM9k54W6CA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.35) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0Rg93GuPxk5N0KtlMyEKO/efa5SGHQlpbOGoEZBLbxs=; b=oOgj721RkdAhF6AGLEYARgA2D/Fa9+VmBXV/q9KA8i80dUiHQnkABu1NxXBGr7Ysro7Nrm/ihvfnkCiEYwzaCHD+p5jTz8zsFjjP/ygB+rGiQFRcS441xg5C8NMqLmIfuPKnDUnKbqA9ikxYy9pvufkKVSRsnPUPFillcMZOjXTWkF9VOuRut89clYAGTviEKQpXE0VqVP5J4uCnu+4ZXCjzekQ9qQk5dL4LoI8yDHnpG4SLF9JbU/9rxqDbC2OC1T1cJqcqzHXXd1iYyX81lPfvKgF3Za17estyKy//WXInja8CAMMcMo2dRD8XUvnb8W4y9+0u58SyfF9Q9tevHg== Received: from BN9P223CA0021.NAMP223.PROD.OUTLOOK.COM (2603:10b6:408:10b::26) by MN2PR12MB4535.namprd12.prod.outlook.com (2603:10b6:208:267::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.18; Wed, 27 Oct 2021 09:58:09 +0000 Received: from BN8NAM11FT045.eop-nam11.prod.protection.outlook.com (2603:10b6:408:10b:cafe::e3) by BN9P223CA0021.outlook.office365.com (2603:10b6:408:10b::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.22 via Frontend Transport; Wed, 27 Oct 2021 09:58:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.35) smtp.mailfrom=nvidia.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.35 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.35; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.35) by BN8NAM11FT045.mail.protection.outlook.com (10.13.177.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4649.14 via Frontend Transport; Wed, 27 Oct 2021 09:58:09 +0000 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 27 Oct 2021 09:58:07 +0000 Received: from vdi.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 27 Oct 2021 09:58:04 +0000 From: Yishai Hadas To: , , , CC: , , , , , , , , Subject: [PATCH V5 mlx5-next 05/13] net/mlx5: Expose APIs to get/put the mlx5 core device Date: Wed, 27 Oct 2021 12:56:50 +0300 Message-ID: <20211027095658.144468-6-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211027095658.144468-1-yishaih@nvidia.com> References: <20211027095658.144468-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: eed23909-cc11-4cbd-e7e0-08d9993047d0 X-MS-TrafficTypeDiagnostic: MN2PR12MB4535: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2000; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bHIAQ3Sm97Ax7Orld/anhq6zulQaHfJkviYqVhoWW5H66w+RrraythelsPBRzt9qoEUFJ9jtUDsPO5fYSwM1SUAqXuKktrN/7K+nYgsdvjGF93+atYR1zRRNngtdgioo/c6OSTTOYOEESuZhmkxWgs3ZBWPE/+B1AeBkndpEarKfMrZ0/yYhMsIy0ezfa7dAzwVRZJawfZT+92PfY2hcU7I20WdKsvEb8jlPVRf148E5hXYEjCTkbPwGxxPRi4lIdZRNOZV/3cg2+XEZJ6Ax9fFnC53EuGsFkptqv5GeDCW+CVEZT2iPGYmFfiiZxLLh97WiKhfFWH+oTY3IS05/YFarIMUSX2D6cY6QScangdJABhWsxO/hoMzCxNmNGHdWyQ+wsP4skOpU5FAhC7I5bDFpSGg4kzgCEhBLVRcy1roRBx3YMDu5tjHQFihzUQTinhuxede3jiuoUZEcO+d3kU7oqHpiOQ1gGzMTTuLSqHdfJvnHGjwjP8F3KdQ7u3cDJBUrc4Rdxf/n/a1NsC+Q4yYKjC4g0udJyixkWuYST9qD8h94O5sddpmF+ZTu0sYSnkiKn/OZYiA+KL9XZMnaMtcQGkYAxs680G11QYGTSBT2YeM7m3/tYvnqbPwQFS4FO8KKKS/Yzc9wCAJoe4hs7Y7tlgyL31RB1Yl9+yH6p9zUBz8+H05889W31H9aqmMvHLoxaoBFZuqqQL1Eq9/56A== X-Forefront-Antispam-Report: CIP:216.228.112.35;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid02.nvidia.com;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(36756003)(36860700001)(36906005)(508600001)(6636002)(83380400001)(82310400003)(6666004)(26005)(5660300002)(426003)(8676002)(54906003)(110136005)(186003)(7696005)(316002)(47076005)(2906002)(1076003)(336012)(7636003)(86362001)(70586007)(2616005)(107886003)(8936002)(356005)(70206006)(4326008);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2021 09:58:09.0339 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eed23909-cc11-4cbd-e7e0-08d9993047d0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.35];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT045.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4535 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Expose an API to get the mlx5 core device from a given VF PCI device if mlx5_core is its driver. Upon the get API we stay with the intf_state_mutex locked to make sure that the device can't be gone/unloaded till the caller will complete its job over the device, this expects to be for a short period of time for any flow that the lock is taken. Upon the put API we unlock the intf_state_mutex. The use case for those APIs is the migration flow of a VF over VFIO PCI. In that case the VF doesn't ride on mlx5_core, because the device is driving *two* different PCI devices, the PF owned by mlx5_core and the VF owned by the vfio driver. The mlx5_core of the PF is accessed only during the narrow window of the VF's ioctl that requires its services. This allows the PF driver to be more independent of the VF driver, so long as it doesn't reset the FW. Signed-off-by: Yishai Hadas Signed-off-by: Leon Romanovsky --- .../net/ethernet/mellanox/mlx5/core/main.c | 43 +++++++++++++++++++ include/linux/mlx5/driver.h | 3 ++ 2 files changed, 46 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index 0b9a911acfc1..38e7c692e733 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -1796,6 +1796,49 @@ static struct pci_driver mlx5_core_driver = { .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count, }; +/** + * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if + * mlx5_core is its driver. + * @pdev: The associated PCI device. + * + * Upon return the interface state lock stay held to let caller uses it safely. + * Caller must ensure to use the returned mlx5 device for a narrow window + * and put it back with mlx5_vf_put_core_dev() immediately once usage was over. + * + * Return: Pointer to the associated mlx5_core_dev or NULL. + */ +struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev) + __acquires(&mdev->intf_state_mutex) +{ + struct mlx5_core_dev *mdev; + + mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver); + if (IS_ERR(mdev)) + return NULL; + + mutex_lock(&mdev->intf_state_mutex); + if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) { + mutex_unlock(&mdev->intf_state_mutex); + return NULL; + } + + return mdev; +} +EXPORT_SYMBOL(mlx5_vf_get_core_dev); + +/** + * mlx5_vf_put_core_dev - Put the mlx5 core device back. + * @mdev: The mlx5 core device. + * + * Upon return the interface state lock is unlocked and caller should not + * access the mdev any more. + */ +void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev) +{ + mutex_unlock(&mdev->intf_state_mutex); +} +EXPORT_SYMBOL(mlx5_vf_put_core_dev); + static void mlx5_core_verify_params(void) { if (prof_sel >= ARRAY_SIZE(profile)) { diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 441a2f8715f8..197a76ea3f0f 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -1138,6 +1138,9 @@ int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, u64 length, u16 uid, phys_addr_t addr, u32 obj_id); +struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev); +void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev); + #ifdef CONFIG_MLX5_CORE_IPOIB struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, struct ib_device *ibdev, From patchwork Wed Oct 27 09:56:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12586931 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C81AC433EF for ; Wed, 27 Oct 2021 09:58:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F013A6109E for ; Wed, 27 Oct 2021 09:58:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241355AbhJ0KAu (ORCPT ); Wed, 27 Oct 2021 06:00:50 -0400 Received: from mail-bn8nam11on2062.outbound.protection.outlook.com ([40.107.236.62]:54592 "EHLO NAM11-BN8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241316AbhJ0KAk (ORCPT ); Wed, 27 Oct 2021 06:00:40 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=LKKsfqbK6B8Rpn1gNiBhSQLp1fUg8LN3VBPfahfscHlzlBI47rF0tq2r2xt/0Z0ygJbnlcs4j9bDYSRil5gJDNeTPjYkRgehPIWbFWPtOGZXZVrGlUmgBTYSm0LL9qAQi+WKnTYHqeG6NBI9SWtsSey6z4pi3nc1cUDPd+WuxTqOB/QDlf2h/irvUvcMTjMVuUrydZBZJrZsLZTc6pSj20PV4zwYRu8f09dLrT0O3BVhdK2qfPlqMMrEkMgYoCSyHDPFW7tJRAyuGEwcgYHv7GmemQ3GDZzcX+g5yoZM6TEbF/31QnqGhja3aBtrUlRi6jLxXf2w0I84hDmHnxp6JQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rIcenR7D/1n/5tfmUSe4ryMHmH3CEgWy3oi3ms6Ckjw=; b=Ws2YJX3e4LgMvzsJTGrL6iytCfavz6jVncJ7+GbH1wwuz7ngpYEsw4OoiSibgvgAOoB5nXO9ZbkRFlTxznHGNGxNlhONde8DCxMfwDAqDOgPuHmmkrGLqv/S3jG+m6kqgcEdp+QulzgNHbfmyZ4aWtxiQbClMuzpwhcJ3f9TsgZeHpfTPsZyYmKtlzWI6xC0H3UrmXUew2Z7UVNzl0JvalL2FbAU4PEuG8xua2Y5J51vsJCcvArydfzYSsOamuZ4Jlo9O4y3opPwtXU7ESfJ70c1ytFCEcrbjmXFoQ+TcLwmALOgWj7XE9XX+Qxwm7bfGjNjSOcK3EMyyTsN03G1og== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.35) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rIcenR7D/1n/5tfmUSe4ryMHmH3CEgWy3oi3ms6Ckjw=; b=EYtKLpOSTSJimg+8iQ7VeZo2aPL+eW8o0NBm3jWI8XFKnEYafEpl/z/CjOUXk13/WarY5MMwPCpexxjxFxTQq6WJmmDS9BpakKUuIS5lX6A07EvBGl+30iLXWOJBA66QnVl7Uuz52D3gwkfu6W1tCueNkj2qfZ5EtuE/l7oV1MjDNUy5EWXfdW/A80Urrwvti7curA5TWMgLB59WYWVyTq05vzLEA53fiGbDk5r3KDc4b92QqL+hteNX59NXWUBzm33WCGtbrmeOe+lL/VSN/I3AZKMZmRhL2ijcpfd695u0i+HZJMH3szdkajcAHuk3s++28OMqsAXbTmYBKNDFgQ== Received: from BN9P223CA0021.NAMP223.PROD.OUTLOOK.COM (2603:10b6:408:10b::26) by MWHPR12MB1293.namprd12.prod.outlook.com (2603:10b6:300:9::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.18; Wed, 27 Oct 2021 09:58:12 +0000 Received: from BN8NAM11FT045.eop-nam11.prod.protection.outlook.com (2603:10b6:408:10b:cafe::26) by BN9P223CA0021.outlook.office365.com (2603:10b6:408:10b::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.22 via Frontend Transport; Wed, 27 Oct 2021 09:58:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.35) smtp.mailfrom=nvidia.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.35 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.35; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.35) by BN8NAM11FT045.mail.protection.outlook.com (10.13.177.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4649.14 via Frontend Transport; Wed, 27 Oct 2021 09:58:12 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 27 Oct 2021 09:58:11 +0000 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 27 Oct 2021 09:58:11 +0000 Received: from vdi.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 27 Oct 2021 09:58:08 +0000 From: Yishai Hadas To: , , , CC: , , , , , , , , , Cornelia Huck Subject: [PATCH V5 mlx5-next 06/13] vfio: Fix VFIO_DEVICE_STATE_SET_ERROR macro Date: Wed, 27 Oct 2021 12:56:51 +0300 Message-ID: <20211027095658.144468-7-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211027095658.144468-1-yishaih@nvidia.com> References: <20211027095658.144468-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 36cf6434-e606-4eb3-db70-08d9993049c7 X-MS-TrafficTypeDiagnostic: MWHPR12MB1293: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2657; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JNz8DMzOqwlt88VK4GUFc8A7P5c8wr7RPt/ZIST4Bhix36wGgHtvv03FxOkxfcn9KQnclbwncG1rPcBiHiybjmTVeOMsjkNT5/Vdm5SVPQu4BTwHoH8pb2qqDRRdU777IgIrSXc/djZJCWbm5rHYTN4ZmLdN8TI/looVT5kEWRFivwthSo3+i/jrjdfMmpuMgs9Un96/yXnGN+ecI8iZIBQHO+a20Fq4DtMC2OtG9eJzg7T9yn+8RV8HPMr2zzDj8LV9QQMLPl36ZZgGfEZeQBkbMxRB6uVM35nG1UcskDatpRtVfCvukHEjRsoDb3moVvuH55uNqmIaqoMu8PpeXFdCF6LST3z4ZU/Lqi5JBLHcyRtUbG0xh/qD+N/ndYJAQsim5QwWFi40tUReluH/ZxE+N3dDtOrBXyT+klQBUbOXCuBgDvurZLFvdSBj8UHpEPEjk+nbl1H/0O2Y8aXAzLFOdwid+JYTeEH5SHVaYBG1BU2l8KwNmjRnsUnILL9q5VJmL6reEohz92XbXxxGfbl1Tgsp0Ov9ThiHAonw+yWk1bXKTIEufjBfkBkHOuBgOWmtynYzDnvZXxPTZJz7UdgKHmYq9hQX9bwD/7D0uajYB2K+L7w14ll4POUINbiVRIMgybJBO8cdJPSiKfZDWZaJjfsGND5v9FMQpSJ/QTpw83xXW+A0jR8hwKmCNbHUv6MuIQyk+gbCRVeVrLnh/g== X-Forefront-Antispam-Report: CIP:216.228.112.35;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid02.nvidia.com;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(2906002)(70206006)(47076005)(2616005)(110136005)(36906005)(356005)(7636003)(70586007)(8936002)(6636002)(7696005)(508600001)(83380400001)(6666004)(426003)(186003)(316002)(54906003)(8676002)(4744005)(1076003)(26005)(82310400003)(4326008)(36860700001)(36756003)(336012)(86362001)(5660300002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2021 09:58:12.3341 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 36cf6434-e606-4eb3-db70-08d9993049c7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.35];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT045.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1293 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Fixed the non-compiled macro VFIO_DEVICE_STATE_SET_ERROR (i.e. SATE instead of STATE). Fixes: a8a24f3f6e38 ("vfio: UAPI for migration interface for device state") Signed-off-by: Yishai Hadas Reviewed-by: Cornelia Huck Signed-off-by: Leon Romanovsky Reviewed-by: Max Gurtovoy --- include/uapi/linux/vfio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index ef33ea002b0b..114ffcefe437 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -622,7 +622,7 @@ struct vfio_device_migration_info { VFIO_DEVICE_STATE_RESUMING)) #define VFIO_DEVICE_STATE_SET_ERROR(state) \ - ((state & ~VFIO_DEVICE_STATE_MASK) | VFIO_DEVICE_SATE_SAVING | \ + ((state & ~VFIO_DEVICE_STATE_MASK) | VFIO_DEVICE_STATE_SAVING | \ VFIO_DEVICE_STATE_RESUMING) __u32 reserved; From patchwork Wed Oct 27 09:56:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12586935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8029C433FE for ; Wed, 27 Oct 2021 09:58:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B04F7610A0 for ; Wed, 27 Oct 2021 09:58:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241298AbhJ0KBL (ORCPT ); Wed, 27 Oct 2021 06:01:11 -0400 Received: from mail-co1nam11on2080.outbound.protection.outlook.com ([40.107.220.80]:5761 "EHLO NAM11-CO1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241334AbhJ0KAo (ORCPT ); Wed, 27 Oct 2021 06:00:44 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=DyjPtaSvy50J4k5/bhNugk1zhqTcfZLzTKpq6vVjkGokipJNkKuPLBP+vF1FjBtSp8qm3ahQaw4+q4VxHAvM4HmGUY5nL0z0Wlhmfi80iLuLk+FuuxeqwxKSKanOH6wSC93Q2yaOvEGaBxUC6FmyoHlRuK2JLHu8UAakxrcEJTRxIFkUzghf8t0St75DUbSd+ZNKL8OUjDi1UB/lMLV36tMd93aVGK4qoxXZmOjH/5kopzXaIxIJg3tXGIMbA8zxG0K2T5us7PKLlsUEGSMYImTiQDbpzN1wzknbPYaLlVF6VPVpJvRIqT3Ql5wv/JR3DMxW43himSGR9Qz54qmY6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=EWUSC24NCfT14SxQlq2ReyGeyhziaCkugOmClyCiu7E=; b=G8Hyt96A+BZr3MQx40zRsp5ylmEPzi+pz2XjDj2PUhmyz1D26jJflGJy+sb20JhS5B0zPp9cCBvxokoqh+tgC4sdaaJ+dO/2Uc08cJA/u8QfWZEHNGbuuOfQeoaA3i1jTJZBZ1Uw0u+i5qhAmLzVyED4DPJT8h/mdKdlLxNaVrayE1O2ta29WsuK3HUOY4B0i7x+7qtuGJ521QNqPgtTKJMfcL9T3KGMweXb5/tQjot/a40RXa5q/IKZcfUqtaiLRj+N/19lPfETUo0zDaELLnBziy6VpBAfFUh5uVB8XDqwsTeMuEYf9JWrcUlwtIFK9D5RVTFlckKVtk8a/AnlJQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=EWUSC24NCfT14SxQlq2ReyGeyhziaCkugOmClyCiu7E=; b=L+hVfuYXF/B/vLKFFxnGTaLflh+xzr24gUOn1tdUGZOX0zkQmAP61TjpgG3lMg4d1rJrF4UlPebLaiAPt4Bo5EN9+frEe54B1KiOVGiil/4pxNFyXWHX7GHssLFfu8Gm8paVGrIMyHKIzEEcSw567SnkOil/igmU93o34PHKi1XAQZ7Djx7ytfnQUuMvZB0VkVVBOqWy/Bf+BEQWDe+Jd0m8KJM+E+z6pGqyA9xKe8XHPa6FJYVcW9HuxXqZcXtVxo7lY5NZ1hzlzm8o+CXZdnJ3nx1l5GO9oulDcuCwMVSI0KHlz5MluvVEVJeurU8NGSuX2Co8Nj9TxpTV+ZbYQg== Received: from DS7PR03CA0077.namprd03.prod.outlook.com (2603:10b6:5:3bb::22) by BN8PR12MB2849.namprd12.prod.outlook.com (2603:10b6:408:6e::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.18; Wed, 27 Oct 2021 09:58:15 +0000 Received: from DM6NAM11FT012.eop-nam11.prod.protection.outlook.com (2603:10b6:5:3bb:cafe::76) by DS7PR03CA0077.outlook.office365.com (2603:10b6:5:3bb::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.13 via Frontend Transport; Wed, 27 Oct 2021 09:58:15 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT012.mail.protection.outlook.com (10.13.173.109) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4649.14 via Frontend Transport; Wed, 27 Oct 2021 09:58:15 +0000 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 27 Oct 2021 09:58:14 +0000 Received: from vdi.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 27 Oct 2021 09:58:11 +0000 From: Yishai Hadas To: , , , CC: , , , , , , , , , Cornelia Huck Subject: [PATCH V5 mlx5-next 07/13] vfio: Add a macro for VFIO_DEVICE_STATE_ERROR Date: Wed, 27 Oct 2021 12:56:52 +0300 Message-ID: <20211027095658.144468-8-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211027095658.144468-1-yishaih@nvidia.com> References: <20211027095658.144468-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d949af63-23c7-4c71-317a-08d999304b92 X-MS-TrafficTypeDiagnostic: BN8PR12MB2849: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2449; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZHNoWywPdowcoUCW0+Vfum1A9A2jxPgrQdGlOq/QNIhP3j3ouNFHa7R5gfwmBe6OOXKo23YbhSzHdpVc5sklPPXTNg4qiT7tQowGhWRRYIsOQ+W+nhIOYvhj9F9gNP43b//NuozOuWlwlsSUzUofXmcmUwVZpWwuRrFzwrVBL06gn/p5jS3GchZ3EnJxTHhvCw/2Rpeqoz36wf+yFaPzXMyLA5unO/Z3lAlZtaldEJD8ObXiEbZ25jZYhzpXaU4RmyP+Djro5x029XhqmjszSTfj/iMMka8QtB8rRL9j3v1+9beyvT7VqopWMB0fM38lWrLpFV4PYbtrLDl1sAdJ+4BsXouNOrVoA0uHUag4XHKyItbU2yh3+YTaZZbabpvdoB587RvUM0j4T5Nat5QEQbwWXj9zmAZCFY0ZSvRgRZxXKei/ucQuG2kkVt1XymNDIGv949QGshNx5wxRUx5jLnLdFy+EkEKDwmwVX1dVl7ZRB6Yl/kYGVHUsxWNFCaFfzLNmf4P0JCu1qEtxi+rJAJsjZlxQtAd/o66fxthitwcjckLZ6AvTPNsKwEb6O20QA2EDtk8ZdSHvmX07F+OMFlQ1bb07TYBmw/ZzO329A4Ul0r0xvAbCuWbTCNV8xBYzbPYFe9hq28p2O/zToGzymUnZpKCRebXcJKSZwWfNe5qh2qJEvXMiWjO0ngzmfAOIwRcSW0zWk1tCWvRc3Joreg== X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(83380400001)(110136005)(36906005)(7636003)(6636002)(70206006)(7696005)(508600001)(86362001)(1076003)(47076005)(336012)(8936002)(356005)(316002)(8676002)(4326008)(36860700001)(186003)(2906002)(426003)(5660300002)(82310400003)(36756003)(54906003)(6666004)(70586007)(2616005)(26005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2021 09:58:15.3968 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d949af63-23c7-4c71-317a-08d999304b92 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB2849 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a macro for VFIO_DEVICE_STATE_ERROR to be used to set/check an error state. In addition, update existing macros that include _SAVING | _RESUMING to use it. Reviewed-by: Cornelia Huck Signed-off-by: Yishai Hadas Reviewed-by: Max Gurtovoy --- include/uapi/linux/vfio.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 114ffcefe437..63ab0b9abd94 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -609,6 +609,8 @@ struct vfio_device_migration_info { #define VFIO_DEVICE_STATE_RUNNING (1 << 0) #define VFIO_DEVICE_STATE_SAVING (1 << 1) #define VFIO_DEVICE_STATE_RESUMING (1 << 2) +#define VFIO_DEVICE_STATE_ERROR (VFIO_DEVICE_STATE_SAVING | \ + VFIO_DEVICE_STATE_RESUMING) #define VFIO_DEVICE_STATE_MASK (VFIO_DEVICE_STATE_RUNNING | \ VFIO_DEVICE_STATE_SAVING | \ VFIO_DEVICE_STATE_RESUMING) @@ -618,12 +620,10 @@ struct vfio_device_migration_info { (state & VFIO_DEVICE_STATE_MASK) == VFIO_DEVICE_STATE_RESUMING : 1) #define VFIO_DEVICE_STATE_IS_ERROR(state) \ - ((state & VFIO_DEVICE_STATE_MASK) == (VFIO_DEVICE_STATE_SAVING | \ - VFIO_DEVICE_STATE_RESUMING)) + ((state & VFIO_DEVICE_STATE_MASK) == (VFIO_DEVICE_STATE_ERROR)) #define VFIO_DEVICE_STATE_SET_ERROR(state) \ - ((state & ~VFIO_DEVICE_STATE_MASK) | VFIO_DEVICE_STATE_SAVING | \ - VFIO_DEVICE_STATE_RESUMING) + ((state & ~VFIO_DEVICE_STATE_MASK) | VFIO_DEVICE_STATE_ERROR) __u32 reserved; __u64 pending_bytes; From patchwork Wed Oct 27 09:56:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12586933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F4C0C43219 for ; Wed, 27 Oct 2021 09:58:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 880986109E for ; Wed, 27 Oct 2021 09:58:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241313AbhJ0KBM (ORCPT ); Wed, 27 Oct 2021 06:01:12 -0400 Received: from mail-mw2nam10on2077.outbound.protection.outlook.com ([40.107.94.77]:61153 "EHLO NAM10-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241342AbhJ0KAp (ORCPT ); Wed, 27 Oct 2021 06:00:45 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=iDDNNZu9kh/NU+XKqAY0B8SxVHpUlZPECZhZI9iHVYpUh7HMrjwtMnQbrpPwSOMaqxOjKK9cOPCGtul6A4iDhXHRF4PmUn9KMHv9GdAFvZaLNQ/AHTiLHd8TZjBgbszmapCc6xRF3gSDc7VwMKCiPx9lbPjHs4NYNn30+LDAxtC9HGSAfFID0tvE2GtPULwNABkEJaZ46xnA4RpwvtIFZ8dxi4+K9lQzC3gOCFsNppHSq0Vd+QAO6zh0p6YnRWfCiEEu8o416utxYykzMvVYwSTIGXsQNqWUh1a13KDjvqhc5+uUsmsP7JsII+eQo/GDYKKmb38kjT00MyiGW7ybXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=DOcFU6eSD++XS6aHs3kXEvGIdsHFeir924wVdQSptkg=; b=oMDgFKn/7koLXQ2XWF+NKLXcskOM0BQdwuhEs1fYIRYE/+taMw48DLfPpYYoYOmguJtmCdQv+TA3LdE+XY+p7FXzKG55r00EXIc4mkJLUvmYI50M9jLO98qQ+piF7Rw/lrkPJaiFNKO0GmgYetFpjRkXvGceBjIq9zijmfC86gyeKZyo0EKgLHrK5O62kokcaYsaLRF2Ae4UTM+AM7KAZ2dgiX8HYzzaFmcFtVytp6VneieWp1m+TDyFO5XhhA1Qv6W2Bzn4D9p8JNFCcIqHbEFbjrz8yeFuay+PSVLMuH+xH1SVqnMNF/LQtXQ9r3ZBB4uq/wQu95fh+5U74lhGAA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=DOcFU6eSD++XS6aHs3kXEvGIdsHFeir924wVdQSptkg=; b=qUNj/omCtMuQPGoP+2WAD2/gkDPVJ8uCtHxbm9Q20O4XbizDTBD73G05UIMjKy0+XrgCHTddkF1H+HQ0jeoXrnOjAg7B+qVpkC2Th6YHPs+jRd+aO343EpX92bUlUkqT475kDwQIS6++ETItjThnXtjnL91aVIUmmnqMpErGw8tNlUOkyYCJIzFjdoWT8g7Ryff/mwTcqhk7AiaEH4eKhMRZFhr50T0WtmhDeiEQA7tfJAywCGDao8ohUvGE/psdRmXtxwNtqS+vukZ4acZYjb2zrCKuzh96FNoeE9oUl8+vJUyr8ssVVmuY2Vh4WvcuJGJR9SZ7qEP5BgjqZ8jx+w== Received: from DM3PR12CA0069.namprd12.prod.outlook.com (2603:10b6:0:57::13) by DM4PR12MB5053.namprd12.prod.outlook.com (2603:10b6:5:388::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.18; Wed, 27 Oct 2021 09:58:19 +0000 Received: from DM6NAM11FT040.eop-nam11.prod.protection.outlook.com (2603:10b6:0:57:cafe::ce) by DM3PR12CA0069.outlook.office365.com (2603:10b6:0:57::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.14 via Frontend Transport; Wed, 27 Oct 2021 09:58:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT040.mail.protection.outlook.com (10.13.173.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4649.14 via Frontend Transport; Wed, 27 Oct 2021 09:58:18 +0000 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 27 Oct 2021 09:58:18 +0000 Received: from vdi.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 27 Oct 2021 09:58:15 +0000 From: Yishai Hadas To: , , , CC: , , , , , , , , Subject: [PATCH V5 mlx5-next 08/13] vfio/pci_core: Make the region->release() function optional Date: Wed, 27 Oct 2021 12:56:53 +0300 Message-ID: <20211027095658.144468-9-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211027095658.144468-1-yishaih@nvidia.com> References: <20211027095658.144468-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9a394f34-a18e-4994-e311-08d999304da3 X-MS-TrafficTypeDiagnostic: DM4PR12MB5053: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GFiCO2L+k9IqXnkvYmmbvUd5ibbz5P/3vQcLEiaQKkb0y+M9LtJJ6B4sFO+bkxvEKduWUCM4LFe0XbE9VJKdxKD4j7SRwujNp3jJSVEdp54L5b1J7abZjJKArmbvSTHJmGvmmYvKS45RNK6ThK5lNIz/iqJK7Mi5Qk/W0s0Rv0xTt6j982ZuHriUj9jVKj6dQ2cLPIhN56zRIqz72XXEwYDIImdTkdbzVS0jpHdWDqCDD7N/k8qq3WEkiNbgSSuxWkIfXaRWK1vN2ZIPu8gsAhgdaSyox2TlKAHuXFrmbgqRvoqCvKS0FAQ5p3fzBzYMdUKcgi3c6aU9FsNQHyVJslFqVODN6CaGs38y4JYJVSL/uOLldQ0vxHAK14ItBF1mWAXE38YJnQvHmedu7HjKXDaMT9Z8wqpcOdz/GwhBGVvKgwut2457/JS1q2gBGviiknJrK+BfwxY+Wbo9wkCYqZWvP/mXJrWampq0bhdDhu0jSTrQM1bJPY7n8O/D8cUmLXhZ9+jvy00wkSrjHmMbMA+2bTsEzZYVt0bCuoNL+hyKoA8dYimNQYYSncqASRhQob8vS/y6ZRTTL1nh+0pekzW928iD8yNRrebM4wLeQRFtbJG/RUrHIeVOCBKYSN73BYqqDZ5+1O8GGf0wKH+eACYUuiJ33yA+kkTllXC+7rVkq1ZJAdYTZ1psWdewOGfubw+zkgx5eOa9CSlyQT6MoQ== X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(36860700001)(36756003)(110136005)(47076005)(36906005)(426003)(83380400001)(7696005)(1076003)(107886003)(4326008)(2616005)(54906003)(86362001)(8936002)(82310400003)(6636002)(186003)(8676002)(70206006)(6666004)(26005)(2906002)(356005)(7636003)(316002)(508600001)(70586007)(5660300002)(336012);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2021 09:58:18.8552 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9a394f34-a18e-4994-e311-08d999304da3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5053 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Make the region->release() function optional as in some cases there is nothing to do by driver as part of it. This is needed for coming patch from this series once we add mlx5_vfio_pci driver to support live migration but we don't need a migration release function. Signed-off-by: Yishai Hadas Signed-off-by: Leon Romanovsky --- drivers/vfio/pci/vfio_pci_core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index a03b5a99c2da..e581a327f90d 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -341,7 +341,8 @@ void vfio_pci_core_disable(struct vfio_pci_core_device *vdev) vdev->virq_disabled = false; for (i = 0; i < vdev->num_regions; i++) - vdev->region[i].ops->release(vdev, &vdev->region[i]); + if (vdev->region[i].ops->release) + vdev->region[i].ops->release(vdev, &vdev->region[i]); vdev->num_regions = 0; kfree(vdev->region); From patchwork Wed Oct 27 09:56:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12586937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 458F7C4321E for ; Wed, 27 Oct 2021 09:58:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 30613610A0 for ; Wed, 27 Oct 2021 09:58:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241405AbhJ0KBO (ORCPT ); Wed, 27 Oct 2021 06:01:14 -0400 Received: from mail-dm6nam12on2043.outbound.protection.outlook.com ([40.107.243.43]:53280 "EHLO NAM12-DM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241317AbhJ0KAs (ORCPT ); Wed, 27 Oct 2021 06:00:48 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=MqXiRh7tSxf/5C9vGex8KwhoDQvwG79xJI9vUE01EO8G3y10wSLKPFU66bjcuvwYKPEtbF0fez6Pk9WguKVSKJ9ovcDEkEmtUwXbjhTb1QZPeT/osWV+nasL7D2aofZ1QECN3ct6aWPzS4d/RUiR+uFATdv3zD9jYUG513UOTMRW6m1OP8pqUbUpJzBzdYQdu6EuSlglC85cJRDtgaDYqkI8Goh/NfB1AQ5BodApprhOH7FxkdZTipVh3rV2o6g+9GQUQYrWuVa9LOPBeohPNaI/xc/bswVjcLxglNI9m+GhMwAFjYXN3dlrEwGZmlJ0A7H84osdddrvL9pPeoEDgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=8EiLFCfX1BIiCoBhJcg49k8D+4oAajiiGkB0J2YJXL4=; b=CCF8saknzAjzUbIjNmxwUNdOSfrlMiJCcLC/ZYvCiqc4do1Ye+R70y1vzi7WXOPMdpX6oxbTE7L7tZY8jaPtiPpkbaJlqMTbpJ/N4qyC1qzOkMqv8/6GjyReAFHDQjEFfZjwvgV1xrU64GoCdnaJt5APzyAX1LMYQlIPpiygcXWscRxYNPfp18jwwusej2hrFKUfPRlRiduNvRpDfMKsIJQ5ow+TNgRl1CXkGixuZv0TOp/IkkqV+SRgB+5VPzRMgnGgDkfhENFL7Q/gNIgSXUnYKACBD0zUiXcPVpmeMkWQ8k8yET1tlUsSLWI6oJxFUnfR8EHymIK+XI5ec6g21Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.32) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=8EiLFCfX1BIiCoBhJcg49k8D+4oAajiiGkB0J2YJXL4=; b=TKMp+hLl82C4irFBTNSdVArEo7RTx34AthtR3KdCPYaxT5YjSe//69W7/WbGYSH6N6IsDle6xrJeup+JXxbrkEIC1ckNeaUI7uKTN5Q/ZLJ+Emi/5JHP4zeTGcZ5EsH4kDq9Z+m6Es3eRuJqqz+ki3utWvhusNJeLAi6/XTaJGc5xnyjJCXYYIpzMlSeQy7TM4BZxQESKAE9/lPbBwhbOedygKNnhVvCY1l05KO8xpO1jm+msC1dObfcaje7XX1Bhb0sokgckx9wXz7qP6ClvHIzzRNQ2pDJnHdsnt+fkSAD3nliAphgAx2+OU77d6QcPCLvDQWToiTU5+ZkQjOPAQ== Received: from DS7PR07CA0002.namprd07.prod.outlook.com (2603:10b6:5:3af::8) by CH0PR12MB5385.namprd12.prod.outlook.com (2603:10b6:610:d4::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.13; Wed, 27 Oct 2021 09:58:22 +0000 Received: from DM6NAM11FT031.eop-nam11.prod.protection.outlook.com (2603:10b6:5:3af:cafe::d4) by DS7PR07CA0002.outlook.office365.com (2603:10b6:5:3af::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.14 via Frontend Transport; Wed, 27 Oct 2021 09:58:22 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.32) smtp.mailfrom=nvidia.com; redhat.com; dkim=none (message not signed) header.d=none;redhat.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.32 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.32; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.32) by DM6NAM11FT031.mail.protection.outlook.com (10.13.172.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4649.14 via Frontend Transport; Wed, 27 Oct 2021 09:58:22 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 27 Oct 2021 02:58:21 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 27 Oct 2021 09:58:21 +0000 Received: from vdi.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 27 Oct 2021 09:58:18 +0000 From: Yishai Hadas To: , , , CC: , , , , , , , , Subject: [PATCH V5 mlx5-next 09/13] net/mlx5: Introduce migration bits and structures Date: Wed, 27 Oct 2021 12:56:54 +0300 Message-ID: <20211027095658.144468-10-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211027095658.144468-1-yishaih@nvidia.com> References: <20211027095658.144468-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 34abdd40-a6bb-49b0-4e85-08d999304fb8 X-MS-TrafficTypeDiagnostic: CH0PR12MB5385: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QFl6UgRsEqHPy5kCqkXw7eKB/kRb8743gOivm8MbIRnFusACBwjaF+iqQWUn182/KLLT4Anz+D58/RZLrocTkZz8DAOkuZHmU7r7FS51Ox0UVKpzwbbYTBVheu4z7ybKkBcQ23ZIRaXsrjb35BJ/8FTDBBUKtSaGi2EaDsUqjuLA4wMYEWBd6oMG+BdMtuxHTFpH5Jg+q4GPPqrNQObYKwvYWnSmHF2yG4Hxu/dhSmQooPGF4K3zXESsnfHzBDCYjs807Q9KKUfORurXdaDZEZQXUASGlPxkDZ/9D9z91/lhDZQ9JRLOxmHuUxsCq+Fyb+taCkjhQMDDf9v5knlmiwT18RzyWpS7zMcdLbJozctndEmFrJETbudbjBY3ehNnfiaQRvqUdNxyDrlTK1GslGBlMavGu4mTuswOE3kITRglEFyvFSF49HmOhQhuKvmbu7oPSSh0s+kuFAi2uSws6hGpGVWbpwWCChxDHANU4+z53LnMsEphxwMjxaWvwWBcTLVsBlUyZ4mdIyTeflL9xykUX000eAzuvWiQbL94V3aGk27FvxKIxqcZlA1+EEm1ramsmA/0JW+1fuipmYmj3hQWAkOH8vvef9lLJD2guu0jLc6BemmyqArqCmg2CXsTkNwLPPOX2Xtsh1GsbpMYYDN62K++uq8wnChFljfI1G+vgRtCgH2fepD9FT1EWsTKBaaA+A7SJ/b9HiwTx9GezA== X-Forefront-Antispam-Report: CIP:216.228.112.32;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid01.nvidia.com;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(83380400001)(107886003)(54906003)(7696005)(70206006)(47076005)(8676002)(2616005)(86362001)(426003)(70586007)(36860700001)(6636002)(2906002)(110136005)(508600001)(336012)(8936002)(36756003)(356005)(1076003)(7636003)(82310400003)(5660300002)(186003)(316002)(6666004)(26005)(4326008);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2021 09:58:22.3495 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 34abdd40-a6bb-49b0-4e85-08d999304fb8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.32];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5385 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Introduce migration IFC related stuff to enable migration commands. Signed-off-by: Yishai Hadas Signed-off-by: Leon Romanovsky --- include/linux/mlx5/mlx5_ifc.h | 147 +++++++++++++++++++++++++++++++++- 1 file changed, 146 insertions(+), 1 deletion(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 864fc6b99b44..fe5566bb00b1 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -126,6 +126,11 @@ enum { MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, MLX5_CMD_OP_ALLOC_SF = 0x113, MLX5_CMD_OP_DEALLOC_SF = 0x114, + MLX5_CMD_OP_SUSPEND_VHCA = 0x115, + MLX5_CMD_OP_RESUME_VHCA = 0x116, + MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, + MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, + MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, MLX5_CMD_OP_CREATE_MKEY = 0x200, MLX5_CMD_OP_QUERY_MKEY = 0x201, MLX5_CMD_OP_DESTROY_MKEY = 0x202, @@ -1719,7 +1724,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 reserved_at_682[0x1]; u8 log_max_sf[0x5]; u8 apu[0x1]; - u8 reserved_at_689[0x7]; + u8 reserved_at_689[0x4]; + u8 migration[0x1]; + u8 reserved_at_68e[0x2]; u8 log_min_sf_size[0x8]; u8 max_num_sf_partitions[0x8]; @@ -11152,4 +11159,142 @@ enum { MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, }; +enum { + MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_MASTER = 0x0, + MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_SLAVE = 0x1, +}; + +struct mlx5_ifc_suspend_vhca_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + + u8 reserved_at_40[0x10]; + u8 vhca_id[0x10]; + + u8 reserved_at_60[0x20]; +}; + +struct mlx5_ifc_suspend_vhca_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + + u8 syndrome[0x20]; + + u8 reserved_at_40[0x40]; +}; + +enum { + MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_SLAVE = 0x0, + MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_MASTER = 0x1, +}; + +struct mlx5_ifc_resume_vhca_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + + u8 reserved_at_40[0x10]; + u8 vhca_id[0x10]; + + u8 reserved_at_60[0x20]; +}; + +struct mlx5_ifc_resume_vhca_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + + u8 syndrome[0x20]; + + u8 reserved_at_40[0x40]; +}; + +struct mlx5_ifc_query_vhca_migration_state_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + + u8 reserved_at_40[0x10]; + u8 vhca_id[0x10]; + + u8 reserved_at_60[0x20]; +}; + +struct mlx5_ifc_query_vhca_migration_state_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + + u8 syndrome[0x20]; + + u8 reserved_at_40[0x40]; + + u8 required_umem_size[0x20]; + + u8 reserved_at_a0[0x160]; +}; + +struct mlx5_ifc_save_vhca_state_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + + u8 reserved_at_40[0x10]; + u8 vhca_id[0x10]; + + u8 reserved_at_60[0x20]; + + u8 va[0x40]; + + u8 mkey[0x20]; + + u8 size[0x20]; +}; + +struct mlx5_ifc_save_vhca_state_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + + u8 syndrome[0x20]; + + u8 actual_image_size[0x20]; + + u8 reserved_at_60[0x20]; +}; + +struct mlx5_ifc_load_vhca_state_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + + u8 reserved_at_40[0x10]; + u8 vhca_id[0x10]; + + u8 reserved_at_60[0x20]; + + u8 va[0x40]; + + u8 mkey[0x20]; + + u8 size[0x20]; +}; + +struct mlx5_ifc_load_vhca_state_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + + u8 syndrome[0x20]; + + u8 reserved_at_40[0x40]; +}; + #endif /* MLX5_IFC_H */ From patchwork Wed Oct 27 09:56:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12586939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 419D5C433FE for ; Wed, 27 Oct 2021 09:59:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2758B61052 for ; Wed, 27 Oct 2021 09:59:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241438AbhJ0KBb (ORCPT ); Wed, 27 Oct 2021 06:01:31 -0400 Received: from mail-dm3nam07on2089.outbound.protection.outlook.com ([40.107.95.89]:62944 "EHLO NAM02-DM3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241366AbhJ0KAy (ORCPT ); Wed, 27 Oct 2021 06:00:54 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=XcI0tkMwxYMm3FHmfH4qJSTM/XbSlbUJkj4qxoOLEndZSYRYgHexNx5oq+ShdhOFzrVOtzMTndnL4tIh7h7t2MWhGVonxiW7/0x9JiWjSdSTVAYAvcqck3Aofj8S0jTefTDfcORepCKQaGwc5iWbeOmgcwN/puZgIaivrxKSUfzL0e4xECZme38G1tN1sSU+7+pE86u4J8fGDaC+xNIgG9X+HWpE6cHZ+NW1E3aitc5iS2ySpW62FSSReuSP/T6gHed/5ioKEYM8GL/FxDk4WVMNVc9T0dPsUQseKyyOAjH2ZpNqV8+cq094nfKoL84hh9SZzdC2PKk3ypKl6w3mhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0qBhMUAfwt8E6ywWDy8Owv/T01/cBk016HI+ZBtUhJk=; b=AV/idjxJc41nRn6JDe9RnMDfvuhKbPaoMVGcqH+gWeQMQf5DXTwq/CTliJJ+VfXMZeyAEk8yS0xPZ36In/pYApXJS3+Xa7QMrSTRg9SrRlZqGFh6yyLDFA02NeihmRxwt1gx95EUd5h0OHa7wkZ/sn9pBPwNH0dg8G8QL8ICqp0+WQWldlE2wH+Y1GyUzKAlxQzNvKUePjjykwWNFcksB2STD45o5SnO3MVLH6S5xEjPfp0MyTUstX6FRCcJ5SUdtpTA1/WDQLuTaLV/S8hct5V/+CAJXaPIbS0lJRMI08KFUcBScSs0kSUUV5UwaUMpPjgNgP7ZC7VZBnpO/UTaVw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.32) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0qBhMUAfwt8E6ywWDy8Owv/T01/cBk016HI+ZBtUhJk=; b=J93cP/cX5tb2e7eNKnj6bDz5FFDaBvNGaqKlR0wXqH3H2nAqBmUvh4W11q+mI3JnD5IGB2oXHAXXawxsC/h0Sc6f8+OiA5z/Szf1rwPUWWTfDbDHzcs8R4RLMv+iqUUdp2wfBDOIcuYrXWz1qDDQLvM8cWckmKlwak8IJSwhl/6TFElGcH5N/OA7wocaMtg/akRmnMxott/bOL123i3VJV6sogz+F8i3DOL7ndL6vKCNAUmETK8cE91OnXhHKYadMYl8VhO7/9ST5Zvj8D4MaPuGG6c4KmDoJcuNaEuk5/6Ns+wGjJnzAce04cCxCFiTN9byb2QrlFIROMhVfNZLgQ== Received: from DS7PR07CA0001.namprd07.prod.outlook.com (2603:10b6:5:3af::10) by BYAPR12MB2998.namprd12.prod.outlook.com (2603:10b6:a03:dd::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.14; Wed, 27 Oct 2021 09:58:25 +0000 Received: from DM6NAM11FT010.eop-nam11.prod.protection.outlook.com (2603:10b6:5:3af:cafe::84) by DS7PR07CA0001.outlook.office365.com (2603:10b6:5:3af::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.14 via Frontend Transport; Wed, 27 Oct 2021 09:58:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.32) smtp.mailfrom=nvidia.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.32 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.32; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.32) by DM6NAM11FT010.mail.protection.outlook.com (10.13.172.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4649.14 via Frontend Transport; Wed, 27 Oct 2021 09:58:25 +0000 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 27 Oct 2021 02:58:24 -0700 Received: from vdi.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 27 Oct 2021 09:58:22 +0000 From: Yishai Hadas To: , , , CC: , , , , , , , , Subject: [PATCH V5 mlx5-next 10/13] vfio/mlx5: Expose migration commands over mlx5 device Date: Wed, 27 Oct 2021 12:56:55 +0300 Message-ID: <20211027095658.144468-11-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211027095658.144468-1-yishaih@nvidia.com> References: <20211027095658.144468-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 006fbf1c-acf2-4dd0-0b4e-08d9993051ae X-MS-TrafficTypeDiagnostic: BYAPR12MB2998: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4+JvIvTwnzHHp/4LuqM4bvqF1ZxgaaHyfeEZReH6Hcr9TC0wS/nBAXbGgS1jH41HiZ9qmHgQva7NkchwN638mMRMMeE3Zo8wb+TzYqnNjYng793k7+l1XCvsC4jiQMHWwaC0h7MfRJMNPm8B/nCE6kSbRlUZ2qgClXn7wJfwf/GjGJGrV+XNClIIhU0vlvhqIY2NMoyLEyzBaAPFlw8dHFS7gelOSni9THCQZv8JbKGvXFMLyqOOSuZW6AzkSVR5utBr/AHWfuNMHj2jsHIH19846AGUdzXPwTp5hPPeXrTUolc6lSEYYhQ/RXbP4+ycukr3ZMyZqP2Grpa7VhAXI1IVpAHQT2YWrDF0ND8Od90kvPZfKI2nmxcTO3WI10FccjcGwvJFaYE2yyOJoY8qwvBx0/FNbLJWkxbihmKPS565di8bH370MOA3GHhWBWDSbMQFk4TWJclcudgSyC0XLyscAZAOaKCCINkLnAwVDIr/MAQKuWV7Z/bNMMyV+gRYjmLV3TyVmWxTX2a3aBqqxlvLeBSo5qAkynYb/PaiWxNoAb40++l9T6Zkz1Edqo4nAGfSU4tZSrFhNobcTF1NYIqOpOHGwEBE8ZITGbzDSyKsJAFPpgtMGdpVckxhifv+5TJieWNRCKf6dwR0moT5xPZr2x5jFEGDrJ7JpKMVnGTRZFiVkETHWWS5nBw/BV/EFpwpm+SrhgKQUmTlpkG4TQ== X-Forefront-Antispam-Report: CIP:216.228.112.32;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid01.nvidia.com;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(36860700001)(2616005)(110136005)(186003)(508600001)(70206006)(54906003)(356005)(8936002)(36756003)(86362001)(4326008)(426003)(5660300002)(7636003)(316002)(7696005)(336012)(2906002)(26005)(83380400001)(107886003)(6666004)(6636002)(8676002)(30864003)(47076005)(70586007)(1076003)(82310400003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2021 09:58:25.5587 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 006fbf1c-acf2-4dd0-0b4e-08d9993051ae X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.32];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT010.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2998 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Expose migration commands over the device, it includes: suspend, resume, get vhca id, query/save/load state. As part of this adds the APIs and data structure that are needed to manage the migration data. Signed-off-by: Yishai Hadas Signed-off-by: Leon Romanovsky --- drivers/vfio/pci/mlx5/cmd.c | 356 ++++++++++++++++++++++++++++++++++++ drivers/vfio/pci/mlx5/cmd.h | 43 +++++ 2 files changed, 399 insertions(+) create mode 100644 drivers/vfio/pci/mlx5/cmd.c create mode 100644 drivers/vfio/pci/mlx5/cmd.h diff --git a/drivers/vfio/pci/mlx5/cmd.c b/drivers/vfio/pci/mlx5/cmd.c new file mode 100644 index 000000000000..add791398d08 --- /dev/null +++ b/drivers/vfio/pci/mlx5/cmd.c @@ -0,0 +1,356 @@ +// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB +/* + * Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved + */ + +#include "cmd.h" + +int mlx5vf_cmd_suspend_vhca(struct pci_dev *pdev, u16 vhca_id, u16 op_mod) +{ + struct mlx5_core_dev *mdev = mlx5_vf_get_core_dev(pdev); + u32 out[MLX5_ST_SZ_DW(suspend_vhca_out)] = {}; + u32 in[MLX5_ST_SZ_DW(suspend_vhca_in)] = {}; + int ret; + + if (!mdev) + return -ENOTCONN; + + MLX5_SET(suspend_vhca_in, in, opcode, MLX5_CMD_OP_SUSPEND_VHCA); + MLX5_SET(suspend_vhca_in, in, vhca_id, vhca_id); + MLX5_SET(suspend_vhca_in, in, op_mod, op_mod); + + ret = mlx5_cmd_exec_inout(mdev, suspend_vhca, in, out); + mlx5_vf_put_core_dev(mdev); + return ret; +} + +int mlx5vf_cmd_resume_vhca(struct pci_dev *pdev, u16 vhca_id, u16 op_mod) +{ + struct mlx5_core_dev *mdev = mlx5_vf_get_core_dev(pdev); + u32 out[MLX5_ST_SZ_DW(resume_vhca_out)] = {}; + u32 in[MLX5_ST_SZ_DW(resume_vhca_in)] = {}; + int ret; + + if (!mdev) + return -ENOTCONN; + + MLX5_SET(resume_vhca_in, in, opcode, MLX5_CMD_OP_RESUME_VHCA); + MLX5_SET(resume_vhca_in, in, vhca_id, vhca_id); + MLX5_SET(resume_vhca_in, in, op_mod, op_mod); + + ret = mlx5_cmd_exec_inout(mdev, resume_vhca, in, out); + mlx5_vf_put_core_dev(mdev); + return ret; +} + +int mlx5vf_cmd_query_vhca_migration_state(struct pci_dev *pdev, u16 vhca_id, + u32 *state_size) +{ + struct mlx5_core_dev *mdev = mlx5_vf_get_core_dev(pdev); + u32 out[MLX5_ST_SZ_DW(query_vhca_migration_state_out)] = {}; + u32 in[MLX5_ST_SZ_DW(query_vhca_migration_state_in)] = {}; + int ret; + + if (!mdev) + return -ENOTCONN; + + MLX5_SET(query_vhca_migration_state_in, in, opcode, + MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE); + MLX5_SET(query_vhca_migration_state_in, in, vhca_id, vhca_id); + MLX5_SET(query_vhca_migration_state_in, in, op_mod, 0); + + ret = mlx5_cmd_exec_inout(mdev, query_vhca_migration_state, in, out); + if (ret) + goto end; + + *state_size = MLX5_GET(query_vhca_migration_state_out, out, + required_umem_size); + +end: + mlx5_vf_put_core_dev(mdev); + return ret; +} + +int mlx5vf_cmd_get_vhca_id(struct pci_dev *pdev, u16 function_id, u16 *vhca_id) +{ + struct mlx5_core_dev *mdev = mlx5_vf_get_core_dev(pdev); + u32 in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {}; + int out_size; + void *out; + int ret; + + if (!mdev) + return -ENOTCONN; + + out_size = MLX5_ST_SZ_BYTES(query_hca_cap_out); + out = kzalloc(out_size, GFP_KERNEL); + if (!out) { + ret = -ENOMEM; + goto end; + } + + MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); + MLX5_SET(query_hca_cap_in, in, other_function, 1); + MLX5_SET(query_hca_cap_in, in, function_id, function_id); + MLX5_SET(query_hca_cap_in, in, op_mod, + MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE << 1 | + HCA_CAP_OPMOD_GET_CUR); + + ret = mlx5_cmd_exec_inout(mdev, query_hca_cap, in, out); + if (ret) + goto err_exec; + + *vhca_id = MLX5_GET(query_hca_cap_out, out, + capability.cmd_hca_cap.vhca_id); + +err_exec: + kfree(out); +end: + mlx5_vf_put_core_dev(mdev); + return ret; +} + +static int _create_state_mkey(struct mlx5_core_dev *mdev, u32 pdn, + struct mlx5_vhca_state_data *state, u32 *mkey) +{ + struct sg_dma_page_iter dma_iter; + int err = 0, inlen; + __be64 *mtt; + void *mkc; + u32 *in; + + inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + + sizeof(*mtt) * round_up(state->num_pages, 2); + + in = kvzalloc(inlen, GFP_KERNEL); + if (!in) + return -ENOMEM; + + MLX5_SET(create_mkey_in, in, translations_octword_actual_size, + DIV_ROUND_UP(state->num_pages, 2)); + mtt = (__be64 *)MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); + + for_each_sgtable_dma_page(&state->mig_data.table.sgt, &dma_iter, 0) + *mtt++ = cpu_to_be64(sg_page_iter_dma_address(&dma_iter)); + + mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); + MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); + MLX5_SET(mkc, mkc, lr, 1); + MLX5_SET(mkc, mkc, lw, 1); + MLX5_SET(mkc, mkc, rr, 1); + MLX5_SET(mkc, mkc, rw, 1); + MLX5_SET(mkc, mkc, pd, pdn); + MLX5_SET(mkc, mkc, bsf_octword_size, 0); + MLX5_SET(mkc, mkc, qpn, 0xffffff); + MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT); + MLX5_SET(mkc, mkc, translations_octword_size, + DIV_ROUND_UP(state->num_pages, 2)); + MLX5_SET64(mkc, mkc, len, state->num_pages * PAGE_SIZE); + err = mlx5_core_create_mkey(mdev, mkey, in, inlen); + + kvfree(in); + + return err; +} + +struct page *mlx5vf_get_migration_page(struct migration_data *data, + unsigned long offset) +{ + unsigned long cur_offset = 0; + struct scatterlist *sg; + unsigned int i; + + if (offset < data->last_offset || !data->last_offset_sg) { + data->last_offset = 0; + data->last_offset_sg = data->table.sgt.sgl; + data->sg_last_entry = 0; + } + + cur_offset = data->last_offset; + + for_each_sg(data->last_offset_sg, sg, + data->table.sgt.orig_nents - data->sg_last_entry, i) { + if (offset < sg->length + cur_offset) { + data->last_offset_sg = sg; + data->sg_last_entry += i; + data->last_offset = cur_offset; + return nth_page(sg_page(sg), + (offset - cur_offset) / PAGE_SIZE); + } + cur_offset += sg->length; + } + return NULL; +} + +void mlx5vf_reset_vhca_state(struct mlx5_vhca_state_data *state) +{ + struct migration_data *data = &state->mig_data; + struct sg_page_iter sg_iter; + + if (!data->table.prv) + goto end; + + /* Undo alloc_pages_bulk_array() */ + for_each_sgtable_page(&data->table.sgt, &sg_iter, 0) + __free_page(sg_page_iter_page(&sg_iter)); + sg_free_append_table(&data->table); +end: + memset(state, 0, sizeof(*state)); +} + +int mlx5vf_add_migration_pages(struct mlx5_vhca_state_data *state, + unsigned int npages) +{ + unsigned int to_alloc = npages; + struct page **page_list; + unsigned long filled; + unsigned int to_fill; + int ret = 0; + + to_fill = min_t(unsigned int, npages, PAGE_SIZE / sizeof(*page_list)); + page_list = kvzalloc(to_fill * sizeof(*page_list), GFP_KERNEL); + if (!page_list) + return -ENOMEM; + + do { + filled = alloc_pages_bulk_array(GFP_KERNEL, to_fill, + page_list); + if (!filled) { + ret = -ENOMEM; + goto err; + } + to_alloc -= filled; + ret = sg_alloc_append_table_from_pages( + &state->mig_data.table, page_list, filled, 0, + filled << PAGE_SHIFT, UINT_MAX, SG_MAX_SINGLE_ALLOC, + GFP_KERNEL); + + if (ret) + goto err; + /* clean input for another bulk allocation */ + memset(page_list, 0, filled * sizeof(*page_list)); + to_fill = min_t(unsigned int, to_alloc, + PAGE_SIZE / sizeof(*page_list)); + } while (to_alloc > 0); + + kvfree(page_list); + state->num_pages += npages; + + return 0; + +err: + kvfree(page_list); + return ret; +} + +int mlx5vf_cmd_save_vhca_state(struct pci_dev *pdev, u16 vhca_id, + u64 state_size, + struct mlx5_vhca_state_data *state) +{ + struct mlx5_core_dev *mdev = mlx5_vf_get_core_dev(pdev); + u32 out[MLX5_ST_SZ_DW(save_vhca_state_out)] = {}; + u32 in[MLX5_ST_SZ_DW(save_vhca_state_in)] = {}; + u32 pdn, mkey; + int err; + + if (!mdev) + return -ENOTCONN; + + err = mlx5_core_alloc_pd(mdev, &pdn); + if (err) + goto end; + + err = mlx5vf_add_migration_pages(state, + DIV_ROUND_UP_ULL(state_size, PAGE_SIZE)); + if (err < 0) + goto err_alloc_pages; + + err = dma_map_sgtable(mdev->device, &state->mig_data.table.sgt, + DMA_FROM_DEVICE, 0); + if (err) + goto err_reg_dma; + + err = _create_state_mkey(mdev, pdn, state, &mkey); + if (err) + goto err_create_mkey; + + MLX5_SET(save_vhca_state_in, in, opcode, + MLX5_CMD_OP_SAVE_VHCA_STATE); + MLX5_SET(save_vhca_state_in, in, op_mod, 0); + MLX5_SET(save_vhca_state_in, in, vhca_id, vhca_id); + MLX5_SET(save_vhca_state_in, in, mkey, mkey); + MLX5_SET(save_vhca_state_in, in, size, state_size); + + err = mlx5_cmd_exec_inout(mdev, save_vhca_state, in, out); + if (err) + goto err_exec; + + state->state_size = MLX5_GET(save_vhca_state_out, out, + actual_image_size); + + mlx5_core_destroy_mkey(mdev, mkey); + mlx5_core_dealloc_pd(mdev, pdn); + dma_unmap_sgtable(mdev->device, &state->mig_data.table.sgt, + DMA_FROM_DEVICE, 0); + mlx5_vf_put_core_dev(mdev); + + return 0; + +err_exec: + mlx5_core_destroy_mkey(mdev, mkey); +err_create_mkey: + dma_unmap_sgtable(mdev->device, &state->mig_data.table.sgt, + DMA_FROM_DEVICE, 0); +err_reg_dma: + mlx5vf_reset_vhca_state(state); +err_alloc_pages: + mlx5_core_dealloc_pd(mdev, pdn); +end: + mlx5_vf_put_core_dev(mdev); + return err; +} + +int mlx5vf_cmd_load_vhca_state(struct pci_dev *pdev, u16 vhca_id, + struct mlx5_vhca_state_data *state) +{ + struct mlx5_core_dev *mdev = mlx5_vf_get_core_dev(pdev); + u32 out[MLX5_ST_SZ_DW(save_vhca_state_out)] = {}; + u32 in[MLX5_ST_SZ_DW(save_vhca_state_in)] = {}; + u32 pdn, mkey; + int err; + + if (!mdev) + return -ENOTCONN; + + err = mlx5_core_alloc_pd(mdev, &pdn); + if (err) + goto end; + + err = dma_map_sgtable(mdev->device, &state->mig_data.table.sgt, + DMA_TO_DEVICE, 0); + if (err) + goto err_reg; + + err = _create_state_mkey(mdev, pdn, state, &mkey); + if (err) + goto err_mkey; + + MLX5_SET(load_vhca_state_in, in, opcode, + MLX5_CMD_OP_LOAD_VHCA_STATE); + MLX5_SET(load_vhca_state_in, in, op_mod, 0); + MLX5_SET(load_vhca_state_in, in, vhca_id, vhca_id); + MLX5_SET(load_vhca_state_in, in, mkey, mkey); + MLX5_SET(load_vhca_state_in, in, size, state->state_size); + + err = mlx5_cmd_exec_inout(mdev, load_vhca_state, in, out); + + mlx5_core_destroy_mkey(mdev, mkey); +err_mkey: + dma_unmap_sgtable(mdev->device, &state->mig_data.table.sgt, + DMA_TO_DEVICE, 0); +err_reg: + mlx5_core_dealloc_pd(mdev, pdn); +end: + mlx5_vf_put_core_dev(mdev); + return err; +} diff --git a/drivers/vfio/pci/mlx5/cmd.h b/drivers/vfio/pci/mlx5/cmd.h new file mode 100644 index 000000000000..66221df24b19 --- /dev/null +++ b/drivers/vfio/pci/mlx5/cmd.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ +/* + * Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + */ + +#ifndef MLX5_VFIO_CMD_H +#define MLX5_VFIO_CMD_H + +#include +#include + +struct migration_data { + struct sg_append_table table; + + struct scatterlist *last_offset_sg; + unsigned int sg_last_entry; + unsigned long last_offset; +}; + +/* state data of vhca to be used as part of migration flow */ +struct mlx5_vhca_state_data { + u64 state_size; + u64 num_pages; + u32 win_start_offset; + struct migration_data mig_data; +}; + +int mlx5vf_cmd_suspend_vhca(struct pci_dev *pdev, u16 vhca_id, u16 op_mod); +int mlx5vf_cmd_resume_vhca(struct pci_dev *pdev, u16 vhca_id, u16 op_mod); +int mlx5vf_cmd_query_vhca_migration_state(struct pci_dev *pdev, u16 vhca_id, + uint32_t *state_size); +int mlx5vf_cmd_get_vhca_id(struct pci_dev *pdev, u16 function_id, u16 *vhca_id); +int mlx5vf_cmd_save_vhca_state(struct pci_dev *pdev, u16 vhca_id, + u64 state_size, + struct mlx5_vhca_state_data *state); +void mlx5vf_reset_vhca_state(struct mlx5_vhca_state_data *state); +int mlx5vf_cmd_load_vhca_state(struct pci_dev *pdev, u16 vhca_id, + struct mlx5_vhca_state_data *state); +int mlx5vf_add_migration_pages(struct mlx5_vhca_state_data *state, + unsigned int npages); +struct page *mlx5vf_get_migration_page(struct migration_data *data, + unsigned long offset); +#endif /* MLX5_VFIO_CMD_H */ From patchwork Wed Oct 27 09:56:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12586941 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBF51C43217 for ; Wed, 27 Oct 2021 09:59:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C9D2861052 for ; Wed, 27 Oct 2021 09:59:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241381AbhJ0KBc (ORCPT ); Wed, 27 Oct 2021 06:01:32 -0400 Received: from mail-mw2nam12on2069.outbound.protection.outlook.com ([40.107.244.69]:57572 "EHLO NAM12-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241375AbhJ0KA4 (ORCPT ); Wed, 27 Oct 2021 06:00:56 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=QDEXL+i+gju1MFSXRYE8n+t+Zz7up9R5IlVrOAVFhla+DiNds6Exnc5w/YDTBRJZ/mimd/kRQjNpQnXBtihzZuLAzEDDbfIwm1YVgoF3vXhFhABKOK7A/eXVHjB4+7AU4aTcTkosJKfFlqrWuLOwL15bNm2p6xf1ZeH9bNdif3as4dkPKI9Me590DJILl/AdpLgeOuZCIEozoaQTxkEZu9K23hTGj6jKVyCfn0c5T1QWv31y9ytELE6N9/YSkSPmQYkxbaKrg3n0WNlPz34REFSuP10sfEUWHxf9iCDZfeh9eLR0bYVnA0YABRFmHD5Lq9+N6WWiInXM8x/wz2EDYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=dpimkJKPyOZW1OGTSaIeJ3yWU0ox8CDVYx7eeU0n7z0=; b=oCxkUV+64D4O6Aom72K36eY+QrK8LWd0i/T8mFz/CtQJBWCOiu3cqXXQtRdlYYmqziO5HU9RP/J9WqrvnuRA+8GhDB5ZiP7bE2WTNzhE5mKf2QV/qCskD1gHzel4vMF0bwuU5iaNnab/8adswkFgllNjFEvi4rkTj73PIA3Hry8dI7obw0tI3PywrM1iXHGQTBgjbL3SVqzQbiHSMYewUghKj7uQS6zD0LRE34RUp299gDzCF2VQtaMSOHd2PC3l1FDtNoimg70VqQvkTAXg7jDhBx/SL9msNC0Sp/6ufEiIYxq/XqZUlEb8Q28IVHFlKdVoqVYh2+1fcWSaBL6KFg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.35) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dpimkJKPyOZW1OGTSaIeJ3yWU0ox8CDVYx7eeU0n7z0=; b=Om5HiZe5RBr9Ef34nlGiL5vYkrVDl5QmkHohVBBq02ro67gf7+yj9ODJRoBQJxT8WWknaAdztucpN9so9fUTuaM5hdAkerhvVWtyFHYhEy5aWaW8aE1Cr5sKBzT2oVYMkElyhxNBRNoQnVZHZtDg0wUEWNh5pycpQXfecMj6JQz+oUXMTLHb/HpL7hfz22tY+DTgyrSppVfPesqYz11agNDdc5X0Pm08l2R27OV2bA8bROJpCUBsHeeuRHFb3gSi8ob7hF0f1vF13Sb7Iie3XtMJHaKp8GGZ0VnR8Mwe1WC+9thtJzjaWqEyMZx+dV9cyq0gmr/OSmOCefdiAyf89w== Received: from BN9PR03CA0879.namprd03.prod.outlook.com (2603:10b6:408:13c::14) by MWHPR1201MB0046.namprd12.prod.outlook.com (2603:10b6:301:5b::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.20; Wed, 27 Oct 2021 09:58:29 +0000 Received: from BN8NAM11FT003.eop-nam11.prod.protection.outlook.com (2603:10b6:408:13c:cafe::a5) by BN9PR03CA0879.outlook.office365.com (2603:10b6:408:13c::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.18 via Frontend Transport; Wed, 27 Oct 2021 09:58:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.35) smtp.mailfrom=nvidia.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.35 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.35; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.35) by BN8NAM11FT003.mail.protection.outlook.com (10.13.177.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4649.14 via Frontend Transport; Wed, 27 Oct 2021 09:58:29 +0000 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 27 Oct 2021 09:58:28 +0000 Received: from vdi.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 27 Oct 2021 09:58:25 +0000 From: Yishai Hadas To: , , , CC: , , , , , , , , Subject: [PATCH V5 mlx5-next 11/13] vfio/mlx5: Implement vfio_pci driver for mlx5 devices Date: Wed, 27 Oct 2021 12:56:56 +0300 Message-ID: <20211027095658.144468-12-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211027095658.144468-1-yishaih@nvidia.com> References: <20211027095658.144468-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7078f3f2-3b4c-4ff2-a11b-08d9993053c3 X-MS-TrafficTypeDiagnostic: MWHPR1201MB0046: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NGgAsv77cxE5wzzifn/Yl5xYwZSq0Q7IsTRic5wMukfVTM0sdHzjTESZG1uEymCtjpI49C19jxfn+lpEPyccMpAvLuyuOtwatFvkAqaitKKC3jUDklXga+h2rcvotBTeuKZNLxuHWwbB14fpnk/wIxNkv2lLIE8NAXg5YQAx1FGx3AnXW/AKz3CBmBM0QZk4N2Wjcj0lkYmxnggmY2SiIkW5Gte3utbuZ3SAKklHPJzGHKpFNuCJD+ff0mRWRi/HENEVfqO+GYhtTxsU7y7iRKlSMU4LFYHAOH11QMbbPxeX1gFhmCT5inf+TA5XGOL1FJpVhk2vYpR4w7Bhmu4v36SmxbYmKf1eSnPjTRV7k92ULl9RiAUvy2LQL6e0F44GrdsVumUBn6wkSrlSRWQrdjQ7rWAxTVpzgouYeGFDDz1rq0PZRb8aqQPGUHL5OTdotdQ7u3sLcMeO+OfH6U17lcPIoeQRYJU8mtbJtVApbHIkiXOwgu7fHRGgUSpdIbFoDWlEB37ykXVh6P1mJh0T/xGQDBlK0P4gt6dTMzcb7Wi58KduZ1AoF6XyiZT0aGi5Zj/G+U5NbNZ68Knu0GxxFj94oIf/Ly93apFUqMw7Td5kykDpguGKaaY3VXhmo+mfZzM8TcIT3DCaPuI7pWOwDzag1Xmsj2sdR0dXicPWjKvWu227izYjdz9Q1SNc1VNgsH30jfp3B8+CXRtXIVtklIbN4uZy/Rii2qvglgdeNhQ= X-Forefront-Antispam-Report: CIP:216.228.112.35;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid02.nvidia.com;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(7696005)(186003)(6636002)(316002)(8676002)(70206006)(356005)(1076003)(70586007)(83380400001)(36906005)(508600001)(30864003)(336012)(54906003)(5660300002)(426003)(110136005)(86362001)(4326008)(36756003)(2616005)(26005)(8936002)(36860700001)(7636003)(6666004)(47076005)(107886003)(2906002)(82310400003)(21314003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2021 09:58:29.0056 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7078f3f2-3b4c-4ff2-a11b-08d9993053c3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.35];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT003.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1201MB0046 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This patch adds support for vfio_pci driver for mlx5 devices. It uses vfio_pci_core to register to the VFIO subsystem and then implements the mlx5 specific logic in the migration area. The migration implementation follows the definition from uapi/vfio.h and uses the mlx5 VF->PF command channel to achieve it. This patch implements the suspend/resume flows. Signed-off-by: Yishai Hadas Signed-off-by: Leon Romanovsky --- MAINTAINERS | 6 + drivers/vfio/pci/Kconfig | 3 + drivers/vfio/pci/Makefile | 2 + drivers/vfio/pci/mlx5/Kconfig | 10 + drivers/vfio/pci/mlx5/Makefile | 4 + drivers/vfio/pci/mlx5/main.c | 698 +++++++++++++++++++++++++++++++++ 6 files changed, 723 insertions(+) create mode 100644 drivers/vfio/pci/mlx5/Kconfig create mode 100644 drivers/vfio/pci/mlx5/Makefile create mode 100644 drivers/vfio/pci/mlx5/main.c diff --git a/MAINTAINERS b/MAINTAINERS index 8d118d7957d2..3689d452b0ed 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19703,6 +19703,12 @@ L: kvm@vger.kernel.org S: Maintained F: drivers/vfio/platform/ +VFIO MLX5 PCI DRIVER +M: Yishai Hadas +L: kvm@vger.kernel.org +S: Maintained +F: drivers/vfio/pci/mlx5/ + VGA_SWITCHEROO R: Lukas Wunner S: Maintained diff --git a/drivers/vfio/pci/Kconfig b/drivers/vfio/pci/Kconfig index 860424ccda1b..187b9c259944 100644 --- a/drivers/vfio/pci/Kconfig +++ b/drivers/vfio/pci/Kconfig @@ -43,4 +43,7 @@ config VFIO_PCI_IGD To enable Intel IGD assignment through vfio-pci, say Y. endif + +source "drivers/vfio/pci/mlx5/Kconfig" + endif diff --git a/drivers/vfio/pci/Makefile b/drivers/vfio/pci/Makefile index 349d68d242b4..ed9d6f2e0555 100644 --- a/drivers/vfio/pci/Makefile +++ b/drivers/vfio/pci/Makefile @@ -7,3 +7,5 @@ obj-$(CONFIG_VFIO_PCI_CORE) += vfio-pci-core.o vfio-pci-y := vfio_pci.o vfio-pci-$(CONFIG_VFIO_PCI_IGD) += vfio_pci_igd.o obj-$(CONFIG_VFIO_PCI) += vfio-pci.o + +obj-$(CONFIG_MLX5_VFIO_PCI) += mlx5/ diff --git a/drivers/vfio/pci/mlx5/Kconfig b/drivers/vfio/pci/mlx5/Kconfig new file mode 100644 index 000000000000..7088edc4fb28 --- /dev/null +++ b/drivers/vfio/pci/mlx5/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only +config MLX5_VFIO_PCI + tristate "VFIO support for MLX5 PCI devices" + depends on MLX5_CORE + select VFIO_PCI_CORE + help + This provides migration support for MLX5 devices using the VFIO + framework. + + If you don't know what to do here, say N. diff --git a/drivers/vfio/pci/mlx5/Makefile b/drivers/vfio/pci/mlx5/Makefile new file mode 100644 index 000000000000..689627da7ff5 --- /dev/null +++ b/drivers/vfio/pci/mlx5/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_MLX5_VFIO_PCI) += mlx5-vfio-pci.o +mlx5-vfio-pci-y := main.o cmd.o + diff --git a/drivers/vfio/pci/mlx5/main.c b/drivers/vfio/pci/mlx5/main.c new file mode 100644 index 000000000000..467dee08ad77 --- /dev/null +++ b/drivers/vfio/pci/mlx5/main.c @@ -0,0 +1,698 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cmd.h" + +enum { + MLX5VF_PCI_FREEZED = 1 << 0, +}; + +enum { + MLX5VF_REGION_PENDING_BYTES = 1 << 0, + MLX5VF_REGION_DATA_SIZE = 1 << 1, +}; + +enum { + MLX5VF_SUPPORTED_DEVICE_STATES = VFIO_DEVICE_STATE_RUNNING | + VFIO_DEVICE_STATE_SAVING | + VFIO_DEVICE_STATE_RESUMING, +}; + +#define MLX5VF_MIG_REGION_DATA_SIZE SZ_128K +/* Data section offset from migration region */ +#define MLX5VF_MIG_REGION_DATA_OFFSET \ + (sizeof(struct vfio_device_migration_info)) + +#define VFIO_DEVICE_MIGRATION_OFFSET(x) \ + (offsetof(struct vfio_device_migration_info, x)) + +struct mlx5vf_pci_migration_info { + u32 vfio_dev_state; /* VFIO_DEVICE_STATE_XXX */ + u32 dev_state; /* device migration state */ + u32 region_state; /* Use MLX5VF_REGION_XXX */ + u16 vhca_id; + struct mlx5_vhca_state_data vhca_state_data; +}; + +struct mlx5vf_pci_core_device { + struct vfio_pci_core_device core_device; + u8 migrate_cap:1; + /* protect migration state */ + struct mutex state_mutex; + struct mlx5vf_pci_migration_info vmig; +}; + +static int mlx5vf_pci_unquiesce_device(struct mlx5vf_pci_core_device *mvdev) +{ + return mlx5vf_cmd_resume_vhca(mvdev->core_device.pdev, + mvdev->vmig.vhca_id, + MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_MASTER); +} + +static int mlx5vf_pci_quiesce_device(struct mlx5vf_pci_core_device *mvdev) +{ + return mlx5vf_cmd_suspend_vhca( + mvdev->core_device.pdev, mvdev->vmig.vhca_id, + MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_MASTER); +} + +static int mlx5vf_pci_unfreeze_device(struct mlx5vf_pci_core_device *mvdev) +{ + int ret; + + ret = mlx5vf_cmd_resume_vhca(mvdev->core_device.pdev, + mvdev->vmig.vhca_id, + MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_SLAVE); + if (ret) + return ret; + + mvdev->vmig.dev_state &= ~MLX5VF_PCI_FREEZED; + return 0; +} + +static int mlx5vf_pci_freeze_device(struct mlx5vf_pci_core_device *mvdev) +{ + int ret; + + ret = mlx5vf_cmd_suspend_vhca( + mvdev->core_device.pdev, mvdev->vmig.vhca_id, + MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_SLAVE); + if (ret) + return ret; + + mvdev->vmig.dev_state |= MLX5VF_PCI_FREEZED; + return 0; +} + +static int mlx5vf_pci_save_device_data(struct mlx5vf_pci_core_device *mvdev) +{ + u32 state_size = 0; + int ret; + + if (!(mvdev->vmig.dev_state & MLX5VF_PCI_FREEZED)) + return -EFAULT; + + /* If we already read state no reason to re-read */ + if (mvdev->vmig.vhca_state_data.state_size) + return 0; + + ret = mlx5vf_cmd_query_vhca_migration_state( + mvdev->core_device.pdev, mvdev->vmig.vhca_id, &state_size); + if (ret) + return ret; + + return mlx5vf_cmd_save_vhca_state(mvdev->core_device.pdev, + mvdev->vmig.vhca_id, state_size, + &mvdev->vmig.vhca_state_data); +} + +static int mlx5vf_pci_new_write_window(struct mlx5vf_pci_core_device *mvdev) +{ + struct mlx5_vhca_state_data *state_data = &mvdev->vmig.vhca_state_data; + u32 num_pages_needed; + u64 allocated_ready; + u32 bytes_needed; + + /* Check how many bytes are available from previous flows */ + WARN_ON(state_data->num_pages * PAGE_SIZE < + state_data->win_start_offset); + allocated_ready = (state_data->num_pages * PAGE_SIZE) - + state_data->win_start_offset; + WARN_ON(allocated_ready > MLX5VF_MIG_REGION_DATA_SIZE); + + bytes_needed = MLX5VF_MIG_REGION_DATA_SIZE - allocated_ready; + if (!bytes_needed) + return 0; + + num_pages_needed = DIV_ROUND_UP_ULL(bytes_needed, PAGE_SIZE); + return mlx5vf_add_migration_pages(state_data, num_pages_needed); +} + +static ssize_t +mlx5vf_pci_handle_migration_data_size(struct mlx5vf_pci_core_device *mvdev, + char __user *buf, bool iswrite) +{ + struct mlx5vf_pci_migration_info *vmig = &mvdev->vmig; + u64 data_size; + int ret; + + if (iswrite) { + /* data_size is writable only during resuming state */ + if (vmig->vfio_dev_state != VFIO_DEVICE_STATE_RESUMING) + return -EINVAL; + + ret = copy_from_user(&data_size, buf, sizeof(data_size)); + if (ret) + return -EFAULT; + + vmig->vhca_state_data.state_size += data_size; + vmig->vhca_state_data.win_start_offset += data_size; + ret = mlx5vf_pci_new_write_window(mvdev); + if (ret) + return ret; + + } else { + if (vmig->vfio_dev_state != VFIO_DEVICE_STATE_SAVING) + return -EINVAL; + + data_size = min_t(u64, MLX5VF_MIG_REGION_DATA_SIZE, + vmig->vhca_state_data.state_size - + vmig->vhca_state_data.win_start_offset); + ret = copy_to_user(buf, &data_size, sizeof(data_size)); + if (ret) + return -EFAULT; + } + + vmig->region_state |= MLX5VF_REGION_DATA_SIZE; + return sizeof(data_size); +} + +static ssize_t +mlx5vf_pci_handle_migration_data_offset(struct mlx5vf_pci_core_device *mvdev, + char __user *buf, bool iswrite) +{ + static const u64 data_offset = MLX5VF_MIG_REGION_DATA_OFFSET; + int ret; + + /* RO field */ + if (iswrite) + return -EFAULT; + + ret = copy_to_user(buf, &data_offset, sizeof(data_offset)); + if (ret) + return -EFAULT; + + return sizeof(data_offset); +} + +static ssize_t +mlx5vf_pci_handle_migration_pending_bytes(struct mlx5vf_pci_core_device *mvdev, + char __user *buf, bool iswrite) +{ + struct mlx5vf_pci_migration_info *vmig = &mvdev->vmig; + u64 pending_bytes; + int ret; + + /* RO field */ + if (iswrite) + return -EFAULT; + + if (vmig->vfio_dev_state == (VFIO_DEVICE_STATE_SAVING | + VFIO_DEVICE_STATE_RUNNING)) { + /* + * In pre-copy state we have no data to return for now, + * return 0 pending bytes + */ + pending_bytes = 0; + } else { + if (!vmig->vhca_state_data.state_size) + return 0; + pending_bytes = vmig->vhca_state_data.state_size - + vmig->vhca_state_data.win_start_offset; + } + + ret = copy_to_user(buf, &pending_bytes, sizeof(pending_bytes)); + if (ret) + return -EFAULT; + + /* Window moves forward once data from previous iteration was read */ + if (vmig->region_state & MLX5VF_REGION_DATA_SIZE) + vmig->vhca_state_data.win_start_offset += + min_t(u64, MLX5VF_MIG_REGION_DATA_SIZE, pending_bytes); + + WARN_ON(vmig->vhca_state_data.win_start_offset > + vmig->vhca_state_data.state_size); + + /* New iteration started */ + vmig->region_state = MLX5VF_REGION_PENDING_BYTES; + return sizeof(pending_bytes); +} + +static int mlx5vf_load_state(struct mlx5vf_pci_core_device *mvdev) +{ + if (!mvdev->vmig.vhca_state_data.state_size) + return 0; + + return mlx5vf_cmd_load_vhca_state(mvdev->core_device.pdev, + mvdev->vmig.vhca_id, + &mvdev->vmig.vhca_state_data); +} + +static void mlx5vf_reset_mig_state(struct mlx5vf_pci_core_device *mvdev) +{ + struct mlx5vf_pci_migration_info *vmig = &mvdev->vmig; + + vmig->region_state = 0; + mlx5vf_reset_vhca_state(&vmig->vhca_state_data); +} + +static int mlx5vf_pci_set_device_state(struct mlx5vf_pci_core_device *mvdev, + u32 state) +{ + struct mlx5vf_pci_migration_info *vmig = &mvdev->vmig; + u32 old_state = vmig->vfio_dev_state; + u32 flipped_bits = old_state ^ state; + int ret = 0; + + if (old_state == VFIO_DEVICE_STATE_ERROR || + !VFIO_DEVICE_STATE_VALID(state) || + (state & ~MLX5VF_SUPPORTED_DEVICE_STATES)) + return -EINVAL; + + /* Running switches off */ + if ((flipped_bits & VFIO_DEVICE_STATE_RUNNING) && + !(state & VFIO_DEVICE_STATE_RUNNING)) { + ret = mlx5vf_pci_quiesce_device(mvdev); + if (ret) + return ret; + ret = mlx5vf_pci_freeze_device(mvdev); + if (ret) { + if (mlx5vf_pci_unquiesce_device(mvdev)) + vmig->vfio_dev_state = VFIO_DEVICE_STATE_ERROR; + return ret; + } + } + + /* Saving switches on and not running */ + if ((flipped_bits & + (VFIO_DEVICE_STATE_RUNNING | VFIO_DEVICE_STATE_SAVING)) && + ((state & (VFIO_DEVICE_STATE_RUNNING | + VFIO_DEVICE_STATE_SAVING)) == VFIO_DEVICE_STATE_SAVING)) { + ret = mlx5vf_pci_save_device_data(mvdev); + if (ret) + return ret; + } + + /* Resuming switches on */ + if ((flipped_bits & VFIO_DEVICE_STATE_RESUMING) && + (state & VFIO_DEVICE_STATE_RESUMING)) { + mlx5vf_reset_mig_state(mvdev); + ret = mlx5vf_pci_new_write_window(mvdev); + if (ret) + return ret; + } + + /* Resuming switches off */ + if ((flipped_bits & VFIO_DEVICE_STATE_RESUMING) && + !(state & VFIO_DEVICE_STATE_RESUMING)) { + /* deserialize state into the device */ + ret = mlx5vf_load_state(mvdev); + if (ret) { + vmig->vfio_dev_state = VFIO_DEVICE_STATE_ERROR; + return ret; + } + } + + /* Running switches on */ + if ((flipped_bits & VFIO_DEVICE_STATE_RUNNING) && + (state & VFIO_DEVICE_STATE_RUNNING)) { + ret = mlx5vf_pci_unfreeze_device(mvdev); + if (ret) + return ret; + ret = mlx5vf_pci_unquiesce_device(mvdev); + if (ret) { + vmig->vfio_dev_state = VFIO_DEVICE_STATE_ERROR; + return ret; + } + } + + vmig->vfio_dev_state = state; + return 0; +} + +static ssize_t +mlx5vf_pci_handle_migration_device_state(struct mlx5vf_pci_core_device *mvdev, + char __user *buf, bool iswrite) +{ + size_t count = sizeof(mvdev->vmig.vfio_dev_state); + int ret; + + if (iswrite) { + u32 device_state; + + ret = copy_from_user(&device_state, buf, count); + if (ret) + return -EFAULT; + + ret = mlx5vf_pci_set_device_state(mvdev, device_state); + if (ret) + return ret; + } else { + ret = copy_to_user(buf, &mvdev->vmig.vfio_dev_state, count); + if (ret) + return -EFAULT; + } + + return count; +} + +static ssize_t +mlx5vf_pci_copy_user_data_to_device_state(struct mlx5vf_pci_core_device *mvdev, + char __user *buf, size_t count, + u64 offset) +{ + struct mlx5_vhca_state_data *state_data = &mvdev->vmig.vhca_state_data; + char __user *from_buff = buf; + u32 curr_offset; + u32 win_page_offset; + u32 copy_count; + struct page *page; + char *to_buff; + int ret; + + curr_offset = state_data->win_start_offset + offset; + + do { + page = mlx5vf_get_migration_page(&state_data->mig_data, + curr_offset); + if (!page) + return -EINVAL; + + win_page_offset = curr_offset % PAGE_SIZE; + copy_count = min_t(u32, PAGE_SIZE - win_page_offset, count); + + to_buff = kmap_local_page(page); + ret = copy_from_user(to_buff + win_page_offset, from_buff, + copy_count); + kunmap_local(to_buff); + if (ret) + return -EFAULT; + + from_buff += copy_count; + curr_offset += copy_count; + count -= copy_count; + } while (count > 0); + + return 0; +} + +static ssize_t +mlx5vf_pci_copy_device_state_to_user(struct mlx5vf_pci_core_device *mvdev, + char __user *buf, u64 offset, size_t count) +{ + struct mlx5_vhca_state_data *state_data = &mvdev->vmig.vhca_state_data; + char __user *to_buff = buf; + u32 win_available_bytes; + u32 win_page_offset; + u32 copy_count; + u32 curr_offset; + char *from_buff; + struct page *page; + int ret; + + win_available_bytes = + min_t(u64, MLX5VF_MIG_REGION_DATA_SIZE, + mvdev->vmig.vhca_state_data.state_size - + mvdev->vmig.vhca_state_data.win_start_offset); + + if (count + offset > win_available_bytes) + return -EINVAL; + + curr_offset = state_data->win_start_offset + offset; + + do { + page = mlx5vf_get_migration_page(&state_data->mig_data, + curr_offset); + if (!page) + return -EINVAL; + + win_page_offset = curr_offset % PAGE_SIZE; + copy_count = min_t(u32, PAGE_SIZE - win_page_offset, count); + + from_buff = kmap_local_page(page); + ret = copy_to_user(buf, from_buff + win_page_offset, + copy_count); + kunmap_local(from_buff); + if (ret) + return -EFAULT; + + curr_offset += copy_count; + count -= copy_count; + to_buff += copy_count; + } while (count); + + return 0; +} + +static ssize_t +mlx5vf_pci_migration_data_rw(struct mlx5vf_pci_core_device *mvdev, + char __user *buf, size_t count, u64 offset, + bool iswrite) +{ + int ret; + + if (offset + count > MLX5VF_MIG_REGION_DATA_SIZE) + return -EINVAL; + + if (iswrite) + ret = mlx5vf_pci_copy_user_data_to_device_state(mvdev, buf, + count, offset); + else + ret = mlx5vf_pci_copy_device_state_to_user(mvdev, buf, offset, + count); + if (ret) + return ret; + return count; +} + +static ssize_t mlx5vf_pci_mig_rw(struct vfio_pci_core_device *vdev, + char __user *buf, size_t count, loff_t *ppos, + bool iswrite) +{ + struct mlx5vf_pci_core_device *mvdev = + container_of(vdev, struct mlx5vf_pci_core_device, core_device); + u64 pos = *ppos & VFIO_PCI_OFFSET_MASK; + int ret; + + mutex_lock(&mvdev->state_mutex); + /* Copy to/from the migration region data section */ + if (pos >= MLX5VF_MIG_REGION_DATA_OFFSET) { + ret = mlx5vf_pci_migration_data_rw( + mvdev, buf, count, pos - MLX5VF_MIG_REGION_DATA_OFFSET, + iswrite); + goto end; + } + + switch (pos) { + case VFIO_DEVICE_MIGRATION_OFFSET(device_state): + /* This is RW field. */ + if (count != sizeof(mvdev->vmig.vfio_dev_state)) { + ret = -EINVAL; + break; + } + ret = mlx5vf_pci_handle_migration_device_state(mvdev, buf, + iswrite); + break; + case VFIO_DEVICE_MIGRATION_OFFSET(pending_bytes): + /* + * The number of pending bytes still to be migrated from the + * vendor driver. This is RO field. + * Reading this field indicates on the start of a new iteration + * to get device data. + * + */ + ret = mlx5vf_pci_handle_migration_pending_bytes(mvdev, buf, + iswrite); + break; + case VFIO_DEVICE_MIGRATION_OFFSET(data_offset): + /* + * The user application should read data_offset field from the + * migration region. The user application should read the + * device data from this offset within the migration region + * during the _SAVING mode or write the device data during the + * _RESUMING mode. This is RO field. + */ + ret = mlx5vf_pci_handle_migration_data_offset(mvdev, buf, + iswrite); + break; + case VFIO_DEVICE_MIGRATION_OFFSET(data_size): + /* + * The user application should read data_size to get the size + * in bytes of the data copied to the migration region during + * the _SAVING state by the device. The user application should + * write the size in bytes of the data that was copied to + * the migration region during the _RESUMING state by the user. + * This is RW field. + */ + ret = mlx5vf_pci_handle_migration_data_size(mvdev, buf, + iswrite); + break; + default: + ret = -EFAULT; + break; + } + +end: + mutex_unlock(&mvdev->state_mutex); + return ret; +} + +static struct vfio_pci_regops migration_ops = { + .rw = mlx5vf_pci_mig_rw, +}; + +static int mlx5vf_pci_open_device(struct vfio_device *core_vdev) +{ + struct mlx5vf_pci_core_device *mvdev = container_of( + core_vdev, struct mlx5vf_pci_core_device, core_device.vdev); + struct vfio_pci_core_device *vdev = &mvdev->core_device; + int vf_id; + int ret; + + ret = vfio_pci_core_enable(vdev); + if (ret) + return ret; + + if (!mvdev->migrate_cap) { + vfio_pci_core_finish_enable(vdev); + return 0; + } + + vf_id = pci_iov_vf_id(vdev->pdev); + if (vf_id < 0) { + ret = vf_id; + goto out_disable; + } + + ret = mlx5vf_cmd_get_vhca_id(vdev->pdev, vf_id + 1, + &mvdev->vmig.vhca_id); + if (ret) + goto out_disable; + + ret = vfio_pci_register_dev_region(vdev, VFIO_REGION_TYPE_MIGRATION, + VFIO_REGION_SUBTYPE_MIGRATION, + &migration_ops, + MLX5VF_MIG_REGION_DATA_OFFSET + + MLX5VF_MIG_REGION_DATA_SIZE, + VFIO_REGION_INFO_FLAG_READ | + VFIO_REGION_INFO_FLAG_WRITE, + NULL); + if (ret) + goto out_disable; + + mvdev->vmig.vfio_dev_state = VFIO_DEVICE_STATE_RUNNING; + vfio_pci_core_finish_enable(vdev); + return 0; +out_disable: + vfio_pci_core_disable(vdev); + return ret; +} + +static void mlx5vf_pci_close_device(struct vfio_device *core_vdev) +{ + struct mlx5vf_pci_core_device *mvdev = container_of( + core_vdev, struct mlx5vf_pci_core_device, core_device.vdev); + + vfio_pci_core_close_device(core_vdev); + mlx5vf_reset_mig_state(mvdev); +} + +static const struct vfio_device_ops mlx5vf_pci_ops = { + .name = "mlx5-vfio-pci", + .open_device = mlx5vf_pci_open_device, + .close_device = mlx5vf_pci_close_device, + .ioctl = vfio_pci_core_ioctl, + .read = vfio_pci_core_read, + .write = vfio_pci_core_write, + .mmap = vfio_pci_core_mmap, + .request = vfio_pci_core_request, + .match = vfio_pci_core_match, +}; + +static int mlx5vf_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + struct mlx5vf_pci_core_device *mvdev; + int ret; + + mvdev = kzalloc(sizeof(*mvdev), GFP_KERNEL); + if (!mvdev) + return -ENOMEM; + vfio_pci_core_init_device(&mvdev->core_device, pdev, &mlx5vf_pci_ops); + + if (pdev->is_virtfn) { + struct mlx5_core_dev *mdev = + mlx5_vf_get_core_dev(pdev); + + if (mdev) { + if (MLX5_CAP_GEN(mdev, migration)) { + mvdev->migrate_cap = 1; + mutex_init(&mvdev->state_mutex); + } + mlx5_vf_put_core_dev(mdev); + } + } + + ret = vfio_pci_core_register_device(&mvdev->core_device); + if (ret) + goto out_free; + + dev_set_drvdata(&pdev->dev, mvdev); + return 0; + +out_free: + vfio_pci_core_uninit_device(&mvdev->core_device); + kfree(mvdev); + return ret; +} + +static void mlx5vf_pci_remove(struct pci_dev *pdev) +{ + struct mlx5vf_pci_core_device *mvdev = dev_get_drvdata(&pdev->dev); + + vfio_pci_core_unregister_device(&mvdev->core_device); + vfio_pci_core_uninit_device(&mvdev->core_device); + kfree(mvdev); +} + +static const struct pci_device_id mlx5vf_pci_table[] = { + { PCI_DRIVER_OVERRIDE_DEVICE_VFIO(PCI_VENDOR_ID_MELLANOX, 0x101e) }, /* ConnectX Family mlx5Gen Virtual Function */ + {} +}; + +MODULE_DEVICE_TABLE(pci, mlx5vf_pci_table); + +static struct pci_driver mlx5vf_pci_driver = { + .name = KBUILD_MODNAME, + .id_table = mlx5vf_pci_table, + .probe = mlx5vf_pci_probe, + .remove = mlx5vf_pci_remove, + .err_handler = &vfio_pci_core_err_handlers, +}; + +static void __exit mlx5vf_pci_cleanup(void) +{ + pci_unregister_driver(&mlx5vf_pci_driver); +} + +static int __init mlx5vf_pci_init(void) +{ + return pci_register_driver(&mlx5vf_pci_driver); +} + +module_init(mlx5vf_pci_init); +module_exit(mlx5vf_pci_cleanup); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Max Gurtovoy "); +MODULE_AUTHOR("Yishai Hadas "); +MODULE_DESCRIPTION( + "MLX5 VFIO PCI - User Level meta-driver for MLX5 device family"); From patchwork Wed Oct 27 09:56:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12586943 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C5B0C433FE for ; Wed, 27 Oct 2021 09:59:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 18F1C610A0 for ; Wed, 27 Oct 2021 09:59:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241451AbhJ0KBg (ORCPT ); Wed, 27 Oct 2021 06:01:36 -0400 Received: from mail-bn8nam12on2073.outbound.protection.outlook.com ([40.107.237.73]:21601 "EHLO NAM12-BN8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241388AbhJ0KBB (ORCPT ); Wed, 27 Oct 2021 06:01:01 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hN4NaTSeO0hZxRp5eDPoJDWWLiHIvdL52XwBZKbxjB64TwQdoZLQAMFYFHIKr3m6vXUyTHXVRUDX1TbbgyrC7cIlqocRVaU3ZGnvn4pXotZUV3QbLngmwEpVwCF8E1e05IyV4+HGUXNJRVmIvO/TpOuruxFndzvBBJJbO5nix/BPDjo95tW4+MpOgxPaIUTD+BQGImH56zvdMV36ANqfZv6af8KEQhDOVzhy5ppdMyy9MXVmFb6POCP9lXBiyl4lQ1bWNgqB5zffkTDs4D+xMjJ0yS+Dg39ntE0erq3Oedp5LKZ4pWh88PRT1gYoHk+Cg2ky/o54mm8iwizwl7cwWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0ja/rUegBB7659EIbtq3Kdem/6ZPQT+8i4/dTHhY78k=; b=I9Sy2gcucxWPfdI3uyUiMCVKyXY4hbs8p++4iA2+ztSVEaYJOgOqB0olE4c8QCgJn8X4TWjBq4ZYP5ijSoaPruitxKmDhp2/V1Ji0jDGGogb9FN/CywSmpb/HN2Efr/GZdrgN5Rc7SZ6hYHqjiyP4mkSS0Ecz/eEejEQfm0J2Yv+PAFrqWdc4M61kBtp4pP72KtiWB0gdRiCA1QHygpMrgfA0/s+irRiBpAhhCePhEL5q6eMAyxRnspaxatzl0i2u4TEBx/qjRUQyqM2zSjVjC+0v0rOc/zcH6mLNbbsU+Bs5dQ7249cMK+d0y8ihACcL+O6GpmmC70FH5VLS8tPJg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.32) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0ja/rUegBB7659EIbtq3Kdem/6ZPQT+8i4/dTHhY78k=; b=bWa2D7g3vZlg9wnxGPuf/hSS4RErjiNDDJKyuNQwmRJeHz3thHzVu4iKhHUzWm6CqKoWNBIdahpJjF2HntREZBkWncVptuaG4R9HowbpOaFd3uG08amgTqGM6DYQ/nhAfc2WFOqVoZyNmzhRH2ehtLlmNDPZu+qxEcSyC671RsLP6oOrgXxamCrFGWhJDaR7BodKrLy0agB0OcuBbBnj72Gf//YtburOf2WnjdEg26EBTyKHKUvOZHUKeGVE/2H/F0GKDXYs3fkwf5vFM6rlhXyvJU4K5KNZZwHtnxZOhjCX1YGeHu0099QnEjNokqO0wTCZ/8dtA+SEzCroRxotBA== Received: from DS7PR03CA0048.namprd03.prod.outlook.com (2603:10b6:5:3b5::23) by BN8PR12MB3250.namprd12.prod.outlook.com (2603:10b6:408:99::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.18; Wed, 27 Oct 2021 09:58:33 +0000 Received: from DM6NAM11FT011.eop-nam11.prod.protection.outlook.com (2603:10b6:5:3b5:cafe::15) by DS7PR03CA0048.outlook.office365.com (2603:10b6:5:3b5::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.15 via Frontend Transport; Wed, 27 Oct 2021 09:58:33 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.32) smtp.mailfrom=nvidia.com; redhat.com; dkim=none (message not signed) header.d=none;redhat.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.32 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.32; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.32) by DM6NAM11FT011.mail.protection.outlook.com (10.13.172.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4649.14 via Frontend Transport; Wed, 27 Oct 2021 09:58:32 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 27 Oct 2021 02:58:31 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 27 Oct 2021 09:58:31 +0000 Received: from vdi.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 27 Oct 2021 09:58:28 +0000 From: Yishai Hadas To: , , , CC: , , , , , , , , Subject: [PATCH V5 mlx5-next 12/13] vfio/pci: Expose vfio_pci_core_aer_err_detected() Date: Wed, 27 Oct 2021 12:56:57 +0300 Message-ID: <20211027095658.144468-13-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211027095658.144468-1-yishaih@nvidia.com> References: <20211027095658.144468-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7534a1ba-2801-4e8d-b8e4-08d999305601 X-MS-TrafficTypeDiagnostic: BN8PR12MB3250: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3968; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qBzf0zSL4VMbtTg62aYY35XlOxgI8vmHuG0hKmHwIYo2VxUC4Dw/acpYK27lPIsU5YxnUK5kN58TNpxzu7mSqeP05Mvu0nAtAeIhbCXu94+q2FHyVU8dEW+hanRWjsMh46zt1FQ0ViTB5FlG0NTgpA2ll69fVeZisCrM1eqL/bxvBqlSAoe6YuC3yNxF4wCHSBTKc623ERbb8x1UE+AI89r40SQmrR47l3TWOSfZViHHhEwvmqWWOZ+G75xAyFxTxUkxtzblOgbL988Q16n2SSpzquMPvAMe4bFNG8GsEoDaQdV1HcJMLfcyh1r4MFdjLcpIZjZGL2ZZeK2vuvjr71WaUBEozilmR3XPIo4ue94tAhnBuUtPcusnrgAQJqhKQuZuhp/GUL2xrpeqKuDJ0LIWtj56gqdJYMYpVeB0RGJXR/H/eh3rlyJ985GXrX6BroeykE+Zp/KNXpoVVxLxicgsA96tWLKWJ1k1DNxx4ChkcC80Cdl0EyfPWvCknH6OjQjVOjcsP7M+G5MEpmXiXBOpT9gzlyVzyHpUyY4WU1E7QXIkZ/r8ybZ3ZqEyccMRa2tVN/NKlb8nQkF5ANV3j5Q2O0Y9hhlsvbA9j59PVLs4/kxJ0hQMfkvqrU+P4opacLl9fsDK6Gsj4X3KZj5qG4ZOaDNbSSKrOdMDGVgJvaZqv7Ay7YBwNW8BX5uZ6mIzR6FQmUKvS4XY8Z91tOeNyQ== X-Forefront-Antispam-Report: CIP:216.228.112.32;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid01.nvidia.com;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(26005)(82310400003)(54906003)(8936002)(83380400001)(426003)(36860700001)(110136005)(4326008)(36756003)(70206006)(186003)(6666004)(508600001)(6636002)(107886003)(316002)(86362001)(2906002)(1076003)(356005)(47076005)(2616005)(70586007)(7696005)(5660300002)(8676002)(336012)(7636003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2021 09:58:32.8010 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7534a1ba-2801-4e8d-b8e4-08d999305601 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.32];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT011.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3250 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Expose vfio_pci_core_aer_err_detected() to be used by drivers as part of their pci_error_handlers structure. Next patch for mlx5 driver will use it. Signed-off-by: Yishai Hadas --- drivers/vfio/pci/vfio_pci_core.c | 7 ++++--- include/linux/vfio_pci_core.h | 2 ++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index e581a327f90d..80e08e17d027 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -1901,8 +1901,8 @@ void vfio_pci_core_unregister_device(struct vfio_pci_core_device *vdev) } EXPORT_SYMBOL_GPL(vfio_pci_core_unregister_device); -static pci_ers_result_t vfio_pci_aer_err_detected(struct pci_dev *pdev, - pci_channel_state_t state) +pci_ers_result_t vfio_pci_core_aer_err_detected(struct pci_dev *pdev, + pci_channel_state_t state) { struct vfio_pci_core_device *vdev; struct vfio_device *device; @@ -1924,6 +1924,7 @@ static pci_ers_result_t vfio_pci_aer_err_detected(struct pci_dev *pdev, return PCI_ERS_RESULT_CAN_RECOVER; } +EXPORT_SYMBOL_GPL(vfio_pci_core_aer_err_detected); int vfio_pci_core_sriov_configure(struct pci_dev *pdev, int nr_virtfn) { @@ -1946,7 +1947,7 @@ int vfio_pci_core_sriov_configure(struct pci_dev *pdev, int nr_virtfn) EXPORT_SYMBOL_GPL(vfio_pci_core_sriov_configure); const struct pci_error_handlers vfio_pci_core_err_handlers = { - .error_detected = vfio_pci_aer_err_detected, + .error_detected = vfio_pci_core_aer_err_detected, }; EXPORT_SYMBOL_GPL(vfio_pci_core_err_handlers); diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index ef9a44b6cf5d..6bde57780311 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -230,6 +230,8 @@ int vfio_pci_core_match(struct vfio_device *core_vdev, char *buf); int vfio_pci_core_enable(struct vfio_pci_core_device *vdev); void vfio_pci_core_disable(struct vfio_pci_core_device *vdev); void vfio_pci_core_finish_enable(struct vfio_pci_core_device *vdev); +pci_ers_result_t vfio_pci_core_aer_err_detected(struct pci_dev *pdev, + pci_channel_state_t state); static inline bool vfio_pci_is_vga(struct pci_dev *pdev) { From patchwork Wed Oct 27 09:56:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12586945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1611EC433F5 for ; Wed, 27 Oct 2021 09:59:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EB3E06109E for ; Wed, 27 Oct 2021 09:59:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241356AbhJ0KCF (ORCPT ); Wed, 27 Oct 2021 06:02:05 -0400 Received: from mail-bn8nam08on2046.outbound.protection.outlook.com ([40.107.100.46]:13952 "EHLO NAM04-BN8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241404AbhJ0KBO (ORCPT ); Wed, 27 Oct 2021 06:01:14 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ZHTvXQYJqgIAeOCWpIO2vUVgGdvKpwnpBQngMRh5uApqdxMowcFCbqDyFzad3TkQxJA9YmRf0p4kkn/tvmxHGuXskfsJbegGMfpqWkFPND59REYqwRlWh+6bGKGUVl+bMo027X0OatkwyDRyCXumBpQShawG479b69GSKIhCd3g2tOaH4R7VrZljkpk6jU3X5S8OXxDus7HTHXcmY4M+33TBwU01rM3EfnXm0S8HE2dO/03LJO0MqAAuI7gzxLzyj2KkHjF844x9GawrQxVwxPDwyqexq0C5L2ifYeGMMWagVJsCYFSVVxs7F5fM/T1etJlbGVBQPIfuNvxCRGtJDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=gWw4s5zff8tpYbvenChfKHDHCcPIEZCXHB0FTB/vMfM=; b=ECmd0WJwUsBMDDL+avrAnF6ZrKM0VPfaXvgKZbmLSAui3wTZce5oATs873Gxqcg0d+771S2+aBg0WUS04LxBCbcduD6fmGbepVDcMA5efmgb8xARg4rZkWqsN81zcJnmtQrZdSWESLrhm9nXZbORfmEhSJcUHjGq28MzsD4fbCJ065iyaek6swMnaKOVPEUwPUl9vosiTMa2kRQ3KhSSgkVPWAJuuSAxqvZv+rIUkXgO8xYSzw7xJi6/3svz16NXkpDaY1LptrPRKSiofN7NOD+xUjP5el9k09h2Sg+LYzMPRzCNMdcvDt6UluYq2ZOpNGApxQIJQFEgh3s0JJJpww== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.36) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=gWw4s5zff8tpYbvenChfKHDHCcPIEZCXHB0FTB/vMfM=; b=tQ22dNZEmMaMp2ew3cTErqovk+sfByu9L6/7i97mTA1T+MLhD4mX7PEXU1IIbv41JPvRnDCkOFgN6njCrsZxwqc84S7Xx26Q63+UXT0XDBq5ynMmTV8r9avArU0pgjzJckenh3AgfuAsBRGJfovB4U96+UcGzjMWGiCtKwAizREdyFQaKnYWGH9S/KqhyfixH6CCuPpPWXdRVTqbQq8yzknK0UKnF5VwCFtDVD0RoJaaI5as+4HT1PqBg0eCtvViCG6ApvHlwM5g7xK/JbvlSzHMOt+v8BfB/CSV/ljm8fLV9m8Fs3kiuPCzpf28bfzd3g+p6L/GTUfox+RIpjZcBQ== Received: from BN6PR14CA0005.namprd14.prod.outlook.com (2603:10b6:404:79::15) by DM6PR12MB5022.namprd12.prod.outlook.com (2603:10b6:5:20e::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.18; Wed, 27 Oct 2021 09:58:47 +0000 Received: from BN8NAM11FT020.eop-nam11.prod.protection.outlook.com (2603:10b6:404:79:cafe::ac) by BN6PR14CA0005.outlook.office365.com (2603:10b6:404:79::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.18 via Frontend Transport; Wed, 27 Oct 2021 09:58:47 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.36) smtp.mailfrom=nvidia.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.36 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.36; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.36) by BN8NAM11FT020.mail.protection.outlook.com (10.13.176.223) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4649.14 via Frontend Transport; Wed, 27 Oct 2021 09:58:46 +0000 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 27 Oct 2021 09:58:34 +0000 Received: from vdi.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 27 Oct 2021 09:58:32 +0000 From: Yishai Hadas To: , , , CC: , , , , , , , , Subject: [PATCH V5 mlx5-next 13/13] vfio/mlx5: Use its own PCI reset_done error handler Date: Wed, 27 Oct 2021 12:56:58 +0300 Message-ID: <20211027095658.144468-14-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211027095658.144468-1-yishaih@nvidia.com> References: <20211027095658.144468-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f89cc3c2-52bb-4d43-9fda-08d999305e65 X-MS-TrafficTypeDiagnostic: DM6PR12MB5022: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QWtf67fSUakBnwl2lTKs/+1KTmwYCV5wy4uFvp2506cWqxGt78D80rhRQCF9+wpVjqb83JJCp/D/wwA+ruWoAlF0893y0SWwjcFBvOE9yrlfsypPnkJDzN01Va1ZpdzNNnV40GezUyIFl8JErpy13/QeLzec903s5NLmbU+KH11JnVoO0LL/a1Hl2gu3zPrsXrCspsliPBBtZRHsXjvJoVAjAnbOprs65HyI0/BT9VbYXT5KQsDJ0sPLZ/OXiU4XUdbSWKN3EneQ29zeXp+ed6oXuI2uEKa/wdl2KSSJV6gCXtUieqB4ns4WIsV4VQUf13l13lraXjQP+TJ2YLmufBFZXduWsszSECeZ/sK2uJOeT1KL7GTF74XqQwpMcrxI3qUaONccIbCg/gHTw1Tywan/Y1vNBX0alkr/6WkLfV7H69xtM4OsN+sz4lWNfqMpQWj4NhIPidBkjX6qeOdOYSEVFYGJ8FBXx6/O4U8rcgyQDF6IS56P6Ei17atyVNtSkmmFewA/IK4MhIcOMs444AYoSqvYlO0Yg2TeJg6wdzcLvyj0KgOZofiywvGqYQrk/LQcJHMm0nNp9DgXr6+/sbmKHweomX3DfpuxQbiSRyJbWIwbhSx9m6BBX3PQ5uXoLXz2UcFVrifiuuoXAPdGS9Z3y6oHCpA9YLpd8VgyDhqFK60dSJzfVaht78nBQDyJXc47RGLcseOCxCFD+5obYA== X-Forefront-Antispam-Report: CIP:216.228.112.36;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid05.nvidia.com;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(36756003)(36906005)(5660300002)(336012)(8676002)(426003)(82310400003)(316002)(7696005)(110136005)(107886003)(508600001)(70206006)(8936002)(36860700001)(6636002)(7636003)(54906003)(186003)(70586007)(83380400001)(1076003)(6666004)(2906002)(4326008)(356005)(2616005)(26005)(47076005)(86362001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2021 09:58:46.7145 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f89cc3c2-52bb-4d43-9fda-08d999305e65 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.36];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB5022 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Register its own handler for pci_error_handlers.reset_done and update state accordingly. Signed-off-by: Yishai Hadas Signed-off-by: Leon Romanovsky --- drivers/vfio/pci/mlx5/main.c | 56 ++++++++++++++++++++++++++++++++++-- 1 file changed, 54 insertions(+), 2 deletions(-) diff --git a/drivers/vfio/pci/mlx5/main.c b/drivers/vfio/pci/mlx5/main.c index 467dee08ad77..a94cb9cdb82e 100644 --- a/drivers/vfio/pci/mlx5/main.c +++ b/drivers/vfio/pci/mlx5/main.c @@ -55,8 +55,11 @@ struct mlx5vf_pci_migration_info { struct mlx5vf_pci_core_device { struct vfio_pci_core_device core_device; u8 migrate_cap:1; + u8 deferred_reset:1; /* protect migration state */ struct mutex state_mutex; + /* protect the reset_done flow */ + spinlock_t reset_lock; struct mlx5vf_pci_migration_info vmig; }; @@ -473,6 +476,49 @@ mlx5vf_pci_migration_data_rw(struct mlx5vf_pci_core_device *mvdev, return count; } +/* + * This function is called in all state_mutex unlock cases to + * handle a 'deferred_reset' if exists. + */ +static void mlx5vf_state_mutex_unlock(struct mlx5vf_pci_core_device *mvdev) +{ +again: + spin_lock(&mvdev->reset_lock); + if (mvdev->deferred_reset) { + mvdev->deferred_reset = false; + spin_unlock(&mvdev->reset_lock); + mlx5vf_reset_mig_state(mvdev); + mvdev->vmig.vfio_dev_state = VFIO_DEVICE_STATE_RUNNING; + goto again; + } + mutex_unlock(&mvdev->state_mutex); + spin_unlock(&mvdev->reset_lock); +} + +static void mlx5vf_pci_aer_reset_done(struct pci_dev *pdev) +{ + struct mlx5vf_pci_core_device *mvdev = dev_get_drvdata(&pdev->dev); + + if (!mvdev->migrate_cap) + return; + + /* + * As the higher VFIO layers are holding locks across reset and using + * those same locks with the mm_lock we need to prevent ABBA deadlock + * with the state_mutex and mm_lock. + * In case the state_mutex was taken already we defer the cleanup work + * to the unlock flow of the other running context. + */ + spin_lock(&mvdev->reset_lock); + mvdev->deferred_reset = true; + if (!mutex_trylock(&mvdev->state_mutex)) { + spin_unlock(&mvdev->reset_lock); + return; + } + spin_unlock(&mvdev->reset_lock); + mlx5vf_state_mutex_unlock(mvdev); +} + static ssize_t mlx5vf_pci_mig_rw(struct vfio_pci_core_device *vdev, char __user *buf, size_t count, loff_t *ppos, bool iswrite) @@ -541,7 +587,7 @@ static ssize_t mlx5vf_pci_mig_rw(struct vfio_pci_core_device *vdev, } end: - mutex_unlock(&mvdev->state_mutex); + mlx5vf_state_mutex_unlock(mvdev); return ret; } @@ -636,6 +682,7 @@ static int mlx5vf_pci_probe(struct pci_dev *pdev, if (MLX5_CAP_GEN(mdev, migration)) { mvdev->migrate_cap = 1; mutex_init(&mvdev->state_mutex); + spin_lock_init(&mvdev->reset_lock); } mlx5_vf_put_core_dev(mdev); } @@ -670,12 +717,17 @@ static const struct pci_device_id mlx5vf_pci_table[] = { MODULE_DEVICE_TABLE(pci, mlx5vf_pci_table); +const struct pci_error_handlers mlx5vf_err_handlers = { + .reset_done = mlx5vf_pci_aer_reset_done, + .error_detected = vfio_pci_core_aer_err_detected, +}; + static struct pci_driver mlx5vf_pci_driver = { .name = KBUILD_MODNAME, .id_table = mlx5vf_pci_table, .probe = mlx5vf_pci_probe, .remove = mlx5vf_pci_remove, - .err_handler = &vfio_pci_core_err_handlers, + .err_handler = &mlx5vf_err_handlers, }; static void __exit mlx5vf_pci_cleanup(void)