From patchwork Thu Oct 28 01:54:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sankeerth Billakanti (QUIC)" X-Patchwork-Id: 12589101 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A973EC433F5 for ; Thu, 28 Oct 2021 01:55:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 880A461175 for ; Thu, 28 Oct 2021 01:55:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229791AbhJ1B5j (ORCPT ); Wed, 27 Oct 2021 21:57:39 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:52873 "EHLO alexa-out-sd-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229534AbhJ1B5j (ORCPT ); Wed, 27 Oct 2021 21:57:39 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1635386113; x=1666922113; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Kw3ao/FFQ37G4UzZQMgO4SaJu5IszBgc/bRHQXs8bio=; b=NUW9FeYjfnfvEneykoDuHK5DPAJs9v40iTx+e6ckZKfR0picn6GDumnr 6EfGret2kmG1oE9vYa3F+uLgrC/LDT7SaQ45h/MLKkpeWju9QvmaVFRJ4 22aNLKiHrSmPBELWyCSJ6DgWIcc0IP/P0k+0SoQAl0/txVW4X6GxGzPFM U=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-01.qualcomm.com with ESMTP; 27 Oct 2021 18:55:13 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2021 18:55:12 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Wed, 27 Oct 2021 18:55:12 -0700 Received: from sbillaka-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Wed, 27 Oct 2021 18:55:08 -0700 From: Sankeerth Billakanti To: , , , CC: Sankeerth Billakanti , , , , , , , , , Sankeerth Billakanti Subject: [PATCH v3 1/6] dt-bindings: msm/dp: Add DP compatible strings for sc7280 Date: Thu, 28 Oct 2021 07:24:43 +0530 Message-ID: <1635386088-18089-2-git-send-email-quic_sbillaka@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1635386088-18089-1-git-send-email-quic_sbillaka@quicinc.com> References: <1635386088-18089-1-git-send-email-quic_sbillaka@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sankeerth Billakanti The Qualcomm SC7280 platform supports one eDP controller and a DP controller. This change will add the compatible string for both eDP and DP to msm dp-controller binding. Signed-off-by: Sankeerth Billakanti changes in v3: - Modify the subject (Doug Anderson) - Add sc7280-dp also to the list (Stephen Boyd) changes in v2: - Sort alphabetically (Stephen Boyd) - Cleanup residual stale changes in the patch (Matthias Kaehlcke) - Modify the subject (Doug Anderson) Reviewed-by: Stephen Boyd --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 63e585f..5457612 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -17,6 +17,8 @@ properties: compatible: enum: - qcom,sc7180-dp + - qcom,sc7280-dp + - qcom,sc7280-edp - qcom,sc8180x-dp - qcom,sc8180x-edp From patchwork Thu Oct 28 01:54:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sankeerth Billakanti (QUIC)" X-Patchwork-Id: 12589103 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E33AC433F5 for ; Thu, 28 Oct 2021 01:55:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 175AC61166 for ; Thu, 28 Oct 2021 01:55:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229822AbhJ1B5t (ORCPT ); Wed, 27 Oct 2021 21:57:49 -0400 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:60028 "EHLO alexa-out-sd-02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229534AbhJ1B5s (ORCPT ); Wed, 27 Oct 2021 21:57:48 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1635386123; x=1666922123; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=2w+3dbaIJvKI6UZBYIHQTP+MHLtDal/bltQL0fKnLvE=; b=ac56nKJq7Q6s7FirlyBMWIA7B6zirbMubx/a1DOLKzvDjqkQKPvWpfcF 6U9drUJBrJRG27+xRQe70ZlCwiV31kfkX8vDaI9fDQvJasPLTY4HV3T0I YwgesqB+ZyEXqwD/UAnhXYlBv+QjyGvBurJ6K+qpcVfFqgh9iUz+tdXLU c=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-02.qualcomm.com with ESMTP; 27 Oct 2021 18:55:22 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2021 18:55:22 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Wed, 27 Oct 2021 18:55:22 -0700 Received: from sbillaka-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Wed, 27 Oct 2021 18:55:17 -0700 From: Sankeerth Billakanti To: , , , CC: Sankeerth Billakanti , , , , , , , , , Subject: [PATCH v3 2/6] drm/msm/dp: Add DP controllers for sc7280 Date: Thu, 28 Oct 2021 07:24:44 +0530 Message-ID: <1635386088-18089-3-git-send-email-quic_sbillaka@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1635386088-18089-1-git-send-email-quic_sbillaka@quicinc.com> References: <1635386088-18089-1-git-send-email-quic_sbillaka@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The eDP controller on SC7280 is similar to the eDP/DP controllers supported by the current driver implementation. SC7280 supports one EDP and one DP controller which can operate concurrently. This change adds the support for eDP and DP controller on sc7280. Signed-off-by: Sankeerth Billakanti changes in v3: - Split into patches according to function (Dmitry Baryshkov) - Use DP_CONTROLLER_1 for eDP controller intf (Dmitry Baryshkov) - Use DP_CONTROLLER_0 for sc7280-dp (Dmitry Baryshkov) - Add macro in drm_helper.h for checking ssc capability (Stephen Boyd) - Use existing macro to check assr capability (Stephen Boyd) - Add comment for HPD_INIT_SETUP delay (Stephen Boyd) changes in v2: - Don't initialize variables to 0 (Stephen Boyd) - Use const for read-only dpcd (Stephen Boyd) - Remove zero pixel clock check (Stephen Boyd) - Sort compatible strings alphabetically (Stephen Boyd) - Use pwm_bl.c for backlight instead of gpio (Stephen Boyd) - Change return type for functions returning always 0 (Matthias Kaehlcke) Reviewed-by: Stephen Boyd --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++-- drivers/gpu/drm/msm/dp/dp_display.c | 9 +++++++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index ce6f32a..2b4dc9d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -856,9 +856,9 @@ static const struct dpu_intf_cfg sm8150_intf[] = { }; static const struct dpu_intf_cfg sc7280_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), - INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), + INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), }; /************************************************************* diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index aba8aa4..61385d6 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -135,8 +135,17 @@ static const struct msm_dp_config sc7180_dp_cfg = { .num_descs = 1, }; +static const struct msm_dp_config sc7280_dp_cfg = { + .descs = (const struct msm_dp_desc[]) { + [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, + [MSM_DP_CONTROLLER_1] = { .io_start = 0x0aea0000, .connector_type = DRM_MODE_CONNECTOR_eDP }, + }, + .num_descs = 2, +}; + static const struct of_device_id dp_dt_match[] = { { .compatible = "qcom,sc7180-dp", .data = &sc7180_dp_cfg }, + { .compatible = "qcom,sc7280-edp", .data = &sc7280_dp_cfg }, {} }; From patchwork Thu Oct 28 01:54:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sankeerth Billakanti (QUIC)" X-Patchwork-Id: 12589105 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CAD6C433EF for ; Thu, 28 Oct 2021 01:55:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4A9D6611AD for ; Thu, 28 Oct 2021 01:55:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229534AbhJ1B54 (ORCPT ); Wed, 27 Oct 2021 21:57:56 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:50010 "EHLO alexa-out-sd-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229703AbhJ1B54 (ORCPT ); Wed, 27 Oct 2021 21:57:56 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1635386130; x=1666922130; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=e6BovwE7mtBe8nBM3DNZlyFYaKk0sA6tsi4+wUSC8HA=; b=D6waxV1ADwizAt2jgnZbegqms/W+5vBt8hR83XAO1L12RgXlTVeEO0Oi 0XBwkNZPHiU4G+g4Up2Py9cw0u2AzE7YNnxEAWktLu8sAR94C66e7WxB7 xZSKvX6sMo9WKCAdzXe8U9PUwmHuQwV8Wu9YH/Zmc8Wwc7ks3AvcPVT5d s=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 27 Oct 2021 18:55:30 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2021 18:55:30 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Wed, 27 Oct 2021 18:55:29 -0700 Received: from sbillaka-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Wed, 27 Oct 2021 18:55:25 -0700 From: Sankeerth Billakanti To: , , , CC: Sankeerth Billakanti , , , , , , , , , Subject: [PATCH v3 3/6] drm/dp: Add macro to check max_downspread capability Date: Thu, 28 Oct 2021 07:24:45 +0530 Message-ID: <1635386088-18089-4-git-send-email-quic_sbillaka@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1635386088-18089-1-git-send-email-quic_sbillaka@quicinc.com> References: <1635386088-18089-1-git-send-email-quic_sbillaka@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a macro to check for the max_downspread capability in drm_dp_helper. Signed-off-by: Sankeerth Billakanti Reviewed-by: Stephen Boyd --- include/drm/drm_dp_helper.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index afdf7f4..b39e7a0 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1784,6 +1784,12 @@ drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) } static inline bool +drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5; +} + +static inline bool drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { return dpcd[DP_DPCD_REV] >= 0x14 && From patchwork Thu Oct 28 01:54:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sankeerth Billakanti (QUIC)" X-Patchwork-Id: 12589107 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24398C433F5 for ; Thu, 28 Oct 2021 01:55:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 090D661212 for ; Thu, 28 Oct 2021 01:55:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229778AbhJ1B6E (ORCPT ); Wed, 27 Oct 2021 21:58:04 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:35090 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229877AbhJ1B6E (ORCPT ); Wed, 27 Oct 2021 21:58:04 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1635386138; x=1666922138; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=ZF1/1qhmIp3g86UTXX3h3Puh9hFYHW37oCxJLoFZmug=; b=u5oL79UrjqctlBpzgKQTdNovVCqgGiSw/41TIrvL5FZWwjcz40nsmpHK BNvAVkm2Y/p6njWZck6m0KlO1dmkP60vMY3wNuIzyctpdaRWxbK35aCi0 LZX+OlHiIW5f974ew8nbchcjfl5lE5+cgskUKTyc+KbTLyQ9Rn5YF01LB s=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 27 Oct 2021 18:55:38 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2021 18:55:37 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Wed, 27 Oct 2021 18:55:36 -0700 Received: from sbillaka-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Wed, 27 Oct 2021 18:55:32 -0700 From: Sankeerth Billakanti To: , , , CC: Sankeerth Billakanti , , , , , , , , , Subject: [PATCH v3 4/6] drm/msm/dp: Enable downspread for supported DP sinks Date: Thu, 28 Oct 2021 07:24:46 +0530 Message-ID: <1635386088-18089-5-git-send-email-quic_sbillaka@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1635386088-18089-1-git-send-email-quic_sbillaka@quicinc.com> References: <1635386088-18089-1-git-send-email-quic_sbillaka@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The sc7280 eDP sink that supports downspread will fail link training if source does not enable SSC / downspread. This change will set the downspread bit in the DP sink if supported and indicate SSC support to the DP PHY driver. Signed-off-by: Sankeerth Billakanti Reviewed-by: Stephen Boyd --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 62e75dc..a40e798 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1228,7 +1228,9 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, int *training_step) { int ret = 0; + const u8 *dpcd = ctrl->panel->dpcd; u8 encoding = DP_SET_ANSI_8B10B; + u8 ssc; struct dp_link_info link_info = {0}; dp_ctrl_config_ctrl(ctrl); @@ -1238,6 +1240,12 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING; dp_aux_link_configure(ctrl->aux, &link_info); + + if (drm_dp_max_downspread(dpcd)) { + ssc = DP_SPREAD_AMP_0_5; + drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, &ssc, 1); + } + drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, &encoding, 1); @@ -1312,9 +1320,11 @@ static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) struct dp_io *dp_io = &ctrl->parser->io; struct phy *phy = dp_io->phy; struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; + const u8 *dpcd = ctrl->panel->dpcd; opts_dp->lanes = ctrl->link->link_params.num_lanes; opts_dp->link_rate = ctrl->link->link_params.rate / 100; + opts_dp->ssc = drm_dp_max_downspread(dpcd); dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link", ctrl->link->link_params.rate * 1000); @@ -1406,7 +1416,7 @@ void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl) static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl) { - u8 *dpcd = ctrl->panel->dpcd; + const u8 *dpcd = ctrl->panel->dpcd; /* * For better interop experience, used a fixed NVID=0x8000 From patchwork Thu Oct 28 01:54:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sankeerth Billakanti (QUIC)" X-Patchwork-Id: 12589109 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D2D7C433EF for ; Thu, 28 Oct 2021 01:55:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 072FF6125F for ; Thu, 28 Oct 2021 01:55:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229906AbhJ1B6M (ORCPT ); Wed, 27 Oct 2021 21:58:12 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:50035 "EHLO alexa-out-sd-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229957AbhJ1B6L (ORCPT ); Wed, 27 Oct 2021 21:58:11 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1635386145; x=1666922145; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=lMD3kYWOFV+pivVI9FG3pMqNQ7yrz03GZ9yD9lYfO+U=; b=FC7GK9pu0LJecxmCeir97Bz4J0401EelK8QY3u3Z5YoCWO2mVywNSLI5 Dj9vahjdYSM4TBlfRq9QrzlphHX8KGSk+PoeaMs0aMgYrsvlWlzCriysH taHb25LZ1wE2m+rpJfZB5G7OlrPAlL4dL/txX8OhEPy6godonDwTasrVq c=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-01.qualcomm.com with ESMTP; 27 Oct 2021 18:55:45 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2021 18:55:44 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Wed, 27 Oct 2021 18:55:44 -0700 Received: from sbillaka-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Wed, 27 Oct 2021 18:55:40 -0700 From: Sankeerth Billakanti To: , , , CC: Sankeerth Billakanti , , , , , , , , , Subject: [PATCH v3 5/6] drm/msm/dp: Enable ASSR for supported DP sinks Date: Thu, 28 Oct 2021 07:24:47 +0530 Message-ID: <1635386088-18089-6-git-send-email-quic_sbillaka@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1635386088-18089-1-git-send-email-quic_sbillaka@quicinc.com> References: <1635386088-18089-1-git-send-email-quic_sbillaka@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The eDP sink on sc7280 supports ASSR and dp driver will enable ASSR in the source hardware. The driver needs to enable the ASSR field in the DPCD configuration register to avoid screen corruption. This change will enable ASSR if supported in the sink device. Signed-off-by: Sankeerth Billakanti Reviewed-by: Stephen Boyd --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index a40e798..c724cb0 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -119,13 +119,13 @@ void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl) static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl) { u32 config = 0, tbd; - u8 *dpcd = ctrl->panel->dpcd; + const u8 *dpcd = ctrl->panel->dpcd; /* Default-> LSCLK DIV: 1/4 LCLK */ config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); /* Scrambler reset enable */ - if (dpcd[DP_EDP_CONFIGURATION_CAP] & DP_ALTERNATE_SCRAMBLER_RESET_CAP) + if (drm_dp_alternate_scrambler_reset_cap(dpcd)) config |= DP_CONFIGURATION_CTRL_ASSR; tbd = dp_link_get_test_bits_depth(ctrl->link, @@ -1231,6 +1231,7 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, const u8 *dpcd = ctrl->panel->dpcd; u8 encoding = DP_SET_ANSI_8B10B; u8 ssc; + u8 assr; struct dp_link_info link_info = {0}; dp_ctrl_config_ctrl(ctrl); @@ -1249,6 +1250,12 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, &encoding, 1); + if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { + assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; + drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET, + &assr, 1); + } + ret = dp_ctrl_link_train_1(ctrl, training_step); if (ret) { DRM_ERROR("link training #1 failed. ret=%d\n", ret); From patchwork Thu Oct 28 01:54:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sankeerth Billakanti (QUIC)" X-Patchwork-Id: 12589111 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76E09C433EF for ; Thu, 28 Oct 2021 01:55:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 538466126A for ; Thu, 28 Oct 2021 01:55:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229888AbhJ1B6S (ORCPT ); Wed, 27 Oct 2021 21:58:18 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:33421 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229885AbhJ1B6S (ORCPT ); Wed, 27 Oct 2021 21:58:18 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1635386152; x=1666922152; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=PumI7KYEnaLZedKWySsRxRR6/fjZlsD1mJD7/WiWdxk=; b=EHI+cn+z/irtcvFviIO/Tc3ad48fi4wBX/LKI9Gxz3cgD572pnjDob0f Ma0LwolewMjARj+C2eGUz/6ceY7hmUmaLIPME7kTYqu58AVLiXNFADJAH oHiZN0h2vdBrGyHej+hq1c6lUcHXQ2Irmf/MyDnR+dJNEbyr6oX/X1F6k 4=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 27 Oct 2021 18:55:52 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2021 18:55:51 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Wed, 27 Oct 2021 18:55:51 -0700 Received: from sbillaka-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Wed, 27 Oct 2021 18:55:46 -0700 From: Sankeerth Billakanti To: , , , CC: Sankeerth Billakanti , , , , , , , , , Subject: [PATCH v3 6/6] drm/msm/dp: Remove the hpd init delay for eDP Date: Thu, 28 Oct 2021 07:24:48 +0530 Message-ID: <1635386088-18089-7-git-send-email-quic_sbillaka@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1635386088-18089-1-git-send-email-quic_sbillaka@quicinc.com> References: <1635386088-18089-1-git-send-email-quic_sbillaka@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org DP driver needs a 10 second delay before phy_init so that the usb combo phy initializes and sets up the necessary clocks for usb devices such as keyboard and mouse. eDP controller uses a standalone phy and need not wait for phy initialization from any other component. This change will remove the delay for eDP controller. Signed-off-by: Sankeerth Billakanti --- drivers/gpu/drm/msm/dp/dp_display.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 61385d6..de6a1fd 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1430,6 +1430,7 @@ void __exit msm_dp_unregister(void) void msm_dp_irq_postinstall(struct msm_dp *dp_display) { struct dp_display_private *dp; + u8 delay; if (!dp_display) return; @@ -1438,7 +1439,15 @@ void msm_dp_irq_postinstall(struct msm_dp *dp_display) dp_hpd_event_setup(dp); - dp_add_event(dp, EV_HPD_INIT_SETUP, 0, 100); + if (dp->dp_display.connector_type == DRM_MODE_CONNECTOR_eDP) { + /* eDP does not need any delay before phy init */ + delay = 0; + } else { + /* DP needs 10 second delay to let usb combo phy initialize */ + delay = 100; + } + + dp_add_event(dp, EV_HPD_INIT_SETUP, 0, delay); } void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor)