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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:57:56.8353 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ee62060-9e87-4152-8a20-08d99a3c7918 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT006.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4354 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The address translation code used for current AMD systems is non-architectural. So move it to EDAC. Cc: Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-2-yazen.ghannam@amd.com v2->v3: * No change. v1->v2: * New in v2. arch/x86/include/asm/mce.h | 3 - arch/x86/kernel/cpu/mce/amd.c | 200 ---------------------------------- drivers/edac/amd64_edac.c | 199 +++++++++++++++++++++++++++++++++ 3 files changed, 199 insertions(+), 203 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 813b4f5b0dd6..1d994b3d2419 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -345,7 +345,6 @@ extern int mce_threshold_create_device(unsigned int cpu); extern int mce_threshold_remove_device(unsigned int cpu); void mce_amd_feature_init(struct cpuinfo_x86 *c); -int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr); #else @@ -353,8 +352,6 @@ static inline int mce_threshold_create_device(unsigned int cpu) { return 0; }; static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; }; static inline bool amd_mce_is_memory_error(struct mce *m) { return false; }; static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } -static inline int -umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; }; #endif static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); } diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 27cacf504663..1b436560a2ac 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -688,206 +688,6 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) deferred_error_interrupt_enable(c); } -int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) -{ - u64 dram_base_addr, dram_limit_addr, dram_hole_base; - /* We start from the normalized address */ - u64 ret_addr = norm_addr; - - u32 tmp; - - u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; - u8 intlv_addr_sel, intlv_addr_bit; - u8 num_intlv_bits, hashed_bit; - u8 lgcy_mmio_hole_en, base = 0; - u8 cs_mask, cs_id = 0; - bool hash_enabled = false; - - /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ - if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp)) - goto out_err; - - /* Remove HiAddrOffset from normalized address, if enabled: */ - if (tmp & BIT(0)) { - u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8; - - if (norm_addr >= hi_addr_offset) { - ret_addr -= hi_addr_offset; - base = 1; - } - } - - /* Read D18F0x110 (DramBaseAddress). */ - if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp)) - goto out_err; - - /* Check if address range is valid. */ - if (!(tmp & BIT(0))) { - pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", - __func__, tmp); - goto out_err; - } - - lgcy_mmio_hole_en = tmp & BIT(1); - intlv_num_chan = (tmp >> 4) & 0xF; - intlv_addr_sel = (tmp >> 8) & 0x7; - dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16; - - /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ - if (intlv_addr_sel > 3) { - pr_err("%s: Invalid interleave address select %d.\n", - __func__, intlv_addr_sel); - goto out_err; - } - - /* Read D18F0x114 (DramLimitAddress). */ - if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) - goto out_err; - - intlv_num_sockets = (tmp >> 8) & 0x1; - intlv_num_dies = (tmp >> 10) & 0x3; - dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); - - intlv_addr_bit = intlv_addr_sel + 8; - - /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ - switch (intlv_num_chan) { - case 0: intlv_num_chan = 0; break; - case 1: intlv_num_chan = 1; break; - case 3: intlv_num_chan = 2; break; - case 5: intlv_num_chan = 3; break; - case 7: intlv_num_chan = 4; break; - - case 8: intlv_num_chan = 1; - hash_enabled = true; - break; - default: - pr_err("%s: Invalid number of interleaved channels %d.\n", - __func__, intlv_num_chan); - goto out_err; - } - - num_intlv_bits = intlv_num_chan; - - if (intlv_num_dies > 2) { - pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", - __func__, intlv_num_dies); - goto out_err; - } - - num_intlv_bits += intlv_num_dies; - - /* Add a bit if sockets are interleaved. */ - num_intlv_bits += intlv_num_sockets; - - /* Assert num_intlv_bits <= 4 */ - if (num_intlv_bits > 4) { - pr_err("%s: Invalid interleave bits %d.\n", - __func__, num_intlv_bits); - goto out_err; - } - - if (num_intlv_bits > 0) { - u64 temp_addr_x, temp_addr_i, temp_addr_y; - u8 die_id_bit, sock_id_bit, cs_fabric_id; - - /* - * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. - * This is the fabric id for this coherent slave. Use - * umc/channel# as instance id of the coherent slave - * for FICAA. - */ - if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp)) - goto out_err; - - cs_fabric_id = (tmp >> 8) & 0xFF; - die_id_bit = 0; - - /* If interleaved over more than 1 channel: */ - if (intlv_num_chan) { - die_id_bit = intlv_num_chan; - cs_mask = (1 << die_id_bit) - 1; - cs_id = cs_fabric_id & cs_mask; - } - - sock_id_bit = die_id_bit; - - /* Read D18F1x208 (SystemFabricIdMask). */ - if (intlv_num_dies || intlv_num_sockets) - if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp)) - goto out_err; - - /* If interleaved over more than 1 die. */ - if (intlv_num_dies) { - sock_id_bit = die_id_bit + intlv_num_dies; - die_id_shift = (tmp >> 24) & 0xF; - die_id_mask = (tmp >> 8) & 0xFF; - - cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; - } - - /* If interleaved over more than 1 socket. */ - if (intlv_num_sockets) { - socket_id_shift = (tmp >> 28) & 0xF; - socket_id_mask = (tmp >> 16) & 0xFF; - - cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; - } - - /* - * The pre-interleaved address consists of XXXXXXIIIYYYYY - * where III is the ID for this CS, and XXXXXXYYYYY are the - * address bits from the post-interleaved address. - * "num_intlv_bits" has been calculated to tell us how many "I" - * bits there are. "intlv_addr_bit" tells us how many "Y" bits - * there are (where "I" starts). - */ - temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0); - temp_addr_i = (cs_id << intlv_addr_bit); - temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; - ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; - } - - /* Add dram base address */ - ret_addr += dram_base_addr; - - /* If legacy MMIO hole enabled */ - if (lgcy_mmio_hole_en) { - if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp)) - goto out_err; - - dram_hole_base = tmp & GENMASK(31, 24); - if (ret_addr >= dram_hole_base) - ret_addr += (BIT_ULL(32) - dram_hole_base); - } - - if (hash_enabled) { - /* Save some parentheses and grab ls-bit at the end. */ - hashed_bit = (ret_addr >> 12) ^ - (ret_addr >> 18) ^ - (ret_addr >> 21) ^ - (ret_addr >> 30) ^ - cs_id; - - hashed_bit &= BIT(0); - - if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) - ret_addr ^= BIT(intlv_addr_bit); - } - - /* Is calculated system address is above DRAM limit address? */ - if (ret_addr > dram_limit_addr) - goto out_err; - - *sys_addr = ret_addr; - return 0; - -out_err: - return -EINVAL; -} -EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr); - bool amd_mce_is_memory_error(struct mce *m) { /* ErrCodeExt[20:16] */ diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index a0dc7ffe63d6..9b87aa38803d 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -986,6 +986,205 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) return csrow; } +static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +{ + u64 dram_base_addr, dram_limit_addr, dram_hole_base; + /* We start from the normalized address */ + u64 ret_addr = norm_addr; + + u32 tmp; + + u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; + u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; + u8 intlv_addr_sel, intlv_addr_bit; + u8 num_intlv_bits, hashed_bit; + u8 lgcy_mmio_hole_en, base = 0; + u8 cs_mask, cs_id = 0; + bool hash_enabled = false; + + /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ + if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp)) + goto out_err; + + /* Remove HiAddrOffset from normalized address, if enabled: */ + if (tmp & BIT(0)) { + u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8; + + if (norm_addr >= hi_addr_offset) { + ret_addr -= hi_addr_offset; + base = 1; + } + } + + /* Read D18F0x110 (DramBaseAddress). */ + if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp)) + goto out_err; + + /* Check if address range is valid. */ + if (!(tmp & BIT(0))) { + pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", + __func__, tmp); + goto out_err; + } + + lgcy_mmio_hole_en = tmp & BIT(1); + intlv_num_chan = (tmp >> 4) & 0xF; + intlv_addr_sel = (tmp >> 8) & 0x7; + dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16; + + /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ + if (intlv_addr_sel > 3) { + pr_err("%s: Invalid interleave address select %d.\n", + __func__, intlv_addr_sel); + goto out_err; + } + + /* Read D18F0x114 (DramLimitAddress). */ + if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) + goto out_err; + + intlv_num_sockets = (tmp >> 8) & 0x1; + intlv_num_dies = (tmp >> 10) & 0x3; + dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); + + intlv_addr_bit = intlv_addr_sel + 8; + + /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ + switch (intlv_num_chan) { + case 0: intlv_num_chan = 0; break; + case 1: intlv_num_chan = 1; break; + case 3: intlv_num_chan = 2; break; + case 5: intlv_num_chan = 3; break; + case 7: intlv_num_chan = 4; break; + + case 8: intlv_num_chan = 1; + hash_enabled = true; + break; + default: + pr_err("%s: Invalid number of interleaved channels %d.\n", + __func__, intlv_num_chan); + goto out_err; + } + + num_intlv_bits = intlv_num_chan; + + if (intlv_num_dies > 2) { + pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", + __func__, intlv_num_dies); + goto out_err; + } + + num_intlv_bits += intlv_num_dies; + + /* Add a bit if sockets are interleaved. */ + num_intlv_bits += intlv_num_sockets; + + /* Assert num_intlv_bits <= 4 */ + if (num_intlv_bits > 4) { + pr_err("%s: Invalid interleave bits %d.\n", + __func__, num_intlv_bits); + goto out_err; + } + + if (num_intlv_bits > 0) { + u64 temp_addr_x, temp_addr_i, temp_addr_y; + u8 die_id_bit, sock_id_bit, cs_fabric_id; + + /* + * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. + * This is the fabric id for this coherent slave. Use + * umc/channel# as instance id of the coherent slave + * for FICAA. + */ + if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp)) + goto out_err; + + cs_fabric_id = (tmp >> 8) & 0xFF; + die_id_bit = 0; + + /* If interleaved over more than 1 channel: */ + if (intlv_num_chan) { + die_id_bit = intlv_num_chan; + cs_mask = (1 << die_id_bit) - 1; + cs_id = cs_fabric_id & cs_mask; + } + + sock_id_bit = die_id_bit; + + /* Read D18F1x208 (SystemFabricIdMask). */ + if (intlv_num_dies || intlv_num_sockets) + if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp)) + goto out_err; + + /* If interleaved over more than 1 die. */ + if (intlv_num_dies) { + sock_id_bit = die_id_bit + intlv_num_dies; + die_id_shift = (tmp >> 24) & 0xF; + die_id_mask = (tmp >> 8) & 0xFF; + + cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; + } + + /* If interleaved over more than 1 socket. */ + if (intlv_num_sockets) { + socket_id_shift = (tmp >> 28) & 0xF; + socket_id_mask = (tmp >> 16) & 0xFF; + + cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; + } + + /* + * The pre-interleaved address consists of XXXXXXIIIYYYYY + * where III is the ID for this CS, and XXXXXXYYYYY are the + * address bits from the post-interleaved address. + * "num_intlv_bits" has been calculated to tell us how many "I" + * bits there are. "intlv_addr_bit" tells us how many "Y" bits + * there are (where "I" starts). + */ + temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0); + temp_addr_i = (cs_id << intlv_addr_bit); + temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; + ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; + } + + /* Add dram base address */ + ret_addr += dram_base_addr; + + /* If legacy MMIO hole enabled */ + if (lgcy_mmio_hole_en) { + if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp)) + goto out_err; + + dram_hole_base = tmp & GENMASK(31, 24); + if (ret_addr >= dram_hole_base) + ret_addr += (BIT_ULL(32) - dram_hole_base); + } + + if (hash_enabled) { + /* Save some parentheses and grab ls-bit at the end. */ + hashed_bit = (ret_addr >> 12) ^ + (ret_addr >> 18) ^ + (ret_addr >> 21) ^ + (ret_addr >> 30) ^ + cs_id; + + hashed_bit &= BIT(0); + + if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) + ret_addr ^= BIT(intlv_addr_bit); + } + + /* Is calculated system address is above DRAM limit address? */ + if (ret_addr > dram_limit_addr) + goto out_err; + + *sys_addr = ret_addr; + return 0; + +out_err: + return -EINVAL; +} + static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16); /* From patchwork Thu Oct 28 17:56:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34617C4332F for ; Thu, 28 Oct 2021 17:58:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 17B5A61152 for ; Thu, 28 Oct 2021 17:58:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231178AbhJ1SAl (ORCPT ); Thu, 28 Oct 2021 14:00:41 -0400 Received: from mail-bn7nam10on2076.outbound.protection.outlook.com ([40.107.92.76]:2369 "EHLO NAM10-BN7-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S230520AbhJ1SA2 (ORCPT ); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:57:57.7537 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 589a151a-5737-40be-af2d-08d99a3c79a4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT006.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3131 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The df_indirect_read() function is only used for address translation. Move this to EDAC along with the translation code. Cc: Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-3-yazen.ghannam@amd.com v2->v3: * No change. v1->v2: * New in v2. arch/x86/include/asm/amd_nb.h | 1 - arch/x86/kernel/amd_nb.c | 49 +--------------------------------- drivers/edac/amd64_edac.c | 50 +++++++++++++++++++++++++++++++++++ 3 files changed, 51 insertions(+), 49 deletions(-) diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h index a78d088dae40..2ccac1efe1e9 100644 --- a/arch/x86/include/asm/amd_nb.h +++ b/arch/x86/include/asm/amd_nb.h @@ -24,7 +24,6 @@ extern int amd_set_subcaches(int, unsigned long); extern int amd_smn_read(u16 node, u32 address, u32 *value); extern int amd_smn_write(u16 node, u32 address, u32 value); -extern int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo); struct amd_l3_cache { unsigned indices; diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 0b495406ab9c..17f4e6e25613 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -31,7 +31,7 @@ #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e #define PCI_DEVICE_ID_AMD_ALDEBARAN_DF_F4 0x14d4 -/* Protect the PCI config register pairs used for SMN and DF indirect access. */ +/* Protect the PCI config register pairs used for SMN. */ static DEFINE_MUTEX(smn_mutex); static u32 *flush_words; @@ -247,53 +247,6 @@ int amd_smn_write(u16 node, u32 address, u32 value) } EXPORT_SYMBOL_GPL(amd_smn_write); -/* - * Data Fabric Indirect Access uses FICAA/FICAD. - * - * Fabric Indirect Configuration Access Address (FICAA): Constructed based - * on the device's Instance Id and the PCI function and register offset of - * the desired register. - * - * Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO - * and FICAD HI registers but so far we only need the LO register. - */ -int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo) -{ - struct pci_dev *F4; - u32 ficaa; - int err = -ENODEV; - - if (node >= amd_northbridges.num) - goto out; - - F4 = node_to_amd_nb(node)->link; - if (!F4) - goto out; - - ficaa = 1; - ficaa |= reg & 0x3FC; - ficaa |= (func & 0x7) << 11; - ficaa |= instance_id << 16; - - mutex_lock(&smn_mutex); - - err = pci_write_config_dword(F4, 0x5C, ficaa); - if (err) { - pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa); - goto out_unlock; - } - - err = pci_read_config_dword(F4, 0x98, lo); - if (err) - pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa); - -out_unlock: - mutex_unlock(&smn_mutex); - -out: - return err; -} -EXPORT_SYMBOL_GPL(amd_df_indirect_read); struct pci_dev *get_root_devs(struct pci_dev *root, const struct pci_device_id *root_ids, diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 9b87aa38803d..28c96fd06019 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -986,6 +986,56 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) return csrow; } +/* Protect the PCI config register pairs used for DF indirect access. */ +static DEFINE_MUTEX(df_indirect_mutex); + +/* + * Data Fabric Indirect Access uses FICAA/FICAD. + * + * Fabric Indirect Configuration Access Address (FICAA): Constructed based + * on the device's Instance Id and the PCI function and register offset of + * the desired register. + * + * Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO + * and FICAD HI registers but so far we only need the LO register. + */ +static int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo) +{ + struct pci_dev *F4; + u32 ficaa; + int err = -ENODEV; + + if (node >= amd_nb_num()) + goto out; + + F4 = node_to_amd_nb(node)->link; + if (!F4) + goto out; + + ficaa = 1; + ficaa |= reg & 0x3FC; + ficaa |= (func & 0x7) << 11; + ficaa |= instance_id << 16; + + mutex_lock(&df_indirect_mutex); + + err = pci_write_config_dword(F4, 0x5C, ficaa); + if (err) { + pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa); + goto out_unlock; + } + + err = pci_read_config_dword(F4, 0x98, lo); + if (err) + pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa); + +out_unlock: + mutex_unlock(&df_indirect_mutex); + +out: + return err; +} + static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_base_addr, dram_limit_addr, dram_hole_base; From patchwork Thu Oct 28 17:56:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92937C433EF for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT006.mail.protection.outlook.com (10.13.174.246) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Thu, 28 Oct 2021 17:57:58 +0000 Received: from yaz-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Thu, 28 Oct 2021 12:57:57 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , Yazen Ghannam Subject: [PATCH v3 03/33] EDAC/amd64: Allow for DF Indirect Broadcast reads Date: Thu, 28 Oct 2021 17:56:58 +0000 Message-ID: <20211028175728.121452-4-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211028175728.121452-1-yazen.ghannam@amd.com> References: <20211028175728.121452-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0490f894-5b44-453b-a9c1-08d99a3c7a5d X-MS-TrafficTypeDiagnostic: MWHPR12MB1133: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:57:58.9650 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0490f894-5b44-453b-a9c1-08d99a3c7a5d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT006.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1133 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The DF Indirect Access method allows for "Broadcast" accesses in which case no specific instance is targeted. Add support using a reserved instance ID of 0xFF to indicate a broadcast access. Set the FICAA register appropriately. Define helpers functions for instance and broadcast reads and use them where appropriate. Drop the "amd_" prefix since these functions are all static. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-5-yazen.ghannam@amd.com v2->v3: * Was patch 4 in v2. * Define wrapper functions for instance/broadcast access. * Drop "amd_" prefix. * Dropped "df_regs" use. v1->v2: * New in v2. drivers/edac/amd64_edac.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 28c96fd06019..bad230745d60 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -998,8 +998,11 @@ static DEFINE_MUTEX(df_indirect_mutex); * * Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO * and FICAD HI registers but so far we only need the LO register. + * + * Use Instance Id 0xFF to indicate a broadcast read. */ -static int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo) +#define DF_BROADCAST 0xFF +static int __df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo) { struct pci_dev *F4; u32 ficaa; @@ -1012,7 +1015,7 @@ static int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 if (!F4) goto out; - ficaa = 1; + ficaa = (instance_id == DF_BROADCAST) ? 0 : 1; ficaa |= reg & 0x3FC; ficaa |= (func & 0x7) << 11; ficaa |= instance_id << 16; @@ -1036,6 +1039,16 @@ static int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 return err; } +static int df_indirect_read_instance(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo) +{ + return __df_indirect_read(node, func, reg, instance_id, lo); +} + +static int df_indirect_read_broadcast(u16 node, u8 func, u16 reg, u32 *lo) +{ + return __df_indirect_read(node, func, reg, DF_BROADCAST, lo); +} + static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_base_addr, dram_limit_addr, dram_hole_base; @@ -1053,7 +1066,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr bool hash_enabled = false; /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ - if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp)) + if (df_indirect_read_instance(nid, 0, 0x1B4, umc, &tmp)) goto out_err; /* Remove HiAddrOffset from normalized address, if enabled: */ @@ -1067,7 +1080,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr } /* Read D18F0x110 (DramBaseAddress). */ - if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp)) + if (df_indirect_read_instance(nid, 0, 0x110 + (8 * base), umc, &tmp)) goto out_err; /* Check if address range is valid. */ @@ -1090,7 +1103,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr } /* Read D18F0x114 (DramLimitAddress). */ - if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) + if (df_indirect_read_instance(nid, 0, 0x114 + (8 * base), umc, &tmp)) goto out_err; intlv_num_sockets = (tmp >> 8) & 0x1; @@ -1146,7 +1159,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr * umc/channel# as instance id of the coherent slave * for FICAA. */ - if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp)) + if (df_indirect_read_instance(nid, 0, 0x50, umc, &tmp)) goto out_err; cs_fabric_id = (tmp >> 8) & 0xFF; @@ -1163,7 +1176,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr /* Read D18F1x208 (SystemFabricIdMask). */ if (intlv_num_dies || intlv_num_sockets) - if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp)) + if (df_indirect_read_broadcast(nid, 1, 0x208, &tmp)) goto out_err; /* If interleaved over more than 1 die. */ @@ -1202,7 +1215,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr /* If legacy MMIO hole enabled */ if (lgcy_mmio_hole_en) { - if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp)) + if (df_indirect_read_broadcast(nid, 0, 0x104, &tmp)) goto out_err; dram_hole_base = tmp & GENMASK(31, 24); From patchwork Thu Oct 28 17:56:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590697 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 652A9C433F5 for ; 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dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT059.mail.protection.outlook.com (10.13.174.160) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Thu, 28 Oct 2021 17:58:04 +0000 Received: from yaz-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Thu, 28 Oct 2021 12:58:03 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , Yazen Ghannam Subject: [PATCH v3 04/33] EDAC/amd64: Add context struct Date: Thu, 28 Oct 2021 17:56:59 +0000 Message-ID: <20211028175728.121452-5-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211028175728.121452-1-yazen.ghannam@amd.com> References: <20211028175728.121452-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b9484b83-30d7-4ac6-b042-08d99a3c7de1 X-MS-TrafficTypeDiagnostic: MN2PR12MB3136: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:04.8704 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b9484b83-30d7-4ac6-b042-08d99a3c7de1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3136 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Define an address translation context struct. This will hold values that will be passed between multiple functions. Save return address, Node ID, and the Instance ID number to start. Currently, the UMC number is used as the Instance ID, but future DF versions may use another value. Also include a "tmp" field to use when reading registers. This is to avoid having to define a temporary variable in multiple functions. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-6-yazen.ghannam@amd.com v2->v3: * Was patch 5 in v2. * Included a "tmp" field. v1->v2: * Moved from arch/x86 to EDAC. * Changed "umc" variable to "inst_id". * Drop df_types enum. drivers/edac/amd64_edac.c | 97 ++++++++++++++++++++++----------------- 1 file changed, 55 insertions(+), 42 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index bad230745d60..3fb137ea74b3 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1049,13 +1049,16 @@ static int df_indirect_read_broadcast(u16 node, u8 func, u16 reg, u32 *lo) return __df_indirect_read(node, func, reg, DF_BROADCAST, lo); } +struct addr_ctx { + u64 ret_addr; + u32 tmp; + u16 nid; + u8 inst_id; +}; + static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_base_addr, dram_limit_addr, dram_hole_base; - /* We start from the normalized address */ - u64 ret_addr = norm_addr; - - u32 tmp; u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; @@ -1065,35 +1068,45 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr u8 cs_mask, cs_id = 0; bool hash_enabled = false; + struct addr_ctx ctx; + + memset(&ctx, 0, sizeof(ctx)); + + /* We start from the normalized address */ + ctx.ret_addr = norm_addr; + + ctx.nid = nid; + ctx.inst_id = umc; + /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ - if (df_indirect_read_instance(nid, 0, 0x1B4, umc, &tmp)) + if (df_indirect_read_instance(nid, 0, 0x1B4, umc, &ctx.tmp)) goto out_err; /* Remove HiAddrOffset from normalized address, if enabled: */ - if (tmp & BIT(0)) { - u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8; + if (ctx.tmp & BIT(0)) { + u64 hi_addr_offset = (ctx.tmp & GENMASK_ULL(31, 20)) << 8; if (norm_addr >= hi_addr_offset) { - ret_addr -= hi_addr_offset; + ctx.ret_addr -= hi_addr_offset; base = 1; } } /* Read D18F0x110 (DramBaseAddress). */ - if (df_indirect_read_instance(nid, 0, 0x110 + (8 * base), umc, &tmp)) + if (df_indirect_read_instance(nid, 0, 0x110 + (8 * base), umc, &ctx.tmp)) goto out_err; /* Check if address range is valid. */ - if (!(tmp & BIT(0))) { + if (!(ctx.tmp & BIT(0))) { pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", - __func__, tmp); + __func__, ctx.tmp); goto out_err; } - lgcy_mmio_hole_en = tmp & BIT(1); - intlv_num_chan = (tmp >> 4) & 0xF; - intlv_addr_sel = (tmp >> 8) & 0x7; - dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16; + lgcy_mmio_hole_en = ctx.tmp & BIT(1); + intlv_num_chan = (ctx.tmp >> 4) & 0xF; + intlv_addr_sel = (ctx.tmp >> 8) & 0x7; + dram_base_addr = (ctx.tmp & GENMASK_ULL(31, 12)) << 16; /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ if (intlv_addr_sel > 3) { @@ -1103,12 +1116,12 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr } /* Read D18F0x114 (DramLimitAddress). */ - if (df_indirect_read_instance(nid, 0, 0x114 + (8 * base), umc, &tmp)) + if (df_indirect_read_instance(nid, 0, 0x114 + (8 * base), umc, &ctx.tmp)) goto out_err; - intlv_num_sockets = (tmp >> 8) & 0x1; - intlv_num_dies = (tmp >> 10) & 0x3; - dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); + intlv_num_sockets = (ctx.tmp >> 8) & 0x1; + intlv_num_dies = (ctx.tmp >> 10) & 0x3; + dram_limit_addr = ((ctx.tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); intlv_addr_bit = intlv_addr_sel + 8; @@ -1159,10 +1172,10 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr * umc/channel# as instance id of the coherent slave * for FICAA. */ - if (df_indirect_read_instance(nid, 0, 0x50, umc, &tmp)) + if (df_indirect_read_instance(nid, 0, 0x50, umc, &ctx.tmp)) goto out_err; - cs_fabric_id = (tmp >> 8) & 0xFF; + cs_fabric_id = (ctx.tmp >> 8) & 0xFF; die_id_bit = 0; /* If interleaved over more than 1 channel: */ @@ -1176,22 +1189,22 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr /* Read D18F1x208 (SystemFabricIdMask). */ if (intlv_num_dies || intlv_num_sockets) - if (df_indirect_read_broadcast(nid, 1, 0x208, &tmp)) + if (df_indirect_read_broadcast(nid, 1, 0x208, &ctx.tmp)) goto out_err; /* If interleaved over more than 1 die. */ if (intlv_num_dies) { sock_id_bit = die_id_bit + intlv_num_dies; - die_id_shift = (tmp >> 24) & 0xF; - die_id_mask = (tmp >> 8) & 0xFF; + die_id_shift = (ctx.tmp >> 24) & 0xF; + die_id_mask = (ctx.tmp >> 8) & 0xFF; cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; } /* If interleaved over more than 1 socket. */ if (intlv_num_sockets) { - socket_id_shift = (tmp >> 28) & 0xF; - socket_id_mask = (tmp >> 16) & 0xFF; + socket_id_shift = (ctx.tmp >> 28) & 0xF; + socket_id_mask = (ctx.tmp >> 16) & 0xFF; cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; } @@ -1204,44 +1217,44 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr * bits there are. "intlv_addr_bit" tells us how many "Y" bits * there are (where "I" starts). */ - temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0); + temp_addr_y = ctx.ret_addr & GENMASK_ULL(intlv_addr_bit - 1, 0); temp_addr_i = (cs_id << intlv_addr_bit); - temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; - ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; + temp_addr_x = (ctx.ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; + ctx.ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; } /* Add dram base address */ - ret_addr += dram_base_addr; + ctx.ret_addr += dram_base_addr; /* If legacy MMIO hole enabled */ if (lgcy_mmio_hole_en) { - if (df_indirect_read_broadcast(nid, 0, 0x104, &tmp)) + if (df_indirect_read_broadcast(nid, 0, 0x104, &ctx.tmp)) goto out_err; - dram_hole_base = tmp & GENMASK(31, 24); - if (ret_addr >= dram_hole_base) - ret_addr += (BIT_ULL(32) - dram_hole_base); + dram_hole_base = ctx.tmp & GENMASK(31, 24); + if (ctx.ret_addr >= dram_hole_base) + ctx.ret_addr += (BIT_ULL(32) - dram_hole_base); } if (hash_enabled) { /* Save some parentheses and grab ls-bit at the end. */ - hashed_bit = (ret_addr >> 12) ^ - (ret_addr >> 18) ^ - (ret_addr >> 21) ^ - (ret_addr >> 30) ^ + hashed_bit = (ctx.ret_addr >> 12) ^ + (ctx.ret_addr >> 18) ^ + (ctx.ret_addr >> 21) ^ + (ctx.ret_addr >> 30) ^ cs_id; hashed_bit &= BIT(0); - if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) - ret_addr ^= BIT(intlv_addr_bit); + if (hashed_bit != ((ctx.ret_addr >> intlv_addr_bit) & BIT(0))) + ctx.ret_addr ^= BIT(intlv_addr_bit); } /* Is calculated system address is above DRAM limit address? */ - if (ret_addr > dram_limit_addr) + if (ctx.ret_addr > dram_limit_addr) goto out_err; - *sys_addr = ret_addr; + *sys_addr = ctx.ret_addr; return 0; out_err: From patchwork Thu Oct 28 17:57:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590695 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92D62C43217 for ; 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dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT059.mail.protection.outlook.com (10.13.174.160) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Thu, 28 Oct 2021 17:58:06 +0000 Received: from yaz-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Thu, 28 Oct 2021 12:58:05 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , Yazen Ghannam Subject: [PATCH v3 05/33] EDAC/amd64: Define Data Fabric operations Date: Thu, 28 Oct 2021 17:57:00 +0000 Message-ID: <20211028175728.121452-6-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211028175728.121452-1-yazen.ghannam@amd.com> References: <20211028175728.121452-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e6cc2e98-c6bb-4447-a408-08d99a3c7ee2 X-MS-TrafficTypeDiagnostic: MW2PR12MB2444: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:06.5554 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e6cc2e98-c6bb-4447-a408-08d99a3c7ee2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR12MB2444 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Define a stub to hold operations for different Data Fabric versions. This will be filled in following patches. Set the operations at init-time as appropriate for each model/family group. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-7-yazen.ghannam@amd.com v2->v3: * Was patch 6 in v2. * "df_ops" is set at init time. v1->v2: * New in v2. drivers/edac/amd64_edac.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 3fb137ea74b3..f83f9813294d 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1056,6 +1056,14 @@ struct addr_ctx { u8 inst_id; }; +struct data_fabric_ops { +}; + +struct data_fabric_ops df2_ops = { +}; + +struct data_fabric_ops *df_ops; + static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_base_addr, dram_limit_addr, dram_hole_base; @@ -1070,6 +1078,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr struct addr_ctx ctx; + if (!df_ops) + return -EINVAL; + memset(&ctx, 0, sizeof(ctx)); /* We start from the normalized address */ @@ -4190,6 +4201,7 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) if (pvt->model >= 0x10 && pvt->model <= 0x2f) { pvt->fam_type = &family_types[F17_M10H_CPUS]; pvt->ops = &family_types[F17_M10H_CPUS].ops; + df_ops = &df2_ops; break; } else if (pvt->model >= 0x30 && pvt->model <= 0x3f) { pvt->fam_type = &family_types[F17_M30H_CPUS]; @@ -4208,6 +4220,7 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) case 0x18: pvt->fam_type = &family_types[F17_CPUS]; pvt->ops = &family_types[F17_CPUS].ops; + df_ops = &df2_ops; if (pvt->fam == 0x18) family_types[F17_CPUS].ctl_name = "F18h"; From patchwork Thu Oct 28 17:57:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50CBFC433F5 for ; Thu, 28 Oct 2021 17:58:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 33A116108F for ; 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Thu, 28 Oct 2021 17:58:09 +0000 Received: from yaz-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Thu, 28 Oct 2021 12:58:07 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , Yazen Ghannam Subject: [PATCH v3 06/33] EDAC/amd64: Define functions for DramOffset Date: Thu, 28 Oct 2021 17:57:01 +0000 Message-ID: <20211028175728.121452-7-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211028175728.121452-1-yazen.ghannam@amd.com> References: <20211028175728.121452-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4786ad81-9f34-4e51-3f8a-08d99a3c8098 X-MS-TrafficTypeDiagnostic: MWHPR1201MB2478: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:09.3613 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4786ad81-9f34-4e51-3f8a-08d99a3c8098 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT010.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1201MB2478 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Add helper functions to read the DramOffset register and to remove the offset from the calculated address. The helper functions will be expanded in future DF versions. Rename the "base" variable to "map_num" to indicate that this is the address map number. An address map is defined with a base and limit value. The map_num variable is used to select the proper base and limit registers to use for the address translation. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-8-yazen.ghannam@amd.com v2->v3: * Was patch 7 in v2. * Dropped "df_regs" use. v1->v2: * Moved from arch/x86 to EDAC. * Add function to data_fabric_ops. drivers/edac/amd64_edac.c | 58 +++++++++++++++++++++++++++++---------- 1 file changed, 43 insertions(+), 15 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index f83f9813294d..d7780e570fd0 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1049,21 +1049,60 @@ static int df_indirect_read_broadcast(u16 node, u8 func, u16 reg, u32 *lo) return __df_indirect_read(node, func, reg, DF_BROADCAST, lo); } +/* Use "reg_" prefix for raw register values. */ struct addr_ctx { u64 ret_addr; u32 tmp; + u32 reg_dram_offset; u16 nid; u8 inst_id; + u8 map_num; }; struct data_fabric_ops { + u64 (*get_hi_addr_offset) (struct addr_ctx *ctx); }; +static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) +{ + return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8; +} + struct data_fabric_ops df2_ops = { + .get_hi_addr_offset = get_hi_addr_offset_df2, }; struct data_fabric_ops *df_ops; +static int get_dram_offset_reg(struct addr_ctx *ctx) +{ + /* Read D18F0x1B4 (DramOffset) */ + if (df_indirect_read_instance(ctx->nid, 0, 0x1B4, ctx->inst_id, &ctx->reg_dram_offset)) + return -EINVAL; + + return 0; +} + +static int remove_dram_offset(struct addr_ctx *ctx) +{ + if (get_dram_offset_reg(ctx)) + return -EINVAL; + + ctx->map_num = 0; + + /* Remove HiAddrOffset from normalized address, if enabled: */ + if (ctx->reg_dram_offset & BIT(0)) { + u64 hi_addr_offset = df_ops->get_hi_addr_offset(ctx); + + if (ctx->ret_addr >= hi_addr_offset) { + ctx->ret_addr -= hi_addr_offset; + ctx->map_num = 1; + } + } + + return 0; +} + static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_base_addr, dram_limit_addr, dram_hole_base; @@ -1072,7 +1111,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; u8 intlv_addr_sel, intlv_addr_bit; u8 num_intlv_bits, hashed_bit; - u8 lgcy_mmio_hole_en, base = 0; + u8 lgcy_mmio_hole_en; u8 cs_mask, cs_id = 0; bool hash_enabled = false; @@ -1089,22 +1128,11 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr ctx.nid = nid; ctx.inst_id = umc; - /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ - if (df_indirect_read_instance(nid, 0, 0x1B4, umc, &ctx.tmp)) + if (remove_dram_offset(&ctx)) goto out_err; - /* Remove HiAddrOffset from normalized address, if enabled: */ - if (ctx.tmp & BIT(0)) { - u64 hi_addr_offset = (ctx.tmp & GENMASK_ULL(31, 20)) << 8; - - if (norm_addr >= hi_addr_offset) { - ctx.ret_addr -= hi_addr_offset; - base = 1; - } - } - /* Read D18F0x110 (DramBaseAddress). */ - if (df_indirect_read_instance(nid, 0, 0x110 + (8 * base), umc, &ctx.tmp)) + if (df_indirect_read_instance(nid, 0, 0x110 + (8 * ctx.map_num), umc, &ctx.tmp)) goto out_err; /* Check if address range is valid. */ @@ -1127,7 +1155,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr } /* Read D18F0x114 (DramLimitAddress). */ - if (df_indirect_read_instance(nid, 0, 0x114 + (8 * base), umc, &ctx.tmp)) + if (df_indirect_read_instance(nid, 0, 0x114 + (8 * ctx.map_num), umc, &ctx.tmp)) goto out_err; intlv_num_sockets = (ctx.tmp >> 8) & 0x1; From patchwork Thu Oct 28 17:57:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CE8DC4332F for ; Thu, 28 Oct 2021 17:58:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 65CAF610E7 for ; Thu, 28 Oct 2021 17:58:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231322AbhJ1SAt (ORCPT ); Thu, 28 Oct 2021 14:00:49 -0400 Received: from mail-dm3nam07on2065.outbound.protection.outlook.com ([40.107.95.65]:63520 "EHLO NAM02-DM3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231248AbhJ1SAl (ORCPT ); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:10.2978 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c3756fa7-133f-4188-47b2-08d99a3c8120 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT010.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB2419 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move the reading of the base and limit registers into a helper function. Save the raw values in the context struct as they will be parsed later. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-9-yazen.ghannam@amd.com v2->v3: * Was patch 8 in v2. * Dropped "df_regs" use. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 51 ++++++++++++++++++++++++--------------- 1 file changed, 31 insertions(+), 20 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index d7780e570fd0..9d49e4a91931 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1054,6 +1054,8 @@ struct addr_ctx { u64 ret_addr; u32 tmp; u32 reg_dram_offset; + u32 reg_base_addr; + u32 reg_limit_addr; u16 nid; u8 inst_id; u8 map_num; @@ -1103,6 +1105,27 @@ static int remove_dram_offset(struct addr_ctx *ctx) return 0; } +static int get_dram_addr_map(struct addr_ctx *ctx) +{ + /* Read D18F0x110 (DramBaseAddress). */ + if (df_indirect_read_instance(ctx->nid, 0, 0x110 + (8 * ctx->map_num), + ctx->inst_id, &ctx->reg_base_addr)) + return -EINVAL; + + /* Check if address range is valid. */ + if (!(ctx->reg_base_addr & BIT(0))) { + pr_debug("Invalid DramBaseAddress range: 0x%x.\n", ctx->reg_base_addr); + return -EINVAL; + } + + /* Read D18F0x114 (DramLimitAddress). */ + if (df_indirect_read_instance(ctx->nid, 0, 0x114 + (8 * ctx->map_num), + ctx->inst_id, &ctx->reg_limit_addr)) + return -EINVAL; + + return 0; +} + static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_base_addr, dram_limit_addr, dram_hole_base; @@ -1131,21 +1154,13 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (remove_dram_offset(&ctx)) goto out_err; - /* Read D18F0x110 (DramBaseAddress). */ - if (df_indirect_read_instance(nid, 0, 0x110 + (8 * ctx.map_num), umc, &ctx.tmp)) + if (get_dram_addr_map(&ctx)) goto out_err; - /* Check if address range is valid. */ - if (!(ctx.tmp & BIT(0))) { - pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", - __func__, ctx.tmp); - goto out_err; - } - - lgcy_mmio_hole_en = ctx.tmp & BIT(1); - intlv_num_chan = (ctx.tmp >> 4) & 0xF; - intlv_addr_sel = (ctx.tmp >> 8) & 0x7; - dram_base_addr = (ctx.tmp & GENMASK_ULL(31, 12)) << 16; + lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); + intlv_num_chan = (ctx.reg_base_addr >> 4) & 0xF; + intlv_addr_sel = (ctx.reg_base_addr >> 8) & 0x7; + dram_base_addr = (ctx.reg_base_addr & GENMASK_ULL(31, 12)) << 16; /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ if (intlv_addr_sel > 3) { @@ -1154,13 +1169,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr goto out_err; } - /* Read D18F0x114 (DramLimitAddress). */ - if (df_indirect_read_instance(nid, 0, 0x114 + (8 * ctx.map_num), umc, &ctx.tmp)) - goto out_err; - - intlv_num_sockets = (ctx.tmp >> 8) & 0x1; - intlv_num_dies = (ctx.tmp >> 10) & 0x3; - dram_limit_addr = ((ctx.tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); + intlv_num_sockets = (ctx.reg_limit_addr >> 8) & 0x1; + intlv_num_dies = (ctx.reg_limit_addr >> 10) & 0x3; + dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); intlv_addr_bit = intlv_addr_sel + 8; From patchwork Thu Oct 28 17:57:03 2021 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:11.8299 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 34407f5a-0476-48d9-c2bc-08d99a3c8209 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT010.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3504 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Define a helper function to find the interleaving mode. Define a DF2-specific function now. Future DF versions will have their own functions. Use an enumeration for the interleaving modes to give a human-readable value. Save the interleaving mode in the context struct, since this will be used in multiple functions. Multiple interleaving modes support hashing, so save a boolean in the context struct to check if hashing is enabled. This boolean will be replaced with a function pointer in a later patch. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-10-yazen.ghannam@amd.com v2->v3: * Was patch 9 in v2. * Updated commit message. v1->v2: * Moved from arch/x86 to EDAC. * Add new function to data_fabric_ops. drivers/edac/amd64_edac.c | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 9d49e4a91931..bc0ec36fe5bb 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1049,8 +1049,16 @@ static int df_indirect_read_broadcast(u16 node, u8 func, u16 reg, u32 *lo) return __df_indirect_read(node, func, reg, DF_BROADCAST, lo); } +/* These are mapped 1:1 to the hardware values. Special cases are set at > 0x20. */ +enum intlv_modes { + NONE = 0x00, + NOHASH_2CH = 0x01, + DF2_HASH_2CH = 0x21, +}; + /* Use "reg_" prefix for raw register values. */ struct addr_ctx { + enum intlv_modes intlv_mode; u64 ret_addr; u32 tmp; u32 reg_dram_offset; @@ -1059,10 +1067,12 @@ struct addr_ctx { u16 nid; u8 inst_id; u8 map_num; + bool hash_enabled; }; struct data_fabric_ops { u64 (*get_hi_addr_offset) (struct addr_ctx *ctx); + int (*get_intlv_mode) (struct addr_ctx *ctx); }; static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) @@ -1070,8 +1080,26 @@ static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8; } +static int get_intlv_mode_df2(struct addr_ctx *ctx) +{ + ctx->intlv_mode = (ctx->reg_base_addr >> 4) & 0xF; + + if (ctx->intlv_mode == 8) { + ctx->intlv_mode = DF2_HASH_2CH; + ctx->hash_enabled = true; + } + + if (ctx->intlv_mode != NONE && + ctx->intlv_mode != NOHASH_2CH && + ctx->intlv_mode != DF2_HASH_2CH) + return -EINVAL; + + return 0; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = get_hi_addr_offset_df2, + .get_intlv_mode = get_intlv_mode_df2, }; struct data_fabric_ops *df_ops; @@ -1136,7 +1164,6 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr u8 num_intlv_bits, hashed_bit; u8 lgcy_mmio_hole_en; u8 cs_mask, cs_id = 0; - bool hash_enabled = false; struct addr_ctx ctx; @@ -1157,6 +1184,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (get_dram_addr_map(&ctx)) goto out_err; + if (df_ops->get_intlv_mode(&ctx)) + goto out_err; + lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); intlv_num_chan = (ctx.reg_base_addr >> 4) & 0xF; intlv_addr_sel = (ctx.reg_base_addr >> 8) & 0x7; @@ -1184,7 +1214,6 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr case 7: intlv_num_chan = 4; break; case 8: intlv_num_chan = 1; - hash_enabled = true; break; default: pr_err("%s: Invalid number of interleaved channels %d.\n", @@ -1286,7 +1315,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr ctx.ret_addr += (BIT_ULL(32) - dram_hole_base); } - if (hash_enabled) { + if (ctx.hash_enabled) { /* Save some parentheses and grab ls-bit at the end. */ hashed_bit = (ctx.ret_addr >> 12) ^ (ctx.ret_addr >> 18) ^ From patchwork Thu Oct 28 17:57:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1A93C433FE for ; Thu, 28 Oct 2021 17:58:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 71C6B610EA for ; Thu, 28 Oct 2021 17:58:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231139AbhJ1SBA (ORCPT ); Thu, 28 Oct 2021 14:01:00 -0400 Received: from mail-mw2nam10on2072.outbound.protection.outlook.com ([40.107.94.72]:12065 "EHLO NAM10-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231213AbhJ1SAo (ORCPT ); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:13.9318 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dfa8e429-f3de-42db-8023-08d99a3c8348 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1435 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move the address denormalization into a separate helper function. This will be further refactored in later patches. Add the interleave address bit and the CS ID to the context struct. These values will be used by multiple functions. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-11-yazen.ghannam@amd.com v2->v3: * Was patch 10 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 135 +++++++++++++++++++++----------------- 1 file changed, 74 insertions(+), 61 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index bc0ec36fe5bb..b4b7c93a6390 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1067,6 +1067,8 @@ struct addr_ctx { u16 nid; u8 inst_id; u8 map_num; + u8 intlv_addr_bit; + u8 cs_id; bool hash_enabled; }; @@ -1154,56 +1156,24 @@ static int get_dram_addr_map(struct addr_ctx *ctx) return 0; } -static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +static int denormalize_addr(struct addr_ctx *ctx) { - u64 dram_base_addr, dram_limit_addr, dram_hole_base; - u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; - u8 intlv_addr_sel, intlv_addr_bit; - u8 num_intlv_bits, hashed_bit; - u8 lgcy_mmio_hole_en; - u8 cs_mask, cs_id = 0; - - struct addr_ctx ctx; - - if (!df_ops) - return -EINVAL; - - memset(&ctx, 0, sizeof(ctx)); - - /* We start from the normalized address */ - ctx.ret_addr = norm_addr; - - ctx.nid = nid; - ctx.inst_id = umc; - - if (remove_dram_offset(&ctx)) - goto out_err; - - if (get_dram_addr_map(&ctx)) - goto out_err; - - if (df_ops->get_intlv_mode(&ctx)) - goto out_err; - - lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); - intlv_num_chan = (ctx.reg_base_addr >> 4) & 0xF; - intlv_addr_sel = (ctx.reg_base_addr >> 8) & 0x7; - dram_base_addr = (ctx.reg_base_addr & GENMASK_ULL(31, 12)) << 16; + u8 intlv_addr_sel = (ctx->reg_base_addr >> 8) & 0x7; + u8 num_intlv_bits, cs_mask = 0; /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ if (intlv_addr_sel > 3) { pr_err("%s: Invalid interleave address select %d.\n", __func__, intlv_addr_sel); - goto out_err; + return -EINVAL; } - intlv_num_sockets = (ctx.reg_limit_addr >> 8) & 0x1; - intlv_num_dies = (ctx.reg_limit_addr >> 10) & 0x3; - dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); + intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; + intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; - intlv_addr_bit = intlv_addr_sel + 8; + ctx->intlv_addr_bit = intlv_addr_sel + 8; /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ switch (intlv_num_chan) { @@ -1218,7 +1188,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr default: pr_err("%s: Invalid number of interleaved channels %d.\n", __func__, intlv_num_chan); - goto out_err; + return -EINVAL; } num_intlv_bits = intlv_num_chan; @@ -1226,7 +1196,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (intlv_num_dies > 2) { pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", __func__, intlv_num_dies); - goto out_err; + return -EINVAL; } num_intlv_bits += intlv_num_dies; @@ -1238,7 +1208,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (num_intlv_bits > 4) { pr_err("%s: Invalid interleave bits %d.\n", __func__, num_intlv_bits); - goto out_err; + return -EINVAL; } if (num_intlv_bits > 0) { @@ -1251,41 +1221,43 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr * umc/channel# as instance id of the coherent slave * for FICAA. */ - if (df_indirect_read_instance(nid, 0, 0x50, umc, &ctx.tmp)) - goto out_err; + if (df_indirect_read_instance(ctx->nid, 0, 0x50, ctx->inst_id, &ctx->tmp)) + return -EINVAL; - cs_fabric_id = (ctx.tmp >> 8) & 0xFF; + cs_fabric_id = (ctx->tmp >> 8) & 0xFF; die_id_bit = 0; /* If interleaved over more than 1 channel: */ if (intlv_num_chan) { die_id_bit = intlv_num_chan; cs_mask = (1 << die_id_bit) - 1; - cs_id = cs_fabric_id & cs_mask; + ctx->cs_id = cs_fabric_id & cs_mask; } sock_id_bit = die_id_bit; /* Read D18F1x208 (SystemFabricIdMask). */ if (intlv_num_dies || intlv_num_sockets) - if (df_indirect_read_broadcast(nid, 1, 0x208, &ctx.tmp)) - goto out_err; + if (df_indirect_read_broadcast(ctx->nid, 1, 0x208, &ctx->tmp)) + return -EINVAL; /* If interleaved over more than 1 die. */ if (intlv_num_dies) { sock_id_bit = die_id_bit + intlv_num_dies; - die_id_shift = (ctx.tmp >> 24) & 0xF; - die_id_mask = (ctx.tmp >> 8) & 0xFF; + die_id_shift = (ctx->tmp >> 24) & 0xF; + die_id_mask = (ctx->tmp >> 8) & 0xFF; - cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; + ctx->cs_id |= ((cs_fabric_id & die_id_mask) + >> die_id_shift) << die_id_bit; } /* If interleaved over more than 1 socket. */ if (intlv_num_sockets) { - socket_id_shift = (ctx.tmp >> 28) & 0xF; - socket_id_mask = (ctx.tmp >> 16) & 0xFF; + socket_id_shift = (ctx->tmp >> 28) & 0xF; + socket_id_mask = (ctx->tmp >> 16) & 0xFF; - cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; + ctx->cs_id |= ((cs_fabric_id & socket_id_mask) + >> socket_id_shift) << sock_id_bit; } /* @@ -1296,12 +1268,53 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr * bits there are. "intlv_addr_bit" tells us how many "Y" bits * there are (where "I" starts). */ - temp_addr_y = ctx.ret_addr & GENMASK_ULL(intlv_addr_bit - 1, 0); - temp_addr_i = (cs_id << intlv_addr_bit); - temp_addr_x = (ctx.ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; - ctx.ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; + temp_addr_y = ctx->ret_addr & GENMASK_ULL(ctx->intlv_addr_bit - 1, 0); + temp_addr_i = (ctx->cs_id << ctx->intlv_addr_bit); + temp_addr_x = (ctx->ret_addr & GENMASK_ULL(63, ctx->intlv_addr_bit)) + << num_intlv_bits; + ctx->ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; } + return 0; +} + +static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +{ + u64 dram_base_addr, dram_limit_addr, dram_hole_base; + + u8 hashed_bit; + u8 lgcy_mmio_hole_en; + + struct addr_ctx ctx; + + if (!df_ops) + return -EINVAL; + + memset(&ctx, 0, sizeof(ctx)); + + /* We start from the normalized address */ + ctx.ret_addr = norm_addr; + + ctx.nid = nid; + ctx.inst_id = umc; + + if (remove_dram_offset(&ctx)) + return -EINVAL; + + if (get_dram_addr_map(&ctx)) + goto out_err; + + if (df_ops->get_intlv_mode(&ctx)) + goto out_err; + + if (denormalize_addr(&ctx)) + goto out_err; + + lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); + dram_base_addr = (ctx.reg_base_addr & GENMASK_ULL(31, 12)) << 16; + + dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); + /* Add dram base address */ ctx.ret_addr += dram_base_addr; @@ -1321,12 +1334,12 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr (ctx.ret_addr >> 18) ^ (ctx.ret_addr >> 21) ^ (ctx.ret_addr >> 30) ^ - cs_id; + ctx.cs_id; hashed_bit &= BIT(0); - if (hashed_bit != ((ctx.ret_addr >> intlv_addr_bit) & BIT(0))) - ctx.ret_addr ^= BIT(intlv_addr_bit); + if (hashed_bit != ((ctx.ret_addr >> ctx.intlv_addr_bit) & BIT(0))) + ctx.ret_addr ^= BIT(ctx.intlv_addr_bit); } /* Is calculated system address is above DRAM limit address? */ From patchwork Thu Oct 28 17:57:05 2021 Content-Type: text/plain; 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Thu, 28 Oct 2021 17:58:17 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT064.mail.protection.outlook.com (10.13.175.77) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Thu, 28 Oct 2021 17:58:14 +0000 Received: from yaz-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Thu, 28 Oct 2021 12:58:13 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , Yazen Ghannam Subject: [PATCH v3 10/33] EDAC/amd64: Define function to add DRAM base and hole Date: Thu, 28 Oct 2021 17:57:05 +0000 Message-ID: <20211028175728.121452-11-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211028175728.121452-1-yazen.ghannam@amd.com> References: <20211028175728.121452-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fe9da657-4987-473a-0aaf-08d99a3c83cb X-MS-TrafficTypeDiagnostic: BL1PR12MB5079: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:14.7873 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fe9da657-4987-473a-0aaf-08d99a3c83cb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5079 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move adding of DRAM base and hole into a separate helper function. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-12-yazen.ghannam@amd.com v2->v3: * Was patch 11 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 43 +++++++++++++++++++++++---------------- 1 file changed, 25 insertions(+), 18 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index b4b7c93a6390..64d894d7944a 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1278,12 +1278,32 @@ static int denormalize_addr(struct addr_ctx *ctx) return 0; } -static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +static int add_base_and_hole(struct addr_ctx *ctx) { - u64 dram_base_addr, dram_limit_addr, dram_hole_base; + u64 dram_base_addr = (ctx->reg_base_addr & GENMASK_ULL(31, 12)) << 16; + + /* Add dram base address */ + ctx->ret_addr += dram_base_addr; + /* If legacy MMIO hole enabled */ + if (ctx->reg_base_addr & BIT(1)) { + u32 dram_hole_base; + + if (df_indirect_read_broadcast(ctx->nid, 0, 0x104, &dram_hole_base)) + return -EINVAL; + + dram_hole_base &= GENMASK(31, 24); + if (ctx->ret_addr >= dram_hole_base) + ctx->ret_addr += (BIT_ULL(32) - dram_hole_base); + } + + return 0; +} + +static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +{ + u64 dram_limit_addr; u8 hashed_bit; - u8 lgcy_mmio_hole_en; struct addr_ctx ctx; @@ -1310,23 +1330,10 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (denormalize_addr(&ctx)) goto out_err; - lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); - dram_base_addr = (ctx.reg_base_addr & GENMASK_ULL(31, 12)) << 16; - dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); - /* Add dram base address */ - ctx.ret_addr += dram_base_addr; - - /* If legacy MMIO hole enabled */ - if (lgcy_mmio_hole_en) { - if (df_indirect_read_broadcast(nid, 0, 0x104, &ctx.tmp)) - goto out_err; - - dram_hole_base = ctx.tmp & GENMASK(31, 24); - if (ctx.ret_addr >= dram_hole_base) - ctx.ret_addr += (BIT_ULL(32) - dram_hole_base); - } + if (add_base_and_hole(&ctx)) + goto out_err; if (ctx.hash_enabled) { /* Save some parentheses and grab ls-bit at the end. */ From patchwork Thu Oct 28 17:57:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE72CC433EF for ; Thu, 28 Oct 2021 17:58:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A9B76610D2 for ; Thu, 28 Oct 2021 17:58:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231328AbhJ1SBO (ORCPT ); Thu, 28 Oct 2021 14:01:14 -0400 Received: from mail-co1nam11on2058.outbound.protection.outlook.com ([40.107.220.58]:52489 "EHLO NAM11-CO1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231335AbhJ1SAu (ORCPT ); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:18.0955 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 453883a9-2e35-4dfb-d21e-08d99a3c85c3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4605 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move the dehashing code into a separate helper function. Define a DF2-specific function for the current code. Specific helper functions will be added for future DF versions. The dehashing function used is based on the interleaving mode rather than the Data Fabric version. So save the function pointer in the context struct. The use of "df2" in the name of the current function is only because the interleaving mode using it only appears on Data Fabric 2 systems. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-13-yazen.ghannam@amd.com v2->v3: * Was patch 12 in v2. v1->v2: * Moved from arch/x86 to EDAC. * Add new function pointer in ctx struct. drivers/edac/amd64_edac.c | 36 ++++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 64d894d7944a..d7a2f621fdc0 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1069,7 +1069,7 @@ struct addr_ctx { u8 map_num; u8 intlv_addr_bit; u8 cs_id; - bool hash_enabled; + int (*dehash_addr)(struct addr_ctx *ctx); }; struct data_fabric_ops { @@ -1082,13 +1082,29 @@ static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8; } +static int dehash_addr_df2(struct addr_ctx *ctx) +{ + u8 hashed_bit = (ctx->ret_addr >> 12) ^ + (ctx->ret_addr >> 18) ^ + (ctx->ret_addr >> 21) ^ + (ctx->ret_addr >> 30) ^ + ctx->cs_id; + + hashed_bit &= BIT(0); + + if (hashed_bit != ((ctx->ret_addr >> ctx->intlv_addr_bit) & BIT(0))) + ctx->ret_addr ^= BIT(ctx->intlv_addr_bit); + + return 0; +} + static int get_intlv_mode_df2(struct addr_ctx *ctx) { ctx->intlv_mode = (ctx->reg_base_addr >> 4) & 0xF; if (ctx->intlv_mode == 8) { ctx->intlv_mode = DF2_HASH_2CH; - ctx->hash_enabled = true; + ctx->dehash_addr = dehash_addr_df2; } if (ctx->intlv_mode != NONE && @@ -1303,7 +1319,6 @@ static int add_base_and_hole(struct addr_ctx *ctx) static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_limit_addr; - u8 hashed_bit; struct addr_ctx ctx; @@ -1335,19 +1350,8 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (add_base_and_hole(&ctx)) goto out_err; - if (ctx.hash_enabled) { - /* Save some parentheses and grab ls-bit at the end. */ - hashed_bit = (ctx.ret_addr >> 12) ^ - (ctx.ret_addr >> 18) ^ - (ctx.ret_addr >> 21) ^ - (ctx.ret_addr >> 30) ^ - ctx.cs_id; - - hashed_bit &= BIT(0); - - if (hashed_bit != ((ctx.ret_addr >> ctx.intlv_addr_bit) & BIT(0))) - ctx.ret_addr ^= BIT(ctx.intlv_addr_bit); - } + if (ctx.dehash_addr && ctx.dehash_addr(&ctx)) + goto out_err; /* Is calculated system address is above DRAM limit address? */ if (ctx.ret_addr > dram_limit_addr) From patchwork Thu Oct 28 17:57:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17A22C433F5 for ; Thu, 28 Oct 2021 17:58:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 02942610D2 for ; Thu, 28 Oct 2021 17:58:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231572AbhJ1SBN (ORCPT ); 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Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-14-yazen.ghannam@amd.com v2->v3: * Was patch 13 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index d7a2f621fdc0..b0bf9dd0ba34 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1316,10 +1316,20 @@ static int add_base_and_hole(struct addr_ctx *ctx) return 0; } -static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +static int addr_over_limit(struct addr_ctx *ctx) { - u64 dram_limit_addr; + u64 dram_limit_addr = ((ctx->reg_limit_addr & GENMASK_ULL(31, 12)) << 16) + | GENMASK_ULL(27, 0); + + /* Is calculated system address above DRAM limit address? */ + if (ctx->ret_addr > dram_limit_addr) + return -EINVAL; + return 0; +} + +static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +{ struct addr_ctx ctx; if (!df_ops) @@ -1345,16 +1355,13 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (denormalize_addr(&ctx)) goto out_err; - dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); - if (add_base_and_hole(&ctx)) goto out_err; if (ctx.dehash_addr && ctx.dehash_addr(&ctx)) goto out_err; - /* Is calculated system address is above DRAM limit address? */ - if (ctx.ret_addr > dram_limit_addr) + if (addr_over_limit(&ctx)) goto out_err; *sys_addr = ctx.ret_addr; From patchwork Thu Oct 28 17:57:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BB1AC4332F for ; Thu, 28 Oct 2021 17:58:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 85800610D2 for ; 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Thu, 28 Oct 2021 17:58:20 +0000 Received: from yaz-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Thu, 28 Oct 2021 12:58:18 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , Yazen Ghannam Subject: [PATCH v3 13/33] EDAC/amd64: Remove goto statements Date: Thu, 28 Oct 2021 17:57:08 +0000 Message-ID: <20211028175728.121452-14-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211028175728.121452-1-yazen.ghannam@amd.com> References: <20211028175728.121452-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e6a42df0-2d10-4af8-f23b-08d99a3c8723 X-MS-TrafficTypeDiagnostic: BYAPR12MB3383: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2276; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:20.3812 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e6a42df0-2d10-4af8-f23b-08d99a3c8723 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3383 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org ...and just return error codes directly. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-15-yazen.ghannam@amd.com v2->v3: * Was patch 14 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index b0bf9dd0ba34..2bacc8111f8e 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1347,28 +1347,25 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr return -EINVAL; if (get_dram_addr_map(&ctx)) - goto out_err; + return -EINVAL; if (df_ops->get_intlv_mode(&ctx)) - goto out_err; + return -EINVAL; if (denormalize_addr(&ctx)) - goto out_err; + return -EINVAL; if (add_base_and_hole(&ctx)) - goto out_err; + return -EINVAL; if (ctx.dehash_addr && ctx.dehash_addr(&ctx)) - goto out_err; + return -EINVAL; if (addr_over_limit(&ctx)) - goto out_err; + return -EINVAL; *sys_addr = ctx.ret_addr; return 0; - -out_err: - return -EINVAL; } static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16); From patchwork Thu Oct 28 17:57:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590715 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99A41C433F5 for ; Thu, 28 Oct 2021 17:59:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7FAFC610D2 for ; Thu, 28 Oct 2021 17:59:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231669AbhJ1SB0 (ORCPT ); Thu, 28 Oct 2021 14:01:26 -0400 Received: from mail-mw2nam12on2068.outbound.protection.outlook.com ([40.107.244.68]:9091 "EHLO NAM12-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231384AbhJ1SAz (ORCPT ); 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Thu, 28 Oct 2021 17:58:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT064.mail.protection.outlook.com (10.13.175.77) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Thu, 28 Oct 2021 17:58:23 +0000 Received: from yaz-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Thu, 28 Oct 2021 12:58:19 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , Yazen Ghannam Subject: [PATCH v3 14/33] EDAC/amd64: Simplify function parameters Date: Thu, 28 Oct 2021 17:57:09 +0000 Message-ID: <20211028175728.121452-15-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211028175728.121452-1-yazen.ghannam@amd.com> References: <20211028175728.121452-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9d6c6620-1b57-42a0-7692-08d99a3c893a X-MS-TrafficTypeDiagnostic: DM5PR12MB1419: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:23.9062 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9d6c6620-1b57-42a0-7692-08d99a3c893a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1419 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Use a single address parameter for input and result to reduce the number of parameters. Also, rename the "umc" parameter to "df_inst_id" to reflect what the value represents. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-16-yazen.ghannam@amd.com v2->v3: * Was patch 15 in v2. * Renamed the "umc" parameter. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 2bacc8111f8e..f4074bc270ec 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1328,7 +1328,7 @@ static int addr_over_limit(struct addr_ctx *ctx) return 0; } -static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +static int umc_normaddr_to_sysaddr(u64 *addr, u16 nid, u8 df_inst_id) { struct addr_ctx ctx; @@ -1338,10 +1338,10 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr memset(&ctx, 0, sizeof(ctx)); /* We start from the normalized address */ - ctx.ret_addr = norm_addr; + ctx.ret_addr = *addr; ctx.nid = nid; - ctx.inst_id = umc; + ctx.inst_id = df_inst_id; if (remove_dram_offset(&ctx)) return -EINVAL; @@ -1364,7 +1364,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (addr_over_limit(&ctx)) return -EINVAL; - *sys_addr = ctx.ret_addr; + *addr = ctx.ret_addr; return 0; } @@ -3475,10 +3475,10 @@ static void decode_umc_error(int node_id, struct mce *m) { u8 ecc_type = (m->status >> 45) & 0x3; struct mem_ctl_info *mci; + u64 sys_addr = m->addr; struct amd64_pvt *pvt; struct err_info err; u8 df_inst_id; - u64 sys_addr; mci = edac_mc_find(node_id); if (!mci) @@ -3517,7 +3517,7 @@ static void decode_umc_error(int node_id, struct mce *m) else df_inst_id = err.channel; - if (umc_normaddr_to_sysaddr(m->addr, pvt->mc_node_id, df_inst_id, &sys_addr)) { + if (umc_normaddr_to_sysaddr(&sys_addr, pvt->mc_node_id, df_inst_id)) { err.err_code = ERR_NORM_ADDR; goto log_error; } From patchwork Thu Oct 28 17:57:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 234D1C4332F for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:24.9865 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7e29377e-1a7f-41c1-2a18-08d99a3c89df X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4404 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move code to find the interleave address bit into a separate helper function. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-17-yazen.ghannam@amd.com v2->v3: * Was patch 16 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index f4074bc270ec..6b19fc5cf340 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1172,25 +1172,33 @@ static int get_dram_addr_map(struct addr_ctx *ctx) return 0; } -static int denormalize_addr(struct addr_ctx *ctx) +static int get_intlv_addr_bit(struct addr_ctx *ctx) { - u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; u8 intlv_addr_sel = (ctx->reg_base_addr >> 8) & 0x7; - u8 num_intlv_bits, cs_mask = 0; /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ if (intlv_addr_sel > 3) { - pr_err("%s: Invalid interleave address select %d.\n", - __func__, intlv_addr_sel); + pr_debug("Invalid interleave address select %d.\n", intlv_addr_sel); return -EINVAL; } + ctx->intlv_addr_bit = intlv_addr_sel + 8; + + return 0; +} + +static int denormalize_addr(struct addr_ctx *ctx) +{ + u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; + u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; + u8 num_intlv_bits, cs_mask = 0; + + if (get_intlv_addr_bit(ctx)) + return -EINVAL; + intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; - ctx->intlv_addr_bit = intlv_addr_sel + 8; - /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ switch (intlv_num_chan) { case 0: intlv_num_chan = 0; break; From patchwork Thu Oct 28 17:57:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590719 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F255C433F5 for ; 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dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT064.mail.protection.outlook.com (10.13.175.77) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Thu, 28 Oct 2021 17:58:25 +0000 Received: from yaz-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Thu, 28 Oct 2021 12:58:22 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , Yazen Ghannam Subject: [PATCH v3 16/33] EDAC/amd64: Skip denormalization if no interleaving Date: Thu, 28 Oct 2021 17:57:11 +0000 Message-ID: <20211028175728.121452-17-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211028175728.121452-1-yazen.ghannam@amd.com> References: <20211028175728.121452-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 68a3896a-b0f4-4b8b-ec50-08d99a3c8a6b X-MS-TrafficTypeDiagnostic: MWHPR12MB1280: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5516; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:25.9090 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 68a3896a-b0f4-4b8b-ec50-08d99a3c8a6b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1280 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Denormalization doesn't apply to the "no interleaving" mode, so return early without error in this case. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-18-yazen.ghannam@amd.com v2->v3: * Was patch 17 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 6b19fc5cf340..b6a8366e40ba 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1193,6 +1193,10 @@ static int denormalize_addr(struct addr_ctx *ctx) u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; u8 num_intlv_bits, cs_mask = 0; + /* Return early if no interleaving. */ + if (ctx->intlv_mode == NONE) + return 0; + if (get_intlv_addr_bit(ctx)) return -EINVAL; From patchwork Thu Oct 28 17:57:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590721 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F2F5C43219 for ; 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dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT064.mail.protection.outlook.com (10.13.175.77) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Thu, 28 Oct 2021 17:58:26 +0000 Received: from yaz-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Thu, 28 Oct 2021 12:58:23 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , Yazen Ghannam Subject: [PATCH v3 17/33] EDAC/amd64: Define function to get number of interleaved channels Date: Thu, 28 Oct 2021 17:57:12 +0000 Message-ID: <20211028175728.121452-18-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211028175728.121452-1-yazen.ghannam@amd.com> References: <20211028175728.121452-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bd52388c-8336-4ee1-9e82-08d99a3c8ae5 X-MS-TrafficTypeDiagnostic: CY4PR1201MB0101: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:530; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:26.7066 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd52388c-8336-4ee1-9e82-08d99a3c8ae5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1201MB0101 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move number of interleaved channel calculation to a separate helper function. Drop unused cases. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-19-yazen.ghannam@amd.com v2->v3: * Was patch 18 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 42 +++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 19 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index b6a8366e40ba..11a54e7a0432 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1068,6 +1068,7 @@ struct addr_ctx { u8 inst_id; u8 map_num; u8 intlv_addr_bit; + u8 intlv_num_chan; u8 cs_id; int (*dehash_addr)(struct addr_ctx *ctx); }; @@ -1187,10 +1188,27 @@ static int get_intlv_addr_bit(struct addr_ctx *ctx) return 0; } +static void get_intlv_num_chan(struct addr_ctx *ctx) +{ + /* Save the log2(# of channels). */ + switch (ctx->intlv_mode) { + case NONE: + ctx->intlv_num_chan = 0; + break; + case NOHASH_2CH: + case DF2_HASH_2CH: + ctx->intlv_num_chan = 1; + break; + default: + /* Valid interleaving modes where checked earlier. */ + break; + } +} + static int denormalize_addr(struct addr_ctx *ctx) { u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; + u8 intlv_num_dies, intlv_num_sockets; u8 num_intlv_bits, cs_mask = 0; /* Return early if no interleaving. */ @@ -1203,23 +1221,9 @@ static int denormalize_addr(struct addr_ctx *ctx) intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; - /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ - switch (intlv_num_chan) { - case 0: intlv_num_chan = 0; break; - case 1: intlv_num_chan = 1; break; - case 3: intlv_num_chan = 2; break; - case 5: intlv_num_chan = 3; break; - case 7: intlv_num_chan = 4; break; - - case 8: intlv_num_chan = 1; - break; - default: - pr_err("%s: Invalid number of interleaved channels %d.\n", - __func__, intlv_num_chan); - return -EINVAL; - } + get_intlv_num_chan(ctx); - num_intlv_bits = intlv_num_chan; + num_intlv_bits = ctx->intlv_num_chan; if (intlv_num_dies > 2) { pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", @@ -1256,8 +1260,8 @@ static int denormalize_addr(struct addr_ctx *ctx) die_id_bit = 0; /* If interleaved over more than 1 channel: */ - if (intlv_num_chan) { - die_id_bit = intlv_num_chan; + if (ctx->intlv_num_chan) { + die_id_bit = ctx->intlv_num_chan; cs_mask = (1 << die_id_bit) - 1; ctx->cs_id = cs_fabric_id & cs_mask; } From patchwork Thu Oct 28 17:57:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 647BCC4332F for ; Thu, 28 Oct 2021 17:59:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4FF39610EA for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:27.5571 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8c72540c-566e-46fa-17b9-08d99a3c8b67 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4450 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move parsing of the number of interleaved dies to a separate helper function. This will be expanded for future DF versions. Also, drop an unneeded assert to match the reference code. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-20-yazen.ghannam@amd.com v2->v3: * Was patch 19 in v2. v1->v2: * Moved from arch/x86 to EDAC. * Add new function to data_fabric_ops. drivers/edac/amd64_edac.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 11a54e7a0432..e76aa8ee906a 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1069,6 +1069,7 @@ struct addr_ctx { u8 map_num; u8 intlv_addr_bit; u8 intlv_num_chan; + u8 intlv_num_dies; u8 cs_id; int (*dehash_addr)(struct addr_ctx *ctx); }; @@ -1076,6 +1077,7 @@ struct addr_ctx { struct data_fabric_ops { u64 (*get_hi_addr_offset) (struct addr_ctx *ctx); int (*get_intlv_mode) (struct addr_ctx *ctx); + void (*get_intlv_num_dies) (struct addr_ctx *ctx); }; static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) @@ -1116,9 +1118,15 @@ static int get_intlv_mode_df2(struct addr_ctx *ctx) return 0; } +static void get_intlv_num_dies_df2(struct addr_ctx *ctx) +{ + ctx->intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = get_hi_addr_offset_df2, .get_intlv_mode = get_intlv_mode_df2, + .get_intlv_num_dies = get_intlv_num_dies_df2, }; struct data_fabric_ops *df_ops; @@ -1208,7 +1216,7 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) static int denormalize_addr(struct addr_ctx *ctx) { u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 intlv_num_dies, intlv_num_sockets; + u8 intlv_num_sockets; u8 num_intlv_bits, cs_mask = 0; /* Return early if no interleaving. */ @@ -1219,19 +1227,12 @@ static int denormalize_addr(struct addr_ctx *ctx) return -EINVAL; intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; - intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; get_intlv_num_chan(ctx); + df_ops->get_intlv_num_dies(ctx); num_intlv_bits = ctx->intlv_num_chan; - - if (intlv_num_dies > 2) { - pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", - __func__, intlv_num_dies); - return -EINVAL; - } - - num_intlv_bits += intlv_num_dies; + num_intlv_bits += ctx->intlv_num_dies; /* Add a bit if sockets are interleaved. */ num_intlv_bits += intlv_num_sockets; @@ -1269,13 +1270,13 @@ static int denormalize_addr(struct addr_ctx *ctx) sock_id_bit = die_id_bit; /* Read D18F1x208 (SystemFabricIdMask). */ - if (intlv_num_dies || intlv_num_sockets) + if (ctx->intlv_num_dies || intlv_num_sockets) if (df_indirect_read_broadcast(ctx->nid, 1, 0x208, &ctx->tmp)) return -EINVAL; /* If interleaved over more than 1 die. */ - if (intlv_num_dies) { - sock_id_bit = die_id_bit + intlv_num_dies; + if (ctx->intlv_num_dies) { + sock_id_bit = die_id_bit + ctx->intlv_num_dies; die_id_shift = (ctx->tmp >> 24) & 0xF; die_id_mask = (ctx->tmp >> 8) & 0xFF; From patchwork Thu Oct 28 17:57:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590727 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4E87C4332F for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:30.4255 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ba75bc57-adb4-41c1-ec77-08d99a3c8d1c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1366 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move parsing of the number of interleaved sockets to a separate helper function. This will be expanded for future DF versions. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-21-yazen.ghannam@amd.com v2->v3: * Was patch 20 in v2. v1->v2: * Moved from arch/x86 to EDAC. * Add new function to data_fabric_ops. drivers/edac/amd64_edac.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index e76aa8ee906a..18e446c59baa 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1070,6 +1070,7 @@ struct addr_ctx { u8 intlv_addr_bit; u8 intlv_num_chan; u8 intlv_num_dies; + u8 intlv_num_sockets; u8 cs_id; int (*dehash_addr)(struct addr_ctx *ctx); }; @@ -1078,6 +1079,7 @@ struct data_fabric_ops { u64 (*get_hi_addr_offset) (struct addr_ctx *ctx); int (*get_intlv_mode) (struct addr_ctx *ctx); void (*get_intlv_num_dies) (struct addr_ctx *ctx); + void (*get_intlv_num_sockets) (struct addr_ctx *ctx); }; static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) @@ -1123,10 +1125,16 @@ static void get_intlv_num_dies_df2(struct addr_ctx *ctx) ctx->intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; } +static void get_intlv_num_sockets_df2(struct addr_ctx *ctx) +{ + ctx->intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = get_hi_addr_offset_df2, .get_intlv_mode = get_intlv_mode_df2, .get_intlv_num_dies = get_intlv_num_dies_df2, + .get_intlv_num_sockets = get_intlv_num_sockets_df2, }; struct data_fabric_ops *df_ops; @@ -1216,7 +1224,6 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) static int denormalize_addr(struct addr_ctx *ctx) { u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 intlv_num_sockets; u8 num_intlv_bits, cs_mask = 0; /* Return early if no interleaving. */ @@ -1226,16 +1233,13 @@ static int denormalize_addr(struct addr_ctx *ctx) if (get_intlv_addr_bit(ctx)) return -EINVAL; - intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; - get_intlv_num_chan(ctx); df_ops->get_intlv_num_dies(ctx); + df_ops->get_intlv_num_sockets(ctx); num_intlv_bits = ctx->intlv_num_chan; num_intlv_bits += ctx->intlv_num_dies; - - /* Add a bit if sockets are interleaved. */ - num_intlv_bits += intlv_num_sockets; + num_intlv_bits += ctx->intlv_num_sockets; /* Assert num_intlv_bits <= 4 */ if (num_intlv_bits > 4) { @@ -1270,7 +1274,7 @@ static int denormalize_addr(struct addr_ctx *ctx) sock_id_bit = die_id_bit; /* Read D18F1x208 (SystemFabricIdMask). */ - if (ctx->intlv_num_dies || intlv_num_sockets) + if (ctx->intlv_num_dies || ctx->intlv_num_sockets) if (df_indirect_read_broadcast(ctx->nid, 1, 0x208, &ctx->tmp)) return -EINVAL; @@ -1285,7 +1289,7 @@ static int denormalize_addr(struct addr_ctx *ctx) } /* If interleaved over more than 1 socket. */ - if (intlv_num_sockets) { + if (ctx->intlv_num_sockets) { socket_id_shift = (ctx->tmp >> 28) & 0xF; socket_id_mask = (ctx->tmp >> 16) & 0xFF; From patchwork Thu Oct 28 17:57:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590725 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DEFBC433FE for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:31.3319 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d231bc7c-55f0-41da-8c25-08d99a3c8da7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5172 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org It was removed in the reference code, so remove it here. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-22-yazen.ghannam@amd.com v2->v3: * Was patch 21 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 18e446c59baa..78b69406b775 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1241,13 +1241,6 @@ static int denormalize_addr(struct addr_ctx *ctx) num_intlv_bits += ctx->intlv_num_dies; num_intlv_bits += ctx->intlv_num_sockets; - /* Assert num_intlv_bits <= 4 */ - if (num_intlv_bits > 4) { - pr_err("%s: Invalid interleave bits %d.\n", - __func__, num_intlv_bits); - return -EINVAL; - } - if (num_intlv_bits > 0) { u64 temp_addr_x, temp_addr_i, temp_addr_y; u8 die_id_bit, sock_id_bit, cs_fabric_id; From patchwork Thu Oct 28 17:57:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590729 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAA91C43219 for ; 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dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT064.mail.protection.outlook.com (10.13.175.77) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Thu, 28 Oct 2021 17:58:33 +0000 Received: from yaz-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Thu, 28 Oct 2021 12:58:31 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , Yazen Ghannam Subject: [PATCH v3 21/33] EDAC/amd64: Define function to make space for CS ID Date: Thu, 28 Oct 2021 17:57:16 +0000 Message-ID: <20211028175728.121452-22-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211028175728.121452-1-yazen.ghannam@amd.com> References: <20211028175728.121452-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0b3e02d4-1374-4c2d-40c9-08d99a3c8f37 X-MS-TrafficTypeDiagnostic: DM5PR12MB1641: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:33.9514 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0b3e02d4-1374-4c2d-40c9-08d99a3c8f37 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1641 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move code that makes a gap for the CS ID into a separate helper function. The exact bits to use vary based on interleaving mode. New interleaving modes in future DF versions will be added as new cases. Also, introduce a helper function that does the bit manipulation to make the gap. The current version of this function is "simple", and future interleaving modes may reuse this or use a more advanced function. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-23-yazen.ghannam@amd.com v2->v3: * Was patch 22 in v2. v1->v2: * Moved from arch/x86 to EDAC. * Added new function pointer to ctx struct. drivers/edac/amd64_edac.c | 37 +++++++++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 8 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 78b69406b775..9ca822c1ea9c 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1073,6 +1073,7 @@ struct addr_ctx { u8 intlv_num_sockets; u8 cs_id; int (*dehash_addr)(struct addr_ctx *ctx); + void (*make_space_for_cs_id)(struct addr_ctx *ctx); }; struct data_fabric_ops { @@ -1082,6 +1083,29 @@ struct data_fabric_ops { void (*get_intlv_num_sockets) (struct addr_ctx *ctx); }; +static void expand_bits(u8 start_bit, u8 num_bits, u64 *value) +{ + u64 temp1, temp2; + + if (start_bit == 0) { + *value <<= num_bits; + return; + } + + temp1 = *value & GENMASK_ULL(start_bit - 1, 0); + temp2 = (*value & GENMASK_ULL(63, start_bit)) << num_bits; + *value = temp1 | temp2; +} + +static void make_space_for_cs_id_simple(struct addr_ctx *ctx) +{ + u8 num_intlv_bits = ctx->intlv_num_chan; + + num_intlv_bits += ctx->intlv_num_dies; + num_intlv_bits += ctx->intlv_num_sockets; + expand_bits(ctx->intlv_addr_bit, num_intlv_bits, &ctx->ret_addr); +} + static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) { return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8; @@ -1112,6 +1136,8 @@ static int get_intlv_mode_df2(struct addr_ctx *ctx) ctx->dehash_addr = dehash_addr_df2; } + ctx->make_space_for_cs_id = make_space_for_cs_id_simple; + if (ctx->intlv_mode != NONE && ctx->intlv_mode != NOHASH_2CH && ctx->intlv_mode != DF2_HASH_2CH) @@ -1237,13 +1263,11 @@ static int denormalize_addr(struct addr_ctx *ctx) df_ops->get_intlv_num_dies(ctx); df_ops->get_intlv_num_sockets(ctx); - num_intlv_bits = ctx->intlv_num_chan; - num_intlv_bits += ctx->intlv_num_dies; - num_intlv_bits += ctx->intlv_num_sockets; + ctx->make_space_for_cs_id(ctx); if (num_intlv_bits > 0) { - u64 temp_addr_x, temp_addr_i, temp_addr_y; u8 die_id_bit, sock_id_bit, cs_fabric_id; + u64 temp_addr_i; /* * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. @@ -1298,11 +1322,8 @@ static int denormalize_addr(struct addr_ctx *ctx) * bits there are. "intlv_addr_bit" tells us how many "Y" bits * there are (where "I" starts). */ - temp_addr_y = ctx->ret_addr & GENMASK_ULL(ctx->intlv_addr_bit - 1, 0); temp_addr_i = (ctx->cs_id << ctx->intlv_addr_bit); - temp_addr_x = (ctx->ret_addr & GENMASK_ULL(63, ctx->intlv_addr_bit)) - << num_intlv_bits; - ctx->ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; + ctx->ret_addr |= temp_addr_i; } return 0; From patchwork Thu Oct 28 17:57:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590731 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6AA9C433F5 for ; Thu, 28 Oct 2021 17:59:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B4EA5610EA for ; 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Thu, 28 Oct 2021 17:58:35 +0000 Received: from yaz-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Thu, 28 Oct 2021 12:58:32 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , Yazen Ghannam Subject: [PATCH v3 22/33] EDAC/amd64: Define function to calculate CS ID Date: Thu, 28 Oct 2021 17:57:17 +0000 Message-ID: <20211028175728.121452-23-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211028175728.121452-1-yazen.ghannam@amd.com> References: <20211028175728.121452-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: af940567-181c-40af-7ff5-08d99a3c900f X-MS-TrafficTypeDiagnostic: MW2PR12MB2491: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:35.3676 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af940567-181c-40af-7ff5-08d99a3c900f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR12MB2491 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move code used to calculate the CS ID into a separate helper function. Drop redundant code comment about reading DF register. The "num_intlv_bits" variable is left uninitialized as it will be removed in a later patch. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-24-yazen.ghannam@amd.com v2->v3: * Was patch 23 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 98 ++++++++++++++++++++------------------- 1 file changed, 50 insertions(+), 48 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 9ca822c1ea9c..2da0170f6d84 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1247,10 +1247,55 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) } } -static int denormalize_addr(struct addr_ctx *ctx) +static int calculate_cs_id(struct addr_ctx *ctx) { u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 num_intlv_bits, cs_mask = 0; + u8 die_id_bit, sock_id_bit, cs_fabric_id, cs_mask = 0; + + /* Read D18F0x50 (FabricBlockInstanceInformation3). */ + if (df_indirect_read_instance(ctx->nid, 0, 0x50, ctx->inst_id, &ctx->tmp)) + return -EINVAL; + + cs_fabric_id = (ctx->tmp >> 8) & 0xFF; + die_id_bit = 0; + + /* If interleaved over more than 1 channel: */ + if (ctx->intlv_num_chan) { + die_id_bit = ctx->intlv_num_chan; + cs_mask = (1 << die_id_bit) - 1; + ctx->cs_id = cs_fabric_id & cs_mask; + } + + sock_id_bit = die_id_bit; + + /* Read D18F1x208 (SystemFabricIdMask). */ + if (ctx->intlv_num_dies || ctx->intlv_num_sockets) + if (df_indirect_read_broadcast(ctx->nid, 1, 0x208, &ctx->tmp)) + return -EINVAL; + + /* If interleaved over more than 1 die: */ + if (ctx->intlv_num_dies) { + sock_id_bit = die_id_bit + ctx->intlv_num_dies; + die_id_shift = (ctx->tmp >> 24) & 0xF; + die_id_mask = (ctx->tmp >> 8) & 0xFF; + + ctx->cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; + } + + /* If interleaved over more than 1 socket: */ + if (ctx->intlv_num_sockets) { + socket_id_shift = (ctx->tmp >> 28) & 0xF; + socket_id_mask = (ctx->tmp >> 16) & 0xFF; + + ctx->cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; + } + + return 0; +} + +static int denormalize_addr(struct addr_ctx *ctx) +{ + u8 num_intlv_bits; /* Return early if no interleaving. */ if (ctx->intlv_mode == NONE) @@ -1265,55 +1310,12 @@ static int denormalize_addr(struct addr_ctx *ctx) ctx->make_space_for_cs_id(ctx); + if (calculate_cs_id(ctx)) + return -EINVAL; + if (num_intlv_bits > 0) { - u8 die_id_bit, sock_id_bit, cs_fabric_id; u64 temp_addr_i; - /* - * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. - * This is the fabric id for this coherent slave. Use - * umc/channel# as instance id of the coherent slave - * for FICAA. - */ - if (df_indirect_read_instance(ctx->nid, 0, 0x50, ctx->inst_id, &ctx->tmp)) - return -EINVAL; - - cs_fabric_id = (ctx->tmp >> 8) & 0xFF; - die_id_bit = 0; - - /* If interleaved over more than 1 channel: */ - if (ctx->intlv_num_chan) { - die_id_bit = ctx->intlv_num_chan; - cs_mask = (1 << die_id_bit) - 1; - ctx->cs_id = cs_fabric_id & cs_mask; - } - - sock_id_bit = die_id_bit; - - /* Read D18F1x208 (SystemFabricIdMask). */ - if (ctx->intlv_num_dies || ctx->intlv_num_sockets) - if (df_indirect_read_broadcast(ctx->nid, 1, 0x208, &ctx->tmp)) - return -EINVAL; - - /* If interleaved over more than 1 die. */ - if (ctx->intlv_num_dies) { - sock_id_bit = die_id_bit + ctx->intlv_num_dies; - die_id_shift = (ctx->tmp >> 24) & 0xF; - die_id_mask = (ctx->tmp >> 8) & 0xFF; - - ctx->cs_id |= ((cs_fabric_id & die_id_mask) - >> die_id_shift) << die_id_bit; - } - - /* If interleaved over more than 1 socket. */ - if (ctx->intlv_num_sockets) { - socket_id_shift = (ctx->tmp >> 28) & 0xF; - socket_id_mask = (ctx->tmp >> 16) & 0xFF; - - ctx->cs_id |= ((cs_fabric_id & socket_id_mask) - >> socket_id_shift) << sock_id_bit; - } - /* * The pre-interleaved address consists of XXXXXXIIIYYYYY * where III is the ID for this CS, and XXXXXXYYYYY are the From patchwork Thu Oct 28 17:57:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E742CC433EF for ; Thu, 28 Oct 2021 17:59:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D4AD3610E7 for ; Thu, 28 Oct 2021 17:59:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231880AbhJ1SB5 (ORCPT ); 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Thu, 28 Oct 2021 17:58:35 +0000 Received: from yaz-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Thu, 28 Oct 2021 12:58:34 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , Yazen Ghannam Subject: [PATCH v3 23/33] EDAC/amd64: Define function to insert CS ID into address Date: Thu, 28 Oct 2021 17:57:18 +0000 Message-ID: <20211028175728.121452-24-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211028175728.121452-1-yazen.ghannam@amd.com> References: <20211028175728.121452-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 091f0e0a-30b1-46c5-49bf-08d99a3c906d X-MS-TrafficTypeDiagnostic: DM5PR12MB1179: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:35.9843 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 091f0e0a-30b1-46c5-49bf-08d99a3c906d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1179 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move the code that inserts the CS ID into the address into a separate helper function. Save the function pointer in the context struct. It will be set based on interleaving mode rather than Data Fabric version. This will be expanded for new interleaving modes added in future Data Fabric versions. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-25-yazen.ghannam@amd.com v2->v3: * Was patch 24 in v2. v1->v2: * Moved from arch/x86 to EDAC. * Added function pointer to ctx struct. drivers/edac/amd64_edac.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 2da0170f6d84..a36df70910aa 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1074,6 +1074,7 @@ struct addr_ctx { u8 cs_id; int (*dehash_addr)(struct addr_ctx *ctx); void (*make_space_for_cs_id)(struct addr_ctx *ctx); + void (*insert_cs_id)(struct addr_ctx *ctx); }; struct data_fabric_ops { @@ -1106,6 +1107,11 @@ static void make_space_for_cs_id_simple(struct addr_ctx *ctx) expand_bits(ctx->intlv_addr_bit, num_intlv_bits, &ctx->ret_addr); } +static void insert_cs_id_simple(struct addr_ctx *ctx) +{ + ctx->ret_addr |= (ctx->cs_id << ctx->intlv_addr_bit); +} + static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) { return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8; @@ -1137,6 +1143,7 @@ static int get_intlv_mode_df2(struct addr_ctx *ctx) } ctx->make_space_for_cs_id = make_space_for_cs_id_simple; + ctx->insert_cs_id = insert_cs_id_simple; if (ctx->intlv_mode != NONE && ctx->intlv_mode != NOHASH_2CH && @@ -1295,8 +1302,6 @@ static int calculate_cs_id(struct addr_ctx *ctx) static int denormalize_addr(struct addr_ctx *ctx) { - u8 num_intlv_bits; - /* Return early if no interleaving. */ if (ctx->intlv_mode == NONE) return 0; @@ -1313,20 +1318,7 @@ static int denormalize_addr(struct addr_ctx *ctx) if (calculate_cs_id(ctx)) return -EINVAL; - if (num_intlv_bits > 0) { - u64 temp_addr_i; - - /* - * The pre-interleaved address consists of XXXXXXIIIYYYYY - * where III is the ID for this CS, and XXXXXXYYYYY are the - * address bits from the post-interleaved address. - * "num_intlv_bits" has been calculated to tell us how many "I" - * bits there are. "intlv_addr_bit" tells us how many "Y" bits - * there are (where "I" starts). - */ - temp_addr_i = (ctx->cs_id << ctx->intlv_addr_bit); - ctx->ret_addr |= temp_addr_i; - } + ctx->insert_cs_id(ctx); return 0; } From patchwork Thu Oct 28 17:57:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590735 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4605C433EF for ; Thu, 28 Oct 2021 17:59:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 99706610D2 for ; Thu, 28 Oct 2021 17:59:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231981AbhJ1SCM (ORCPT ); Thu, 28 Oct 2021 14:02:12 -0400 Received: from mail-dm6nam10on2047.outbound.protection.outlook.com ([40.107.93.47]:62351 "EHLO NAM10-DM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231530AbhJ1SBI (ORCPT ); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:37.7867 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 14c99eff-4329-490c-7772-08d99a3c9180 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT037.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2735 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move code that gets the CS Fabric ID into a separate helper function. This will be expanded for future DF versions. The bitfield used for this value may be larger than the 8 bits currently used. So make it a u16 type which is large enough to hold all known sizes of this bitfield across DF versions. Also, call this function early as future DF versions may need the value early. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-26-yazen.ghannam@amd.com v2->v3: * Was patch 25 in v2. v1->v2: * Moved from arch/x86 to EDAC. * Added function to data_fabric_ops. drivers/edac/amd64_edac.c | 33 ++++++++++++++++++++++----------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index a36df70910aa..5aae735f1389 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1064,6 +1064,7 @@ struct addr_ctx { u32 reg_dram_offset; u32 reg_base_addr; u32 reg_limit_addr; + u16 cs_fabric_id; u16 nid; u8 inst_id; u8 map_num; @@ -1080,6 +1081,7 @@ struct addr_ctx { struct data_fabric_ops { u64 (*get_hi_addr_offset) (struct addr_ctx *ctx); int (*get_intlv_mode) (struct addr_ctx *ctx); + int (*get_cs_fabric_id) (struct addr_ctx *ctx); void (*get_intlv_num_dies) (struct addr_ctx *ctx); void (*get_intlv_num_sockets) (struct addr_ctx *ctx); }; @@ -1163,11 +1165,23 @@ static void get_intlv_num_sockets_df2(struct addr_ctx *ctx) ctx->intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; } +static int get_cs_fabric_id_df2(struct addr_ctx *ctx) +{ + /* Read D18F0x50 (FabricBlockInstanceInformation3). */ + if (df_indirect_read_instance(ctx->nid, 0, 0x50, ctx->inst_id, &ctx->tmp)) + return -EINVAL; + + ctx->cs_fabric_id = (ctx->tmp >> 8) & 0xFF; + + return 0; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = get_hi_addr_offset_df2, .get_intlv_mode = get_intlv_mode_df2, .get_intlv_num_dies = get_intlv_num_dies_df2, .get_intlv_num_sockets = get_intlv_num_sockets_df2, + .get_cs_fabric_id = get_cs_fabric_id_df2, }; struct data_fabric_ops *df_ops; @@ -1257,20 +1271,13 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) static int calculate_cs_id(struct addr_ctx *ctx) { u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 die_id_bit, sock_id_bit, cs_fabric_id, cs_mask = 0; - - /* Read D18F0x50 (FabricBlockInstanceInformation3). */ - if (df_indirect_read_instance(ctx->nid, 0, 0x50, ctx->inst_id, &ctx->tmp)) - return -EINVAL; - - cs_fabric_id = (ctx->tmp >> 8) & 0xFF; - die_id_bit = 0; + u8 die_id_bit = 0, sock_id_bit, cs_mask = 0; /* If interleaved over more than 1 channel: */ if (ctx->intlv_num_chan) { die_id_bit = ctx->intlv_num_chan; cs_mask = (1 << die_id_bit) - 1; - ctx->cs_id = cs_fabric_id & cs_mask; + ctx->cs_id = ctx->cs_fabric_id & cs_mask; } sock_id_bit = die_id_bit; @@ -1286,7 +1293,7 @@ static int calculate_cs_id(struct addr_ctx *ctx) die_id_shift = (ctx->tmp >> 24) & 0xF; die_id_mask = (ctx->tmp >> 8) & 0xFF; - ctx->cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; + ctx->cs_id |= ((ctx->cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; } /* If interleaved over more than 1 socket: */ @@ -1294,7 +1301,8 @@ static int calculate_cs_id(struct addr_ctx *ctx) socket_id_shift = (ctx->tmp >> 28) & 0xF; socket_id_mask = (ctx->tmp >> 16) & 0xFF; - ctx->cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; + ctx->cs_id |= ((ctx->cs_fabric_id & socket_id_mask) + >> socket_id_shift) << sock_id_bit; } return 0; @@ -1372,6 +1380,9 @@ static int umc_normaddr_to_sysaddr(u64 *addr, u16 nid, u8 df_inst_id) ctx.nid = nid; ctx.inst_id = df_inst_id; + if (df_ops->get_cs_fabric_id(&ctx)) + return -EINVAL; + if (remove_dram_offset(&ctx)) return -EINVAL; From patchwork Thu Oct 28 17:57:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73D96C433F5 for ; Thu, 28 Oct 2021 17:59:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5DF6F610FC for ; Thu, 28 Oct 2021 17:59:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231555AbhJ1SCT (ORCPT ); Thu, 28 Oct 2021 14:02:19 -0400 Received: from mail-bn8nam11on2086.outbound.protection.outlook.com ([40.107.236.86]:21504 "EHLO NAM11-BN8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231558AbhJ1SBL (ORCPT ); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:38.8551 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 746f8570-7b46-4590-5593-08d99a3c9223 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT037.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3260 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move code to find the shift and mask values used in die and socket interleaving into separate helper functions. These will be expanded for future DF versions. Make the die_id_mask and socket_id_mask values u16 type to accommodate larger bitfields in future DF versions. Also, move reading of the System Fabric ID Mask register into get_masks(). This will be expanded for future DF versions. Call get_masks() early since future DF versions may need these values early. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-27-yazen.ghannam@amd.com v2->v3: * Was patch 26 in v2. * Remove early code related to "df_ops". v1->v2: * Moved from arch/x86 to EDAC. * Added functions to data_fabric_ops. drivers/edac/amd64_edac.c | 57 ++++++++++++++++++++++++++++++--------- 1 file changed, 44 insertions(+), 13 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 5aae735f1389..9312784b2b0f 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1064,7 +1064,10 @@ struct addr_ctx { u32 reg_dram_offset; u32 reg_base_addr; u32 reg_limit_addr; + u32 reg_fab_id_mask0; u16 cs_fabric_id; + u16 die_id_mask; + u16 socket_id_mask; u16 nid; u8 inst_id; u8 map_num; @@ -1080,8 +1083,11 @@ struct addr_ctx { struct data_fabric_ops { u64 (*get_hi_addr_offset) (struct addr_ctx *ctx); + u8 (*get_die_id_shift) (struct addr_ctx *ctx); + u8 (*get_socket_id_shift) (struct addr_ctx *ctx); int (*get_intlv_mode) (struct addr_ctx *ctx); int (*get_cs_fabric_id) (struct addr_ctx *ctx); + int (*get_masks) (struct addr_ctx *ctx); void (*get_intlv_num_dies) (struct addr_ctx *ctx); void (*get_intlv_num_sockets) (struct addr_ctx *ctx); }; @@ -1176,12 +1182,37 @@ static int get_cs_fabric_id_df2(struct addr_ctx *ctx) return 0; } +static int get_masks_df2(struct addr_ctx *ctx) +{ + /* Read D18F1x208 (SystemFabricIdMask). */ + if (df_indirect_read_broadcast(ctx->nid, 1, 0x208, &ctx->reg_fab_id_mask0)) + return -EINVAL; + + ctx->die_id_mask = (ctx->reg_fab_id_mask0 >> 8) & 0xFF; + ctx->socket_id_mask = (ctx->reg_fab_id_mask0 >> 16) & 0xFF; + + return 0; +} + +static u8 get_die_id_shift_df2(struct addr_ctx *ctx) +{ + return (ctx->reg_fab_id_mask0 >> 24) & 0xF; +} + +static u8 get_socket_id_shift_df2(struct addr_ctx *ctx) +{ + return (ctx->reg_fab_id_mask0 >> 28) & 0xF; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = get_hi_addr_offset_df2, .get_intlv_mode = get_intlv_mode_df2, .get_intlv_num_dies = get_intlv_num_dies_df2, .get_intlv_num_sockets = get_intlv_num_sockets_df2, .get_cs_fabric_id = get_cs_fabric_id_df2, + .get_masks = get_masks_df2, + .get_die_id_shift = get_die_id_shift_df2, + .get_socket_id_shift = get_socket_id_shift_df2, }; struct data_fabric_ops *df_ops; @@ -1270,7 +1301,6 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) static int calculate_cs_id(struct addr_ctx *ctx) { - u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; u8 die_id_bit = 0, sock_id_bit, cs_mask = 0; /* If interleaved over more than 1 channel: */ @@ -1280,28 +1310,26 @@ static int calculate_cs_id(struct addr_ctx *ctx) ctx->cs_id = ctx->cs_fabric_id & cs_mask; } - sock_id_bit = die_id_bit; + /* Return early if no die interleaving and no socket interleaving. */ + if (!(ctx->intlv_num_dies || ctx->intlv_num_sockets)) + return 0; - /* Read D18F1x208 (SystemFabricIdMask). */ - if (ctx->intlv_num_dies || ctx->intlv_num_sockets) - if (df_indirect_read_broadcast(ctx->nid, 1, 0x208, &ctx->tmp)) - return -EINVAL; + sock_id_bit = die_id_bit; /* If interleaved over more than 1 die: */ if (ctx->intlv_num_dies) { - sock_id_bit = die_id_bit + ctx->intlv_num_dies; - die_id_shift = (ctx->tmp >> 24) & 0xF; - die_id_mask = (ctx->tmp >> 8) & 0xFF; + u8 die_id_shift = df_ops->get_die_id_shift(ctx); - ctx->cs_id |= ((ctx->cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; + sock_id_bit = die_id_bit + ctx->intlv_num_dies; + ctx->cs_id |= ((ctx->cs_fabric_id & ctx->die_id_mask) + >> die_id_shift) << die_id_bit; } /* If interleaved over more than 1 socket: */ if (ctx->intlv_num_sockets) { - socket_id_shift = (ctx->tmp >> 28) & 0xF; - socket_id_mask = (ctx->tmp >> 16) & 0xFF; + u8 socket_id_shift = df_ops->get_socket_id_shift(ctx); - ctx->cs_id |= ((ctx->cs_fabric_id & socket_id_mask) + ctx->cs_id |= ((ctx->cs_fabric_id & ctx->socket_id_mask) >> socket_id_shift) << sock_id_bit; } @@ -1380,6 +1408,9 @@ static int umc_normaddr_to_sysaddr(u64 *addr, u16 nid, u8 df_inst_id) ctx.nid = nid; ctx.inst_id = df_inst_id; + if (df_ops->get_masks(&ctx)) + return -EINVAL; + if (df_ops->get_cs_fabric_id(&ctx)) return -EINVAL; From patchwork Thu Oct 28 17:57:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E2C8C433F5 for ; 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dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT037.mail.protection.outlook.com (10.13.174.91) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Thu, 28 Oct 2021 17:58:40 +0000 Received: from yaz-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Thu, 28 Oct 2021 12:58:38 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , Yazen Ghannam Subject: [PATCH v3 26/33] EDAC/amd64: Update CS ID calculation to match reference code Date: Thu, 28 Oct 2021 17:57:21 +0000 Message-ID: <20211028175728.121452-27-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211028175728.121452-1-yazen.ghannam@amd.com> References: <20211028175728.121452-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 931eee8f-4f43-4494-8d7f-08d99a3c934c X-MS-TrafficTypeDiagnostic: DM4PR12MB5360: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:40.8029 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 931eee8f-4f43-4494-8d7f-08d99a3c934c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT037.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5360 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Redo the current CS ID calculations to match the reference code. Helper functions are introduced that will be expanded for future DF versions. Use u16 type for dst_fabric_id and component_id_mask values to accommodate larger bitfields in future DF versions. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-28-yazen.ghannam@amd.com v2->v3: * Was patch 27 in v2. v1->v2: * Moved from arch/x86 to EDAC. * Added functions to data_fabric_ops. drivers/edac/amd64_edac.c | 52 ++++++++++++++++++++++++++------------- 1 file changed, 35 insertions(+), 17 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 9312784b2b0f..9c74813c4128 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1083,6 +1083,8 @@ struct addr_ctx { struct data_fabric_ops { u64 (*get_hi_addr_offset) (struct addr_ctx *ctx); + u16 (*get_dst_fabric_id) (struct addr_ctx *ctx); + u16 (*get_component_id_mask) (struct addr_ctx *ctx); u8 (*get_die_id_shift) (struct addr_ctx *ctx); u8 (*get_socket_id_shift) (struct addr_ctx *ctx); int (*get_intlv_mode) (struct addr_ctx *ctx); @@ -1204,6 +1206,16 @@ static u8 get_socket_id_shift_df2(struct addr_ctx *ctx) return (ctx->reg_fab_id_mask0 >> 28) & 0xF; } +static u16 get_dst_fabric_id_df2(struct addr_ctx *ctx) +{ + return ctx->reg_limit_addr & 0xFF; +} + +static u16 get_component_id_mask_df2(struct addr_ctx *ctx) +{ + return (~(ctx->socket_id_mask | ctx->die_id_mask)) & 0xFF; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = get_hi_addr_offset_df2, .get_intlv_mode = get_intlv_mode_df2, @@ -1213,6 +1225,8 @@ struct data_fabric_ops df2_ops = { .get_masks = get_masks_df2, .get_die_id_shift = get_die_id_shift_df2, .get_socket_id_shift = get_socket_id_shift_df2, + .get_dst_fabric_id = get_dst_fabric_id_df2, + .get_component_id_mask = get_component_id_mask_df2, }; struct data_fabric_ops *df_ops; @@ -1299,38 +1313,42 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) } } -static int calculate_cs_id(struct addr_ctx *ctx) +static u8 calc_level_bits(u8 id, u8 level_mask, u8 shift, u8 mask, u8 num_bits) { - u8 die_id_bit = 0, sock_id_bit, cs_mask = 0; + return (((id & level_mask) >> shift) & mask) << num_bits; +} - /* If interleaved over more than 1 channel: */ - if (ctx->intlv_num_chan) { - die_id_bit = ctx->intlv_num_chan; - cs_mask = (1 << die_id_bit) - 1; - ctx->cs_id = ctx->cs_fabric_id & cs_mask; - } +static int calculate_cs_id(struct addr_ctx *ctx) +{ + u16 dst_fabric_id = df_ops->get_dst_fabric_id(ctx); + u16 mask, num_intlv_bits = ctx->intlv_num_chan; - /* Return early if no die interleaving and no socket interleaving. */ - if (!(ctx->intlv_num_dies || ctx->intlv_num_sockets)) - return 0; + mask = df_ops->get_component_id_mask(ctx); + ctx->cs_id = (ctx->cs_fabric_id & mask) - (dst_fabric_id & mask); - sock_id_bit = die_id_bit; + mask = (1 << num_intlv_bits) - 1; + ctx->cs_id &= mask; /* If interleaved over more than 1 die: */ if (ctx->intlv_num_dies) { u8 die_id_shift = df_ops->get_die_id_shift(ctx); - sock_id_bit = die_id_bit + ctx->intlv_num_dies; - ctx->cs_id |= ((ctx->cs_fabric_id & ctx->die_id_mask) - >> die_id_shift) << die_id_bit; + mask = (1 << ctx->intlv_num_dies) - 1; + + ctx->cs_id |= calc_level_bits(ctx->cs_fabric_id, ctx->die_id_mask, + die_id_shift, mask, num_intlv_bits); + + num_intlv_bits += ctx->intlv_num_dies; } /* If interleaved over more than 1 socket: */ if (ctx->intlv_num_sockets) { u8 socket_id_shift = df_ops->get_socket_id_shift(ctx); - ctx->cs_id |= ((ctx->cs_fabric_id & ctx->socket_id_mask) - >> socket_id_shift) << sock_id_bit; + mask = (1 << ctx->intlv_num_sockets) - 1; + + ctx->cs_id |= calc_level_bits(ctx->cs_fabric_id, ctx->socket_id_mask, + socket_id_shift, mask, num_intlv_bits); } return 0; From patchwork Thu Oct 28 17:57:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590739 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC6FAC433FE for ; Thu, 28 Oct 2021 17:59:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BB07E610E7 for ; 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Thu, 28 Oct 2021 17:58:41 +0000 Received: from yaz-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Thu, 28 Oct 2021 12:58:40 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , Yazen Ghannam Subject: [PATCH v3 27/33] EDAC/amd64: Match hash function to reference code Date: Thu, 28 Oct 2021 17:57:22 +0000 Message-ID: <20211028175728.121452-28-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211028175728.121452-1-yazen.ghannam@amd.com> References: <20211028175728.121452-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 131c8156-1806-4212-c934-08d99a3c93ce X-MS-TrafficTypeDiagnostic: DM6PR12MB4140: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:41.6574 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 131c8156-1806-4212-c934-08d99a3c93ce X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT037.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4140 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The reference code for DF2 hashing was changed to XOR the interleave address bit rather than the CS ID. Match that here. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-29-yazen.ghannam@amd.com v2->v3: * Was patch 28 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 9c74813c4128..c6fd813f596f 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1133,7 +1133,7 @@ static int dehash_addr_df2(struct addr_ctx *ctx) (ctx->ret_addr >> 18) ^ (ctx->ret_addr >> 21) ^ (ctx->ret_addr >> 30) ^ - ctx->cs_id; + (ctx->ret_addr >> ctx->intlv_addr_bit); hashed_bit &= BIT(0); From patchwork Thu Oct 28 17:57:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590743 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CB5CC433F5 for ; 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Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-30-yazen.ghannam@amd.com v2->v3: * Was patch 29 in v2. v1->v2: * New in v2. drivers/edac/amd64_edac.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index c6fd813f596f..cf5849a9a969 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1087,6 +1087,7 @@ struct data_fabric_ops { u16 (*get_component_id_mask) (struct addr_ctx *ctx); u8 (*get_die_id_shift) (struct addr_ctx *ctx); u8 (*get_socket_id_shift) (struct addr_ctx *ctx); + u8 (*get_intlv_addr_sel) (struct addr_ctx *ctx); int (*get_intlv_mode) (struct addr_ctx *ctx); int (*get_cs_fabric_id) (struct addr_ctx *ctx); int (*get_masks) (struct addr_ctx *ctx); @@ -1163,6 +1164,11 @@ static int get_intlv_mode_df2(struct addr_ctx *ctx) return 0; } +static u8 get_intlv_addr_sel_df2(struct addr_ctx *ctx) +{ + return (ctx->reg_base_addr >> 8) & 0x7; +} + static void get_intlv_num_dies_df2(struct addr_ctx *ctx) { ctx->intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; @@ -1219,6 +1225,7 @@ static u16 get_component_id_mask_df2(struct addr_ctx *ctx) struct data_fabric_ops df2_ops = { .get_hi_addr_offset = get_hi_addr_offset_df2, .get_intlv_mode = get_intlv_mode_df2, + .get_intlv_addr_sel = get_intlv_addr_sel_df2, .get_intlv_num_dies = get_intlv_num_dies_df2, .get_intlv_num_sockets = get_intlv_num_sockets_df2, .get_cs_fabric_id = get_cs_fabric_id_df2, @@ -1283,7 +1290,7 @@ static int get_dram_addr_map(struct addr_ctx *ctx) static int get_intlv_addr_bit(struct addr_ctx *ctx) { - u8 intlv_addr_sel = (ctx->reg_base_addr >> 8) & 0x7; + u8 intlv_addr_sel = df_ops->get_intlv_addr_sel(ctx); /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ if (intlv_addr_sel > 3) { From patchwork Thu Oct 28 17:57:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590745 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9C9EC433FE for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:44.4676 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ec82d90b-6fe0-4b06-bed1-08d99a3c957b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5057 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org DF3-based systems (Rome and later) support new interleaving modes and a number of bit fields have changed or moved entirely. Add support for these new modes and fields. Refactoring should be minimal due to earlier changes, and most updates will be additions. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-31-yazen.ghannam@amd.com v2->v3: * Was patch 30 in v2. * Drop "df_regs" use. * Set "df_ops" during module init. v1->v2: * Moved from arch/x86 to EDAC. * Use function pointers as needed. drivers/edac/amd64_edac.c | 187 +++++++++++++++++++++++++++++++++++++- 1 file changed, 185 insertions(+), 2 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index cf5849a9a969..c97b336361bc 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1053,6 +1053,11 @@ static int df_indirect_read_broadcast(u16 node, u8 func, u16 reg, u32 *lo) enum intlv_modes { NONE = 0x00, NOHASH_2CH = 0x01, + NOHASH_4CH = 0x03, + NOHASH_8CH = 0x05, + HASH_COD4_2CH = 0x0C, + HASH_COD2_4CH = 0x0D, + HASH_COD1_8CH = 0x0E, DF2_HASH_2CH = 0x21, }; @@ -1065,6 +1070,7 @@ struct addr_ctx { u32 reg_base_addr; u32 reg_limit_addr; u32 reg_fab_id_mask0; + u32 reg_fab_id_mask1; u16 cs_fabric_id; u16 die_id_mask; u16 socket_id_mask; @@ -1076,6 +1082,7 @@ struct addr_ctx { u8 intlv_num_dies; u8 intlv_num_sockets; u8 cs_id; + u8 node_id_shift; int (*dehash_addr)(struct addr_ctx *ctx); void (*make_space_for_cs_id)(struct addr_ctx *ctx); void (*insert_cs_id)(struct addr_ctx *ctx); @@ -1236,6 +1243,168 @@ struct data_fabric_ops df2_ops = { .get_component_id_mask = get_component_id_mask_df2, }; +static u64 get_hi_addr_offset_df3(struct addr_ctx *ctx) +{ + return (ctx->reg_dram_offset & GENMASK_ULL(31, 12)) << 16; +} + +static void make_space_for_cs_id_cod_hash(struct addr_ctx *ctx) +{ + u8 num_intlv_bits = ctx->intlv_num_chan; + + num_intlv_bits += ctx->intlv_num_sockets; + expand_bits(ctx->intlv_addr_bit, 1, &ctx->ret_addr); + if (num_intlv_bits > 1) + expand_bits(12, num_intlv_bits - 1, &ctx->ret_addr); +} + +static void insert_cs_id_cod_hash(struct addr_ctx *ctx) +{ + ctx->ret_addr |= ((ctx->cs_id & 0x1) << ctx->intlv_addr_bit); + ctx->ret_addr |= ((ctx->cs_id & 0xE) << 11); +} + +static int dehash_addr_df3(struct addr_ctx *ctx) +{ + u8 hashed_bit, intlv_ctl_64k, intlv_ctl_2M, intlv_ctl_1G; + + /* Read D18F0x3F8 (DfGlobalCtrl). */ + if (df_indirect_read_broadcast(0, 0, 0x3F8, &ctx->tmp)) + return -EINVAL; + + intlv_ctl_64k = !!((ctx->tmp >> 20) & 0x1); + intlv_ctl_2M = !!((ctx->tmp >> 21) & 0x1); + intlv_ctl_1G = !!((ctx->tmp >> 22) & 0x1); + + hashed_bit = (ctx->ret_addr >> 14) ^ + ((ctx->ret_addr >> 18) & intlv_ctl_64k) ^ + ((ctx->ret_addr >> 23) & intlv_ctl_2M) ^ + ((ctx->ret_addr >> 32) & intlv_ctl_1G) ^ + (ctx->ret_addr >> ctx->intlv_addr_bit); + + hashed_bit &= BIT(0); + + if (hashed_bit != ((ctx->ret_addr >> ctx->intlv_addr_bit) & BIT(0))) + ctx->ret_addr ^= BIT(ctx->intlv_addr_bit); + + if (ctx->intlv_mode != HASH_COD2_4CH && + ctx->intlv_mode != HASH_COD1_8CH) + return 0; + + hashed_bit = (ctx->ret_addr >> 12) ^ + ((ctx->ret_addr >> 16) & intlv_ctl_64k) ^ + ((ctx->ret_addr >> 21) & intlv_ctl_2M) ^ + ((ctx->ret_addr >> 30) & intlv_ctl_1G); + + hashed_bit &= BIT(0); + + if (hashed_bit != ((ctx->ret_addr >> 12) & BIT(0))) + ctx->ret_addr ^= BIT(12); + + if (ctx->intlv_mode != HASH_COD1_8CH) + return 0; + + hashed_bit = (ctx->ret_addr >> 13) ^ + ((ctx->ret_addr >> 17) & intlv_ctl_64k) ^ + ((ctx->ret_addr >> 22) & intlv_ctl_2M) ^ + ((ctx->ret_addr >> 31) & intlv_ctl_1G); + + hashed_bit &= BIT(0); + + if (hashed_bit != ((ctx->ret_addr >> 13) & BIT(0))) + ctx->ret_addr ^= BIT(13); + + return 0; +} + +static int get_intlv_mode_df3(struct addr_ctx *ctx) +{ + ctx->intlv_mode = (ctx->reg_base_addr >> 2) & 0xF; + + if (ctx->intlv_mode == HASH_COD4_2CH || + ctx->intlv_mode == HASH_COD2_4CH || + ctx->intlv_mode == HASH_COD1_8CH) { + ctx->make_space_for_cs_id = make_space_for_cs_id_cod_hash; + ctx->insert_cs_id = insert_cs_id_cod_hash; + ctx->dehash_addr = dehash_addr_df3; + } else { + ctx->make_space_for_cs_id = make_space_for_cs_id_simple; + ctx->insert_cs_id = insert_cs_id_simple; + } + + return 0; +} + +static u8 get_intlv_addr_sel_df3(struct addr_ctx *ctx) +{ + return (ctx->reg_base_addr >> 9) & 0x7; +} + +static void get_intlv_num_dies_df3(struct addr_ctx *ctx) +{ + ctx->intlv_num_dies = (ctx->reg_base_addr >> 6) & 0x3; +} + +static void get_intlv_num_sockets_df3(struct addr_ctx *ctx) +{ + ctx->intlv_num_sockets = (ctx->reg_base_addr >> 8) & 0x1; +} + +static u8 get_die_id_shift_df3(struct addr_ctx *ctx) +{ + return ctx->node_id_shift; +} + +static u8 get_socket_id_shift_df3(struct addr_ctx *ctx) +{ + return ((ctx->reg_fab_id_mask1 >> 8) & 0x3) + ctx->node_id_shift; +} + +static int get_masks_df3(struct addr_ctx *ctx) +{ + /* Read D18F1x208 (SystemFabricIdMask). */ + if (df_indirect_read_broadcast(ctx->nid, 1, 0x208, &ctx->reg_fab_id_mask0)) + return -EINVAL; + + /* Read D18F1x20C (SystemFabricIdMask1) */ + if (df_indirect_read_broadcast(0, 1, 0x20C, &ctx->reg_fab_id_mask1)) + return -EINVAL; + + ctx->node_id_shift = ctx->reg_fab_id_mask1 & 0xF; + + ctx->die_id_mask = (ctx->reg_fab_id_mask1 >> 16) & 0x7; + ctx->die_id_mask <<= ctx->node_id_shift; + + ctx->socket_id_mask = (ctx->reg_fab_id_mask1 >> 24) & 0x7; + ctx->socket_id_mask <<= ctx->node_id_shift; + + return 0; +} + +static u16 get_dst_fabric_id_df3(struct addr_ctx *ctx) +{ + return ctx->reg_limit_addr & 0x3FF; +} + +static u16 get_component_id_mask_df3(struct addr_ctx *ctx) +{ + return ctx->reg_fab_id_mask0 & 0x3FF; +} + +struct data_fabric_ops df3_ops = { + .get_hi_addr_offset = get_hi_addr_offset_df3, + .get_intlv_mode = get_intlv_mode_df3, + .get_intlv_addr_sel = get_intlv_addr_sel_df3, + .get_intlv_num_dies = get_intlv_num_dies_df3, + .get_intlv_num_sockets = get_intlv_num_sockets_df3, + .get_cs_fabric_id = get_cs_fabric_id_df2, + .get_masks = get_masks_df3, + .get_die_id_shift = get_die_id_shift_df3, + .get_socket_id_shift = get_socket_id_shift_df3, + .get_dst_fabric_id = get_dst_fabric_id_df3, + .get_component_id_mask = get_component_id_mask_df3, +}; + struct data_fabric_ops *df_ops; static int get_dram_offset_reg(struct addr_ctx *ctx) @@ -1292,8 +1461,8 @@ static int get_intlv_addr_bit(struct addr_ctx *ctx) { u8 intlv_addr_sel = df_ops->get_intlv_addr_sel(ctx); - /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ - if (intlv_addr_sel > 3) { + /* {0, 1, 2, 3, 4} map to address bits {8, 9, 10, 11, 12} respectively */ + if (intlv_addr_sel > 4) { pr_debug("Invalid interleave address select %d.\n", intlv_addr_sel); return -EINVAL; } @@ -1311,9 +1480,18 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) ctx->intlv_num_chan = 0; break; case NOHASH_2CH: + case HASH_COD4_2CH: case DF2_HASH_2CH: ctx->intlv_num_chan = 1; break; + case NOHASH_4CH: + case HASH_COD2_4CH: + ctx->intlv_num_chan = 2; + break; + case NOHASH_8CH: + case HASH_COD1_8CH: + ctx->intlv_num_chan = 3; + break; default: /* Valid interleaving modes where checked earlier. */ break; @@ -4398,14 +4576,17 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) } else if (pvt->model >= 0x30 && pvt->model <= 0x3f) { pvt->fam_type = &family_types[F17_M30H_CPUS]; pvt->ops = &family_types[F17_M30H_CPUS].ops; + df_ops = &df3_ops; break; } else if (pvt->model >= 0x60 && pvt->model <= 0x6f) { pvt->fam_type = &family_types[F17_M60H_CPUS]; pvt->ops = &family_types[F17_M60H_CPUS].ops; + df_ops = &df3_ops; break; } else if (pvt->model >= 0x70 && pvt->model <= 0x7f) { pvt->fam_type = &family_types[F17_M70H_CPUS]; pvt->ops = &family_types[F17_M70H_CPUS].ops; + df_ops = &df3_ops; break; } fallthrough; @@ -4423,6 +4604,7 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) pvt->fam_type = &family_types[F17_M70H_CPUS]; pvt->ops = &family_types[F17_M70H_CPUS].ops; pvt->fam_type->ctl_name = "F19h_M20h"; + df_ops = &df3_ops; break; } else if (pvt->model >= 0x30 && pvt->model <= 0x3f) { if (pvt->mc_node_id >= amd_cpu_node_count()) { @@ -4438,6 +4620,7 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) pvt->fam_type = &family_types[F19_CPUS]; pvt->ops = &family_types[F19_CPUS].ops; family_types[F19_CPUS].ctl_name = "F19h"; + df_ops = &df3_ops; } break; From patchwork Thu Oct 28 17:57:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590747 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AB3BC433EF for ; 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dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT063.mail.protection.outlook.com (10.13.175.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Thu, 28 Oct 2021 17:58:46 +0000 Received: from yaz-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Thu, 28 Oct 2021 12:58:44 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , Yazen Ghannam Subject: [PATCH v3 30/33] EDAC/amd64: Add glossary of acronyms for address translation Date: Thu, 28 Oct 2021 17:57:25 +0000 Message-ID: <20211028175728.121452-31-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211028175728.121452-1-yazen.ghannam@amd.com> References: <20211028175728.121452-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2a74a867-cd14-4c3b-fb1b-08d99a3c96d4 X-MS-TrafficTypeDiagnostic: DM6PR12MB4895: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5516; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:46.7312 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2a74a867-cd14-4c3b-fb1b-08d99a3c96d4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4895 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Add a short glossary of the acronyms used for address translation. Some terms may be seen with other AMD code, and some are only used within the translation code. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210623192002.3671647-32-yazen.ghannam@amd.com v2->v3: * Was patch 31 in v2. v1->v2: * New in v2. drivers/edac/amd64_edac.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index c97b336361bc..5dacd7e03202 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -986,6 +986,15 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) return csrow; } +/* + * Glossary of acronyms used in address translation for Zen-based systems + * + * COD = Cluster-on-Die + * CS = Coherent Slave + * DF = Data Fabric + * UMC = Unified Memory Controller + */ + /* Protect the PCI config register pairs used for DF indirect access. */ static DEFINE_MUTEX(df_indirect_mutex); From patchwork Thu Oct 28 17:57:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590749 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 031C9C4332F for ; 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dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT063.mail.protection.outlook.com (10.13.175.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Thu, 28 Oct 2021 17:58:47 +0000 Received: from yaz-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Thu, 28 Oct 2021 12:58:46 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , Yazen Ghannam Subject: [PATCH v3 31/33] EDAC/amd64: Add check for when to add DRAM base and hole Date: Thu, 28 Oct 2021 17:57:26 +0000 Message-ID: <20211028175728.121452-32-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211028175728.121452-1-yazen.ghannam@amd.com> References: <20211028175728.121452-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4191d8a9-4a9c-46f2-d0c7-08d99a3c977b X-MS-TrafficTypeDiagnostic: BL1PR12MB5030: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:47.8246 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4191d8a9-4a9c-46f2-d0c7-08d99a3c977b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5030 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Some DF versions and interleaving modes require the DRAM base address and hole adjustments to be done before accounting for hashing. Others require this to be done after. Add a check for this behavior. Save a boolean in the ctx struct which can be appropriately set based on DF version or interleaving mode. Signed-off-by: Yazen Ghannam --- v2->v3: * New in v3. drivers/edac/amd64_edac.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 5dacd7e03202..07009901a283 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1092,6 +1092,7 @@ struct addr_ctx { u8 intlv_num_sockets; u8 cs_id; u8 node_id_shift; + bool late_hole_remove; int (*dehash_addr)(struct addr_ctx *ctx); void (*make_space_for_cs_id)(struct addr_ctx *ctx); void (*insert_cs_id)(struct addr_ctx *ctx); @@ -1638,12 +1639,15 @@ static int umc_normaddr_to_sysaddr(u64 *addr, u16 nid, u8 df_inst_id) if (denormalize_addr(&ctx)) return -EINVAL; - if (add_base_and_hole(&ctx)) + if (!ctx.late_hole_remove && add_base_and_hole(&ctx)) return -EINVAL; if (ctx.dehash_addr && ctx.dehash_addr(&ctx)) return -EINVAL; + if (ctx.late_hole_remove && add_base_and_hole(&ctx)) + return -EINVAL; + if (addr_over_limit(&ctx)) return -EINVAL; From patchwork Thu Oct 28 17:57:27 2021 Content-Type: text/plain; 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This value is needed by future DF versions. Signed-off-by: Yazen Ghannam --- v2->v3: * New in v3. drivers/edac/amd64_edac.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 07009901a283..bc1aa6292408 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1092,6 +1092,7 @@ struct addr_ctx { u8 intlv_num_sockets; u8 cs_id; u8 node_id_shift; + u8 num_blk_instances; bool late_hole_remove; int (*dehash_addr)(struct addr_ctx *ctx); void (*make_space_for_cs_id)(struct addr_ctx *ctx); @@ -1417,6 +1418,17 @@ struct data_fabric_ops df3_ops = { struct data_fabric_ops *df_ops; +static int get_blk_inst_cnt(struct addr_ctx *ctx) +{ + /* Read D18F0x40 (FabricBlockInstanceCount). */ + if (df_indirect_read_broadcast(0, 0, 0x40, &ctx->tmp)) + return -EINVAL; + + ctx->num_blk_instances = ctx->tmp & 0xFF; + + return 0; +} + static int get_dram_offset_reg(struct addr_ctx *ctx) { /* Read D18F0x1B4 (DramOffset) */ @@ -1621,6 +1633,9 @@ static int umc_normaddr_to_sysaddr(u64 *addr, u16 nid, u8 df_inst_id) ctx.nid = nid; ctx.inst_id = df_inst_id; + if (get_blk_inst_cnt(&ctx)) + return -EINVAL; + if (df_ops->get_masks(&ctx)) return -EINVAL; From patchwork Thu Oct 28 17:57:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12590753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C8CCC433F5 for ; Thu, 28 Oct 2021 18:00:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4AD1C610FD for ; Thu, 28 Oct 2021 18:00:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231154AbhJ1SCr (ORCPT ); Thu, 28 Oct 2021 14:02:47 -0400 Received: from mail-dm6nam12on2069.outbound.protection.outlook.com ([40.107.243.69]:57605 "EHLO NAM12-DM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231627AbhJ1SBW (ORCPT ); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:50.8123 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4692cb02-6ac7-4076-257f-08d99a3c9946 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4471 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add support for address translation on Data Fabric version 3.5. Add new data fabric ops and interleaving modes. Also, adjust how the DRAM address maps are found early in the translation for certain cases. Signed-off-by: Muralidhara M K Co-developed-by: Yazen Ghannam Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210630152828.162659-7-nchatrad@amd.com v2->v3: * New in v3. Original version at link above. * Squashed the following into this patch: https://lkml.kernel.org/r/20210630152828.162659-8-nchatrad@amd.com * Dropped "df_regs" use. * Set "df_ops" during module init. * Dropped hard-coded Node ID values. drivers/edac/amd64_edac.c | 224 +++++++++++++++++++++++++++++++++++++- 1 file changed, 220 insertions(+), 4 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index bc1aa6292408..9728571f9d67 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -989,6 +989,7 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) /* * Glossary of acronyms used in address translation for Zen-based systems * + * CCM = CPU Core Coherent Module * COD = Cluster-on-Die * CS = Coherent Slave * DF = Data Fabric @@ -1064,9 +1065,14 @@ enum intlv_modes { NOHASH_2CH = 0x01, NOHASH_4CH = 0x03, NOHASH_8CH = 0x05, + NOHASH_16CH = 0x07, + NOHASH_32CH = 0x08, HASH_COD4_2CH = 0x0C, HASH_COD2_4CH = 0x0D, HASH_COD1_8CH = 0x0E, + HASH_8CH = 0x1C, + HASH_16CH = 0x1D, + HASH_32CH = 0x1E, DF2_HASH_2CH = 0x21, }; @@ -1080,6 +1086,7 @@ struct addr_ctx { u32 reg_limit_addr; u32 reg_fab_id_mask0; u32 reg_fab_id_mask1; + u32 reg_fab_id_mask2; u16 cs_fabric_id; u16 die_id_mask; u16 socket_id_mask; @@ -1416,6 +1423,157 @@ struct data_fabric_ops df3_ops = { .get_component_id_mask = get_component_id_mask_df3, }; +static int dehash_addr_df35(struct addr_ctx *ctx) +{ + u8 hashed_bit, intlv_ctl_64k, intlv_ctl_2M, intlv_ctl_1G; + u8 num_intlv_bits = ctx->intlv_num_chan; + u32 i; + + /* Read D18F0x3F8 (DfGlobalCtrl). */ + if (df_indirect_read_broadcast(0, 0, 0x3F8, &ctx->tmp)) + return -EINVAL; + + intlv_ctl_64k = !!((ctx->tmp >> 20) & 0x1); + intlv_ctl_2M = !!((ctx->tmp >> 21) & 0x1); + intlv_ctl_1G = !!((ctx->tmp >> 22) & 0x1); + + /* + * CSSelect[0] = XOR of addr{8, 16, 21, 30}; + * CSSelect[1] = XOR of addr{9, 17, 22, 31}; + * CSSelect[2] = XOR of addr{10, 18, 23, 32}; + * CSSelect[3] = XOR of addr{11, 19, 24, 33}; - 16 and 32 channel only + * CSSelect[4] = XOR of addr{12, 20, 25, 34}; - 32 channel only + */ + for (i = 0; i < num_intlv_bits; i++) { + hashed_bit = ((ctx->ret_addr >> (8 + i)) ^ + ((ctx->ret_addr >> (16 + i)) & intlv_ctl_64k) ^ + ((ctx->ret_addr >> (21 + i)) & intlv_ctl_2M) ^ + ((ctx->ret_addr >> (30 + i)) & intlv_ctl_1G)); + + hashed_bit &= BIT(0); + if (hashed_bit != ((ctx->ret_addr >> (8 + i)) & BIT(0))) + ctx->ret_addr ^= BIT(8 + i); + } + + return 0; +} + +static int get_intlv_mode_df35(struct addr_ctx *ctx) +{ + ctx->intlv_mode = (ctx->reg_base_addr >> 2) & 0x1F; + + if (ctx->intlv_mode == HASH_COD4_2CH || + ctx->intlv_mode == HASH_COD2_4CH || + ctx->intlv_mode == HASH_COD1_8CH) { + ctx->make_space_for_cs_id = make_space_for_cs_id_cod_hash; + ctx->insert_cs_id = insert_cs_id_cod_hash; + ctx->dehash_addr = dehash_addr_df3; + } else { + ctx->make_space_for_cs_id = make_space_for_cs_id_simple; + ctx->insert_cs_id = insert_cs_id_simple; + ctx->dehash_addr = dehash_addr_df35; + } + + return 0; +} + +static void get_intlv_num_dies_df35(struct addr_ctx *ctx) +{ + ctx->intlv_num_dies = (ctx->reg_base_addr >> 7) & 0x1; +} + +static u8 get_die_id_shift_df35(struct addr_ctx *ctx) +{ + return ctx->node_id_shift; +} + +static u8 get_socket_id_shift_df35(struct addr_ctx *ctx) +{ + return (ctx->reg_fab_id_mask1 >> 8) & 0xF; +} + +static int get_masks_df35(struct addr_ctx *ctx) +{ + /* Read D18F1x150 (SystemFabricIdMask0). */ + if (df_indirect_read_broadcast(0, 1, 0x150, &ctx->reg_fab_id_mask0)) + return -EINVAL; + + /* Read D18F1x154 (SystemFabricIdMask1). */ + if (df_indirect_read_broadcast(0, 1, 0x154, &ctx->reg_fab_id_mask1)) + return -EINVAL; + + /* Read D18F1x158 (SystemFabricIdMask2). */ + if (df_indirect_read_broadcast(0, 1, 0x158, &ctx->reg_fab_id_mask2)) + return -EINVAL; + + ctx->node_id_shift = ctx->reg_fab_id_mask1 & 0xF; + + ctx->die_id_mask = ctx->reg_fab_id_mask2 & 0xFFFF; + + ctx->socket_id_mask = (ctx->reg_fab_id_mask2 >> 16) & 0xFFFF; + + return 0; +} + +static u16 get_dst_fabric_id_df35(struct addr_ctx *ctx) +{ + return ctx->reg_limit_addr & 0xFFF; +} + +/* Aldebaran nodes have an arbitrary UMC to CS mapping based on physical layout. */ +u8 umc_to_cs_mapping_aldebaran[] = { 28, 20, 24, 16, 12, 4, 8, 0, + 6, 30, 2, 26, 22, 14, 18, 10, + 19, 11, 15, 7, 3, 27, 31, 23, + 9, 1, 5, 29, 25, 17, 21, 13}; + +int get_umc_to_cs_mapping(struct addr_ctx *ctx) +{ + if (ctx->inst_id >= sizeof(umc_to_cs_mapping_aldebaran)) + return -EINVAL; + + ctx->inst_id = umc_to_cs_mapping_aldebaran[ctx->inst_id]; + + return 0; +} + +static int get_cs_fabric_id_df35(struct addr_ctx *ctx) +{ + u16 nid = ctx->nid; + + /* Special handling for GPU nodes.*/ + if (nid >= amd_cpu_node_count()) { + if (get_umc_to_cs_mapping(ctx)) + return -EINVAL; + + /* Need to convert back to the hardware-provided Node ID. */ + nid -= amd_cpu_node_count(); + nid += amd_gpu_node_start_id(); + } + + ctx->cs_fabric_id = ctx->inst_id | (nid << ctx->node_id_shift); + + return 0; +} + +static u16 get_component_id_mask_df35(struct addr_ctx *ctx) +{ + return ctx->reg_fab_id_mask0 & 0xFFFF; +} + +struct data_fabric_ops df3point5_ops = { + .get_hi_addr_offset = get_hi_addr_offset_df3, + .get_intlv_mode = get_intlv_mode_df35, + .get_intlv_addr_sel = get_intlv_addr_sel_df3, + .get_intlv_num_dies = get_intlv_num_dies_df35, + .get_intlv_num_sockets = get_intlv_num_sockets_df3, + .get_masks = get_masks_df35, + .get_die_id_shift = get_die_id_shift_df35, + .get_socket_id_shift = get_socket_id_shift_df35, + .get_dst_fabric_id = get_dst_fabric_id_df35, + .get_cs_fabric_id = get_cs_fabric_id_df35, + .get_component_id_mask = get_component_id_mask_df35, +}; + struct data_fabric_ops *df_ops; static int get_blk_inst_cnt(struct addr_ctx *ctx) @@ -1512,8 +1670,17 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) break; case NOHASH_8CH: case HASH_COD1_8CH: + case HASH_8CH: ctx->intlv_num_chan = 3; break; + case NOHASH_16CH: + case HASH_16CH: + ctx->intlv_num_chan = 4; + break; + case NOHASH_32CH: + case HASH_32CH: + ctx->intlv_num_chan = 5; + break; default: /* Valid interleaving modes where checked earlier. */ break; @@ -1618,6 +1785,42 @@ static int addr_over_limit(struct addr_ctx *ctx) return 0; } +static int find_ccm_instance_id(struct addr_ctx *ctx) +{ + for (ctx->inst_id = 0; ctx->inst_id < ctx->num_blk_instances; ctx->inst_id++) { + /* Read D18F0x44 (FabricBlockInstanceInformation0). */ + if (df_indirect_read_instance(0, 0, 0x44, ctx->inst_id, &ctx->tmp)) + return -EINVAL; + + if (ctx->tmp == 0) + continue; + + if ((ctx->tmp & 0xF) == 0) + return 0; + } + + return -EINVAL; +} + +#define DF_NUM_DRAM_MAPS_AVAILABLE 16 +static int find_map_reg_by_dstfabricid(struct addr_ctx *ctx) +{ + u16 node_id_mask = (ctx->reg_fab_id_mask0 >> 16) & 0xFFFF; + u16 dst_fabric_id; + + for (ctx->map_num = 0; ctx->map_num < DF_NUM_DRAM_MAPS_AVAILABLE ; ctx->map_num++) { + if (get_dram_addr_map(ctx)) + continue; + + dst_fabric_id = df_ops->get_dst_fabric_id(ctx); + + if ((dst_fabric_id & node_id_mask) == (ctx->cs_fabric_id & node_id_mask)) + return 0; + } + + return -EINVAL; +} + static int umc_normaddr_to_sysaddr(u64 *addr, u16 nid, u8 df_inst_id) { struct addr_ctx ctx; @@ -1633,6 +1836,9 @@ static int umc_normaddr_to_sysaddr(u64 *addr, u16 nid, u8 df_inst_id) ctx.nid = nid; ctx.inst_id = df_inst_id; + if (df_ops == &df3point5_ops) + ctx.late_hole_remove = true; + if (get_blk_inst_cnt(&ctx)) return -EINVAL; @@ -1642,11 +1848,20 @@ static int umc_normaddr_to_sysaddr(u64 *addr, u16 nid, u8 df_inst_id) if (df_ops->get_cs_fabric_id(&ctx)) return -EINVAL; - if (remove_dram_offset(&ctx)) - return -EINVAL; + /* Special handling for GPU nodes.*/ + if (ctx.nid >= amd_cpu_node_count()) { + if (find_ccm_instance_id(&ctx)) + return -EINVAL; - if (get_dram_addr_map(&ctx)) - return -EINVAL; + if (find_map_reg_by_dstfabricid(&ctx)) + return -EINVAL; + } else { + if (remove_dram_offset(&ctx)) + return -EINVAL; + + if (get_dram_addr_map(&ctx)) + return -EINVAL; + } if (df_ops->get_intlv_mode(&ctx)) return -EINVAL; @@ -4644,6 +4859,7 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) pvt->ops = &family_types[F19_CPUS].ops; family_types[F19_CPUS].ctl_name = "F19h_M30h"; } + df_ops = &df3point5_ops; } else { pvt->fam_type = &family_types[F19_CPUS]; pvt->ops = &family_types[F19_CPUS].ops;