From patchwork Thu Oct 28 18:35:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 12590855 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA18BC43217 for ; Thu, 28 Oct 2021 18:35:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 93EFC61040 for ; Thu, 28 Oct 2021 18:35:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231178AbhJ1SiA (ORCPT ); Thu, 28 Oct 2021 14:38:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231211AbhJ1Sh7 (ORCPT ); Thu, 28 Oct 2021 14:37:59 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CCDB5C061767 for ; Thu, 28 Oct 2021 11:35:31 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id l2so12284285lji.6 for ; Thu, 28 Oct 2021 11:35:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0h9MI5+nWpL7nv3kn46aEjYMVGjl4934m5PO+DJKiLI=; b=MKEq0geXa1eT2tQFBS/WYl3gwCPfOmg2L0DmJjAS75wUxFQaLny2BqlgQqgc67JX8T 1eU7Wo7elUOYI5w08gD3ujyLzYlT74MOXokrkpIJa3HLZiW8cVqXWM5wNjU2lfLhkLoI TIKI3YVP4DAws7hoQGvLzFOJqLhnG+mGZKyrMxjOt2lddr1jFBEIhgnXREPdMIDT+T31 verhiIhT6LNatzJB3wZGR/qostXudLyIli6eDJiV0Fx6Q8yxhqKjjeDGQRt0C8169sdQ UbzsDpDwLlZt2GoI3GEuLPz4Tb+qDIrJsNkcK6Q0LHC8HEjEzaAXwPJrcC9w34NYfJhK 2U9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0h9MI5+nWpL7nv3kn46aEjYMVGjl4934m5PO+DJKiLI=; b=xykhaml0Q83FHiNcfwC8dMcgiWlAzsyiO6kvqByNXx3WtxgNa8Jfnq5C7ztdynDepv zP4gO1lnIR7ih3OFbc9C7gwwczXRA1iHtkHj82ZSvlgonf2RRpzZIHa1I66CoJJ892KS No7/91F0xlhfpWMwJf19avIWOjqSmQplsio69GYELV1Z4igBOplWEUuMk87TWCqS4CJE x78VUNoBUFDLo57wj8EM9fBGGhTG142pqAlesAfXuyRWdkPODb9nj7LyR+46E90WoMjT HVpmJEjBx1+jwj+xVMgdr7BZ4nWJhlx5vHrNtlZeJe0UxkhdrwbQuvSdcb9H+oMmLvjk TYXQ== X-Gm-Message-State: AOAM530mEBwUI00h69St6IH+2wNb1SMdrygh8BwW7/KquymLHDnl8zZz s6DVyUZP+JoG86xWwAL08D5Bpg== X-Google-Smtp-Source: ABdhPJwxy/T1TXHAOSTfUZChLQnwHDSBgFoC2mGqdGsqWUdVRmYvf9KqsTRArBLOPGpZRJYiCdK+lQ== X-Received: by 2002:a2e:a40f:: with SMTP id p15mr6597055ljn.497.1635446130085; Thu, 28 Oct 2021 11:35:30 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id r127sm389488lff.62.2021.10.28.11.35.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 11:35:29 -0700 (PDT) From: Sam Protsenko To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 1/7] dt-bindings: watchdog: Require samsung,syscon-phandle for Exynos7 Date: Thu, 28 Oct 2021 21:35:21 +0300 Message-Id: <20211028183527.3050-2-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211028183527.3050-1-semen.protsenko@linaro.org> References: <20211028183527.3050-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Exynos7 watchdog driver is clearly indicating that its dts node must define syscon phandle property. That was probably forgotten, so add it. Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml index 76cb9586ee00..93cd77a6e92c 100644 --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml @@ -39,8 +39,8 @@ properties: samsung,syscon-phandle: $ref: /schemas/types.yaml#/definitions/phandle description: - Phandle to the PMU system controller node (in case of Exynos5250 - and Exynos5420). + Phandle to the PMU system controller node (in case of Exynos5250, + Exynos5420 and Exynos7). required: - compatible @@ -58,6 +58,7 @@ allOf: enum: - samsung,exynos5250-wdt - samsung,exynos5420-wdt + - samsung,exynos7-wdt then: required: - samsung,syscon-phandle From patchwork Thu Oct 28 18:35:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 12590859 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B578C433F5 for ; Thu, 28 Oct 2021 18:35:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7FF5D61139 for ; Thu, 28 Oct 2021 18:35:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231237AbhJ1SiC (ORCPT ); Thu, 28 Oct 2021 14:38:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231224AbhJ1SiB (ORCPT ); Thu, 28 Oct 2021 14:38:01 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B266C061745 for ; Thu, 28 Oct 2021 11:35:33 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id s19so12231696ljj.11 for ; Thu, 28 Oct 2021 11:35:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qxGj8ruYQXbdMlsDQaWiFHYINmJfNHh4ixIh1XClyl0=; b=ckofLK7Sa+sucC0aMZYSqjyi1MWCkTqu39gaJTKlg3UW5Et83dm1pTloYpabd0qeuV ZJ+tqbCJu0vO2+Fw4Pkq7IkUzSiE8I/NxYRfzGC61o3MnnT6v3h4FKIQE6tYaBzdUP+p 4A6YFe4YwWDQmbGBb5cOE1+uUIo4wFmvRWLHq1ZfNEuwUDR5/a/SWSyO3CvKEUymFAA7 P1y6oYXgilnjfYt7HfIrbwv2tYvY3m4d5eIW+VRC1+N9OPZw3eVO76HYFfQi7bGaWKAG GfHt8GNfYj8N7AfOI4ZEsebO2ZvgJXHlQW2iuH9lDz1+cRflpxU0VMFhSrqG+9TecA0K yYXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qxGj8ruYQXbdMlsDQaWiFHYINmJfNHh4ixIh1XClyl0=; b=Wq7mrBkzTcR6LVG80RJnqmv0nCsYAZUHQsL53TUBCYuO85dyDODB1y+LgpRQiKMNk6 1AA6a6+vylbvvBzKhx5cI6kLcSpMvVyndJuKUvoypSEiqR9QtajjMVPxEPfdx3YpFkN7 jR0OlPiHyhdadq3YDTr872A2tVgvatox2qvWd7UmnDDZrFSModDJY4WZ5aIy6Wicl6ps ZmbYKxoofYBcdoio/6GVkDeorAlAPAxoS0RTrZKg95iI40sLuHzOmVUn4mIT92SHbXbh /Ipskcf6IAXPfGjqo3E13QDmyZNhqImhOdrUbPNokjtXtKNJU8OWlZCU0bIOSuZKj7Cl eVhw== X-Gm-Message-State: AOAM5333AvwLnINU8X2ReqloFsLzM8tXarOZot9zhIIguO/ecssYfBY0 iETwMuaBSUP1ojvXph20Sw3F3Q== X-Google-Smtp-Source: ABdhPJwWl2cWkn/oMEy+9pMPff1K5svaTl8d+C7T6biY14aKQY1iB58MomSenBJbmQsXLkO7Gv9ZfA== X-Received: by 2002:a2e:a58f:: with SMTP id m15mr6315368ljp.449.1635446131729; Thu, 28 Oct 2021 11:35:31 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id w40sm389589lfu.48.2021.10.28.11.35.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 11:35:31 -0700 (PDT) From: Sam Protsenko To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 2/7] dt-bindings: watchdog: Document Exynos850 watchdog bindings Date: Thu, 28 Oct 2021 21:35:22 +0300 Message-Id: <20211028183527.3050-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211028183527.3050-1-semen.protsenko@linaro.org> References: <20211028183527.3050-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Exynos850 SoC has two CPU clusters: - cluster 0: contains CPUs #0, #1, #2, #3 - cluster 1: contains CPUs #4, #5, #6, #7 Each cluster has its own dedicater watchdog timer. Those WDT instances are controlled using different bits in PMU registers, so there should be two different compatible strings (for each cluster), to tell the driver which bits to use for each WDT instance. Also on Exynos850 the peripheral clock and the source clock are two different clocks. Provide a way to specify two clocks in watchdog device tree node. Signed-off-by: Sam Protsenko --- .../devicetree/bindings/watchdog/samsung-wdt.yaml | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml index 93cd77a6e92c..19c7f7767559 100644 --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml @@ -22,16 +22,24 @@ properties: - samsung,exynos5250-wdt # for Exynos5250 - samsung,exynos5420-wdt # for Exynos5420 - samsung,exynos7-wdt # for Exynos7 + - samsung,exynos850-cl0-wdt # for Exynos850 (CPU cluster 0) + - samsung,exynos850-cl1-wdt # for Exynos850 (CPU cluster 1) reg: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + items: + - description: Peripheral clock used for register interface; if it's the + only clock, it's also a source clock + - description: Source clock (optional) clock-names: + minItems: 1 items: - const: watchdog + - const: watchdog_src interrupts: maxItems: 1 @@ -40,7 +48,7 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to the PMU system controller node (in case of Exynos5250, - Exynos5420 and Exynos7). + Exynos5420, Exynos7 and Exynos850). required: - compatible @@ -59,6 +67,8 @@ allOf: - samsung,exynos5250-wdt - samsung,exynos5420-wdt - samsung,exynos7-wdt + - samsung,exynos850-cl0-wdt + - samsung,exynos850-cl1-wdt then: required: - samsung,syscon-phandle From patchwork Thu Oct 28 18:35:23 2021 Content-Type: text/plain; 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Thu, 28 Oct 2021 11:35:33 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id f8sm390614lfu.5.2021.10.28.11.35.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 11:35:32 -0700 (PDT) From: Sam Protsenko To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 3/7] watchdog: s3c2410: Make reset disable optional Date: Thu, 28 Oct 2021 21:35:23 +0300 Message-Id: <20211028183527.3050-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211028183527.3050-1-semen.protsenko@linaro.org> References: <20211028183527.3050-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Not all SoCs have AUTOMATIC_WDT_RESET_DISABLE register, examples are Exynos850 and Exynos9. On such chips reset disable register shouldn't be accessed. Provide a way to avoid handling that register. This is done by introducing separate callbacks to driver data structure: one for reset disable register, and one for mask reset register. Now those callbacks can be checked and called only when those were set in driver data. This commit doesn't bring any functional change to existing devices, but merely provides an infrastructure for upcoming chips support. Signed-off-by: Sam Protsenko --- drivers/watchdog/s3c2410_wdt.c | 81 ++++++++++++++++++++++++---------- 1 file changed, 58 insertions(+), 23 deletions(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 2395f353e52d..7c163a257d3c 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -83,6 +83,8 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default 0)"); +struct s3c2410_wdt; + /** * struct s3c2410_wdt_variant - Per-variant config data * @@ -96,6 +98,11 @@ MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog * reset. * @quirks: A bitfield of quirks. + * @disable_auto_reset: If set, this function will be called to disable + * automatic setting the WDT as a reset reason in RST_STAT on CPU reset; uses + * disable_reg field. + * @mask_reset: If set, this function will be called to mask WDT reset request; + * uses mask_reset_reg and mask_bit fields. */ struct s3c2410_wdt_variant { @@ -105,6 +112,8 @@ struct s3c2410_wdt_variant { int rst_stat_reg; int rst_stat_bit; u32 quirks; + int (*disable_auto_reset)(struct s3c2410_wdt *wdt, bool mask); + int (*mask_reset)(struct s3c2410_wdt *wdt, bool mask); }; struct s3c2410_wdt { @@ -121,6 +130,9 @@ struct s3c2410_wdt { struct regmap *pmureg; }; +static int s3c2410wdt_disable_wdt_reset(struct s3c2410_wdt *wdt, bool mask); +static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask); + static const struct s3c2410_wdt_variant drv_data_s3c2410 = { .quirks = 0 }; @@ -138,6 +150,8 @@ static const struct s3c2410_wdt_variant drv_data_exynos5250 = { .rst_stat_bit = 20, .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \ | QUIRK_HAS_WTCLRINT_REG, + .disable_auto_reset = s3c2410wdt_disable_wdt_reset, + .mask_reset = s3c2410wdt_mask_wdt_reset, }; static const struct s3c2410_wdt_variant drv_data_exynos5420 = { @@ -148,6 +162,8 @@ static const struct s3c2410_wdt_variant drv_data_exynos5420 = { .rst_stat_bit = 9, .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \ | QUIRK_HAS_WTCLRINT_REG, + .disable_auto_reset = s3c2410wdt_disable_wdt_reset, + .mask_reset = s3c2410wdt_mask_wdt_reset, }; static const struct s3c2410_wdt_variant drv_data_exynos7 = { @@ -158,6 +174,8 @@ static const struct s3c2410_wdt_variant drv_data_exynos7 = { .rst_stat_bit = 23, /* A57 WDTRESET */ .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \ | QUIRK_HAS_WTCLRINT_REG, + .disable_auto_reset = s3c2410wdt_disable_wdt_reset, + .mask_reset = s3c2410wdt_mask_wdt_reset, }; static const struct of_device_id s3c2410_wdt_match[] = { @@ -200,35 +218,53 @@ static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb) return container_of(nb, struct s3c2410_wdt, freq_transition); } -static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask) +static int s3c2410wdt_disable_wdt_reset(struct s3c2410_wdt *wdt, bool mask) { + const u32 mask_val = 1 << wdt->drv_data->mask_bit; + const u32 val = mask ? mask_val : 0; int ret; - u32 mask_val = 1 << wdt->drv_data->mask_bit; - u32 val = 0; - /* No need to do anything if no PMU CONFIG needed */ - if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG)) - return 0; + ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->disable_reg, + mask_val, val); + if (ret < 0) + dev_err(wdt->dev, "failed to update reg(%d)\n", ret); - if (mask) - val = mask_val; + return ret; +} - ret = regmap_update_bits(wdt->pmureg, - wdt->drv_data->disable_reg, - mask_val, val); - if (ret < 0) - goto error; +static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask) +{ + const u32 mask_val = 1 << wdt->drv_data->mask_bit; + const u32 val = mask ? mask_val : 0; + int ret; - ret = regmap_update_bits(wdt->pmureg, - wdt->drv_data->mask_reset_reg, - mask_val, val); - error: + ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->mask_reset_reg, + mask_val, val); if (ret < 0) dev_err(wdt->dev, "failed to update reg(%d)\n", ret); return ret; } +static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) +{ + int ret; + + if (wdt->drv_data->disable_auto_reset) { + ret = wdt->drv_data->disable_auto_reset(wdt, !en); + if (ret < 0) + return ret; + } + + if (wdt->drv_data->mask_reset) { + ret = wdt->drv_data->mask_reset(wdt, !en); + if (ret < 0) + return ret; + } + + return 0; +} + static int s3c2410wdt_keepalive(struct watchdog_device *wdd) { struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); @@ -609,7 +645,7 @@ static int s3c2410wdt_probe(struct platform_device *pdev) if (ret) goto err_cpufreq; - ret = s3c2410wdt_mask_and_disable_reset(wdt, false); + ret = s3c2410wdt_enable(wdt, true); if (ret < 0) goto err_unregister; @@ -655,7 +691,7 @@ static int s3c2410wdt_remove(struct platform_device *dev) int ret; struct s3c2410_wdt *wdt = platform_get_drvdata(dev); - ret = s3c2410wdt_mask_and_disable_reset(wdt, true); + ret = s3c2410wdt_enable(wdt, false); if (ret < 0) return ret; @@ -672,8 +708,7 @@ static void s3c2410wdt_shutdown(struct platform_device *dev) { struct s3c2410_wdt *wdt = platform_get_drvdata(dev); - s3c2410wdt_mask_and_disable_reset(wdt, true); - + s3c2410wdt_enable(wdt, false); s3c2410wdt_stop(&wdt->wdt_device); } @@ -688,7 +723,7 @@ static int s3c2410wdt_suspend(struct device *dev) wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON); wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT); - ret = s3c2410wdt_mask_and_disable_reset(wdt, true); + ret = s3c2410wdt_enable(wdt, false); if (ret < 0) return ret; @@ -708,7 +743,7 @@ static int s3c2410wdt_resume(struct device *dev) writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */ writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON); - ret = s3c2410wdt_mask_and_disable_reset(wdt, false); + ret = s3c2410wdt_enable(wdt, true); if (ret < 0) return ret; From patchwork Thu Oct 28 18:35:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 12590863 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4F5CC4321E for ; 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Thu, 28 Oct 2021 11:35:34 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id h1sm239725ljb.121.2021.10.28.11.35.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 11:35:34 -0700 (PDT) From: Sam Protsenko To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 4/7] watchdog: s3c2410: Add support for WDT counter enable Date: Thu, 28 Oct 2021 21:35:24 +0300 Message-Id: <20211028183527.3050-5-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211028183527.3050-1-semen.protsenko@linaro.org> References: <20211028183527.3050-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org On new Exynos chips (like Exynos850) WDT counter must be enabled to make WDT functional. It's done via CLUSTERx_NONCPU_OUT register, in CNT_EN_WDT bit. Add infrastructure needed to enable that counter. Signed-off-by: Sam Protsenko --- drivers/watchdog/s3c2410_wdt.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 7c163a257d3c..a5ef7171a90e 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -97,12 +97,16 @@ struct s3c2410_wdt; * @rst_stat_reg: Offset in pmureg for the register that has the reset status. * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog * reset. + * @cnt_en_reg: Offset in pmureg for the register that enables WDT counter. + * @cnt_en_bit: Bit number for "watchdog counter enable" in cnt_en register. * @quirks: A bitfield of quirks. * @disable_auto_reset: If set, this function will be called to disable * automatic setting the WDT as a reset reason in RST_STAT on CPU reset; uses * disable_reg field. * @mask_reset: If set, this function will be called to mask WDT reset request; * uses mask_reset_reg and mask_bit fields. + * @enable_counter: If set, this function will be called to enable WDT counter; + * uses cnt_en_reg and cnt_en_bit fields. */ struct s3c2410_wdt_variant { @@ -111,9 +115,12 @@ struct s3c2410_wdt_variant { int mask_bit; int rst_stat_reg; int rst_stat_bit; + int cnt_en_reg; + int cnt_en_bit; u32 quirks; int (*disable_auto_reset)(struct s3c2410_wdt *wdt, bool mask); int (*mask_reset)(struct s3c2410_wdt *wdt, bool mask); + int (*enable_counter)(struct s3c2410_wdt *wdt, bool mask); }; struct s3c2410_wdt { @@ -132,6 +139,7 @@ struct s3c2410_wdt { static int s3c2410wdt_disable_wdt_reset(struct s3c2410_wdt *wdt, bool mask); static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask); +static int s3c2410wdt_enable_counter(struct s3c2410_wdt *wdt, bool en); static const struct s3c2410_wdt_variant drv_data_s3c2410 = { .quirks = 0 @@ -246,6 +254,20 @@ static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask) return ret; } +static int s3c2410wdt_enable_counter(struct s3c2410_wdt *wdt, bool en) +{ + const u32 mask_val = 1 << wdt->drv_data->cnt_en_bit; + const u32 val = en ? mask_val : 0; + int ret; + + ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->cnt_en_reg, + mask_val, val); + if (ret < 0) + dev_err(wdt->dev, "failed to update reg(%d)\n", ret); + + return ret; +} + static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) { int ret; @@ -262,6 +284,12 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) return ret; } + if (wdt->drv_data->enable_counter) { + ret = wdt->drv_data->enable_counter(wdt, en); + if (ret < 0) + return ret; + } + return 0; } From patchwork Thu Oct 28 18:35:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 12590865 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C44FC4332F for ; Thu, 28 Oct 2021 18:35:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6D2A761040 for ; Thu, 28 Oct 2021 18:35:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231345AbhJ1SiI (ORCPT ); Thu, 28 Oct 2021 14:38:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231299AbhJ1SiF (ORCPT ); Thu, 28 Oct 2021 14:38:05 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2737CC061570 for ; Thu, 28 Oct 2021 11:35:38 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id b32so12325711lfv.0 for ; Thu, 28 Oct 2021 11:35:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xUHzXfSH6odzUwHjMxG39dfwoppvALDIvwNfLlmnrkU=; b=wJRcnTKnS0oB3tuyMNi3MchugAm1UQkIqMWn7RLhGZz7lxsCJMRud0nZnZBTKA6ukH GVcd2zcrzdpEWR6TJn14ufk+EP/jAHQEYsBKURSmUhvWztsYlD40qN+xIGlvH9Yzryi3 /LygQtXCq1fJ29IjxjPuaP3ZjR9Uctkiq2r+539sZULG2UTyGkNWB4GFqWLpUMkMdxcu r4TUoL+A5eoSBtrbd7hOOv2VhxeS9f7BSEf+T3FhWJ7XB87DzU9pazOOEoZQl8A7vDpe XW2AupDG+sspfNbfqckQ/QhAzGxMMRw0ADWFLvp7y9EHaF12GtYPxqd6pQlyTQcki55i lMrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xUHzXfSH6odzUwHjMxG39dfwoppvALDIvwNfLlmnrkU=; b=crrTEHE4sFYTJiNq9giy2YpU64aFqPMUGfaBN8yUO+HYdV2NbGMplWAE+l/E52b+zX BCZFQIg/DUseFMPu1nFYDUqlgLmqHp7Nn68to1/zCn36baCg571qdJP6gLQ9W7x0Hr3s l79TFVDCsIgE8UT4P3rXSulwee8sAUwJYjpi43ZHICmGN41u9SowDTHYxC2xUW4dlcI8 3tIKtgUN9M0qCL+6fi3Wh7ly9eh3OAdTm14LnXv0vBBlMU2O8g4QNnEUg3jVOX5AeAcY KOnnvHomLVp1MiKMIYd364vI4PknvHtTvJ2geg0z2Y4EsAigjzbMNlENXTupJXtNCsqr 1uPw== X-Gm-Message-State: AOAM5322C8aGLpkt+CdnXLCtW8MjkU8Dx/b7+8A2npZxn35CQwmhglOo WB14jM52YwH9hoSYE3vjaH+wIA== X-Google-Smtp-Source: ABdhPJxvOfUnubHbOQBtOfqnhkAp5qCfbvmGIdv2MB6mRaKsShfIi0eO9rlvaJpR0LCa7PBU/1K19Q== X-Received: by 2002:ac2:4bc2:: with SMTP id o2mr5615126lfq.307.1635446136411; Thu, 28 Oct 2021 11:35:36 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id g18sm434306lfr.120.2021.10.28.11.35.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 11:35:36 -0700 (PDT) From: Sam Protsenko To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 5/7] watchdog: s3c2410: Introduce separate source clock Date: Thu, 28 Oct 2021 21:35:25 +0300 Message-Id: <20211028183527.3050-6-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211028183527.3050-1-semen.protsenko@linaro.org> References: <20211028183527.3050-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Some Exynos chips (like Exynos850) have dedicated source clock. That clock is provided from device tree as "watchdog_src" clock. In such case, "watchdog" clock is just a peripheral clock used for register interface. If "watchdog_src" is present, use its rate instead of "watchdog" for all timer related calculations. Signed-off-by: Sam Protsenko --- drivers/watchdog/s3c2410_wdt.c | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index a5ef7171a90e..bfc5872ca497 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -126,6 +126,8 @@ struct s3c2410_wdt_variant { struct s3c2410_wdt { struct device *dev; struct clk *clock; + struct clk *clock_src; + unsigned long freq_src; void __iomem *reg_base; unsigned int count; spinlock_t lock; @@ -213,10 +215,8 @@ MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids); /* functions */ -static inline unsigned int s3c2410wdt_max_timeout(struct clk *clock) +static inline unsigned int s3c2410wdt_max_timeout(unsigned long freq) { - unsigned long freq = clk_get_rate(clock); - return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1) / S3C2410_WTCON_MAXDIV); } @@ -364,7 +364,7 @@ static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned int timeout) { struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); - unsigned long freq = clk_get_rate(wdt->clock); + unsigned long freq = wdt->freq_src; unsigned int count; unsigned int divisor = 1; unsigned long wtcon; @@ -627,13 +627,27 @@ static int s3c2410wdt_probe(struct platform_device *pdev) return ret; } + /* "watchdog_src" clock is optional; if it's not present -- just skip */ + wdt->clock_src = devm_clk_get(dev, "watchdog_src"); + if (!IS_ERR(wdt->clock_src)) { + ret = clk_prepare_enable(wdt->clock_src); + if (ret < 0) { + dev_err(dev, "failed to enable source clock\n"); + ret = PTR_ERR(wdt->clock_src); + goto err_clk; + } + wdt->freq_src = clk_get_rate(wdt->clock_src); + } else { + wdt->freq_src = clk_get_rate(wdt->clock); + } + wdt->wdt_device.min_timeout = 1; - wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt->clock); + wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt->freq_src); ret = s3c2410wdt_cpufreq_register(wdt); if (ret < 0) { dev_err(dev, "failed to register cpufreq\n"); - goto err_clk; + goto err_clk_src; } watchdog_set_drvdata(&wdt->wdt_device, wdt); @@ -707,6 +721,10 @@ static int s3c2410wdt_probe(struct platform_device *pdev) err_cpufreq: s3c2410wdt_cpufreq_deregister(wdt); + err_clk_src: + if (!IS_ERR(wdt->clock_src)) + clk_disable_unprepare(wdt->clock_src); + err_clk: clk_disable_unprepare(wdt->clock); @@ -727,6 +745,9 @@ static int s3c2410wdt_remove(struct platform_device *dev) s3c2410wdt_cpufreq_deregister(wdt); + if (!IS_ERR(wdt->clock_src)) + clk_disable_unprepare(wdt->clock_src); + clk_disable_unprepare(wdt->clock); return 0; From patchwork Thu Oct 28 18:35:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 12590867 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19D98C433EF for ; Thu, 28 Oct 2021 18:35:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 014D861040 for ; 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Thu, 28 Oct 2021 11:35:37 -0700 (PDT) From: Sam Protsenko To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 6/7] watchdog: s3c2410: Add Exynos850 support Date: Thu, 28 Oct 2021 21:35:26 +0300 Message-Id: <20211028183527.3050-7-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211028183527.3050-1-semen.protsenko@linaro.org> References: <20211028183527.3050-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Exynos850 is a bit different from SoCs already supported in WDT driver: - AUTOMATIC_WDT_RESET_DISABLE register is removed, so its value is always 0; .disable_auto_reset callback is not set for that reason - MASK_WDT_RESET_REQUEST register is replaced with CLUSTERx_NONCPU_IN_EN register; instead of masking (disabling) WDT reset interrupt it's now enabled with the same value; .mask_reset callback is reused for that functionality though - To make WDT functional, WDT counter needs to be enabled in CLUSTERx_NONCPU_OUT register; it's done using .enable_counter callback Also Exynos850 has two CPU clusters, each has its own dedicated WDT instance. It takes two different driver data structures (and thus two different compatibles), as for each cluster there are different registers and different bits used. Signed-off-by: Sam Protsenko --- drivers/watchdog/s3c2410_wdt.c | 49 ++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index bfc5872ca497..ca082b1226e3 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -56,6 +56,10 @@ #define EXYNOS5_RST_STAT_REG_OFFSET 0x0404 #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408 #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c +#define EXYNOS850_CLUSTER0_NONCPU_OUT 0x1220 +#define EXYNOS850_CLUSTER0_NONCPU_INT_EN 0x1244 +#define EXYNOS850_CLUSTER1_NONCPU_OUT 0x1620 +#define EXYNOS850_CLUSTER1_NONCPU_INT_EN 0x1644 #define QUIRK_HAS_PMU_CONFIG (1 << 0) #define QUIRK_HAS_RST_STAT (1 << 1) #define QUIRK_HAS_WTCLRINT_REG (1 << 2) @@ -141,6 +145,7 @@ struct s3c2410_wdt { static int s3c2410wdt_disable_wdt_reset(struct s3c2410_wdt *wdt, bool mask); static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask); +static int s3c2410wdt_enable_wdt_reset(struct s3c2410_wdt *wdt, bool mask); static int s3c2410wdt_enable_counter(struct s3c2410_wdt *wdt, bool en); static const struct s3c2410_wdt_variant drv_data_s3c2410 = { @@ -188,6 +193,32 @@ static const struct s3c2410_wdt_variant drv_data_exynos7 = { .mask_reset = s3c2410wdt_mask_wdt_reset, }; +static const struct s3c2410_wdt_variant drv_data_exynos850_cl0 = { + .mask_reset_reg = EXYNOS850_CLUSTER0_NONCPU_INT_EN, + .mask_bit = 2, + .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, + .rst_stat_bit = 24, /* CLUSTER0 WDTRESET */ + .cnt_en_reg = EXYNOS850_CLUSTER0_NONCPU_OUT, + .cnt_en_bit = 7, + .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \ + | QUIRK_HAS_WTCLRINT_REG, + .mask_reset = s3c2410wdt_enable_wdt_reset, + .enable_counter = s3c2410wdt_enable_counter, +}; + +static const struct s3c2410_wdt_variant drv_data_exynos850_cl1 = { + .mask_reset_reg = EXYNOS850_CLUSTER1_NONCPU_INT_EN, + .mask_bit = 2, + .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, + .rst_stat_bit = 23, /* CLUSTER1 WDTRESET */ + .cnt_en_reg = EXYNOS850_CLUSTER1_NONCPU_OUT, + .cnt_en_bit = 7, + .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \ + | QUIRK_HAS_WTCLRINT_REG, + .mask_reset = s3c2410wdt_enable_wdt_reset, + .enable_counter = s3c2410wdt_enable_counter, +}; + static const struct of_device_id s3c2410_wdt_match[] = { { .compatible = "samsung,s3c2410-wdt", .data = &drv_data_s3c2410 }, @@ -199,6 +230,10 @@ static const struct of_device_id s3c2410_wdt_match[] = { .data = &drv_data_exynos5420 }, { .compatible = "samsung,exynos7-wdt", .data = &drv_data_exynos7 }, + { .compatible = "samsung,exynos850-cl0-wdt", + .data = &drv_data_exynos850_cl0 }, + { .compatible = "samsung,exynos850-cl1-wdt", + .data = &drv_data_exynos850_cl1 }, {}, }; MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); @@ -254,6 +289,20 @@ static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask) return ret; } +static int s3c2410wdt_enable_wdt_reset(struct s3c2410_wdt *wdt, bool mask) +{ + const u32 mask_val = 1 << wdt->drv_data->mask_bit; + const u32 val = mask ? 0 : mask_val; /* reset interrupt enable value */ + int ret; + + ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->mask_reset_reg, + mask_val, val); + if (ret < 0) + dev_err(wdt->dev, "failed to update reg(%d)\n", ret); + + return ret; +} + static int s3c2410wdt_enable_counter(struct s3c2410_wdt *wdt, bool en) { const u32 mask_val = 1 << wdt->drv_data->cnt_en_bit; From patchwork Thu Oct 28 18:35:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 12590869 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0627BC433EF for ; Thu, 28 Oct 2021 18:36:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E4C8761040 for ; Thu, 28 Oct 2021 18:36:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231438AbhJ1Sia (ORCPT ); Thu, 28 Oct 2021 14:38:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231443AbhJ1SiT (ORCPT ); Thu, 28 Oct 2021 14:38:19 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D736C061227 for ; Thu, 28 Oct 2021 11:35:41 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id p16so15570658lfa.2 for ; Thu, 28 Oct 2021 11:35:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PW+Xu5KR0LGnC5ZiTBKpf+hcc7E/gJL7mbWD5u2IRSI=; b=xuSKeHbbC4nc+EU9CT3wXw3es14n16X3aTlTv7hYY/KFi/EOzkDwotp+e4efrBTknK yoXUrbGpXJzKzCjzaG1j2A3XS7QA6Vkku+P+25hkokJOcLpEg5IgS+CIUUThzgLyOZot ixdiNjWNwZmL59+5KZVYYBlD3pFB6IDde6RQnFqssxwjfOYYhvoqkGqK1FW0UmcvsAro lUJxahpkhEtl55/8fKE6OJjf2oOTWxcLIbh2gZIIHqmPO/st30RnIKXXfNs+U95VwAJ+ 2eOpm/1W5muC8xWhRfJnskHvK66/3RjGJX991wlDnnhdOURT5Bk7nNdLzwNfv6K4ijIh OnUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PW+Xu5KR0LGnC5ZiTBKpf+hcc7E/gJL7mbWD5u2IRSI=; b=3M4Y2OHUwSNLaoUlKRebfooPZiapqBRtJs6reOHWkHVfzSGf/At4YUqIqav9SSNX3R gkkNE1Em+XY8PD3N496qHA089+fSAQmfKBmT9czQ5O8Fcn/gynroulrRZSds01Y2dmPO E11IFs9jk0+v36yF9QsTdzX5sDDArvKtU10op6ZkcbQ/yRcVH3O1rOvdmbu0rdc8sF4w wZIcZ8c3OIyQDRpthOWetL7yU2P8BEss4CqnzTB9C+EAgvrNBId9x+7K1quibB8P5THp pPsHW/ibc6cGSUM+c9YYRwbsTdctyMOUnr7e8vCMkjFw+Tdrdl/pGMowcna5BFw8B8GQ 6wLg== X-Gm-Message-State: AOAM5311aALPdRjXctEBeZ2CQVvK6ernVKlZkq5wg3nzFH/OnR+9NAHp HcdqdJj7JJgYcNilP4YNScDWNA== X-Google-Smtp-Source: ABdhPJwOsTrd35+23hcuPbz+sZ6ig7/NhHcGSWEcNkbNR9PlXij1vTP5BSLOqRqr2hbykWMc+rOx2Q== X-Received: by 2002:a05:6512:1294:: with SMTP id u20mr5634502lfs.218.1635446139796; Thu, 28 Oct 2021 11:35:39 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id d20sm388979lfg.8.2021.10.28.11.35.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 11:35:39 -0700 (PDT) From: Sam Protsenko To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 7/7] watchdog: s3c2410: Let kernel kick watchdog Date: Thu, 28 Oct 2021 21:35:27 +0300 Message-Id: <20211028183527.3050-8-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211028183527.3050-1-semen.protsenko@linaro.org> References: <20211028183527.3050-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org When "tmr_atboot" module param is set, the watchdog is started in driver's probe. In that case, also set WDOG_HW_RUNNING bit to let watchdog core driver know it's running. This way wathcdog core can kick the watchdog for us (if CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED option is enabled), until user space takes control. Signed-off-by: Sam Protsenko --- drivers/watchdog/s3c2410_wdt.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index ca082b1226e3..9af014ff1468 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -732,6 +732,21 @@ static int s3c2410wdt_probe(struct platform_device *pdev) wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); wdt->wdt_device.parent = dev; + /* + * If "tmr_atboot" param is non-zero, start the watchdog right now. Also + * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog. + * + * If we're not enabling the watchdog, then ensure it is disabled if it + * has been left running from the bootloader or other source. + */ + if (tmr_atboot && started == 0) { + dev_info(dev, "starting watchdog timer\n"); + s3c2410wdt_start(&wdt->wdt_device); + set_bit(WDOG_HW_RUNNING, &wdt->wdt_device.status); + } else if (!tmr_atboot) { + s3c2410wdt_stop(&wdt->wdt_device); + } + ret = watchdog_register_device(&wdt->wdt_device); if (ret) goto err_cpufreq; @@ -740,17 +755,6 @@ static int s3c2410wdt_probe(struct platform_device *pdev) if (ret < 0) goto err_unregister; - if (tmr_atboot && started == 0) { - dev_info(dev, "starting watchdog timer\n"); - s3c2410wdt_start(&wdt->wdt_device); - } else if (!tmr_atboot) { - /* if we're not enabling the watchdog, then ensure it is - * disabled if it has been left running from the bootloader - * or other source */ - - s3c2410wdt_stop(&wdt->wdt_device); - } - platform_set_drvdata(pdev, wdt); /* print out a statement of readiness */