From patchwork Thu Oct 28 18:56:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12590903 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F286C433EF for ; Thu, 28 Oct 2021 18:57:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 57DDE610CA for ; Thu, 28 Oct 2021 18:57:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230496AbhJ1S7b (ORCPT ); Thu, 28 Oct 2021 14:59:31 -0400 Received: from mail.kernel.org ([198.145.29.99]:56910 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229645AbhJ1S7b (ORCPT ); Thu, 28 Oct 2021 14:59:31 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 1DF5D610D2; Thu, 28 Oct 2021 18:57:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1635447424; bh=DgDwJyTpY2SNF+BMO6REe24ZpCAwiBRSvTJpcdEY/8A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IRSsuA7zjk2MUDHhiAqpryIrcMnonXfKcbIt371IkUurDx2HzPT23nXwTc9AUieLZ ebb78SBrQ1wxgKzpRkowHX+43IBbkKan9sk9CuLt6J5hspSIvbBHLcSUVGw2Q9E0+a LoZqouRO4N16SpIrGeRMuAHrnqsJQGspXpq2YvKOI9yHzteewHuNHl/wVPmk/Vvd5T VKJ3QFagB60WdkRwnHOC1RSmQqVboYxgLmFj5vjnOO942iQcI7u+cUp7L4Ci015BZu s2avrP+V0OM3BiosE+5GkOYnCA0ORk9RNvSqexnU2mh8mW/zkl/tAR4l3arDfYgECe wfwrIWHLWfH1A== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH v2 1/7] PCI: pci-bridge-emul: Fix emulation of W1C bits Date: Thu, 28 Oct 2021 20:56:53 +0200 Message-Id: <20211028185659.20329-2-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211028185659.20329-1-kabel@kernel.org> References: <20211028185659.20329-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The pci_bridge_emul_conf_write() function correctly clears W1C bits in cfgspace cache, but it does not inform the underlying implementation about the clear request: the .write_op() method is given the value with these bits cleared. This is wrong if the .write_op() needs to know which bits were requested to be cleared. Fix the value to be passed into the .write_op() method to have requested W1C bits set, so that it can clear them. Both pci-bridge-emul users (mvebu and aardvark) are compatible with this change. Fixes: 23a5fba4d941 ("PCI: Introduce PCI bridge emulated config space common logic") Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Cc: stable@vger.kernel.org Cc: Russell King --- drivers/pci/pci-bridge-emul.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c index fdaf86a888b7..db97cddfc85e 100644 --- a/drivers/pci/pci-bridge-emul.c +++ b/drivers/pci/pci-bridge-emul.c @@ -431,8 +431,21 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, /* Clear the W1C bits */ new &= ~((value << shift) & (behavior[reg / 4].w1c & mask)); + /* Save the new value with the cleared W1C bits into the cfgspace */ cfgspace[reg / 4] = cpu_to_le32(new); + /* + * Clear the W1C bits not specified by the write mask, so that the + * write_op() does not clear them. + */ + new &= ~(behavior[reg / 4].w1c & ~mask); + + /* + * Set the W1C bits specified by the write mask, so that write_op() + * knows about that they are to be cleared. + */ + new |= (value << shift) & (behavior[reg / 4].w1c & mask); + if (write_op) write_op(bridge, reg, old, new, mask); From patchwork Thu Oct 28 18:56:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12590905 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3C71C433F5 for ; Thu, 28 Oct 2021 18:57:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D9393610FD for ; Thu, 28 Oct 2021 18:57:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229645AbhJ1S7c (ORCPT ); Thu, 28 Oct 2021 14:59:32 -0400 Received: from mail.kernel.org ([198.145.29.99]:56964 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230505AbhJ1S7c (ORCPT ); Thu, 28 Oct 2021 14:59:32 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 5C287610EA; Thu, 28 Oct 2021 18:57:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1635447425; bh=jVL6U9PYqMj5MznymMVeGWdXkPuD32M/xjwPj8WwgIY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VzaZhWRhfTQf8/Xy97oFgf2O2Jr3sQ4XkrRYnpp2QfryrZXHyq0QLd2QZoeMXRG2h 0o7quDRbhZUROa6n/fYbnsROY1yyCuIL4vYXAXgttI9CvuzaYnXQSvlvJi3azT3tL8 ue6i+PfzZp6pTWgKWmIly7L/3I1yMRt1uri7I7RE/7HhfHhtAM+LeHASzJZBDZGRyJ Bl6WqoaMY9MxmmMfaxZ7Ilyt0tD7IDSYJxNpVbEHXfa6f2ETs+ZlLqJL16v05JU5dV dg5FS7hbD5bI14BEEbNvLXGqmBYM/5nfX3LA3HeLuKog+ROKjyrPf3gDJ7pL4/PCPS rqfdMGxlg3BTA== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH v2 2/7] PCI: aardvark: Fix return value of MSI domain .alloc() method Date: Thu, 28 Oct 2021 20:56:54 +0200 Message-Id: <20211028185659.20329-3-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211028185659.20329-1-kabel@kernel.org> References: <20211028185659.20329-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org MSI domain callback .alloc() (implemented by advk_msi_irq_domain_alloc() function) should return zero on success, since non-zero value indicates failure. When the driver was converted to generic MSI API in commit f21a8b1b6837 ("PCI: aardvark: Move to MSI handling using generic MSI support"), it was converted so that it returns hwirq number. Fix this. Fixes: f21a8b1b6837 ("PCI: aardvark: Move to MSI handling using generic MSI support") Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 10476c00b312..b45ff2911c80 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1138,7 +1138,7 @@ static int advk_msi_irq_domain_alloc(struct irq_domain *domain, domain->host_data, handle_simple_irq, NULL, NULL); - return hwirq; + return 0; } static void advk_msi_irq_domain_free(struct irq_domain *domain, From patchwork Thu Oct 28 18:56:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12590907 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0467C433EF for ; Thu, 28 Oct 2021 18:57:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C894F610E7 for ; Thu, 28 Oct 2021 18:57:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230481AbhJ1S7e (ORCPT ); Thu, 28 Oct 2021 14:59:34 -0400 Received: from mail.kernel.org ([198.145.29.99]:56992 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230505AbhJ1S7d (ORCPT ); Thu, 28 Oct 2021 14:59:33 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 97876610CA; Thu, 28 Oct 2021 18:57:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1635447426; bh=cIk5CTmQGMvBuZSubVxd7w+ybwyutKyYpsutNgifE1U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WibUL8601yx7NaIOHXp5mcqSdskYmf6uyUmrVQfMIhMDjPq3fpDHh2ITay2vdCAgi ZuJfvw7WtqqyqgzQrJsz8ODQ7rDwbAv01K5RXy4Ogx7jp96bFo3dLAQShVFwjxbauF cjn7hzw92y0wMRpjkdVwGi5KZTmxIy+PwtFmG9KLHIkrXgWPuFAkZZdBeI1MyNlwSW w+Snz9sDfCrnGav9EmR1FDT/slIrynsWOK/ypPjXdICJ1JAKg6da/PINogygAERmYd JZbZKwyckQYg6EgsSeUzxsmLvPnGXA1xjRIj8+w1vltqtmjfwYozKF/vduUTk+SPzc qmCC8l++H49Kg== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH v2 3/7] PCI: aardvark: Read all 16-bits from PCIE_MSI_PAYLOAD_REG Date: Thu, 28 Oct 2021 20:56:55 +0200 Message-Id: <20211028185659.20329-4-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211028185659.20329-1-kabel@kernel.org> References: <20211028185659.20329-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The PCIE_MSI_PAYLOAD_REG contains 16-bit MSI number, not only lower 8 bits. Fix reading content of this register and add a comment describing the access to this register. Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver") Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index b45ff2911c80..389ebba1dd9b 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -119,6 +119,7 @@ #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58) #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C) #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C) +#define PCIE_MSI_DATA_MASK GENMASK(15, 0) /* PCIe window configuration */ #define OB_WIN_BASE_ADDR 0x4c00 @@ -1319,8 +1320,12 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie) if (!(BIT(msi_idx) & msi_status)) continue; + /* + * msi_idx contains bits [4:0] of the msi_data and msi_data + * contains 16bit MSI interrupt number + */ advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); - msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF; + msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & PCIE_MSI_DATA_MASK; generic_handle_irq(msi_data); } From patchwork Thu Oct 28 18:56:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12590909 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07347C433FE for ; Thu, 28 Oct 2021 18:57:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E2CA76023E for ; Thu, 28 Oct 2021 18:57:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230517AbhJ1S7f (ORCPT ); Thu, 28 Oct 2021 14:59:35 -0400 Received: from mail.kernel.org ([198.145.29.99]:57030 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230505AbhJ1S7e (ORCPT ); Thu, 28 Oct 2021 14:59:34 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id D317460232; Thu, 28 Oct 2021 18:57:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1635447427; bh=dqIcLzKobLU15jhsBn8y0D5cnA9xwu5wfL8NwiVCOcg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OSGyRzkSqWcqKk/nBaxU/pmpG4vK/ik0s+6UsYMkRaE+wZtUDglVxiQ7AaAthxteY hjN4eWyio6tDD++VciI6Lo6NA7qe+rT4HfOmqsrU/HZrnbvXG8zi91puh3fu97IOkK XgcvTXH8O0luxYhw3C7ORsxihW9d4l/2ubIgtJ7wfUTCdu9Zj3ckdxe+KJiTV3UB+t z4iJMyE4SDz1Z+MIvaPdyLbkGY5MDMF2+vPyoI6yI9G7KzILTuYmrmuTtUzFeRpO+u qAkaOUqDjjs1Db0s/bvmln6dYVB5T00IEX9w1guV5pauS66wVAt8Pq1KxDgiSmqXDH qnWItPrICcfDg== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH v2 4/7] PCI: aardvark: Fix support for bus mastering and PCI_COMMAND on emulated bridge Date: Thu, 28 Oct 2021 20:56:56 +0200 Message-Id: <20211028185659.20329-5-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211028185659.20329-1-kabel@kernel.org> References: <20211028185659.20329-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár From very vague, ambiguous and incomplete information from Marvell we deduced that the 32-bit Aardvark register at address 0x4 (PCIE_CORE_CMD_STATUS_REG), which is not documented for Root Complex mode in the Functional Specification (only for Endpoint mode), controls two 16-bit PCIe registers: Command Register and Status Registers of PCIe Root Port. This means that bit 2 controls bus mastering and forwarding of memory and I/O requests in the upstream direction. According to PCI specifications bits [0:2] of Command Register, this should be by default disabled on reset. So explicitly disable these bits at early setup of the Aardvark driver. Remove code which unconditionally enables all 3 bits and let kernel code (via pci_set_master() function) to handle bus mastering of Root PCIe Bridge via emulated PCI_COMMAND on emulated bridge. Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Cc: stable@vger.kernel.org # b2a56469d550 ("PCI: aardvark: Add FIXME comment for PCIE_CORE_CMD_STATUS_REG access") --- drivers/pci/controller/pci-aardvark.c | 54 +++++++++++++++++++-------- 1 file changed, 38 insertions(+), 16 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 389ebba1dd9b..d7db03da4d1c 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -31,9 +31,6 @@ /* PCIe core registers */ #define PCIE_CORE_DEV_ID_REG 0x0 #define PCIE_CORE_CMD_STATUS_REG 0x4 -#define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0) -#define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1) -#define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) #define PCIE_CORE_DEV_REV_REG 0x8 #define PCIE_CORE_PCIEXP_CAP 0xc0 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 @@ -514,6 +511,11 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL; advk_writel(pcie, reg, VENDOR_ID_REG); + /* Disable Root Bridge I/O space, memory space and bus mastering */ + reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); + reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); + /* Set Advanced Error Capabilities and Control PF0 register */ reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | @@ -612,19 +614,6 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) advk_pcie_disable_ob_win(pcie, i); advk_pcie_train_link(pcie); - - /* - * FIXME: The following register update is suspicious. This register is - * applicable only when the PCI controller is configured for Endpoint - * mode, not as a Root Complex. But apparently when this code is - * removed, some cards stop working. This should be investigated and - * a comment explaining this should be put here. - */ - reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); - reg |= PCIE_CORE_CMD_MEM_ACCESS_EN | - PCIE_CORE_CMD_IO_ACCESS_EN | - PCIE_CORE_CMD_MEM_IO_REQ_EN; - advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); } static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val) @@ -753,6 +742,37 @@ static int advk_pcie_wait_pio(struct advk_pcie *pcie) return -ETIMEDOUT; } +static pci_bridge_emul_read_status_t +advk_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge, + int reg, u32 *value) +{ + struct advk_pcie *pcie = bridge->data; + + switch (reg) { + case PCI_COMMAND: + *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); + return PCI_BRIDGE_EMUL_HANDLED; + + default: + return PCI_BRIDGE_EMUL_NOT_HANDLED; + } +} + +static void +advk_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, + int reg, u32 old, u32 new, u32 mask) +{ + struct advk_pcie *pcie = bridge->data; + + switch (reg) { + case PCI_COMMAND: + advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG); + break; + + default: + break; + } +} static pci_bridge_emul_read_status_t advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, @@ -854,6 +874,8 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, } static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { + .read_base = advk_pci_bridge_emul_base_conf_read, + .write_base = advk_pci_bridge_emul_base_conf_write, .read_pcie = advk_pci_bridge_emul_pcie_conf_read, .write_pcie = advk_pci_bridge_emul_pcie_conf_write, }; From patchwork Thu Oct 28 18:56:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12590911 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 585FEC433EF for ; Thu, 28 Oct 2021 18:57:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3815A610CA for ; Thu, 28 Oct 2021 18:57:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230505AbhJ1S7g (ORCPT ); Thu, 28 Oct 2021 14:59:36 -0400 Received: from mail.kernel.org ([198.145.29.99]:57070 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231132AbhJ1S7g (ORCPT ); Thu, 28 Oct 2021 14:59:36 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 1A26D610FD; Thu, 28 Oct 2021 18:57:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1635447429; bh=7Qve900myusAiuJ52EKMbKQbQLqBfQ6yVPIdzZTGc1I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qQIAG2wVGlArGmVeo5kIRlwxf2Y0Vhwz4yjMtytKmXdIUV1eavh+Nl4d7x1O29Knc QpNimaCI0J2k7V6Qk9Po33apQakDwSPqiyGufGlvOfVeIxA01Fj9BKkGOX2I1N01OU mwjNKECVyT+GxRJwm1VdsfYRDUjZ5GCg6qc1eiOYBY8Vf0f4mQirbNLYSg0D1rN6uZ m2+k1XQS4FSrhBVoeUcOnAYVldzsaC1pbF148DS5vbPcMWUd4JFFKUtyH48aN9Foh5 tflWG9bj3LahczIRzWIFAkAl+Ts9/E16aR2phBD1WpP4gnh78rgU2wEyIjnivvDQDC +MxttoGjB1POw== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH v2 5/7] PCI: aardvark: Set PCI Bridge Class Code to PCI Bridge Date: Thu, 28 Oct 2021 20:56:57 +0200 Message-Id: <20211028185659.20329-6-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211028185659.20329-1-kabel@kernel.org> References: <20211028185659.20329-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Aardvark controller has something like config space of a Root Port available at offset 0x0 of internal registers - these registers are used for implementation of the emulated bridge. The default value of Class Code of this bridge corresponds to a RAID Mass storage controller, though. (This is probably intended for when the controller is used as Endpoint.) Change the Class Code to correspond to a PCI Bridge. Add comment explaining this change. Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index d7db03da4d1c..ddca45415c65 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -511,6 +511,26 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL; advk_writel(pcie, reg, VENDOR_ID_REG); + /* + * Change Class Code of PCI Bridge device to PCI Bridge (0x600400), + * because the default value is Mass storage controller (0x010400). + * + * Note that this Aardvark PCI Bridge does not have compliant Type 1 + * Configuration Space and it even cannot be accessed via Aardvark's + * PCI config space access method. Something like config space is + * available in internal Aardvark registers starting at offset 0x0 + * and is reported as Type 0. In range 0x10 - 0x34 it has totally + * different registers. + * + * Therefore driver uses emulation of PCI Bridge which emulates + * access to configuration space via internal Aardvark registers or + * emulated configuration buffer. + */ + reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG); + reg &= ~0xffffff00; + reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8; + advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG); + /* Disable Root Bridge I/O space, memory space and bus mastering */ reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); From patchwork Thu Oct 28 18:56:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12590913 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 912D2C433FE for ; Thu, 28 Oct 2021 18:57:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 79C1860232 for ; Thu, 28 Oct 2021 18:57:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230514AbhJ1S7h (ORCPT ); Thu, 28 Oct 2021 14:59:37 -0400 Received: from mail.kernel.org ([198.145.29.99]:57098 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231132AbhJ1S7h (ORCPT ); Thu, 28 Oct 2021 14:59:37 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 56A2960524; Thu, 28 Oct 2021 18:57:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1635447430; bh=C4FJ23s27YCakqOQiNvO9J1kK2UzbDmtLdJe251uZA8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lnrNpErzNkPBA0zpCL+55U9As+2C6fG1lYYzd1eX+GVoQpBriWgvVD++jojwR0OmL hQ11JTlnsdI+8eb7jk8uhu39egWjWGjYjs9c1zQ+YRe/xYj3WUcqkUidz4U2gqJvql aqXUb2u2yoa3uWKkAMq5/KaTw6xSh4L7uQrknucQILQ2m4sNA1dqrsXGGPlsHX+6ra G1GSt5c0qu/5NXgRf5zrVB0XUtyHykJzp0eV4CBaUm87Mv+yDFCw0WBfjw/Mot+bGv wJreFzvYOeUy8Zq2WuKwzIB9h1Ocp5h64G/p3ZjUu2Wl3vkS8rlFDLV+McFiRmWJDJ RMMG6akRH5DSg== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH v2 6/7] PCI: aardvark: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridge Date: Thu, 28 Oct 2021 20:56:58 +0200 Message-Id: <20211028185659.20329-7-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211028185659.20329-1-kabel@kernel.org> References: <20211028185659.20329-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Aardvark supports PCIe Hot Reset via PCIE_CORE_CTRL1_REG. Use it for implementing PCI_BRIDGE_CTL_BUS_RESET bit of PCI_BRIDGE_CONTROL register on emulated bridge. With this, the function pci_reset_secondary_bus() starts working and can reset connected PCIe card. Custom userspace script [1] which uses setpci can trigger PCIe Hot Reset and reset the card manually. [1] https://alexforencich.com/wiki/en/pcie/hot-reset-linux Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index ddca45415c65..c3b725afa11f 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -773,6 +773,22 @@ advk_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge, *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); return PCI_BRIDGE_EMUL_HANDLED; + case PCI_INTERRUPT_LINE: { + /* + * From the whole 32bit register we support reading from HW only + * one bit: PCI_BRIDGE_CTL_BUS_RESET. + * Other bits are retrieved only from emulated config buffer. + */ + __le32 *cfgspace = (__le32 *)&bridge->conf; + u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]); + if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN) + val |= PCI_BRIDGE_CTL_BUS_RESET << 16; + else + val &= ~(PCI_BRIDGE_CTL_BUS_RESET << 16); + *value = val; + return PCI_BRIDGE_EMUL_HANDLED; + } + default: return PCI_BRIDGE_EMUL_NOT_HANDLED; } @@ -789,6 +805,17 @@ advk_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG); break; + case PCI_INTERRUPT_LINE: + if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) { + u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG); + if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16)) + val |= HOT_RESET_GEN; + else + val &= ~HOT_RESET_GEN; + advk_writel(pcie, val, PCIE_CORE_CTRL1_REG); + } + break; + default: break; } From patchwork Thu Oct 28 18:56:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12590915 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1561C433EF for ; Thu, 28 Oct 2021 18:57:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CA86860232 for ; Thu, 28 Oct 2021 18:57:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230384AbhJ1S7j (ORCPT ); Thu, 28 Oct 2021 14:59:39 -0400 Received: from mail.kernel.org ([198.145.29.99]:57116 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231132AbhJ1S7i (ORCPT ); Thu, 28 Oct 2021 14:59:38 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 922B1610CA; Thu, 28 Oct 2021 18:57:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1635447431; bh=0v5e9CTnatZ5QZIboPa/3Ck7k53KXq9StP9XVz31j04=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N7GKA/xeq39IC1dUy9IaJ6VtyrvLseUzuCcTf1UAgjnrEtryvbVEOKyv+yoWAne8e XGH2uGGrdcG0lHkO1F5vOdrTqU+dVy8oTjDKAAxbdTgoNDOrWAVGdi52x8gEKvVxT6 cRluGM5XHa4xHxC3bkBgCvDG9sTRPoGn5RVTLP8jr8Feq1bMZt7LumZFOGs1wYuqnR kEvu2PYjx5dGDPR+C1sfcz4UbsIJVM276aiwPrYOsrSpxleb2aOyBvMhHEoBFwGPkU ulgNQyROi1n5TtdqoK3w8YYaZOW5NsRUrSNxPsB4w+ZqxnUxs3QUiDnkcLTqcQjb/K p96sI7kgxx9+A== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH v2 7/7] PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 on emulated bridge Date: Thu, 28 Oct 2021 20:56:59 +0200 Message-Id: <20211028185659.20329-8-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211028185659.20329-1-kabel@kernel.org> References: <20211028185659.20329-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár This register is exported at address offset 0x30. Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index c3b725afa11f..c5300d49807a 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -32,6 +32,7 @@ #define PCIE_CORE_DEV_ID_REG 0x0 #define PCIE_CORE_CMD_STATUS_REG 0x4 #define PCIE_CORE_DEV_REV_REG 0x8 +#define PCIE_CORE_EXP_ROM_BAR_REG 0x30 #define PCIE_CORE_PCIEXP_CAP 0xc0 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) @@ -773,6 +774,10 @@ advk_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge, *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); return PCI_BRIDGE_EMUL_HANDLED; + case PCI_ROM_ADDRESS1: + *value = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG); + return PCI_BRIDGE_EMUL_HANDLED; + case PCI_INTERRUPT_LINE: { /* * From the whole 32bit register we support reading from HW only @@ -805,6 +810,10 @@ advk_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG); break; + case PCI_ROM_ADDRESS1: + advk_writel(pcie, new, PCIE_CORE_EXP_ROM_BAR_REG); + break; + case PCI_INTERRUPT_LINE: if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) { u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG);