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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 01/21] x86/cpufreatures: add AMD Collaborative Processor Performance Control feature flag Date: Fri, 29 Oct 2021 21:02:21 +0800 Message-ID: <20211029130241.1984459-2-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: abcd2449-2acb-4c4e-5947-08d99adc7e0c X-MS-TrafficTypeDiagnostic: DM6PR12MB3113: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Eh6If/60hkW+C5GVWP3pci2sNPxzUK/R2Oabz9/Y39Sf7CDZvodwj+/0MQgYuY9zOXOsYW2BQZzcKamS0kasYp6anFuA+oesAhD0eDBwcKh3UG5S87fMh624jS2uoiDjDUByJtNgslom4Evz88J5lZHmpg3PXptYHpDz9t9vlJCvDCQW5lk3aAZM8mqSYIondEy97w3eodBdoCYe4IxG/gU6ZDkMuZVMyOearM/3MdKCw0Eizg9B2WTp25M6cjQjJYLx8tfvCQ02GRzJ3cNj70CiZsywSbNe8PiQL801JRPzPOdpah+OL1jM/RI+d4/KY2HAZaIKBzHA3qItmWui1B87xPehAWwcMsjnhZYI74N/UbuaBDFq8VMvVfsYDzu42Ca/onh0S/Ma+Fch8eNTKWXdsfuXdwhUX39oq93axniqEpzSG1CokwGnok3aTGOV9iyAwbU0OI7OFXaYeWy5M0QE0+iamWndBDDa6Qu+z2ADtpoup6np6mwAb4R5HpYi8AKs1uggC1LbVG9leIDRt7vNN5Qvtl86AQ99GIjxxmHcxWekKIj8Jp8G50FoSlESwNNaXzoeGEi6S/L84wx0XGIJEt5A2EG6PJn4cNhFLmBVjTnpZe2WJ+PkWd2djnh4HYeXGpQOFHffF4snCBAu4WUomTLrHIMvzwtfFChw3iwIvi1aYNvzhW01k+L4rSgw698cPeOeA7J6tqGNcgHrvS0QGmw9CkOrd1iU/4I7MgU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(47076005)(508600001)(70206006)(82310400003)(70586007)(1076003)(36756003)(6666004)(5660300002)(26005)(54906003)(4326008)(336012)(110136005)(16526019)(7696005)(81166007)(36860700001)(2906002)(186003)(316002)(426003)(8936002)(8676002)(356005)(86362001)(7416002)(2616005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:03:24.5878 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: abcd2449-2acb-4c4e-5947-08d99adc7e0c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT067.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3113 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add Collaborative Processor Performance Control feature flag for AMD processors. This feature flag will be used on the following amd-pstate driver. The amd-pstate driver has two approaches to implement the frequency control behavior. That depends on the CPU hardware implementation. One is "Full MSR Support" and another is "Shared Memory Support". The feature flag indicates the current processors with "Full MSR Support". Signed-off-by: Huang Rui Acked-by: Borislav Petkov --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index d0ce5cfd3ac1..f23dc1abd485 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -313,6 +313,7 @@ #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ +#define X86_FEATURE_AMD_CPPC (13*32+27) /* Collaborative Processor Performance Control */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ From patchwork Fri Oct 29 13:02:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12592657 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C48A2C433F5 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT027.mail.protection.outlook.com (10.13.174.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Fri, 29 Oct 2021 13:03:30 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Fri, 29 Oct 2021 08:03:23 -0500 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 02/21] x86/msr: add AMD CPPC MSR definitions Date: Fri, 29 Oct 2021 21:02:22 +0800 Message-ID: <20211029130241.1984459-3-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 42eb8a05-b429-4fe3-83c4-08d99adc81b6 X-MS-TrafficTypeDiagnostic: BY5PR12MB4965: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1107; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: abd8ChP2Y7yHLrWOL/TpcKnI9zoU1+MPS41+F/ge/TZ39+K3/alYa7UktJzUY3dfhGeOE087zMyK4LztHIpC20JvoM9vLIhr0XGbbXAfGS/UFp0JHw4TkLUbx+xgiTBdZTc8uhoCv8aWT+DH1BlzMwdTvSELn/MbRUBkY7q/I79N5UMoHeO/w+iezJu3JH+8+gSz2G9OkvVlfh7xtv3CY4bCuBrm24iJ8MHeaPGysbb7zFVsHkF4TWrsRJLf4/KIy0oV/mQH0mwA/ouQKfjAqDHa7JpK9j/OpKEhZvFEJziOvx/u3mZfvexLLPic6wQDARHn9FaxzrVJRpBNlwcjXZYTUP3Ydia/GmeKNBgmtjjke20aAfgyn/OCIM9dc4SgCCyOJ4OD4gf3rbN6ba496HpE464ctCzeohNAkGaUgtA4RmmFzAuMV+TcqQ/HzkCgWT1s6m3ZU0zW5MC9tSeitlY5sKBPG6q04q0HD5sPaJJXcLD7U7JoyihQpgb1btbgVGekC1e1pb2NJwFKwCP7MKqB34emqCuzSA9MiTVCvxMFLAEI4jL9tptv/Ln3G8c1Jrc5BWOkjk+198oUiURIaz35nUQKvj0scwN5tBQXbs0HLIGLoGZkbz+SXx+sgbDokmFWORLVMjysOX30mPfkGz4NObigF2kw7sbt6sUk7kE8KCnhGimtnsl7a2l7VWMpMApy2ciS+A7EpN7LtvJPUXOTwP8dlotF8H/vBsab76s= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(2906002)(70586007)(70206006)(54906003)(1076003)(26005)(356005)(4326008)(7416002)(508600001)(336012)(82310400003)(47076005)(316002)(186003)(81166007)(5660300002)(426003)(86362001)(7696005)(8936002)(36756003)(2616005)(8676002)(36860700001)(110136005)(16526019)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:03:30.7631 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 42eb8a05-b429-4fe3-83c4-08d99adc81b6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4965 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org AMD CPPC (Collaborative Processor Performance Control) function uses MSR registers to manage the performance hints. So add the MSR register macro here. Signed-off-by: Huang Rui --- arch/x86/include/asm/msr-index.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index a7c413432b33..ce42e15cf303 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -486,6 +486,23 @@ #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f +/* AMD Collaborative Processor Performance Control MSRs */ +#define MSR_AMD_CPPC_CAP1 0xc00102b0 +#define MSR_AMD_CPPC_ENABLE 0xc00102b1 +#define MSR_AMD_CPPC_CAP2 0xc00102b2 +#define MSR_AMD_CPPC_REQ 0xc00102b3 +#define MSR_AMD_CPPC_STATUS 0xc00102b4 + +#define CAP1_LOWEST_PERF(x) (((x) >> 0) & 0xff) +#define CAP1_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) +#define CAP1_NOMINAL_PERF(x) (((x) >> 16) & 0xff) +#define CAP1_HIGHEST_PERF(x) (((x) >> 24) & 0xff) + +#define REQ_MAX_PERF(x) (((x) & 0xff) << 0) +#define REQ_MIN_PERF(x) (((x) & 0xff) << 8) +#define REQ_DES_PERF(x) (((x) & 0xff) << 16) +#define REQ_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) + /* Fam 17h MSRs */ #define MSR_F17H_IRPERF 0xc00000e9 From patchwork Fri Oct 29 13:02:23 2021 Content-Type: text/plain; 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Fri, 29 Oct 2021 13:03:32 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT027.mail.protection.outlook.com (10.13.174.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Fri, 29 Oct 2021 13:03:32 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Fri, 29 Oct 2021 08:03:27 -0500 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 03/21] ACPI: CPPC: implement support for SystemIO registers Date: Fri, 29 Oct 2021 21:02:23 +0800 Message-ID: <20211029130241.1984459-4-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bb807444-c7ae-408a-6acd-08d99adc82ad X-MS-TrafficTypeDiagnostic: BY5PR12MB4834: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3513; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wF+9pSIDNOiZTncqy7T3reXoABYTXnrvrgVaajlVXdoqADByz5g1/XnBAYxrZmQKwVcfkqKyywOOYRaQI+lwhmzL5AJXgMHVUUgVuRITMKRP4JjNSngMoem1+GSvdBVIseNlO5Xqy2f0d51lfJGlvvDWh31ZAET2FsEXemCLOx89zd4iQE5FyocWpqRikHPANfRMktgUgyapLzBT48spFCcZRDAoMbzFaITvNPdjRzahBZAzvcoD8+sAc0Vpi2zlwEsWHFv9Deh/yWN573AdvMZ6ST2j29vn+/J0br1Zrjk3mg8FxYTj+Fi+E9taJaFaUrN92acCaU2Fjt+GS6eUnh9sHcI7+T2Zo4AQLJuxWL/1LNscfOTyXKafqYY6ncI2Q5yi4F1aYPdp1JyzI3iG0jb5u8nelvI1cop00cOPj4hxiDuu47CjF5zunqupYtYbqdoQc5vdCo/5j6zyCn8NkOWVz4topf6llsnhOL1HwGXHi6Mx078IrvYRl/RUrowfOrhgInOy4NGUiaR8ro61dfHJmvMpGDyxpk/PUPXrJ7GKVUNeExSwl6PvU8Sng9us5LZLOEde34/i0/RhVesl1A9X040rWVIMsAYgX7jdV16rzN+x0wzmemAf2Z8EnN79fKOZqgr3R612vFlZXb7AWgfTkliyoFKH7WGO0XHXALG9eInC9RzOz+bzaLsvvsCxlS/yo0S8Fl7qSmC5VmXymGUNBRn7PWQiJLC66vBiBLw= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(16526019)(186003)(5660300002)(316002)(2616005)(426003)(86362001)(4326008)(336012)(2906002)(7416002)(1076003)(82310400003)(70586007)(70206006)(26005)(508600001)(36860700001)(8936002)(81166007)(36756003)(356005)(7696005)(83380400001)(54906003)(47076005)(8676002)(6666004)(110136005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:03:32.3802 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb807444-c7ae-408a-6acd-08d99adc82ad X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4834 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Steven Noonan According to the ACPI v6.2 (and later) specification, SystemIO can be used for _CPC registers. This teaches cppc_acpi how to handle such registers. This patch was tested using the amd_pstate driver on my Zephyrus G15 (model GA503QS) using the current version 410 BIOS, which uses a SystemIO register for the HighestPerformance element in _CPC. Signed-off-by: Steven Noonan Signed-off-by: Huang Rui --- drivers/acpi/cppc_acpi.c | 46 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 43 insertions(+), 3 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index bd482108310c..444c7a4605ad 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -759,9 +759,24 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr) goto out_free; cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr; } + } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { + if (gas_t->access_width < 1 || gas_t->access_width > 3) { + /* 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit. SystemIO doesn't + * implement 64-bit registers. + */ + pr_debug("Invalid access width %d for SystemIO register\n", + gas_t->access_width); + goto out_free; + } + if (gas_t->address & ~0xFFFFULL) { + /* SystemIO registers use 16-bit integer addresses */ + pr_debug("Invalid IO port %llu for SystemIO register\n", + gas_t->address); + goto out_free; + } } else { if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) { - /* Support only PCC ,SYS MEM and FFH type regs */ + /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */ pr_debug("Unsupported register type: %d\n", gas_t->space_id); goto out_free; } @@ -936,7 +951,20 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) } *val = 0; - if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) + + if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { + u32 width = 8 << (reg->access_width - 1); + acpi_status status; + + status = acpi_os_read_port((acpi_io_address)reg->address, (u32 *)val, width); + + if (status != AE_OK) { + pr_debug("Error: Failed to read SystemIO port %llx\n", reg->address); + return -EFAULT; + } + + return 0; + } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) vaddr = reg_res->sys_mem_vaddr; @@ -975,7 +1003,19 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); struct cpc_reg *reg = ®_res->cpc_entry.reg; - if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) + if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { + u32 width = 8 << (reg->access_width - 1); + acpi_status status; + + status = acpi_os_write_port((acpi_io_address)reg->address, (u32)val, width); + + if (status != AE_OK) { + pr_debug("Error: Failed to write SystemIO port %llx\n", reg->address); + return -EFAULT; + } + + return 0; + } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) vaddr = reg_res->sys_mem_vaddr; From patchwork Fri Oct 29 13:02:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12592661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BFBAC433EF for ; Fri, 29 Oct 2021 13:03:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 86C6961165 for ; Fri, 29 Oct 2021 13:03:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231695AbhJ2NGR (ORCPT ); Fri, 29 Oct 2021 09:06:17 -0400 Received: from mail-bn8nam12on2055.outbound.protection.outlook.com ([40.107.237.55]:46908 "EHLO NAM12-BN8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S230273AbhJ2NGI (ORCPT ); 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Fri, 29 Oct 2021 13:03:37 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT019.mail.protection.outlook.com (10.13.176.158) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Fri, 29 Oct 2021 13:03:37 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Fri, 29 Oct 2021 08:03:32 -0500 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 04/21] ACPI: CPPC: Check present CPUs for determining _CPC is valid Date: Fri, 29 Oct 2021 21:02:24 +0800 Message-ID: <20211029130241.1984459-5-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ab09a66f-1b2c-4776-dc33-08d99adc856e X-MS-TrafficTypeDiagnostic: MN2PR12MB3392: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0UA8lkwEv2IEHMX8ctnoviaSQbJk7dWuvwZhEEL/ASeigSQuHJtxpTfDyPsVJFmrXzT/okzKMYiJRi8G9yGkYw16ovSz/L0/QphP/Et+VfGqzKq/gUsLEWLgVDtz2rBwxjgG8PDMMAlpIMfWaF6+nfkb4UDchct4H9bCNBdj5lrLaRKmQwq3YQM+HzTr9F5FBL7tF0na8yPhnSVIpQCWv47sq+IGHcDnUg+Pn2X9Cg1LU27l4r4Po4+KLAgcR94FlCSkybNR2ODw5oRLT7XxljueUHqY0n7iDfk4jCN+g3XBgg8cbXTWUVxf9/qnTxaGOhFG4KbpEJF8dx9jCjlcoJPAf4QrZk7yItUPgCC37wYWvYqDxhg0+yasK4H+R/9fPiTEP7cQspEpkN6DphH1dO4hSXiFxnPqTo1lo7HLJEwNfexA6icXtRLZO6jvGqxeGN/1k67o+LRpiJI30eksACcncXkRFySm1D7HBS8kgg8B4qcBYyezx/kEmW4wcCr15dgOnsOgeYVlIsJ8Pu2dq28dE5rFdR4Z4Sp9a93QsigPk0Wa2TZ3EEIXrryr8OUINH1EoDc3iqbxnRD7zFOq42L07uphWr1WzZD4OBFPq5ojpB8ypeiRgWCC/wHwbEmopUu5NdYGdTq02di1/ZM/mGf4iqZ9dDMSjtvjrDbekjiyTHQhFLWGRMLR13pwWkbxSAdsO6qii4w/vANUbIeqxrmjTPnSDFSfFRKIuvG5Bj8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(26005)(70206006)(8676002)(8936002)(110136005)(36756003)(54906003)(83380400001)(1076003)(316002)(5660300002)(7696005)(82310400003)(6666004)(2906002)(426003)(2616005)(356005)(508600001)(86362001)(70586007)(47076005)(336012)(81166007)(36860700001)(186003)(16526019)(7416002)(4326008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:03:37.1283 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ab09a66f-1b2c-4776-dc33-08d99adc856e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3392 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Mario Limonciello As this is a static check, it should be based upon what is currently present on the system. This makes probeing more deterministic. While local APIC flags field (lapic_flags) of cpu core in MADT table is 0, then the cpu core won't be enabled. In this case, _CPC won't be found in this core, and return back to _CPC invalid with walking through possible cpus (include disable cpus). This is not expected, so switch to check present CPUs instead. Reported-by: Jinzhou Su Signed-off-by: Mario Limonciello Signed-off-by: Huang Rui --- drivers/acpi/cppc_acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 444c7a4605ad..c9169c221209 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -411,7 +411,7 @@ bool acpi_cpc_valid(void) struct cpc_desc *cpc_ptr; int cpu; - for_each_possible_cpu(cpu) { + for_each_present_cpu(cpu) { cpc_ptr = per_cpu(cpc_desc_ptr, cpu); if (!cpc_ptr) return false; From patchwork Fri Oct 29 13:02:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12592663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DC7FC433F5 for ; Fri, 29 Oct 2021 13:03:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8807E60FC4 for ; Fri, 29 Oct 2021 13:03:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231791AbhJ2NGV (ORCPT ); Fri, 29 Oct 2021 09:06:21 -0400 Received: from mail-bn8nam12on2068.outbound.protection.outlook.com ([40.107.237.68]:52033 "EHLO NAM12-BN8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231675AbhJ2NGO (ORCPT ); Fri, 29 Oct 2021 09:06:14 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=kyRcwCQK8+3GcmMqblC+5XhSKhXanOVzrUy7r0Xei/MsUnJeozTU0N0s4nzbKDNN3uteGTAI2DTiN7G6q2i5Pwn/jV56K6xIl2maG6lyao5TQKCw8xGu9ab11qypUN0okVvpH++kuPSy3LywENzhI7z5nXhSiQDd/KzAsU/NCWvBQcsJaExKGkIv9DN/XkAkrl23/9pgYEOwLhJ6Q1FPtcVDeukRPRH9Dcn6Y1hotOLVxuBdeo5ff7uAK2fOFkbsTbH/nrOo9+v1N30V+BbKbi7DRI5Sd/y2e396jo8NMpS4t0HfAEBUbeZZxe02hHw1Liub91dz87AmUm2Vt79f/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ulqWiFO2OQVl+qsQNAFOw9lFRIZakoliWCa7zqH7RTI=; b=bY0RFVqo6KgENFy+yGe11OGorIBor28jiWzPL78n7oNu0bCkUoKktrQe+R5NkzMsLM6mGEdgqMPp2nB2vp7oyRN4oJbOrnqIATbRxvhoopFNrCQl6uIdgpWA4c7Kzq7wtj22hMaQq9jVqUWDk9BxgRn1I7W5x9Ji7xSOxruxyPFKd/1pUjaNibB+86sGfJbGWS04AtVTaQZzhwmfN2ehdEmIYiBj6zCkOB374giujjAleMei8FKcdGsaYej3FvMrVei3Q+X9kQWreGENuCZwrj5QdV7uEX4ESDd4Tzet3XRu8yj/azd7xzqCto8uz1XU7IQvXG9htMweK5y2EJoo6A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ulqWiFO2OQVl+qsQNAFOw9lFRIZakoliWCa7zqH7RTI=; b=4qSSFrXbgV6CSeCwZDOJk8LDRo80kwN2SdLVEtnNuBdeBpnBeCOCBgjsiKuAJdKRIY9uLUzgbeZOpNzs2kw0LUDFIH5INOE8PXAbSDav1GXxsmN7jbPB2SI0IfCv+LIMmDUNg5zKF0axVZwzJlmgMmtSKHXwsockcICZ9jEHvlg= Received: from BN9PR03CA0574.namprd03.prod.outlook.com (2603:10b6:408:10d::9) by BL1PR12MB5174.namprd12.prod.outlook.com (2603:10b6:208:31c::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.14; Fri, 29 Oct 2021 13:03:41 +0000 Received: from BN8NAM11FT034.eop-nam11.prod.protection.outlook.com (2603:10b6:408:10d:cafe::5f) by BN9PR03CA0574.outlook.office365.com (2603:10b6:408:10d::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.14 via Frontend Transport; Fri, 29 Oct 2021 13:03:41 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT034.mail.protection.outlook.com (10.13.176.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Fri, 29 Oct 2021 13:03:41 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Fri, 29 Oct 2021 08:03:36 -0500 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 05/21] ACPI: CPPC: add cppc enable register function Date: Fri, 29 Oct 2021 21:02:25 +0800 Message-ID: <20211029130241.1984459-6-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 393fe9d7-e514-498f-25e4-08d99adc87ff X-MS-TrafficTypeDiagnostic: BL1PR12MB5174: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: E38YsRBVzyyKD7mx4SVSEWG07TmpGhDqPtLaBZUg41mpgxuQxxG+nMFZHdc93CKkbXGFk9/6+13uLdoIMd3qHXr8qLBSusAHV8m1FknmKyKlyd0ArTzdXzxqCspRx3gNUhVYgR75HhC/4kogzy8EKaQj0UOodEPHoBq7J1sM3VxqpC7tHX2ByX9nMc8Hw7740l8FttGkjw6XNjjUYAzIkU+Pj3FTDb8KINxaMh47EOehpOIUL6DeCfEqVZ8WmZamO0sbnN3MayxAov+nn3HzyEjDGxUSBj86YmuDEMVTobTDcQL0Em5OSwDnHMfG8aM7V/2p0BlYJLoQAx6MMt+/x827AbmicZouIRQB5LoaW+/FUNmCz0wR6v7NJv7V/lMXWs50CsO8fg+kkzsInc5HAhE/ULrIWlGMlIq/6V5xeGXiGwYSRvYXsADbRA1TnzPFJYrrLQdYIGqHt+Q7Ui7YrcoItgwHMm7+klo6chP36Ag0aGz5mTHYiZ1yNq9g0xulf6J8JZsTgEegouLRfgAr84SXqu3eVcABWCJtHkg/jpX7gjBjFdnfn2cxNipQfz85TfYjm9kvbZp0dqziVkMbOsxtzjtWtkkvhckA5v5mwUcjp3CIcoXLBc0/8SPhHHVivN689/nPbVBCr4CHRQle2qRZK63f2xNC0unJS/dbNT+/gfsgICuBhoqPPAtICE9d+Da2nqTrumPewmeR+yvhMyi1HrDjolhDNDBdRyEsOfU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(70586007)(186003)(16526019)(7696005)(426003)(70206006)(26005)(5660300002)(336012)(83380400001)(86362001)(47076005)(1076003)(8676002)(2906002)(6666004)(82310400003)(36756003)(110136005)(356005)(508600001)(2616005)(8936002)(36860700001)(54906003)(4326008)(316002)(7416002)(81166007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:03:41.3884 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 393fe9d7-e514-498f-25e4-08d99adc87ff X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5174 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Jinzhou Su Add a new function to enable CPPC feature. This function will write Continuous Performance Control package EnableRegister field on the processor. CPPC EnableRegister register described in section 8.4.7.1 of ACPI 6.4: This element is optional. If supported, contains a resource descriptor with a single Register() descriptor that describes a register to which OSPM writes a One to enable CPPC on this processor. Before this register is set, the processor will be controlled by legacy mechanisms (ACPI Pstates, firmware, etc.). This register will be used for AMD processors to enable amd-pstate function instead of legacy ACPI P-States. Signed-off-by: Jinzhou Su Signed-off-by: Huang Rui --- drivers/acpi/cppc_acpi.c | 45 ++++++++++++++++++++++++++++++++++++++++ include/acpi/cppc_acpi.h | 5 +++++ 2 files changed, 50 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index c9169c221209..2d2297ef5bf9 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1275,6 +1275,51 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) } EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); +/** + * cppc_set_enable - Set to enable CPPC on the processor by writing the + * Continuous Performance Control package EnableRegister feild. + * @cpu: CPU for which to enable CPPC register. + * @enable: 0 - disable, 1 - enable CPPC feature on the processor. + * + * Return: 0 for success, -ERRNO or -EIO otherwise. + */ +int cppc_set_enable(int cpu, bool enable) +{ + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cpc_register_resource *enable_reg; + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = -EINVAL; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpu); + return -EINVAL; + } + + enable_reg = &cpc_desc->cpc_regs[ENABLE]; + + if (CPC_IN_PCC(enable_reg)) { + + if (pcc_ss_id < 0) + return -EIO; + + ret = cpc_write(cpu, enable_reg, enable); + if (ret) + return ret; + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + /* after writing CPC, transfer the ownership of PCC to platfrom */ + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); + up_write(&pcc_ss_data->pcc_lock); + return ret; + } + + return cpc_write(cpu, enable_reg, enable); +} +EXPORT_SYMBOL_GPL(cppc_set_enable); + /** * cppc_set_perf - Set a CPU's performance controls. * @cpu: CPU for which to set performance controls. diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index bc159a9b4a73..92b7ea8d8f5e 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -138,6 +138,7 @@ extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); extern int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); +extern int cppc_set_enable(int cpu, bool enable); extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); extern bool acpi_cpc_valid(void); extern int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data); @@ -162,6 +163,10 @@ static inline int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) { return -ENOTSUPP; } +static inline int cppc_set_enable(int cpu, bool enable) +{ + return -ENOTSUPP; +} static inline int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps) { return -ENOTSUPP; From patchwork Fri Oct 29 13:02:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12592665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 134FFC43219 for ; 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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 06/21] cpufreq: amd: introduce a new amd pstate driver to support future processors Date: Fri, 29 Oct 2021 21:02:26 +0800 Message-ID: <20211029130241.1984459-7-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7fc5cfe1-27c1-4cf4-912d-08d99adc8bd7 X-MS-TrafficTypeDiagnostic: DM6PR12MB4089: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: G53FwXhl9hPtbsmmYZq+I93v9UtpIjXV+RTCGcll6/6TS90zSaKu5OsT0AwFwtht9G6rgKxjxfCrmce25kq97J16tHZ1T+F8SPdGUKrI3EPIrwzQXRY5tzTrrD9Td+HLquzwasK1OWzb8uu4NVphSqym8iPWUuCFU00BW4DElqOYkXifPKMrDvSqDUQBzu4pELDBLPxEdVOl2xyP3ucS3A93+5qVsJC/7WafecAM4/o1IO3QLUnUZ5Z2kqXU98pL4Q6hWyrMq3a5nBMpFD9VHKFXSgmCMm+wp189110pYDpul9IXk3J7OWh6TgSQ0cki0HGLceIyoVlBbV/dqsQXqwkAw0N66WecU5yM3nbLjEBYqFb5RgwKHZHrzi+/ASQCGqr8hKdbZcgWLjkZLvffRmf6NvLUfBoK7/78Kt9h8HnSCi4hEhBJ4NpGhuoP2h9mT+skpbdKIUXNkEWewUAchuY6BdYoyU4TxKSEzyus/9FEuDBM7ncTmFMTnGovdJIkgeUMF87h+wfarKxX2e1FwjpKpFKkevC6nzFm4THQRcZMx3sXyE/uYNcK68H0TLUrpPAN9LG9lNK2wRWfJhzczPK02K6x+cV0A99WkjDpSkn15Rgh9L7Haozd0VMkVS6m+Rp57xdnrcsQBiVAg5uRKcixphtlmXhUyiL27AUS9Tf18rwaiVEqcKOdnCMN/N0wjnjC/Ph/s38pTxnxpKv1BIv5tfdb8Lyr5O/aOWFEkMkapL5qyEGSx4U5tJb6fFQt5+6e/QxUZf8sBqyXc0WaCz+WuCvdhuAA0wXQT17hoxO4YZTiZlj/FbRcmK0Fz1X0YHsK3/Vwf8BapNthv9CZmg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(508600001)(47076005)(8676002)(36756003)(30864003)(966005)(26005)(7416002)(16526019)(186003)(6666004)(8936002)(70206006)(70586007)(86362001)(2616005)(1076003)(63350400001)(426003)(36860700001)(63370400001)(82310400003)(5660300002)(336012)(316002)(2906002)(54906003)(110136005)(4326008)(356005)(81166007)(83380400001)(7696005)(2004002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:03:47.4381 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7fc5cfe1-27c1-4cf4-912d-08d99adc8bd7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT068.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4089 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org amd-pstate is the AMD CPU performance scaling driver that introduces a new CPU frequency control mechanism on AMD Zen based CPU series in Linux kernel. The new mechanism is based on Collaborative processor performance control (CPPC) which is finer grain frequency management than legacy ACPI hardware P-States. Current AMD CPU platforms are using the ACPI P-states driver to manage CPU frequency and clocks with switching only in 3 P-states. AMD P-States is to replace the ACPI P-states controls, allows a flexible, low-latency interface for the Linux kernel to directly communicate the performance hints to hardware. "amd-pstate" leverages the Linux kernel governors such as *schedutil*, *ondemand*, etc. to manage the performance hints which are provided by CPPC hardware functionality. The first version for amd-pstate is to support one of the Zen3 processors, and we will support more in future after we verify the hardware and SBIOS functionalities. There are two types of hardware implementations for amd-pstate: one is full MSR support and another is shared memory support. It can use X86_FEATURE_AMD_CPPC_EXT feature flag to distinguish the different types. Using the new AMD P-States method + kernel governors (*schedutil*, *ondemand*, ...) to manage the frequency update is the most appropriate bridge between AMD Zen based hardware processor and Linux kernel, the processor is able to ajust to the most efficiency frequency according to the kernel scheduler loading. Performance Per Watt (PPW) Caculation: The PPW caculation is referred by below paper: https://software.intel.com/content/dam/develop/external/us/en/documents/performance-per-what-paper.pdf Below formula is referred from below spec to measure the PPW: (F / t) / P = F * t / (t * E) = F / E, "F" is the number of frames per second. "P" is power measurd in watts. "E" is energy measured in joules. We use the RAPL interface with "perf" tool to get the energy data of the package power. The data comparsions between amd-pstate and acpi-freq module are tested on AMD Cezanne processor: 1) TBench CPU benchmark: +---------------------------------------------------------------------+ | | | TBench (Performance Per Watt) | | Higher is better | +-------------------+------------------------+------------------------+ | | Performance Per Watt | Performance Per Watt | | Kernel Module | (Schedutil) | (Ondemand) | | | Unit: MB / (s * J) | Unit: MB / (s * J) | +-------------------+------------------------+------------------------+ | | | | | acpi-cpufreq | 3.022 | 2.969 | | | | | +-------------------+------------------------+------------------------+ | | | | | amd-pstate | 3.131 | 3.284 | | | | | +-------------------+------------------------+------------------------+ 2) Gitsource CPU benchmark: +---------------------------------------------------------------------+ | | | Gitsource (Performance Per Watt) | | Higher is better | +-------------------+------------------------+------------------------+ | | Performance Per Watt | Performance Per Watt | | Kernel Module | (Schedutil) | (Ondemand) | | | Unit: 1 / (s * J) | Unit: 1 / (s * J) | +-------------------+------------------------+------------------------+ | | | | | acpi-cpufreq | 3.42172E-07 | 2.74508E-07 | | | | | +-------------------+------------------------+------------------------+ | | | | | amd-pstate | 4.09141E-07 | 3.47610E-07 | | | | | +-------------------+------------------------+------------------------+ 3) Speedometer 2.0 CPU benchmark: +---------------------------------------------------------------------+ | | | Speedometer 2.0 (Performance Per Watt) | | Higher is better | +-------------------+------------------------+------------------------+ | | Performance Per Watt | Performance Per Watt | | Kernel Module | (Schedutil) | (Ondemand) | | | Unit: 1 / (s * J) | Unit: 1 / (s * J) | +-------------------+------------------------+------------------------+ | | | | | acpi-cpufreq | 0.116111767 | 0.110321664 | | | | | +-------------------+------------------------+------------------------+ | | | | | amd-pstate | 0.115825281 | 0.122024299 | | | | | +-------------------+------------------------+------------------------+ According to above average data, we can see this solution has shown better performance per watt scaling on mobile CPU benchmarks in most of cases. Signed-off-by: Huang Rui --- drivers/cpufreq/Kconfig.x86 | 17 ++ drivers/cpufreq/Makefile | 1 + drivers/cpufreq/amd-pstate.c | 413 +++++++++++++++++++++++++++++++++++ 3 files changed, 431 insertions(+) create mode 100644 drivers/cpufreq/amd-pstate.c diff --git a/drivers/cpufreq/Kconfig.x86 b/drivers/cpufreq/Kconfig.x86 index 92701a18bdd9..2e798b2c0bdb 100644 --- a/drivers/cpufreq/Kconfig.x86 +++ b/drivers/cpufreq/Kconfig.x86 @@ -34,6 +34,23 @@ config X86_PCC_CPUFREQ If in doubt, say N. +config X86_AMD_PSTATE + bool "AMD Processor P-State driver" + depends on X86 + select ACPI_PROCESSOR if ACPI + select ACPI_CPPC_LIB if X86_64 && ACPI && SCHED_MC_PRIO + select CPU_FREQ_GOV_SCHEDUTIL if SMP + help + This driver adds a CPUFreq driver which utilizes a fine grain + processor performance freqency control range instead of legacy + performance levels. This driver supports the AMD processors with + _CPC object in the SBIOS. + + For details, take a look at: + . + + If in doubt, say N. + config X86_ACPI_CPUFREQ tristate "ACPI Processor P-States driver" depends on ACPI_PROCESSOR diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 48ee5859030c..c8d307010922 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_CPUFREQ_DT_PLATDEV) += cpufreq-dt-platdev.o # speedstep-* is preferred over p4-clockmod. obj-$(CONFIG_X86_ACPI_CPUFREQ) += acpi-cpufreq.o +obj-$(CONFIG_X86_AMD_PSTATE) += amd-pstate.o obj-$(CONFIG_X86_POWERNOW_K8) += powernow-k8.o obj-$(CONFIG_X86_PCC_CPUFREQ) += pcc-cpufreq.o obj-$(CONFIG_X86_POWERNOW_K6) += powernow-k6.o diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c new file mode 100644 index 000000000000..a400861c7fdc --- /dev/null +++ b/drivers/cpufreq/amd-pstate.c @@ -0,0 +1,413 @@ +/* + * amd-pstate.c - AMD Processor P-state Frequency Driver + * + * Copyright (C) 2021 Advanced Micro Devices, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * Author: Huang Rui + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#define AMD_PSTATE_TRANSITION_LATENCY 0x20000 +#define AMD_PSTATE_TRANSITION_DELAY 500 + +static struct cpufreq_driver amd_pstate_driver; + +struct amd_cpudata { + int cpu; + + struct freq_qos_request req[2]; + + u64 cppc_req_cached; + + u32 highest_perf; + u32 nominal_perf; + u32 lowest_nonlinear_perf; + u32 lowest_perf; + + u32 max_freq; + u32 min_freq; + u32 nominal_freq; + u32 lowest_nonlinear_freq; +}; + +static inline int pstate_enable(bool enable) +{ + return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable ? 1 : 0); +} + +DEFINE_STATIC_CALL(amd_pstate_enable, pstate_enable); + +static inline int amd_pstate_enable(bool enable) +{ + return static_call(amd_pstate_enable)(enable); +} + +static int pstate_init_perf(struct amd_cpudata *cpudata) +{ + u64 cap1; + + int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, + &cap1); + if (ret) + return ret; + + /* + * TODO: Introduce AMD specific power feature. + * + * CPPC entry doesn't indicate the highest performance in some ASICs. + */ + WRITE_ONCE(cpudata->highest_perf, amd_get_highest_perf()); + + WRITE_ONCE(cpudata->nominal_perf, CAP1_NOMINAL_PERF(cap1)); + WRITE_ONCE(cpudata->lowest_nonlinear_perf, CAP1_LOWNONLIN_PERF(cap1)); + WRITE_ONCE(cpudata->lowest_perf, CAP1_LOWEST_PERF(cap1)); + + return 0; +} + +DEFINE_STATIC_CALL(amd_pstate_init_perf, pstate_init_perf); + +static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata) +{ + return static_call(amd_pstate_init_perf)(cpudata); +} + +static void pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf, + u32 des_perf, u32 max_perf, bool fast_switch) +{ + if (fast_switch) + wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached)); + else + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, + READ_ONCE(cpudata->cppc_req_cached)); +} + +DEFINE_STATIC_CALL(amd_pstate_update_perf, pstate_update_perf); + +static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata, + u32 min_perf, u32 des_perf, + u32 max_perf, bool fast_switch) +{ + static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf, + max_perf, fast_switch); +} + +static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, + u32 des_perf, u32 max_perf, bool fast_switch) +{ + u64 prev = READ_ONCE(cpudata->cppc_req_cached); + u64 value = prev; + + value &= ~REQ_MIN_PERF(~0L); + value |= REQ_MIN_PERF(min_perf); + + value &= ~REQ_DES_PERF(~0L); + value |= REQ_DES_PERF(des_perf); + + value &= ~REQ_MAX_PERF(~0L); + value |= REQ_MAX_PERF(max_perf); + + if (value == prev) + return; + + WRITE_ONCE(cpudata->cppc_req_cached, value); + + amd_pstate_update_perf(cpudata, min_perf, des_perf, + max_perf, fast_switch); +} + +static int amd_pstate_verify(struct cpufreq_policy_data *policy) +{ + cpufreq_verify_within_cpu_limits(policy); + + return 0; +} + +static int amd_pstate_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + struct cpufreq_freqs freqs; + struct amd_cpudata *cpudata = policy->driver_data; + unsigned long amd_max_perf, amd_min_perf, amd_des_perf, + amd_cap_perf; + + if (!cpudata->max_freq) + return -ENODEV; + + amd_cap_perf = READ_ONCE(cpudata->highest_perf); + amd_min_perf = READ_ONCE(cpudata->lowest_nonlinear_perf); + amd_max_perf = amd_cap_perf; + + freqs.old = policy->cur; + freqs.new = target_freq; + + amd_des_perf = DIV_ROUND_CLOSEST(target_freq * amd_cap_perf, + cpudata->max_freq); + + cpufreq_freq_transition_begin(policy, &freqs); + amd_pstate_update(cpudata, amd_min_perf, amd_des_perf, + amd_max_perf, false); + cpufreq_freq_transition_end(policy, &freqs, false); + + return 0; +} + +static int amd_get_min_freq(struct amd_cpudata *cpudata) +{ + struct cppc_perf_caps cppc_perf; + + int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); + if (ret) + return ret; + + /* Switch to khz */ + return cppc_perf.lowest_freq * 1000; +} + +static int amd_get_max_freq(struct amd_cpudata *cpudata) +{ + struct cppc_perf_caps cppc_perf; + u32 max_perf, max_freq, nominal_freq, nominal_perf; + u64 boost_ratio; + + int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); + if (ret) + return ret; + + nominal_freq = cppc_perf.nominal_freq; + nominal_perf = READ_ONCE(cpudata->nominal_perf); + max_perf = READ_ONCE(cpudata->highest_perf); + + boost_ratio = div_u64(max_perf << SCHED_CAPACITY_SHIFT, + nominal_perf); + + max_freq = nominal_freq * boost_ratio >> SCHED_CAPACITY_SHIFT; + + /* Switch to khz */ + return max_freq * 1000; +} + +static int amd_get_nominal_freq(struct amd_cpudata *cpudata) +{ + struct cppc_perf_caps cppc_perf; + u32 nominal_freq; + + int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); + if (ret) + return ret; + + nominal_freq = cppc_perf.nominal_freq; + + /* Switch to khz */ + return nominal_freq * 1000; +} + +static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata) +{ + struct cppc_perf_caps cppc_perf; + u32 lowest_nonlinear_freq, lowest_nonlinear_perf, + nominal_freq, nominal_perf; + u64 lowest_nonlinear_ratio; + + int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); + if (ret) + return ret; + + nominal_freq = cppc_perf.nominal_freq; + nominal_perf = READ_ONCE(cpudata->nominal_perf); + + lowest_nonlinear_perf = cppc_perf.lowest_nonlinear_perf; + + lowest_nonlinear_ratio = div_u64(lowest_nonlinear_perf << + SCHED_CAPACITY_SHIFT, nominal_perf); + + lowest_nonlinear_freq = nominal_freq * lowest_nonlinear_ratio >> SCHED_CAPACITY_SHIFT; + + /* Switch to khz */ + return lowest_nonlinear_freq * 1000; +} + +static int amd_pstate_cpu_init(struct cpufreq_policy *policy) +{ + int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; + unsigned int cpu = policy->cpu; + struct device *dev; + struct amd_cpudata *cpudata; + + dev = get_cpu_device(policy->cpu); + if (!dev) + return -ENODEV; + + cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL); + if (!cpudata) + return -ENOMEM; + + cpudata->cpu = cpu; + + ret = amd_pstate_init_perf(cpudata); + if (ret) + goto free_cpudata1; + + min_freq = amd_get_min_freq(cpudata); + max_freq = amd_get_max_freq(cpudata); + nominal_freq = amd_get_nominal_freq(cpudata); + lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata); + + if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) { + dev_err(dev, "min_freq(%d) or max_freq(%d) value is incorrect\n", + min_freq, max_freq); + ret = -EINVAL; + goto free_cpudata1; + } + + policy->cpuinfo.transition_latency = AMD_PSTATE_TRANSITION_LATENCY; + policy->transition_delay_us = AMD_PSTATE_TRANSITION_DELAY; + + policy->min = min_freq; + policy->max = max_freq; + + policy->cpuinfo.min_freq = min_freq; + policy->cpuinfo.max_freq = max_freq; + + /* It will be updated by governor */ + policy->cur = policy->cpuinfo.min_freq; + + ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], + FREQ_QOS_MIN, policy->cpuinfo.min_freq); + if (ret < 0) { + dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); + goto free_cpudata1; + } + + ret = freq_qos_add_request(&policy->constraints, &cpudata->req[1], + FREQ_QOS_MAX, policy->cpuinfo.max_freq); + if (ret < 0) { + dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); + goto free_cpudata2; + } + + /* Initial processor data capability frequencies */ + cpudata->max_freq = max_freq; + cpudata->min_freq = min_freq; + cpudata->nominal_freq = nominal_freq; + cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq; + + policy->driver_data = cpudata; + + return 0; + + freq_qos_remove_request(&cpudata->req[1]); +free_cpudata2: + freq_qos_remove_request(&cpudata->req[0]); +free_cpudata1: + kfree(cpudata); + return ret; +} + +static int amd_pstate_cpu_exit(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata; + + cpudata = policy->driver_data; + + freq_qos_remove_request(&cpudata->req[1]); + freq_qos_remove_request(&cpudata->req[0]); + kfree(cpudata); + + return 0; +} + +static struct cpufreq_driver amd_pstate_driver = { + .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, + .verify = amd_pstate_verify, + .target = amd_pstate_target, + .init = amd_pstate_cpu_init, + .exit = amd_pstate_cpu_exit, + .name = "amd-pstate", +}; + +static int __init amd_pstate_init(void) +{ + int ret; + + if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) + return -ENODEV; + + if (!acpi_cpc_valid()) { + pr_debug("%s, the _CPC object is not present in SBIOS\n", + __func__); + return -ENODEV; + } + + /* don't keep reloading if cpufreq_driver exists */ + if (cpufreq_get_current_driver()) + return -EEXIST; + + /* capability check */ + if (!boot_cpu_has(X86_FEATURE_AMD_CPPC)) { + pr_debug("%s, AMD CPPC MSR based functionality is not supported\n", + __func__); + return -ENODEV; + } + + /* enable amd pstate feature */ + ret = amd_pstate_enable(true); + if (ret) { + pr_err("%s, failed to enable amd-pstate with return %d\n", + __func__, ret); + return ret; + } + + ret = cpufreq_register_driver(&amd_pstate_driver); + if (ret) { + pr_err("%s, return %d\n", __func__, ret); + return ret; + } + + return 0; +} + +device_initcall(amd_pstate_init); + +MODULE_AUTHOR("Huang Rui "); +MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver"); +MODULE_LICENSE("GPL"); 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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 07/21] cpufreq: amd: add fast switch function for amd-pstate Date: Fri, 29 Oct 2021 21:02:27 +0800 Message-ID: <20211029130241.1984459-8-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 617ea4af-10ca-41dc-7ec9-08d99adc8e3e X-MS-TrafficTypeDiagnostic: MWHPR12MB1135: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2803; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0Prm7UN0GTyrPXIVnMWbXPuD5coFBGq5w/tsusNJnNg1eL0w6asxEKbGBLR7ZetbJG4kp1e1AgLDlO0IKe+m5BS6uEujlQmJ5QI3pzncDL+E+ucTe549ffBa3n0aXQ/ujAludZhaipGSZIC/4uF0242PY1rlF/CttzuNSGqs0r0PwDGCbPKKVHhttjj4zr23nedKT5l5q/rIRtZk3+ntOV2IStzkm8QcSs/XE5I+XY0pS0gkF/5N+Ex3u09pgNogEnKRTicn6B6qC+D3wVxdcQXIKNuCWjTWNCq2laH/kSuDYSCz8W0xvXr50K81iDpfi3eG/2vvP5Tl4+qKEwZ5cgFkdmGitb0+bJaM+6hhHIPK5Rflgyhn0dVYG14aMpiy7gsSwysUHYYTjILXs0TPGJ6sLc86iR08LCdcD0Q9RxTFyXsCrt7qbVKg5aiNUL8xh9vSACiQl+RMq/hIEpr44+UkP9pp/6z/dgApHhRKLT0LHRWvr/HvgfJzODygNHGJR7smiXs6LxDM65g4knC9oS++LS/IfheR48pC5bjxa5GoZRbuN0ury6YaupR5tJXSQjt6u0Bw2DYUVFj1EyHvQjzErv5Tzf7vn1tlejzLpHODyn6rX/GjnCuKTUizPyeDuqgjtqq7KAX4znIMm37WcL8hrLty4Ll4NCZc11QQcJrlDeIUh7hfB61MDDSNOT2/M6avzWcadSicxGgEd9XppHTtAtkPPNo6pwI7pp187pY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(7416002)(54906003)(336012)(83380400001)(356005)(508600001)(186003)(47076005)(2906002)(426003)(2616005)(82310400003)(70586007)(16526019)(70206006)(110136005)(8676002)(7696005)(4326008)(8936002)(86362001)(36756003)(26005)(1076003)(36860700001)(316002)(5660300002)(81166007)(6666004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:03:51.8949 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 617ea4af-10ca-41dc-7ec9-08d99adc8e3e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1135 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce the fast switch function for amd-pstate on the AMD processors which support the full MSR register control. It's able to decrease the lattency on interrupt context. Signed-off-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 38 ++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index a400861c7fdc..55ff03f85608 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -191,6 +191,41 @@ static int amd_pstate_target(struct cpufreq_policy *policy, return 0; } +static void amd_pstate_adjust_perf(unsigned int cpu, + unsigned long min_perf, + unsigned long target_perf, + unsigned long capacity) +{ + unsigned long amd_max_perf, amd_min_perf, amd_des_perf, + amd_cap_perf, lowest_nonlinear_perf; + struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); + struct amd_cpudata *cpudata = policy->driver_data; + + amd_cap_perf = READ_ONCE(cpudata->highest_perf); + lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf); + + if (target_perf < capacity) + amd_des_perf = DIV_ROUND_UP(amd_cap_perf * target_perf, + capacity); + + amd_min_perf = READ_ONCE(cpudata->highest_perf); + if (min_perf < capacity) + amd_min_perf = DIV_ROUND_UP(amd_cap_perf * min_perf, capacity); + + if (amd_min_perf < lowest_nonlinear_perf) + amd_min_perf = lowest_nonlinear_perf; + + amd_max_perf = amd_cap_perf; + if (amd_max_perf < amd_min_perf) + amd_max_perf = amd_min_perf; + + amd_des_perf = clamp_t(unsigned long, amd_des_perf, + amd_min_perf, amd_max_perf); + + amd_pstate_update(cpudata, amd_min_perf, amd_des_perf, + amd_max_perf, true); +} + static int amd_get_min_freq(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; @@ -311,6 +346,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) /* It will be updated by governor */ policy->cur = policy->cpuinfo.min_freq; + policy->fast_switch_possible = true; + ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], FREQ_QOS_MIN, policy->cpuinfo.min_freq); if (ret < 0) { @@ -360,6 +397,7 @@ static struct cpufreq_driver amd_pstate_driver = { .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, .verify = amd_pstate_verify, .target = amd_pstate_target, + .adjust_perf = amd_pstate_adjust_perf, .init = amd_pstate_cpu_init, .exit = amd_pstate_cpu_exit, .name = "amd-pstate", From patchwork Fri Oct 29 13:02:28 2021 Content-Type: text/plain; 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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 08/21] cpufreq: amd: add acpi cppc function as the backend for legacy processors Date: Fri, 29 Oct 2021 21:02:28 +0800 Message-ID: <20211029130241.1984459-9-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f2302096-d2c1-494e-2f9e-08d99adc911a X-MS-TrafficTypeDiagnostic: SN1PR12MB2415: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:268; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PEaQvijcXNu7FcVcas38QELywIzn0NqZvBah+yXB1jAn8ajW0xrP4QjBFxeonxMW1dwY/st1Mf97JukiwzVvLipG4lD4zZCn5Z+hAlzraJCveFjBJybzWBkOOIuHuW/eyY0JAIyZXj2ycQEIpn4nVnHFoLFqoWazQc7ZLc1YCxdy37P26ZYuGAdw98ReLs84CeSIY2Y1lN4C85ZcxJHaqL3NSdepRHqc07x1jfs4C3GwR2SFmg/dEFLZ5pUe9LbEMBWMw4QQat7BCqAk2/6byiqcgAivQSUlhpjy/5EQYdj+uOsKt54n8neOVrcPrlfAftUrFTO9LWL5r0T7bBK/W43aCHFttbfBDfCcr4Xbqlyl2GW3wnfEZw6sLH0G8XE3OgGSf3r2Pen3vBPg9GeJ56Ba276tP/zwZuh5d3lZlsO1iEc4s135DkXDC7QfxHkN3oeN07MVjhNiKC8mwjK9lHjMLKIfCr19jAYvatncpV/7bzWXI+1/FIJf5cHy1IXzOLk4rY8926BAZXEpXLmTvn57TKnzGqUQtQRa/Eia6UY0je42rqfnClXQ8jwYN//LYhSBVZCeJLsdmCArhskcHBPMgWwWtB/IhEERshCri3/eW2YmyZxP1nnnRfkpZmDyuEnjf4Lh91HtU5wLc2eACVM4VH11V4eztyXi5s8Ll/Dcx/rCCspJpGEmIpUllG1NQ28jSM22fRurtlCGmNb5iVB3hJ5XiQNyxHlny0bVScQ= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(426003)(1076003)(8676002)(7696005)(83380400001)(2616005)(6666004)(8936002)(336012)(36756003)(356005)(26005)(70206006)(7416002)(86362001)(81166007)(70586007)(186003)(508600001)(16526019)(47076005)(4326008)(5660300002)(82310400003)(2906002)(316002)(110136005)(54906003)(36860700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:03:56.7091 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2302096-d2c1-494e-2f9e-08d99adc911a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT033.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR12MB2415 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org In some old Zen based processors, they are using the shared memory that exposed from ACPI SBIOS. Signed-off-by: Jinzhou Su Signed-off-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 58 ++++++++++++++++++++++++++++++++---- 1 file changed, 53 insertions(+), 5 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 55ff03f85608..d399938d6d85 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -73,6 +73,19 @@ static inline int pstate_enable(bool enable) return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable ? 1 : 0); } +static int cppc_enable(bool enable) +{ + int cpu, ret = 0; + + for_each_online_cpu(cpu) { + ret = cppc_set_enable(cpu, enable ? 1 : 0); + if (ret) + return ret; + } + + return ret; +} + DEFINE_STATIC_CALL(amd_pstate_enable, pstate_enable); static inline int amd_pstate_enable(bool enable) @@ -103,6 +116,24 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) return 0; } +static int cppc_init_perf(struct amd_cpudata *cpudata) +{ + struct cppc_perf_caps cppc_perf; + + int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); + if (ret) + return ret; + + WRITE_ONCE(cpudata->highest_perf, amd_get_highest_perf()); + + WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); + WRITE_ONCE(cpudata->lowest_nonlinear_perf, + cppc_perf.lowest_nonlinear_perf); + WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf); + + return 0; +} + DEFINE_STATIC_CALL(amd_pstate_init_perf, pstate_init_perf); static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata) @@ -120,6 +151,19 @@ static void pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf, READ_ONCE(cpudata->cppc_req_cached)); } +static void cppc_update_perf(struct amd_cpudata *cpudata, + u32 min_perf, u32 des_perf, + u32 max_perf, bool fast_switch) +{ + struct cppc_perf_ctrls perf_ctrls; + + perf_ctrls.max_perf = max_perf; + perf_ctrls.min_perf = min_perf; + perf_ctrls.desired_perf = des_perf; + + cppc_set_perf(cpudata->cpu, &perf_ctrls); +} + DEFINE_STATIC_CALL(amd_pstate_update_perf, pstate_update_perf); static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata, @@ -346,7 +390,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) /* It will be updated by governor */ policy->cur = policy->cpuinfo.min_freq; - policy->fast_switch_possible = true; + if (boot_cpu_has(X86_FEATURE_AMD_CPPC)) + policy->fast_switch_possible = true; ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], FREQ_QOS_MIN, policy->cpuinfo.min_freq); @@ -397,7 +442,6 @@ static struct cpufreq_driver amd_pstate_driver = { .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, .verify = amd_pstate_verify, .target = amd_pstate_target, - .adjust_perf = amd_pstate_adjust_perf, .init = amd_pstate_cpu_init, .exit = amd_pstate_cpu_exit, .name = "amd-pstate", @@ -421,10 +465,14 @@ static int __init amd_pstate_init(void) return -EEXIST; /* capability check */ - if (!boot_cpu_has(X86_FEATURE_AMD_CPPC)) { - pr_debug("%s, AMD CPPC MSR based functionality is not supported\n", + if (boot_cpu_has(X86_FEATURE_AMD_CPPC)) { + pr_debug("%s, AMD CPPC MSR based functionality is supported\n", __func__); - return -ENODEV; + amd_pstate_driver.adjust_perf = amd_pstate_adjust_perf; + } else { + static_call_update(amd_pstate_enable, cppc_enable); + static_call_update(amd_pstate_init_perf, cppc_init_perf); + static_call_update(amd_pstate_update_perf, cppc_update_perf); } /* enable amd pstate feature */ From patchwork Fri Oct 29 13:02:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12592671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7726C433FE for ; Fri, 29 Oct 2021 13:04:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9605361184 for ; Fri, 29 Oct 2021 13:04:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231803AbhJ2NGo (ORCPT ); Fri, 29 Oct 2021 09:06:44 -0400 Received: from mail-co1nam11on2088.outbound.protection.outlook.com ([40.107.220.88]:48737 "EHLO NAM11-CO1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231810AbhJ2NGf (ORCPT ); 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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 09/21] cpufreq: amd: add trace for amd-pstate module Date: Fri, 29 Oct 2021 21:02:29 +0800 Message-ID: <20211029130241.1984459-10-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 986ed24c-4c46-4e05-c300-08d99adc93de X-MS-TrafficTypeDiagnostic: CH0PR12MB5186: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:73; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eQKf1MWLLiHxUsWW4PU9L6MKwah91Wg3/QZv39zKvdo6Addl16pg0ZNpiy68D64Qx5pGa1KmtVN5xsRAYOCloQItbXbEaIN7Sc0vJWacbYET7DNXSCaqIjaGAff9UBmfYsqjDVQyGjxP6DimVeQ0QVDOUxSo2z+Ft3YN1YVqamaQzWjTsHYG41/dMASICsG8XN6CwA77hato0jC93o95Q3YJwHqvofPE0l7brY3uLfq45o5vpEqbeT0t4yJPzo3izJynxoR3oaIw+N3Y1Rw3TorS5NGJ4FW98YZ7/jRhpo/7ymYnLpl5X/IHtv5icOhECPPAb06t4lcLzmKkf2TNt02L0Jcy2RVWCgonYs4CuslBAfdDjFumQEPIrv1PfyImK6+veD7ocdkJvNzbyYMt4tM+ggHjTmgUYdfw1Gn5aGMAiV4QDKtp37CU3X4EbaSDtjXxnQsV54m90PlTC0PsTEKpkuSfp2cTqNljSUboyqIPHICWwQslvmmUTzARaBEt0s77ZX3EStVh0r47Sx+OOV4QsBsOnpC617E/e+a+kyu2L7fgOiw59L37VTsDRFz5KbT/wMQmQix1t69F60uwWR05gB+OMGB5/FvCtmX1faC07zfG3MiEPvj6bQYXEePzAav8G+i37KuOL7JGoUThQzOr56KFwhnnL6Gw3lbUO66I7jSOSjTiS7ds2b94xVwaK6YiXNba5HyIbRnNYoiL1OLU/dSMvGwtEN06pjPm3NQ= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(83380400001)(5660300002)(2906002)(316002)(508600001)(82310400003)(16526019)(26005)(4326008)(356005)(110136005)(7696005)(6666004)(81166007)(54906003)(8936002)(86362001)(186003)(336012)(7416002)(36860700001)(426003)(2616005)(70586007)(8676002)(1076003)(70206006)(36756003)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:04:01.2279 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 986ed24c-4c46-4e05-c300-08d99adc93de X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5186 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add trace event to monitor the performance value changes which is controlled by cpu governors. Signed-off-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 4 ++++ include/trace/events/power.h | 46 ++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index d399938d6d85..6037590e82a6 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include @@ -189,6 +190,9 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, value &= ~REQ_MAX_PERF(~0L); value |= REQ_MAX_PERF(max_perf); + trace_amd_pstate_perf(min_perf, des_perf, max_perf, cpudata->cpu, + (value != prev), fast_switch); + if (value == prev) return; diff --git a/include/trace/events/power.h b/include/trace/events/power.h index af5018aa9517..c95c0b8d443d 100644 --- a/include/trace/events/power.h +++ b/include/trace/events/power.h @@ -173,6 +173,52 @@ TRACE_EVENT(cpu_frequency_limits, (unsigned long)__entry->cpu_id) ); +TRACE_EVENT(amd_pstate_perf, + + TP_PROTO(unsigned long min_perf, + unsigned long target_perf, + unsigned long capacity, + unsigned int cpu_id, + bool changed, + bool fast_switch + ), + + TP_ARGS(min_perf, + target_perf, + capacity, + cpu_id, + changed, + fast_switch + ), + + TP_STRUCT__entry( + __field(unsigned long, min_perf) + __field(unsigned long, target_perf) + __field(unsigned long, capacity) + __field(unsigned int, cpu_id) + __field(bool, changed) + __field(bool, fast_switch) + ), + + TP_fast_assign( + __entry->min_perf = min_perf; + __entry->target_perf = target_perf; + __entry->capacity = capacity; + __entry->cpu_id = cpu_id; + __entry->changed = changed; + __entry->fast_switch = fast_switch; + ), + + TP_printk("amd_min_perf=%lu amd_des_perf=%lu amd_max_perf=%lu cpu_id=%u changed=%s fast_switch=%s", + (unsigned long)__entry->min_perf, + (unsigned long)__entry->target_perf, + (unsigned long)__entry->capacity, + (unsigned int)__entry->cpu_id, + (__entry->changed) ? "true" : "false", + (__entry->fast_switch) ? "true" : "false" + ) +); + TRACE_EVENT(device_pm_callback_start, TP_PROTO(struct device *dev, const char *pm_ops, int event), From patchwork Fri Oct 29 13:02:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12592673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEEA1C433EF for ; Fri, 29 Oct 2021 13:04:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D89D761167 for ; Fri, 29 Oct 2021 13:04:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231946AbhJ2NGw (ORCPT ); Fri, 29 Oct 2021 09:06:52 -0400 Received: from mail-dm3nam07on2080.outbound.protection.outlook.com ([40.107.95.80]:3356 "EHLO NAM02-DM3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231755AbhJ2NGi (ORCPT ); Fri, 29 Oct 2021 09:06:38 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=BWmfxTdnBEROuUFid5NQ8vbLBvBWR/tbNYuf2Lqha8zSe6dVd28wW/w2JMy024gExNdaS95fL256EKWQBaZYyHtV7AbyPrmxm7ucN3X1pjgUrhWPSrbjVnY8YbZqorDAd99eslC0I6WWeXNMWJSfi3tGUSxY66G6pTQphxFC51Ybm3M5xBatM+hw3S4xQ/G/sZmWd2Eq+XZofdlyNTT3cxn4gsGrjQO0vDVoyv8GC2ERiPOVeZa4QN6w4EZlJeMVNjyASaW//EITOrqnuytu7Ex1peIL7u5TH/Sj7GLwWULFcXOdvFW/kZj/OLSfmtJ9T6Trx3q7CT3ixpUijvp+dQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=sK1Tx2TrB5J0aDp4pfCIUh4gDNku1ZU1OSw53PsLKkg=; b=Hrneai5qE2jhVQl6Z1PXDH04q21Rp/LN106AaLhut2Mj2eSwNutw3QZoh4X0yRNUXo8dq21h7WujUDJKeMItjVd1IAn3SXbp3xF/4B7Gczb4XKKNfdBVUzJkuG1g4mkXJZNiMXY8+0TaSWUcuTzpY2W7uvOTOU+9w49HuX1xKilkj9dJM71xazHoSAVtP0gUCQpTdt6YBkPpsScbOsCy7I0J/2yCrTNbkRfvRgBN5u6Y0u6s4Is0rb64/zgQyHoM3Bi0AqzBDp0Et6KOc8d/ukpJh7vOHGcVob7/eBLzsyOyYCUZ+pgYBTMlLWygFal829lCQj0Fevq5x+j6AbXxuA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sK1Tx2TrB5J0aDp4pfCIUh4gDNku1ZU1OSw53PsLKkg=; b=D9CZt5zEWuVXMGpl4oClV+fg03l4gpoPu2eDjP0oz5coh6QhkoTcOWJG3kmbPMo4lpiLyuRAm0EVKI8i6iMj9OKKaBQhhNZiXszg+ejrfzTIubNi/J9y4dKNtZr2XtVCU9gbnXkF5YxVikzr8ZiiIWNIv0nsGLp0Gqq90TPsxGQ= Received: from BN9PR03CA0073.namprd03.prod.outlook.com (2603:10b6:408:fc::18) by DM6PR12MB3290.namprd12.prod.outlook.com (2603:10b6:5:189::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.20; Fri, 29 Oct 2021 13:04:06 +0000 Received: from BN8NAM11FT048.eop-nam11.prod.protection.outlook.com (2603:10b6:408:fc:cafe::a5) by BN9PR03CA0073.outlook.office365.com (2603:10b6:408:fc::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.15 via Frontend Transport; Fri, 29 Oct 2021 13:04:06 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT048.mail.protection.outlook.com (10.13.177.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Fri, 29 Oct 2021 13:04:06 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Fri, 29 Oct 2021 08:04:00 -0500 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 10/21] cpufreq: amd: add boost mode support for amd-pstate Date: Fri, 29 Oct 2021 21:02:30 +0800 Message-ID: <20211029130241.1984459-11-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ec9a5427-6bc8-4169-05c1-08d99adc96c3 X-MS-TrafficTypeDiagnostic: DM6PR12MB3290: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2331; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /JSEzHENxd5KgaDe2p8XXufTGvinRtfKqTKoX0KG8IK0GkpM1E+9CW80kr1UuszS5q7mbo9No5GQQoyHrV71hb4zzE4MbzyVO6W3Hlo2OPyNkN50N2dKzasXUazvii3ypFpNeUw5UoY+J6USGjE/RjtMR+be4gKwxeAO2wFaZfKT4BXQBYf+5ouRmewTzoiNd3wZThIdKhGEQVGms+OTyKPbupbZlRX6r0uSlA+cGo5L689DlDA0FMbVPIJ/vq6QsmRD0YU3YcFKBOQenTWD7y3up1VIco24CawRFTKx5gOBoujD2x4AEtx57i+CqVdo+QeWt0DSvpNJFV/i2r+p0tRGnieGMAmwYY0CIH1CXeg549l7sQeQnsGgdY5/g90cG3Orkpqm9VmlcQFdZru7blM3i/0YQJan+tWZmAQGmuyjB3jvj0l+XO4qeeWZ2o2YUgMaw5Xin+SK+9jv5phRZ2b0oVz3zRYZ3IUkz6RHOTKgPiybbwtlfj9iF9ii3IyG1magU9zcSsskh5jofV2PJ/OC0Fab2oQ2RqIfJtiFZJhE9twrEhqMEX9t2ssEJdUnd0ha6LKlTzg0bigmjW46iebNBJWP5740UyJ4tBWm8KJ1xX/AzutaNcLjORYrZd46syBD8kQaOHlFp9DcYk9ue1TQ1ZukGSTOA68rJYai09u2IzDRRZ10mG35dDNUffzi2COgBY+TJkxSgjwr8FZda1md9seXic5r11OeSu7vTjg= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(7416002)(336012)(2616005)(83380400001)(8676002)(26005)(5660300002)(36860700001)(47076005)(186003)(16526019)(86362001)(82310400003)(426003)(54906003)(4326008)(508600001)(1076003)(81166007)(36756003)(2906002)(110136005)(70586007)(356005)(6666004)(316002)(70206006)(8936002)(7696005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:04:06.1532 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ec9a5427-6bc8-4169-05c1-08d99adc96c3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3290 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org If the sbios supports the boost mode of amd-pstate, let's switch to boost enabled by default. Signed-off-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 44 ++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 6037590e82a6..9af27ac1f818 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -67,6 +67,8 @@ struct amd_cpudata { u32 min_freq; u32 nominal_freq; u32 lowest_nonlinear_freq; + + bool boost_supported; }; static inline int pstate_enable(bool enable) @@ -349,6 +351,45 @@ static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata) return lowest_nonlinear_freq * 1000; } +static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) +{ + struct amd_cpudata *cpudata = policy->driver_data; + int ret; + + if (!cpudata->boost_supported) { + pr_err("Boost mode is not supported by this processor or SBIOS\n"); + return -EINVAL; + } + + if (state) + policy->cpuinfo.max_freq = cpudata->max_freq; + else + policy->cpuinfo.max_freq = cpudata->nominal_freq; + + policy->max = policy->cpuinfo.max_freq; + + ret = freq_qos_update_request(&cpudata->req[1], + policy->cpuinfo.max_freq); + if (ret < 0) + return ret; + + return 0; +} + +static void amd_pstate_boost_init(struct amd_cpudata *cpudata) +{ + u32 highest_perf, nominal_perf; + + highest_perf = READ_ONCE(cpudata->highest_perf); + nominal_perf = READ_ONCE(cpudata->nominal_perf); + + if (highest_perf <= nominal_perf) + return; + + cpudata->boost_supported = true; + amd_pstate_driver.boost_enabled = true; +} + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; @@ -419,6 +460,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) policy->driver_data = cpudata; + amd_pstate_boost_init(cpudata); + return 0; freq_qos_remove_request(&cpudata->req[1]); @@ -448,6 +491,7 @@ static struct cpufreq_driver amd_pstate_driver = { .target = amd_pstate_target, .init = amd_pstate_cpu_init, .exit = amd_pstate_cpu_exit, + .set_boost = amd_pstate_set_boost, .name = "amd-pstate", }; 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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 11/21] cpufreq: amd: add amd-pstate frequencies attributes Date: Fri, 29 Oct 2021 21:02:31 +0800 Message-ID: <20211029130241.1984459-12-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0b1114c0-bebc-48df-36b9-08d99adc99bf X-MS-TrafficTypeDiagnostic: BY5PR12MB4130: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eE3AhLSkZdwhmrXBSQlrnLnDztoaFnqOqtOiS7oUFTwgVUVkF3oeompPY0hFFImu8GQgwoZMEzerjyfj8ctCURgOVbRnmdGlkbwa302AZozfxYggKS9HEMAL15BV2xDaabOVoBIzQVFy3sWGzHwIekLAZkJxHHFRcaU+INEmuws7ttEoQWqwJ3VdoKvyTh+7JXU6u1oafZWYIesRHhFhpyVX5C2QOaRtuv0fS/c8827uL8a9IKtty/uZZcaHyuzF1DH35XhFnxIgWD1iFwoXQC3hJSsk0I/VqPQQOGF2pbCcw43MqpgT/8SZBs/pQ4YWr2SIax8n6hQ8zKicL//3pc6pbPtSJDuihTU58PylG5fQ8bcJmKrzp4bwziAbZ+7/Ljanl27i2H1AFIlJpWRvBX0VNUCtmb0YDzERDz5G0XnLmEzwuaXFmtTPMS7AMSAIug9eq5gfNOMssU3c5rfrGFcnfKW7/O6ZE+CNSrdCewgtiLn8IDtP86SupHcBgUHJSl9lwkyRQUSswA7x8dtaWzSOY7OvXeh05SLmfN2OGLEc87MaYRjEkET0O6REFq1UQYFmDRKGqUxsYrLCoTPpILBoc2X2aMnuky/N6uKXhy4cPhl9N7+VdI7nv1d6jiaEZQy8tI68b/svr6VHXZP//hLCnX81knMlZOvtBArkWk9ROqONwUEed6hlTkNfD/tolNQbF7kpMSUtt/pyOe4fvbO8NcgijvCzJm6HoPDsthM= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(47076005)(16526019)(26005)(70586007)(70206006)(7696005)(86362001)(426003)(316002)(5660300002)(8676002)(186003)(83380400001)(336012)(1076003)(508600001)(110136005)(356005)(36756003)(6666004)(82310400003)(8936002)(2616005)(54906003)(7416002)(81166007)(2906002)(36860700001)(4326008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:04:11.2134 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0b1114c0-bebc-48df-36b9-08d99adc99bf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT003.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4130 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce sysfs attributes to get the different level processor frequencies. Signed-off-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 63 ++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 9af27ac1f818..8cf1e80f44e0 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -485,6 +485,68 @@ static int amd_pstate_cpu_exit(struct cpufreq_policy *policy) return 0; } +/* Sysfs attributes */ + +/* This frequency is to indicate the maximum hardware frequency. + * If boost is not active but supported, the frequency will be larger than the + * one in cpuinfo. + */ +static ssize_t show_amd_pstate_max_freq(struct cpufreq_policy *policy, + char *buf) +{ + int max_freq; + struct amd_cpudata *cpudata; + + cpudata = policy->driver_data; + + max_freq = amd_get_max_freq(cpudata); + if (max_freq < 0) + return max_freq; + + return sprintf(&buf[0], "%u\n", max_freq); +} + +static ssize_t show_amd_pstate_nominal_freq(struct cpufreq_policy *policy, + char *buf) +{ + int nominal_freq; + struct amd_cpudata *cpudata; + + cpudata = policy->driver_data; + + nominal_freq = amd_get_nominal_freq(cpudata); + if (nominal_freq < 0) + return nominal_freq; + + return sprintf(&buf[0], "%u\n", nominal_freq); +} + +static ssize_t show_amd_pstate_lowest_nonlinear_freq(struct cpufreq_policy *policy, + char *buf) +{ + int freq; + struct amd_cpudata *cpudata; + + cpudata = policy->driver_data; + + freq = amd_get_lowest_nonlinear_freq(cpudata); + if (freq < 0) + return freq; + + return sprintf(&buf[0], "%u\n", freq); +} + +cpufreq_freq_attr_ro(amd_pstate_max_freq); +cpufreq_freq_attr_ro(amd_pstate_nominal_freq); +cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); + +static struct freq_attr *amd_pstate_attr[] = { + &amd_pstate_max_freq, + &amd_pstate_nominal_freq, + &amd_pstate_lowest_nonlinear_freq, + NULL, +}; + static struct cpufreq_driver amd_pstate_driver = { .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, .verify = amd_pstate_verify, @@ -493,6 +555,7 @@ static struct cpufreq_driver amd_pstate_driver = { .exit = amd_pstate_cpu_exit, .set_boost = amd_pstate_set_boost, .name = "amd-pstate", + .attr = amd_pstate_attr, }; static int __init amd_pstate_init(void) From patchwork Fri Oct 29 13:02:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12592677 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 505A6C433FE for ; Fri, 29 Oct 2021 13:04:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3C316611C0 for ; Fri, 29 Oct 2021 13:04:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231892AbhJ2NHG (ORCPT ); Fri, 29 Oct 2021 09:07:06 -0400 Received: from mail-bn8nam12on2041.outbound.protection.outlook.com ([40.107.237.41]:11232 "EHLO NAM12-BN8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231920AbhJ2NGr (ORCPT ); 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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 12/21] cpufreq: amd: add amd-pstate performance attributes Date: Fri, 29 Oct 2021 21:02:32 +0800 Message-ID: <20211029130241.1984459-13-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 58869c22-71e4-49a1-6038-08d99adc9cf1 X-MS-TrafficTypeDiagnostic: SJ0PR12MB5422: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:411; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VgtHFQmNlPQw+XDuwOHvfKfh3a8zSGABAaHYonlqP9P4AJWOVxzKpPMpsmOxpzNQTJViGlblfOJnQhMyzx8ydE3cxLtkvh9r5gbZMWWZP72Zis9c1H1W78jl39f6vRvvCiAobdLmsFTPRLYce4CnzE0MYT+b2/O8KWFdAUJXa2jFUPI/KT1hTXX03vtQnlxvhIm3S4gfw6alNrIjS/BfXDZLYSaoySkrhFORKLsUu/SJE0V7fW3SDVkSXvO+0SGHhTdZq+jkD8/nAPNvbUu5SWQ+Kf3EaCcdP0AOJ1pecvYjnFe2puV6IxHhGKBoE/Pga+TSZrRv4J1DA/x+qFPhg7t41SnXbdPeOj7lJ/EcDCMxHLR+MEzIyJFl8iBKvAB9Lk+yVARprF3e4EBukS37oU5Io/dTv+QgUcP89XO3picUJfOYi/Vd8sYdDoQQBxlmB1MS/akVD3ieQ3kAs01CjJM5DGwEslpzUtuDxHDzSYUV37WM9N4Evvxv5qh+z2TrUuVSSSRXUNhNEXeMFegb+TEI0mi+GMg7JvKWNg1fc1UvVQMqsa18Kkvx2WFnDBHPG3DtbMIsqA/3ilQ2HJJ7RQuC2vHgI+hqy/N2ysUMZcbxthI6Jn8sev3+R+pVuGZJ7n6OZ4Xk+dwl/4Hyzx04sQKhsC87eD7vmzLsNq+hUX4QJVM8VETseGgN+LugUaYJ0kSQhNEq1t+QLm4JoOap3YGwjCdGLhMiBgyFD0uYqnc= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(70586007)(5660300002)(7696005)(426003)(8676002)(2616005)(86362001)(83380400001)(7416002)(70206006)(1076003)(36860700001)(36756003)(8936002)(186003)(336012)(6666004)(26005)(508600001)(316002)(356005)(81166007)(16526019)(4326008)(54906003)(110136005)(47076005)(82310400003)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:04:16.5753 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 58869c22-71e4-49a1-6038-08d99adc9cf1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5422 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce sysfs attributes to get the different level amd-pstate performances. Signed-off-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 53 ++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 8cf1e80f44e0..58ee50bf492b 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -536,14 +536,67 @@ static ssize_t show_amd_pstate_lowest_nonlinear_freq(struct cpufreq_policy *poli return sprintf(&buf[0], "%u\n", freq); } +static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, + char *buf) +{ + u32 perf; + struct amd_cpudata *cpudata = policy->driver_data; + + perf = READ_ONCE(cpudata->highest_perf); + + return sprintf(&buf[0], "%u\n", perf); +} + +static ssize_t show_amd_pstate_nominal_perf(struct cpufreq_policy *policy, + char *buf) +{ + u32 perf; + struct amd_cpudata *cpudata = policy->driver_data; + + perf = READ_ONCE(cpudata->nominal_perf); + + return sprintf(&buf[0], "%u\n", perf); +} + +static ssize_t show_amd_pstate_lowest_nonlinear_perf(struct cpufreq_policy *policy, + char *buf) +{ + u32 perf; + struct amd_cpudata *cpudata = policy->driver_data; + + perf = READ_ONCE(cpudata->lowest_nonlinear_perf); + + return sprintf(&buf[0], "%u\n", perf); +} + +static ssize_t show_amd_pstate_lowest_perf(struct cpufreq_policy *policy, + char *buf) +{ + u32 perf; + struct amd_cpudata *cpudata = policy->driver_data; + + perf = READ_ONCE(cpudata->lowest_perf); + + return sprintf(&buf[0], "%u\n", perf); +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_nominal_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); +cpufreq_freq_attr_ro(amd_pstate_highest_perf); +cpufreq_freq_attr_ro(amd_pstate_nominal_perf); +cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_perf); +cpufreq_freq_attr_ro(amd_pstate_lowest_perf); + static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, &amd_pstate_nominal_freq, &amd_pstate_lowest_nonlinear_freq, + &amd_pstate_highest_perf, + &amd_pstate_nominal_perf, + &amd_pstate_lowest_nonlinear_perf, + &amd_pstate_lowest_perf, NULL, }; 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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 13/21] cpupower: add AMD P-state capability flag Date: Fri, 29 Oct 2021 21:02:33 +0800 Message-ID: <20211029130241.1984459-14-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 42cbbf09-fdc8-481a-ef4b-08d99adc9ff1 X-MS-TrafficTypeDiagnostic: DM6PR12MB3532: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1265; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: m6eYd0fTCU3L4AChUkcUdphfeMT2g/nYdkogknPIy6Bu0MuP/4UQSUL3iFjJtSge1HgwCxD5zZ0waTq2CTycLGPy29LSGgapNGGQbBq2BNC9unA7fTDwAL2tLOJBxou5CtbB1Ozpn6KsgZVv+ilG9IJajmqVo7F+EoU58qJPETEaoRHHUEGShGBmJUXAVKXx4F/7cw8BzgcrUa7HbFunU69ru/FVvr3AgXfP7tlEJuqkkiu8HBpv7UN4NUqZQBsV9+Ou9VTiX0tyPFdxQUIQLbGoirhOxOBA7BUBKMHLBSZ7rL9cxVfkM6TXDfZZIpgzLse/NZaH3+QLiPc5BP5Ak7k9aBExEQGN0GLAxP9zLSKXNxEykfctopNh8fVfdxWzuRoSfDKtan6JS1J7zgO0jSKJEJJmnEH4fmzAfTsL6fNe1oy2V3AavsxRrtiZpPih6wE3QxuHlhELdbd/9mvX+GMLhAM6Qn3yBVHgkO3GPEGPUmJfZpgSbl7uvnL/J6H2s1Lt59hR79LpG5XQhGiySb1SJL5Ig5/zZ0YxBkl5Ca4vFWPKGRKmZwI2h75z0q0e6iifcxzIUrOd31zn19sdEzmJ+CDEK05Zgoedtf6jLJefVQUvMh8NCLUk7WKueFZ1WeTHsoGnvHWEApD1eSA94ysc7cWVbPBizkwIqL8utddsIfXa3M6LekvYOa57WGcloVHCPahP+R1uRFyjyyET1Ad1KxnJ40xlxGw+FpazNEc= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(110136005)(336012)(426003)(54906003)(8936002)(5660300002)(86362001)(2616005)(82310400003)(7416002)(4326008)(81166007)(70586007)(316002)(70206006)(1076003)(356005)(4744005)(8676002)(36860700001)(7696005)(2906002)(186003)(47076005)(26005)(16526019)(36756003)(508600001)(6666004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:04:21.6121 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 42cbbf09-fdc8-481a-ef4b-08d99adc9ff1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3532 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add AMD P-state capability flag in cpupower to indicate AMD new P-state kernel module support on Ryzen processors. Signed-off-by: Huang Rui --- tools/power/cpupower/utils/helpers/helpers.h | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/power/cpupower/utils/helpers/helpers.h b/tools/power/cpupower/utils/helpers/helpers.h index 33ffacee7fcb..b4813efdfb00 100644 --- a/tools/power/cpupower/utils/helpers/helpers.h +++ b/tools/power/cpupower/utils/helpers/helpers.h @@ -73,6 +73,7 @@ enum cpupower_cpu_vendor {X86_VENDOR_UNKNOWN = 0, X86_VENDOR_INTEL, #define CPUPOWER_CAP_AMD_HW_PSTATE 0x00000100 #define CPUPOWER_CAP_AMD_PSTATEDEF 0x00000200 #define CPUPOWER_CAP_AMD_CPB_MSR 0x00000400 +#define CPUPOWER_CAP_AMD_PSTATE 0x00000800 #define CPUPOWER_AMD_CPBDIS 0x02000000 From patchwork Fri Oct 29 13:02:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12592681 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36315C433F5 for ; Fri, 29 Oct 2021 13:04:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 20EB06117A for ; Fri, 29 Oct 2021 13:04:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231858AbhJ2NHX (ORCPT ); Fri, 29 Oct 2021 09:07:23 -0400 Received: from mail-bn7nam10on2082.outbound.protection.outlook.com ([40.107.92.82]:18555 "EHLO NAM10-BN7-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231754AbhJ2NHE (ORCPT ); Fri, 29 Oct 2021 09:07:04 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TRqq7aljMENnYHcT96vpMloKg+NHG0I+/qYnXBg0NiRqQVaomQ0prDXefWhC6cDT9ZjEHRdaF67ERo50SFmt7LkFDpjsYfdeqLe0Uxpy7z3B+hiwIa82/9SiRaS0X2P+BhPwQ7JnYXdYltLdhHjmM6ckjYgxYEAr+ZtbDh9vbVtZrfPoUZuLLxVkdaivLmpB94TClW3d07jokj9hnwGXzJys5YwjU0mS2DqDw7Bw/bupWBvs2LptssTisYPLZczmBHjddP0NK5GyHrHlxoVk8+ZYLTMSIt6SEDqUtTrV/gGI5rK4AN7B78+PkflEb9F8BKFtsZrE9HW2yBphFBfSTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=UcWX6wnAZ9kKR3lnWrFfRGLYbt7fR1JVVSvMwIGnjnk=; b=AFyB/T0mF5D69A5YrMlWFITJSu+PUVNreXGusUKDOB80kYEoW5uKLZKE4gcUEIr0gKwigQCWtEWwJwtIkx3fW6Ow75nuLG71KhT5SCxHAfCTNVAXG/T4KznkmCGgtvqr355HcGewvy/HDhIqHfSVF4sLd1FkU89JgOnDhhx5umzXQcBqoO5y4zFhpTuilqvCL3GQfcI9jDcHvt9jmN/JxZH5t3EOQxnmK6B5izkjXefVyGXrLs8gMFzWxJeUvGnBJijmujfhtcy+lUmt4w1/LDwywEcPUD5XU+T2bUmKl1ZEN8fEOgAfJvB/gXkd2ogzKlxjnOC4zKSs0lsaUgX5lA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UcWX6wnAZ9kKR3lnWrFfRGLYbt7fR1JVVSvMwIGnjnk=; b=a2aBwqk4ZiHWMFGD3+OwiZKboQFTLvf+96/rL/8RB9PetPMZNPPfR17XZZhN1C0ZZwGyLMnNcxqn04RkjRNTULYa5gkQiXcsDnGnX5sUcLp7ybp3wGsAaQ4q4cMf5byzzCNukRLLi3OYdDixRpdrhfWuJln02/FxIpDscLD6oQU= Received: from BN9PR03CA0649.namprd03.prod.outlook.com (2603:10b6:408:13b::24) by CH2PR12MB3752.namprd12.prod.outlook.com (2603:10b6:610:15::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.14; Fri, 29 Oct 2021 13:04:29 +0000 Received: from BN8NAM11FT013.eop-nam11.prod.protection.outlook.com (2603:10b6:408:13b:cafe::ad) by BN9PR03CA0649.outlook.office365.com (2603:10b6:408:13b::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.14 via Frontend Transport; Fri, 29 Oct 2021 13:04:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT013.mail.protection.outlook.com (10.13.176.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Fri, 29 Oct 2021 13:04:28 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Fri, 29 Oct 2021 08:04:21 -0500 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 14/21] cpupower: add the function to check amd-pstate enabled Date: Fri, 29 Oct 2021 21:02:34 +0800 Message-ID: <20211029130241.1984459-15-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 879de70f-93ef-4899-76e6-08d99adca441 X-MS-TrafficTypeDiagnostic: CH2PR12MB3752: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2733; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +jCoTZZE23nNrso9hKFOuODE1OFJAsT2WcRzMvHINnom1bbDqpoxIJVJhuTsmIO5ai4dbJ8bZQmryJgmwZO33R1smZqOmCYtj4ZLR/P9SWi3uJzjwa3DtnQzbvSgr3VxyILWm2o+Ghyx/yWclWT0xqvG6MXX65iPrWP5/LUvFovUd2bWgD/oGIsX58dUjhHhFMcFlADU0qI/O9l3pIyI/vMjRraFP9MDIHFiUzvOslKReQoeHdhAYDym2pQvGPdtj68CCMdPptC1guo5GgIKKsylsKQb1er5c6yh2lHOvPWgB4RFdIr1343B+dTL6SsVe35KdXQyASJN0AaLrlqSeGHXm1/T1z5yqTxESp3tvV1d39lUCrZbUTOmDT5pnOE7EZPVHdsMqTfTM/iJov6rhspRMUsnR3QBsGpDYxTniBYzF0HtvCzUERGsm3/JVn1+/h9UmFBk8Rv7NVpyrqw5QlYBwrRGqvnaC0Ghmqw0/Q+VO37lAGDgIlYoxtbwB+27UUctIkZwfEl1uxRi/i4rwhUn24QQIckh1gYZ7Gm+O2Eig+gjuJlHpDbXeaoRT+x5Q/6G38AxgX5RbFNDmlSU6vwqPYSPaAquZ/e9FPr/V7ft34fiB+a/epZ3afR/JFXKuwFQHPcgP2si9w72Aqg/RhoJUY6feuojIuiypv1oHmisJy6euuHZxlcVTsCGJWQUQrNHy9G4eHBAmFNht9vn6nZNfkEZvbzvOvEsVDoTcjU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(4326008)(36860700001)(7416002)(356005)(81166007)(1076003)(5660300002)(26005)(316002)(47076005)(2906002)(8676002)(6666004)(16526019)(2616005)(426003)(82310400003)(86362001)(186003)(110136005)(7696005)(8936002)(508600001)(336012)(36756003)(54906003)(70586007)(70206006)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:04:28.8442 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 879de70f-93ef-4899-76e6-08d99adca441 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB3752 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The processor with amd-pstate function also supports legacy ACPI hardware P-States feature as well. Once driver sets amd-pstate eanbled, the processor will respond the finer grain amd-pstate feature instead of legacy ACPI P-States. So it introduces the cpupower_amd_pstate_enabled() to check whether the current kernel enables amd-pstate or acpi-cpufreq module. Signed-off-by: Huang Rui --- tools/power/cpupower/utils/helpers/helpers.h | 10 ++++++++++ tools/power/cpupower/utils/helpers/misc.c | 18 ++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/tools/power/cpupower/utils/helpers/helpers.h b/tools/power/cpupower/utils/helpers/helpers.h index b4813efdfb00..e03cc97297aa 100644 --- a/tools/power/cpupower/utils/helpers/helpers.h +++ b/tools/power/cpupower/utils/helpers/helpers.h @@ -11,6 +11,7 @@ #include #include +#include #include "helpers/bitmask.h" #include @@ -136,6 +137,12 @@ extern int decode_pstates(unsigned int cpu, int boost_states, extern int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active, int * states); + +/* AMD P-States stuff **************************/ +extern bool cpupower_amd_pstate_enabled(void); + +/* AMD P-States stuff **************************/ + /* * CPUID functions returning a single datum */ @@ -168,6 +175,9 @@ static inline int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active, int * states) { return -1; } +static inline bool cpupower_amd_pstate_enabled(void) +{ return false; } + /* cpuid and cpuinfo helpers **************************/ static inline unsigned int cpuid_eax(unsigned int op) { return 0; }; diff --git a/tools/power/cpupower/utils/helpers/misc.c b/tools/power/cpupower/utils/helpers/misc.c index fc6e34511721..0c483cdefcc2 100644 --- a/tools/power/cpupower/utils/helpers/misc.c +++ b/tools/power/cpupower/utils/helpers/misc.c @@ -3,9 +3,11 @@ #include #include #include +#include #include "helpers/helpers.h" #include "helpers/sysfs.h" +#include "cpufreq.h" #if defined(__i386__) || defined(__x86_64__) @@ -83,6 +85,22 @@ int cpupower_intel_set_perf_bias(unsigned int cpu, unsigned int val) return 0; } +bool cpupower_amd_pstate_enabled(void) +{ + char *driver = cpufreq_get_driver(0); + bool ret = false; + + if (!driver) + return ret; + + if (!strcmp(driver, "amd-pstate")) + ret = true; + + cpufreq_put_driver(driver); + + return ret; +} + #endif /* #if defined(__i386__) || defined(__x86_64__) */ /* get_cpustate From patchwork Fri Oct 29 13:02:35 2021 Content-Type: text/plain; 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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 15/21] cpupower: initial AMD P-state capability Date: Fri, 29 Oct 2021 21:02:35 +0800 Message-ID: <20211029130241.1984459-16-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 409315bb-6dcd-404e-4e9e-08d99adca5df X-MS-TrafficTypeDiagnostic: BYAPR12MB3416: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1923; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /KX87V7XPuk4VrsfLu0QNYojgtR0/Xp42HluNTQJa3JcmKn/18yeXS25ZcNcLSAbUaj+cX6ZIhht1GaOvqVDDZZ2ZA2ez7IcNE16UhREXka0pu/a/YL4wq6OCEauzE8vufLAGMOqdBiNKqlW7ehf9ASZhdlD3wQfxg1Cs/SblXPZ8IKYm+MGtxhFfL3gFpn+tIRTNU16jqkqZ1pKlg/e6CbZjOF9T++BtECKd4Lc49hDv+G+e3oynXSka9KTn+8he4GXaSFP+pYdtsQBSP0NoDGJCeYi6irwyG0yV08ARuhbNQKnLJKdRqZ2kabLmtPG4Or864qEHtzJaR/VCj9KV74KdoG3OqKYpJ75i7T1JTPqciYi94VuPfhyAq4ohW1WhgZgyY41Lphffsuj5v89IbZ4qR6SvJh2UqYarvnK+m06xxxfP7lAhb6kGHH3g5C7JsfM7P3U1MsGNWcDM4PCHKK14iWxeiu+w0ORIPSNd/OlKy8ww4TETlVzxCMvg7dwSLW5iY+c4m4f0clFHNTGP5GKvksQaWJvNjcySJYt2MVXy3PaelZeKogOe6Y1ThEz7yp+kYXOxDQ8ev8I9b/8QDi15SmyKgOzt5ORt3A0UNrGMqht4s9iEmstZfoxnB1ENxa+XqB2LfhdtEUGK3zTYyj57Nf+8mAjfWDMbaRdQ0822GHDG54/nVTi4v2S5W4tvvFuw2slFajnNsvAd+FSbntPbfuh0V2N/FfM3kSLRzM= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(508600001)(186003)(54906003)(4326008)(356005)(7696005)(7416002)(82310400003)(8676002)(81166007)(1076003)(2616005)(110136005)(426003)(70206006)(336012)(26005)(70586007)(5660300002)(16526019)(36860700001)(6666004)(47076005)(316002)(36756003)(2906002)(86362001)(8936002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:04:31.5224 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 409315bb-6dcd-404e-4e9e-08d99adca5df X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT018.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3416 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org If kernel starts the amd-pstate module, the cpupower will initial the capability flag as CPUPOWER_CAP_AMD_PSTATE. And once amd-pstate capability is set, it won't need to set legacy ACPI relative capabilities anymore. Signed-off-by: Huang Rui --- tools/power/cpupower/utils/helpers/cpuid.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/tools/power/cpupower/utils/helpers/cpuid.c b/tools/power/cpupower/utils/helpers/cpuid.c index 72eb43593180..2a6dc104e76b 100644 --- a/tools/power/cpupower/utils/helpers/cpuid.c +++ b/tools/power/cpupower/utils/helpers/cpuid.c @@ -149,6 +149,19 @@ int get_cpu_info(struct cpupower_cpu_info *cpu_info) if (ext_cpuid_level >= 0x80000008 && cpuid_ebx(0x80000008) & (1 << 4)) cpu_info->caps |= CPUPOWER_CAP_AMD_RDPRU; + + if (cpupower_amd_pstate_enabled()) { + cpu_info->caps |= CPUPOWER_CAP_AMD_PSTATE; + + /* + * If AMD P-state is enabled, the firmware will treat + * AMD P-state function as high priority. + */ + cpu_info->caps &= ~CPUPOWER_CAP_AMD_CPB; + cpu_info->caps &= ~CPUPOWER_CAP_AMD_CPB_MSR; + cpu_info->caps &= ~CPUPOWER_CAP_AMD_HW_PSTATE; + cpu_info->caps &= ~CPUPOWER_CAP_AMD_PSTATEDEF; + } } if (cpu_info->vendor == X86_VENDOR_INTEL) { From patchwork Fri Oct 29 13:02:36 2021 Content-Type: text/plain; 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Fri, 29 Oct 2021 13:04:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT050.mail.protection.outlook.com (10.13.177.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Fri, 29 Oct 2021 13:04:35 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Fri, 29 Oct 2021 08:04:31 -0500 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 16/21] cpupower: add the function to get the sysfs value from specific table Date: Fri, 29 Oct 2021 21:02:36 +0800 Message-ID: <20211029130241.1984459-17-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3433a568-fcff-46af-f666-08d99adca877 X-MS-TrafficTypeDiagnostic: MN2PR12MB4422: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3383; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5vLWa+uZfncRhDxJErpaRhVvvwI1nDh3mkO0UTGj5DaxTmoQjHaiqky/lEDUBqUu2clnznn2vBiC/eU4U2NkdLRnoyQjw586DDWwcLG1Fq2BLKPJWssElwAsPo6Cb8DpqOQRMY9UYc13xV86oJHTeoo6RC6Uk8i8ra5FOGdTzbzNK1bXcKN9YXNHjoOqvA1dChNWjx31BB+5HCXXzrjDAimGHt0SxLMgLHoYIEo9U2kMzh4dwn4gOFCpcfMmhT3jgrqlicR3OZGHG4ci1KpepHEdOW6ppd6kf9vy/BaMqQRsRVgaQiR0anLJ4Lt4TZDz7un8uNc+BCbHIg86DGgGhAi9+XDgLdphV8bP665TCY55zqcUJqgB4lZ86v7qYaNVgY05lTfXsF6m/Dl+0jXff50XIGxtUebZs7QPW1NluuD8apRSevYe4nfYj0HX/IrEubFE7SSWyp3P0jWvoztd724UxkXbtVBIeeYLkDBMxWnnaYGZn9SSyUCOgvfh01N8EEK2RL6oKVd6gGmmscfTg8M10pNgGKvIiKHGLxS5hZkO3Tv+RX6qUIg00pd4pDdAmbQVsphkFCahmha6S3KtjbuoPq7PofCO9q+8KWDC35clod9vhQrcVa6QM/nvzF3lJZ9FWONBSav+3EM6FQAZLpFnHITgIk1k8fmY4FVbEXpBpap93XJxDJth4rxj11MgqlWvaeFwvpZs+paSCdl7KbqzGYxoVQvw4Afu3t4Oa0RhXTltga1aOVvtAXLLmIC8ghLyIvNPPsxD6fCalXRA1g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(5660300002)(70586007)(70206006)(316002)(36860700001)(2616005)(426003)(26005)(16526019)(86362001)(336012)(8936002)(186003)(2906002)(47076005)(36756003)(83380400001)(356005)(4326008)(508600001)(54906003)(110136005)(8676002)(82310400003)(7696005)(7416002)(1076003)(81166007)(15583001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:04:35.9112 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3433a568-fcff-46af-f666-08d99adca877 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT050.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4422 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Expose the helper into cpufreq header, then cpufreq driver can use this function to get the sysfs value if it has any specific sysfs interfaces. Signed-off-by: Huang Rui --- tools/power/cpupower/lib/cpufreq.c | 21 +++++++++++++++------ tools/power/cpupower/lib/cpufreq.h | 12 ++++++++++++ 2 files changed, 27 insertions(+), 6 deletions(-) diff --git a/tools/power/cpupower/lib/cpufreq.c b/tools/power/cpupower/lib/cpufreq.c index c3b56db8b921..02719cc400a1 100644 --- a/tools/power/cpupower/lib/cpufreq.c +++ b/tools/power/cpupower/lib/cpufreq.c @@ -83,20 +83,21 @@ static const char *cpufreq_value_files[MAX_CPUFREQ_VALUE_READ_FILES] = { [STATS_NUM_TRANSITIONS] = "stats/total_trans" }; - -static unsigned long sysfs_cpufreq_get_one_value(unsigned int cpu, - enum cpufreq_value which) +unsigned long cpufreq_get_sysfs_value_from_table(unsigned int cpu, + const char **table, + unsigned index, + unsigned size) { unsigned long value; unsigned int len; char linebuf[MAX_LINE_LEN]; char *endp; - if (which >= MAX_CPUFREQ_VALUE_READ_FILES) + if (!table && !table[index] && index >= size) return 0; - len = sysfs_cpufreq_read_file(cpu, cpufreq_value_files[which], - linebuf, sizeof(linebuf)); + len = sysfs_cpufreq_read_file(cpu, table[index], linebuf, + sizeof(linebuf)); if (len == 0) return 0; @@ -109,6 +110,14 @@ static unsigned long sysfs_cpufreq_get_one_value(unsigned int cpu, return value; } +static unsigned long sysfs_cpufreq_get_one_value(unsigned int cpu, + enum cpufreq_value which) +{ + return cpufreq_get_sysfs_value_from_table(cpu, cpufreq_value_files, + which, + MAX_CPUFREQ_VALUE_READ_FILES); +} + /* read access to files which contain one string */ enum cpufreq_string { diff --git a/tools/power/cpupower/lib/cpufreq.h b/tools/power/cpupower/lib/cpufreq.h index 95f4fd9e2656..107668c0c454 100644 --- a/tools/power/cpupower/lib/cpufreq.h +++ b/tools/power/cpupower/lib/cpufreq.h @@ -203,6 +203,18 @@ int cpufreq_modify_policy_governor(unsigned int cpu, char *governor); int cpufreq_set_frequency(unsigned int cpu, unsigned long target_frequency); +/* + * get the sysfs value from specific table + * + * Read the value with the sysfs file name from specific table. Does + * only work if the cpufreq driver has the specific sysfs interfaces. + */ + +unsigned long cpufreq_get_sysfs_value_from_table(unsigned int cpu, + const char **table, + unsigned index, + unsigned size); + #ifdef __cplusplus } #endif From patchwork Fri Oct 29 13:02:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12592687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D74BBC433F5 for ; Fri, 29 Oct 2021 13:05:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BC051611CC for ; Fri, 29 Oct 2021 13:05:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231936AbhJ2NHs (ORCPT ); Fri, 29 Oct 2021 09:07:48 -0400 Received: from mail-co1nam11on2050.outbound.protection.outlook.com ([40.107.220.50]:21345 "EHLO NAM11-CO1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S232040AbhJ2NHO (ORCPT ); Fri, 29 Oct 2021 09:07:14 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=BUMrfk82SJ74GSzyN3Lt4RIRENNRsmAkLq/AAERjBiS61BaKXoCf5DKmes899yyAyVrKoMsZQiWxgXkG5oCXYyjtkTvEc3WwpohcByvuLUBDBGoW7M5DykrT6QTB00Is4gCHypJZNkWO4qcW+d+BCQUvIGg8q279xCecsgIQvuGOz1x7zwKYYOb+uW5gjOGi/YAbdZIUOJdE0SnLBorB4s6LkBGUK8QhaRzaYHVDtmaG+dRYdCzvSgLbLQ9Ng3Ud5LSjBzlap49MECiXsKwZxKOw7tj7iytdwXsEgqNbHwHwoBgE0DpvA5Pl6iTW5BO79emiuy196y2nNSfnadJAGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ETquVncU506XWbqhhCDbmpNtGFTe0qd5JCgu9D9iaJo=; b=dkHgvGONWXPefDmz5DLw9rlnahxQCMFVNhfq7H4xXhA0oNApnECbwjMKRQKsuAE2bhtjxaetSDv11nrUQeYye1TrmBQEDz0/E604ThD8NCVxHbSPZjai7x/FRuJ68HaJMCshVQGjmCN4ao6a0DIUgUZlTFATJrTYlV0vFHWvfXqct2LpuXX/NS8boCWUqpIVfflms1L0iwHA8A9SKOZ1nY2Txm/GwcdCrKu+cm0qVlD1GjgvWMLAK4K7gdyHfF8r1WJTume8IwPlFF1ldXOgAx7oangPddBGhZUeLpUNITDc7HE3ShDaoUgi9vWDJt15wNNkacD88MTRWhe1Ddu2CQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ETquVncU506XWbqhhCDbmpNtGFTe0qd5JCgu9D9iaJo=; b=ub8osPgLudDupegf2XG6jRHSpoPHgTy3uzkU662Kzxo7Fpk77QoA3/ApLiybbMG3MDRgREvXDeFtiFxTu6UarZQenDNENQW2m4uV200A/68mmQy/X9k9PmM5+A590A4V7AccIL1aUgW8LKohLmBgdiK/efsGaza75swyoUr0mHk= Received: from BN0PR10CA0004.namprd10.prod.outlook.com (2603:10b6:408:143::18) by SN1PR12MB2448.namprd12.prod.outlook.com (2603:10b6:802:28::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.18; Fri, 29 Oct 2021 13:04:42 +0000 Received: from BN8NAM11FT009.eop-nam11.prod.protection.outlook.com (2603:10b6:408:143:cafe::34) by BN0PR10CA0004.outlook.office365.com (2603:10b6:408:143::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.15 via Frontend Transport; Fri, 29 Oct 2021 13:04:41 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT009.mail.protection.outlook.com (10.13.176.65) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Fri, 29 Oct 2021 13:04:40 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Fri, 29 Oct 2021 08:04:35 -0500 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 17/21] cpupower: add amd-pstate sysfs definition and access helper Date: Fri, 29 Oct 2021 21:02:37 +0800 Message-ID: <20211029130241.1984459-18-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5b186e00-9c2d-4041-bd2c-08d99adcab78 X-MS-TrafficTypeDiagnostic: SN1PR12MB2448: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rqkEQXe/S6CL7n6V9uvv/ARrNkwu6BR80nGZfWUejGPR3HKfxakM7dLXOhaIM61OjL5zab59JeDCMmYbSIvgoJj+CUTAIR+2v+BYdf7Ecqdohiw6IuqJrczQhZeaZER2VH3RIhqGgNGlSfJJfj5F/rp7xn55jexxLw+SsqxB5QVU9VAMUVpiye2FDfdrOkjTk6jA8CStN5AlXRW5gRrAsQ6TrbjdqjcYqcQgqiYAUGaHML6fWFDWNzXyBUzxEwyMUEdS6erC+w3RNn3MS5i90lr6d7vcTcWDRCzZpLghxl83bohuEEtQ1rcfbmSIzUB19QT8fF6MJa2Pq3HaMpxWSBsu9UMkxrSiMY4S+r3k4QNit7o2EDzmYiQuIGc3AS+CnNvgd7J8sE5QCLHegurmtz1B99FxYoVoul1jkZg4w+1J6YUlN0XnXG/TqcAQYr4yAGq9WdFzqKyiq63arlS6cw9WwiQ2bcTlRRxkFR8FCKfMEWTbq+puBTyNVWhYILb9rP8BToCYh9qUaMKHD/Q4IfwsdpK8pflAiHFaNVVs+EncUy3Np8P+LWxqXv0rku8gaTUG4RwmqbkMLcmxkHkx3//T4qGwso38ElQ4scqpG+IBNbSYejgX8XfxIGGzvmR10K8eutD6dUrG6mJJPFlp7Q1WghyoGKjB4fnUVLAlWhanupxkp5W2SdUUINsbUzUQWAGsbXwmu0mQrwkejojPRE6cJ5yOFKBUp4gK8aDKxL8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(70206006)(5660300002)(508600001)(83380400001)(8676002)(16526019)(82310400003)(8936002)(1076003)(70586007)(54906003)(2616005)(36756003)(2906002)(81166007)(26005)(426003)(356005)(47076005)(110136005)(316002)(336012)(36860700001)(86362001)(7696005)(186003)(7416002)(4326008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:04:40.9505 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b186e00-9c2d-4041-bd2c-08d99adcab78 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR12MB2448 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce the marco definitions and access helper function for amd-pstate sysfs interfaces such as each performance goals and frequency levels in amd helper file. They will be used to read the sysfs attribute from amd-pstate cpufreq driver for cpupower utilities. Signed-off-by: Huang Rui --- tools/power/cpupower/utils/helpers/amd.c | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/tools/power/cpupower/utils/helpers/amd.c b/tools/power/cpupower/utils/helpers/amd.c index 97f2c857048e..f233a6ab75ac 100644 --- a/tools/power/cpupower/utils/helpers/amd.c +++ b/tools/power/cpupower/utils/helpers/amd.c @@ -8,7 +8,9 @@ #include #include "helpers/helpers.h" +#include "cpufreq.h" +/* ACPI P-States Helper Functions for AMD Processors ***************/ #define MSR_AMD_PSTATE_STATUS 0xc0010063 #define MSR_AMD_PSTATE 0xc0010064 #define MSR_AMD_PSTATE_LIMIT 0xc0010061 @@ -146,4 +148,39 @@ int amd_pci_get_num_boost_states(int *active, int *states) pci_cleanup(pci_acc); return 0; } + +/* ACPI P-States Helper Functions for AMD Processors ***************/ + +/* AMD P-States Helper Functions ***************/ +enum amd_pstate_value { + AMD_PSTATE_HIGHEST_PERF, + AMD_PSTATE_NOMINAL_PERF, + AMD_PSTATE_LOWEST_NONLINEAR_PERF, + AMD_PSTATE_LOWEST_PERF, + AMD_PSTATE_MAX_FREQ, + AMD_PSTATE_NOMINAL_FREQ, + AMD_PSTATE_LOWEST_NONLINEAR_FREQ, + MAX_AMD_PSTATE_VALUE_READ_FILES +}; + +static const char *amd_pstate_value_files[MAX_AMD_PSTATE_VALUE_READ_FILES] = { + [AMD_PSTATE_HIGHEST_PERF] = "amd_pstate_highest_perf", + [AMD_PSTATE_NOMINAL_PERF] = "amd_pstate_nominal_perf", + [AMD_PSTATE_LOWEST_NONLINEAR_PERF] = "amd_pstate_lowest_nonlinear_perf", + [AMD_PSTATE_LOWEST_PERF] = "amd_pstate_lowest_perf", + [AMD_PSTATE_MAX_FREQ] = "amd_pstate_max_freq", + [AMD_PSTATE_NOMINAL_FREQ] = "amd_pstate_nominal_freq", + [AMD_PSTATE_LOWEST_NONLINEAR_FREQ] = "amd_pstate_lowest_nonlinear_freq", +}; + +static unsigned long amd_pstate_get_data(unsigned int cpu, + enum amd_pstate_value value) +{ + return cpufreq_get_sysfs_value_from_table(cpu, + amd_pstate_value_files, + value, + MAX_AMD_PSTATE_VALUE_READ_FILES); +} + +/* AMD P-States Helper Functions ***************/ #endif /* defined(__i386__) || defined(__x86_64__) */ From patchwork Fri Oct 29 13:02:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12592689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50CB7C433EF for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT061.mail.protection.outlook.com (10.13.177.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Fri, 29 Oct 2021 13:04:45 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Fri, 29 Oct 2021 08:04:40 -0500 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 18/21] cpupower: enable boost state support for amd-pstate module Date: Fri, 29 Oct 2021 21:02:38 +0800 Message-ID: <20211029130241.1984459-19-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 108ce025-2e4b-4aab-c267-08d99adcae4f X-MS-TrafficTypeDiagnostic: BN8PR12MB3347: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4tvcWhjlsxSO0kWOR4Fw32yExK5ihEfMk5dNTbtnQffCSY/y9ruWAMbmHZCd/9Xoq2T6onvv2T6EFAyCf4HXqq/SK6CsQL3J4gyWOhW4cby2a2jnXJOgo8PpK3wpMCNO8F51V4wF90DzuLtuD52LMG8Zt1E326ruxlfBIp2hiJGO8wZXH3jAIej1wAVGXscnCq65tTyjsZpBFoTjUbn9sT/07UPCt1fJJDz7nIzFbLbvzbpOSBGBF7w6EEd6ouBTmYDCKEnM0vXYndozbNOKqGiq9JMper9VFOkGg1Wa0sI1DMmAFz/ciVTadRG3cIk3hk4NSw0YWnY8jv+OrWioK5z2SCVW5hI48OXryN9D5lbmIDeQB1QafUa/K/V49z3jNMKYWRR1rfQCTLEGE6okJiYqTyiRItKDzMK/tOVhcQ/Bor2jmlxt2JHR897PtdHF/zfUIj+r7BiR1iOyYzXRBPqqARfqWuvy414OA3U07Q5VlxU4w6X/izY2F91tlD5zINTfERj6LYEmPlEG8RcozwZEHtCC7TS7tgCXAJQmbzW1zkBYeI1giDWHASH3+oiB4RpcqZylP5392vEcsp5zePuSGENppuNGVz4hgi2NfNtqNrN8ncHzIcVUWfZr989Y+UxnDCcxqQxvXxpn2g9xmocBEl4HSWi7I9znljJN2N1jfiI7qmhrGw0jk59JzrrTDeqdQj/RmudKXwXej451VRtHcCn/VVSmcBOkzEBDLlE= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(36860700001)(336012)(82310400003)(2616005)(86362001)(426003)(26005)(508600001)(36756003)(186003)(16526019)(83380400001)(8676002)(2906002)(54906003)(110136005)(316002)(8936002)(5660300002)(1076003)(7696005)(7416002)(4326008)(81166007)(356005)(70586007)(70206006)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:04:45.7151 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 108ce025-2e4b-4aab-c267-08d99adcae4f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT061.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3347 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The legacy ACPI hardware P-States function has 3 P-States on ACPI table, the CPU frequency only can be switched between the 3 P-States. While the processor supports the boost state, it will have another boost state that the frequency can be higher than P0 state, and the state can be decoded by the function of decode_pstates() and read by amd_pci_get_num_boost_states(). However, the new AMD P-States function is different than legacy ACPI hardware P-State on AMD processors. That has a finer grain frequency range between the highest and lowest frequency. And boost frequency is actually the frequency which is mapped on highest performance ratio. The similiar previous P0 frequency is mapped on nominal performance ratio. If the highest performance on the processor is higher than nominal performance, then we think the current processor supports the boost state. And it uses amd_pstate_boost_init() to initialize boost for AMD P-States function. Signed-off-by: Huang Rui --- tools/power/cpupower/utils/helpers/amd.c | 18 ++++++++++++++++++ tools/power/cpupower/utils/helpers/helpers.h | 5 +++++ tools/power/cpupower/utils/helpers/misc.c | 2 ++ 3 files changed, 25 insertions(+) diff --git a/tools/power/cpupower/utils/helpers/amd.c b/tools/power/cpupower/utils/helpers/amd.c index f233a6ab75ac..92b9fb631768 100644 --- a/tools/power/cpupower/utils/helpers/amd.c +++ b/tools/power/cpupower/utils/helpers/amd.c @@ -182,5 +182,23 @@ static unsigned long amd_pstate_get_data(unsigned int cpu, MAX_AMD_PSTATE_VALUE_READ_FILES); } +void amd_pstate_boost_init(unsigned int cpu, int *support, int *active) +{ + unsigned long highest_perf, nominal_perf, cpuinfo_min, + cpuinfo_max, amd_pstate_max; + + highest_perf = amd_pstate_get_data(cpu, AMD_PSTATE_HIGHEST_PERF); + nominal_perf = amd_pstate_get_data(cpu, AMD_PSTATE_NOMINAL_PERF); + + *support = highest_perf > nominal_perf ? 1 : 0; + if (!(*support)) + return; + + cpufreq_get_hardware_limits(cpu, &cpuinfo_min, &cpuinfo_max); + amd_pstate_max = amd_pstate_get_data(cpu, AMD_PSTATE_MAX_FREQ); + + *active = cpuinfo_max == amd_pstate_max ? 1 : 0; +} + /* AMD P-States Helper Functions ***************/ #endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/tools/power/cpupower/utils/helpers/helpers.h b/tools/power/cpupower/utils/helpers/helpers.h index e03cc97297aa..c03925bea655 100644 --- a/tools/power/cpupower/utils/helpers/helpers.h +++ b/tools/power/cpupower/utils/helpers/helpers.h @@ -140,6 +140,8 @@ extern int cpufreq_has_boost_support(unsigned int cpu, int *support, /* AMD P-States stuff **************************/ extern bool cpupower_amd_pstate_enabled(void); +extern void amd_pstate_boost_init(unsigned int cpu, + int *support, int *active); /* AMD P-States stuff **************************/ @@ -177,6 +179,9 @@ static inline int cpufreq_has_boost_support(unsigned int cpu, int *support, static inline bool cpupower_amd_pstate_enabled(void) { return false; } +static void amd_pstate_boost_init(unsigned int cpu, + int *support, int *active) +{ return; } /* cpuid and cpuinfo helpers **************************/ diff --git a/tools/power/cpupower/utils/helpers/misc.c b/tools/power/cpupower/utils/helpers/misc.c index 0c483cdefcc2..e0d3145434d3 100644 --- a/tools/power/cpupower/utils/helpers/misc.c +++ b/tools/power/cpupower/utils/helpers/misc.c @@ -41,6 +41,8 @@ int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active, if (ret) return ret; } + } else if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_PSTATE) { + amd_pstate_boost_init(cpu, support, active); } else if (cpupower_cpu_info.caps & CPUPOWER_CAP_INTEL_IDA) *support = *active = 1; return 0; From patchwork Fri Oct 29 13:02:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12592691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06F16C433F5 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT036.mail.protection.outlook.com (10.13.177.168) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Fri, 29 Oct 2021 13:04:51 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Fri, 29 Oct 2021 08:04:45 -0500 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 19/21] cpupower: move print_speed function into misc helper Date: Fri, 29 Oct 2021 21:02:39 +0800 Message-ID: <20211029130241.1984459-20-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bea388a7-d0d8-4f3a-bab4-08d99adcb1ae X-MS-TrafficTypeDiagnostic: CO6PR12MB5492: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4125; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QfxWHz20fIBKuDzHEO0MaMAIir5gtGUzgyjpn9Ek8jdChMOiG0qofItxKSdmT0v/ucaculAfvD7JzOpM1nJghQFYhFfx6fGpNgtOQgxIQ6nAwU05qaZafuEfh324yBdO95Po744qttspuGPOsy/jRboBezHtmuBao3JikzWLoj7AKT9swQhsorgj01S1ZplQ7uUO+7AnyTpsyVMlUfhZs8R8tMGO7EXLTZWfYPxTtkipKPeUlGVa1dHf7Fam/S3DDqIlxxkObVeg6AfuX13TRLagZs29w4qC+zBNtN4C6JtC3MOYCwBemCTluIfJP/e/tqRf2E5UOvFNvrAGRNkmV8C4wVqyJC6GBT3MIRJczNUpSD+Vu5ab9Uis86E7d5PSAt2zmNlU9zzAjiRCQt5bJyN9B64/024izNps5EE/PRXIwz11G4HqpNIXBFl04YZGP1IvAZ79a+qgAlW9q0yUtXPGLeNcV84gdIp3o6Q2rbByTsKyCfuhj/sC8yjNSaws7Z0jQzACRDyb4IZDdV3H0V5MzpmotYCKmkUHZ4s+qUc6Hy9FPV7ChacdasLl8iekWOUEGFRk+kh6dW4EXrp48invG3rSsEYfQgnkjWuvOV6QGbaOw/LUQXDf5xmDrKq/REICIMrMjJsJ4pY/SRbu65Q7jdVu2d0GFO2t9ONt5zlS0QIhgeZRxTNxePPkxz220JRDV9Kqb14lFWzv/BQCABFnAZy1VMR0KMQDKaUgf5Q= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(82310400003)(47076005)(7696005)(316002)(16526019)(86362001)(70586007)(4326008)(26005)(81166007)(8936002)(186003)(5660300002)(83380400001)(508600001)(70206006)(36756003)(36860700001)(336012)(110136005)(6666004)(8676002)(356005)(1076003)(2616005)(426003)(2906002)(54906003)(7416002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:04:51.3716 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bea388a7-d0d8-4f3a-bab4-08d99adcb1ae X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR12MB5492 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The print_speed can be as a common function, and expose it into misc helper header. Then it can be used on other helper files as well. Signed-off-by: Huang Rui --- tools/power/cpupower/utils/cpufreq-info.c | 59 ++++---------------- tools/power/cpupower/utils/helpers/helpers.h | 1 + tools/power/cpupower/utils/helpers/misc.c | 42 ++++++++++++++ 3 files changed, 54 insertions(+), 48 deletions(-) diff --git a/tools/power/cpupower/utils/cpufreq-info.c b/tools/power/cpupower/utils/cpufreq-info.c index f9895e31ff5a..b429454bf3ae 100644 --- a/tools/power/cpupower/utils/cpufreq-info.c +++ b/tools/power/cpupower/utils/cpufreq-info.c @@ -84,43 +84,6 @@ static void proc_cpufreq_output(void) } static int no_rounding; -static void print_speed(unsigned long speed) -{ - unsigned long tmp; - - if (no_rounding) { - if (speed > 1000000) - printf("%u.%06u GHz", ((unsigned int) speed/1000000), - ((unsigned int) speed%1000000)); - else if (speed > 1000) - printf("%u.%03u MHz", ((unsigned int) speed/1000), - (unsigned int) (speed%1000)); - else - printf("%lu kHz", speed); - } else { - if (speed > 1000000) { - tmp = speed%10000; - if (tmp >= 5000) - speed += 10000; - printf("%u.%02u GHz", ((unsigned int) speed/1000000), - ((unsigned int) (speed%1000000)/10000)); - } else if (speed > 100000) { - tmp = speed%1000; - if (tmp >= 500) - speed += 1000; - printf("%u MHz", ((unsigned int) speed/1000)); - } else if (speed > 1000) { - tmp = speed%100; - if (tmp >= 50) - speed += 100; - printf("%u.%01u MHz", ((unsigned int) speed/1000), - ((unsigned int) (speed%1000)/100)); - } - } - - return; -} - static void print_duration(unsigned long duration) { unsigned long tmp; @@ -254,11 +217,11 @@ static int get_boost_mode(unsigned int cpu) if (freqs) { printf(_(" boost frequency steps: ")); while (freqs->next) { - print_speed(freqs->frequency); + print_speed(freqs->frequency, no_rounding); printf(", "); freqs = freqs->next; } - print_speed(freqs->frequency); + print_speed(freqs->frequency, no_rounding); printf("\n"); cpufreq_put_available_frequencies(freqs); } @@ -277,7 +240,7 @@ static int get_freq_kernel(unsigned int cpu, unsigned int human) return -EINVAL; } if (human) { - print_speed(freq); + print_speed(freq, no_rounding); } else printf("%lu", freq); printf(_(" (asserted by call to kernel)\n")); @@ -296,7 +259,7 @@ static int get_freq_hardware(unsigned int cpu, unsigned int human) return -EINVAL; } if (human) { - print_speed(freq); + print_speed(freq, no_rounding); } else printf("%lu", freq); printf(_(" (asserted by call to hardware)\n")); @@ -316,9 +279,9 @@ static int get_hardware_limits(unsigned int cpu, unsigned int human) if (human) { printf(_(" hardware limits: ")); - print_speed(min); + print_speed(min, no_rounding); printf(" - "); - print_speed(max); + print_speed(max, no_rounding); printf("\n"); } else { printf("%lu %lu\n", min, max); @@ -350,9 +313,9 @@ static int get_policy(unsigned int cpu) return -EINVAL; } printf(_(" current policy: frequency should be within ")); - print_speed(policy->min); + print_speed(policy->min, no_rounding); printf(_(" and ")); - print_speed(policy->max); + print_speed(policy->max, no_rounding); printf(".\n "); printf(_("The governor \"%s\" may decide which speed to use\n" @@ -436,7 +399,7 @@ static int get_freq_stats(unsigned int cpu, unsigned int human) struct cpufreq_stats *stats = cpufreq_get_stats(cpu, &total_time); while (stats) { if (human) { - print_speed(stats->frequency); + print_speed(stats->frequency, no_rounding); printf(":%.2f%%", (100.0 * stats->time_in_state) / total_time); } else @@ -486,11 +449,11 @@ static void debug_output_one(unsigned int cpu) if (freqs) { printf(_(" available frequency steps: ")); while (freqs->next) { - print_speed(freqs->frequency); + print_speed(freqs->frequency, no_rounding); printf(", "); freqs = freqs->next; } - print_speed(freqs->frequency); + print_speed(freqs->frequency, no_rounding); printf("\n"); cpufreq_put_available_frequencies(freqs); } diff --git a/tools/power/cpupower/utils/helpers/helpers.h b/tools/power/cpupower/utils/helpers/helpers.h index c03925bea655..fbbfa6047c83 100644 --- a/tools/power/cpupower/utils/helpers/helpers.h +++ b/tools/power/cpupower/utils/helpers/helpers.h @@ -200,5 +200,6 @@ extern struct bitmask *offline_cpus; void get_cpustate(void); void print_online_cpus(void); void print_offline_cpus(void); +void print_speed(unsigned long speed, int no_rounding); #endif /* __CPUPOWERUTILS_HELPERS__ */ diff --git a/tools/power/cpupower/utils/helpers/misc.c b/tools/power/cpupower/utils/helpers/misc.c index e0d3145434d3..d693c96cd09c 100644 --- a/tools/power/cpupower/utils/helpers/misc.c +++ b/tools/power/cpupower/utils/helpers/misc.c @@ -164,3 +164,45 @@ void print_offline_cpus(void) printf(_("cpupower set operation was not performed on them\n")); } } + +/* + * print_speed + * + * Print the exact CPU frequency with appropriate unit + */ +void print_speed(unsigned long speed, int no_rounding) +{ + unsigned long tmp; + + if (no_rounding) { + if (speed > 1000000) + printf("%u.%06u GHz", ((unsigned int) speed/1000000), + ((unsigned int) speed%1000000)); + else if (speed > 1000) + printf("%u.%03u MHz", ((unsigned int) speed/1000), + (unsigned int) (speed%1000)); + else + printf("%lu kHz", speed); + } else { + if (speed > 1000000) { + tmp = speed%10000; + if (tmp >= 5000) + speed += 10000; + printf("%u.%02u GHz", ((unsigned int) speed/1000000), + ((unsigned int) (speed%1000000)/10000)); + } else if (speed > 100000) { + tmp = speed%1000; + if (tmp >= 500) + speed += 1000; + printf("%u MHz", ((unsigned int) speed/1000)); + } else if (speed > 1000) { + tmp = speed%100; + if (tmp >= 50) + speed += 100; + printf("%u.%01u MHz", ((unsigned int) speed/1000), + ((unsigned int) (speed%1000)/100)); + } + } + + return; +} From patchwork Fri Oct 29 13:02:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12592693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51DE2C433EF for ; Fri, 29 Oct 2021 13:05:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 38A6061165 for ; Fri, 29 Oct 2021 13:05:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232107AbhJ2NIH (ORCPT ); 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Fri, 29 Oct 2021 08:04:51 -0500 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 20/21] cpupower: print amd-pstate information on cpupower Date: Fri, 29 Oct 2021 21:02:40 +0800 Message-ID: <20211029130241.1984459-21-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 31c52d86-12e4-4b59-1e24-08d99adcb893 X-MS-TrafficTypeDiagnostic: SN6PR12MB2845: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:655; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hxa2BydepOxS4xDexmF62lcv4zQWqOdZHxvIsCKVIX8X7BMGpez/5c3BzGuzZ6NFUNY7Ztm4jeJODrGcbasSAUvRHrF0evBasccD0Fg6CyLfw5QRnrRjHaZq+3kciqfY/BQnUnAp6CZyT4Q+OrLZB144L78nfUMuNu91/Wq2lSlcFNAU/hlgBZCjfDvPbFHIGh3Nm8PctFVe0EFFMQwvR/ZZvAQsqtryH69RBV6BV876O74oR1lHJSLn63FD4FRMYpRpNeaoDzFwr+v2jxk8kLFmI6mbbdY8idMad60xXNc1DawLtmktAck94Asj0+JD4J0xLfCkm+wMLro+P9EGO61Pmger/7MKK0cVWCrmnhmklUCmdxmK6n2twmL+iBiyiwljxL4t5PWPfU2JVuhJFDI9EOLLZkPb1lmQqMpS9NI8gm5f07KTAFDtor3xUOz33NXwtvojRa2KxXyLZeayP178EcTh9l9oqsY4oVuv77QUepby8ypnixvKZ+bNGeRka9P34gtgT4QEGpSTXsdalowI7bTFapxp/yI40HmISELW5dx/TYY1phwoYmFzr3UNnLPIB+SxTivSCRW1qEjHDZbcLhzRdehwC29vu22rtR1BzISfXtCZP1LoKhZpvDcHB1MbEjdoSau2moTG11mGOnH8/TN6Jxideab101u39e1/SKUgBW0Max8SD1LdHizEwaEkxv4PiofMASCV85uTWTuz0qbT7ccYse4i8LcMlJ8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(356005)(83380400001)(36756003)(81166007)(8936002)(47076005)(7416002)(82310400003)(426003)(54906003)(8676002)(86362001)(508600001)(110136005)(5660300002)(336012)(4326008)(16526019)(36860700001)(186003)(2616005)(316002)(6666004)(70586007)(2906002)(26005)(7696005)(70206006)(1076003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:05:02.7119 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 31c52d86-12e4-4b59-1e24-08d99adcb893 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2845 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org amd-pstate kernel module is using the fine grain frequency instead of acpi hardware pstate. So the performance and frequency values should be printed in frequency-info. Signed-off-by: Huang Rui --- tools/power/cpupower/utils/cpufreq-info.c | 9 ++++-- tools/power/cpupower/utils/helpers/amd.c | 32 ++++++++++++++++++++ tools/power/cpupower/utils/helpers/helpers.h | 5 +++ 3 files changed, 43 insertions(+), 3 deletions(-) diff --git a/tools/power/cpupower/utils/cpufreq-info.c b/tools/power/cpupower/utils/cpufreq-info.c index b429454bf3ae..f828f3c35a6f 100644 --- a/tools/power/cpupower/utils/cpufreq-info.c +++ b/tools/power/cpupower/utils/cpufreq-info.c @@ -146,9 +146,12 @@ static int get_boost_mode_x86(unsigned int cpu) printf(_(" Supported: %s\n"), support ? _("yes") : _("no")); printf(_(" Active: %s\n"), active ? _("yes") : _("no")); - if ((cpupower_cpu_info.vendor == X86_VENDOR_AMD && - cpupower_cpu_info.family >= 0x10) || - cpupower_cpu_info.vendor == X86_VENDOR_HYGON) { + if (cpupower_cpu_info.vendor == X86_VENDOR_AMD && + cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_PSTATE) { + amd_pstate_show_perf_and_freq(cpu, no_rounding); + } else if ((cpupower_cpu_info.vendor == X86_VENDOR_AMD && + cpupower_cpu_info.family >= 0x10) || + cpupower_cpu_info.vendor == X86_VENDOR_HYGON) { ret = decode_pstates(cpu, b_states, pstates, &pstate_no); if (ret) return ret; diff --git a/tools/power/cpupower/utils/helpers/amd.c b/tools/power/cpupower/utils/helpers/amd.c index 92b9fb631768..fa38d3da42ce 100644 --- a/tools/power/cpupower/utils/helpers/amd.c +++ b/tools/power/cpupower/utils/helpers/amd.c @@ -200,5 +200,37 @@ void amd_pstate_boost_init(unsigned int cpu, int *support, int *active) *active = cpuinfo_max == amd_pstate_max ? 1 : 0; } +void amd_pstate_show_perf_and_freq(unsigned int cpu, int no_rounding) +{ + unsigned long cpuinfo_max, cpuinfo_min; + + cpufreq_get_hardware_limits(cpu, &cpuinfo_min, &cpuinfo_max); + + printf(_(" AMD PSTATE Highest Performance: %lu. Maximum Frequency: "), + amd_pstate_get_data(cpu, AMD_PSTATE_HIGHEST_PERF)); + /* If boost isn't active, the cpuinfo_max doesn't indicate real max + * frequency. So we read it back from amd-pstate sysfs entry. + */ + print_speed(amd_pstate_get_data(cpu, AMD_PSTATE_MAX_FREQ), no_rounding); + printf(".\n"); + + printf(_(" AMD PSTATE Nominal Performance: %lu. Nominal Frequency: "), + amd_pstate_get_data(cpu, AMD_PSTATE_NOMINAL_PERF)); + print_speed(amd_pstate_get_data(cpu, AMD_PSTATE_NOMINAL_FREQ), + no_rounding); + printf(".\n"); + + printf(_(" AMD PSTATE Lowest Non-linear Performance: %lu. Lowest Non-linear Frequency: "), + amd_pstate_get_data(cpu, AMD_PSTATE_LOWEST_NONLINEAR_PERF)); + print_speed(amd_pstate_get_data(cpu, AMD_PSTATE_LOWEST_NONLINEAR_FREQ), + no_rounding); + printf(".\n"); + + printf(_(" AMD PSTATE Lowest Performance: %lu. Lowest Frequency: "), + amd_pstate_get_data(cpu, AMD_PSTATE_LOWEST_PERF)); + print_speed(cpuinfo_min, no_rounding); + printf(".\n"); +} + /* AMD P-States Helper Functions ***************/ #endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/tools/power/cpupower/utils/helpers/helpers.h b/tools/power/cpupower/utils/helpers/helpers.h index fbbfa6047c83..5f6862502dbf 100644 --- a/tools/power/cpupower/utils/helpers/helpers.h +++ b/tools/power/cpupower/utils/helpers/helpers.h @@ -142,6 +142,8 @@ extern int cpufreq_has_boost_support(unsigned int cpu, int *support, extern bool cpupower_amd_pstate_enabled(void); extern void amd_pstate_boost_init(unsigned int cpu, int *support, int *active); +extern void amd_pstate_show_perf_and_freq(unsigned int cpu, + int no_rounding); /* AMD P-States stuff **************************/ @@ -182,6 +184,9 @@ static inline bool cpupower_amd_pstate_enabled(void) static void amd_pstate_boost_init(unsigned int cpu, int *support, int *active) { return; } +static inline void amd_pstate_show_perf_and_freq(unsigned int cpu, + int no_rounding) +{ return; } /* cpuid and cpuinfo helpers **************************/ From patchwork Fri Oct 29 13:02:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12592695 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F4C5C433FE for ; Fri, 29 Oct 2021 13:05:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 33BA261165 for ; Fri, 29 Oct 2021 13:05:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231621AbhJ2NIX (ORCPT ); Fri, 29 Oct 2021 09:08:23 -0400 Received: from mail-bn8nam12on2065.outbound.protection.outlook.com ([40.107.237.65]:27498 "EHLO NAM12-BN8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231929AbhJ2NHp (ORCPT ); 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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 21/21] Documentation: amd-pstate: add amd-pstate driver introduction Date: Fri, 29 Oct 2021 21:02:41 +0800 Message-ID: <20211029130241.1984459-22-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: af2e3f79-11df-4d38-3420-08d99adcbd71 X-MS-TrafficTypeDiagnostic: BN7PR12MB2724: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /nk77tOrXBqf15EboNwYmAJp7HD49lDG57brjIdJgc4rWTNGoL9E0mhpQ4QJQGKldxTG6ChhNuf2lhSfH1JSvCoEA2UtVmpUoWYsMhw1qMg9bolWi2Ot5s0tJojATjFslVGsYZkb7OaN03JCenhct5Qd11TE5jmjfyWDBd4tKDI1mB2UNkQRxFND7zyjGLh4q4mf+4NrmGPuKbyD2naqnx95hiCi9X/kWZSB6htF9eK/cUyBSKYAygU7OwJOP0Bczc1C8dpYINd+k9dqCDO4XQ748hNFKVOs+ToE4JwYiQNOjm0dJoXAhoxV+XmBy1iMamE2tLRO9jVcc6Q96gyz80R+XrgErn4qL0/ynDr5BYjEJOkHffSt6/QHoctL8KxS/ItU64iYca3mS7TQAvT9YfA5bejE2aij/xCHlbZfDshuSyA0CApiDd/XFP4DJdrlpvw3cIfbuA6UYhOeCxM1hH8xh7dAAlUX3hBQwcvQDY8fyiSl5QuCFa2Mxinlvp04Wjd75X1gkxNOBqbd6QK2w/TkUxd5YdC/vftCZ8HuVi7AK6jxzM713PHGEHwFFdhySNmwnYubPJ+QPSs1mQXpGNQU21ITriKQYWtJtldTLFtHYj+YVNflQRZyGOggL+DKzKJl4ZIGDWwQHuWqytLJS1cbBfdiHPurlVjzEhI3uH/GQRdRxNYU+FpGnd/kfeHiv6Xaa2LKIdQPr3vq/8e7kG5tjpEx0Huk0cQ+DqCla2dcsqglK6eM7lF+kEXTfHRQKhtApjOUUSrvUYYYamONu0CkzOV0bL3K65wucJEzGefa9/kUjdCJtzU/9jTg1Uqt8n/woqjWdq3nuvPp1zj5taJrqGaSIdj1RaqtaT2sMaI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(186003)(316002)(7696005)(5660300002)(16526019)(356005)(6666004)(426003)(54906003)(26005)(110136005)(82310400003)(36860700001)(508600001)(47076005)(81166007)(70206006)(1076003)(36756003)(86362001)(2906002)(336012)(70586007)(8936002)(4326008)(83380400001)(2616005)(30864003)(966005)(7416002)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:05:11.0761 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af2e3f79-11df-4d38-3420-08d99adcbd71 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR12MB2724 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce the amd-pstate driver design and implementation. Signed-off-by: Huang Rui --- Documentation/admin-guide/pm/amd-pstate.rst | 373 ++++++++++++++++++ .../admin-guide/pm/working-state.rst | 1 + 2 files changed, 374 insertions(+) create mode 100644 Documentation/admin-guide/pm/amd-pstate.rst diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst new file mode 100644 index 000000000000..375374e3eb80 --- /dev/null +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -0,0 +1,373 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. include:: + +=============================================== +``amd-pstate`` CPU Performance Scaling Driver +=============================================== + +:Copyright: |copy| 2021 Advanced Micro Devices, Inc. + +:Author: Huang Rui + + +Introduction +=================== + +``amd-pstate`` is the AMD CPU performance scaling driver that introduces a +new CPU frequency control mechanism on modern AMD APU and CPU series in +Linux kernel. The new mechanism is based on Collaborative Processor +Performance Control (CPPC) which provides finer grain frequency management +than legacy ACPI hardware P-States. Current AMD CPU/APU platforms are using +the ACPI P-states driver to manage CPU frequency and clocks with switching +only in 3 P-states. CPPC replaces the ACPI P-states controls, allows a +flexible, low-latency interface for the Linux kernel to directly +communicate the performance hints to hardware. + +``amd-pstate`` leverages the Linux kernel governors such as ``schedutil``, +``ondemand``, etc. to manage the performance hints which are provided by +CPPC hardware functionality that internally follows the hardware +specification (for details refer to AMD64 Architecture Programmer's Manual +Volume 2: System Programming [1]_). Currently ``amd-pstate`` supports basic +frequency control function according to kernel governors on some of the +Zen2 and Zen3 processors, and we will implement more AMD specific functions +in future after we verify them on the hardware and SBIOS. + + +AMD CPPC Overview +======================= + +Collaborative Processor Performance Control (CPPC) interface enumerates a +continuous, abstract, and unit-less performance value in a scale that is +not tied to a specific performance state / frequency. This is an ACPI +standard [2]_ which software can specify application performance goals and +hints as a relative target to the infrastructure limits. AMD processors +provides the low latency register model (MSR) instead of AML code +interpreter for performance adjustments. ``amd-pstate`` will initialize a +``struct cpufreq_driver`` instance ``amd_pstate_driver`` with the callbacks +to manage each performance update behavior. :: + + Highest Perf ------>+-----------------------+ +-----------------------+ + | | | | + | | | | + | | Max Perf ---->| | + | | | | + | | | | + Nominal Perf ------>+-----------------------+ +-----------------------+ + | | | | + | | | | + | | | | + | | | | + | | | | + | | | | + | | Desired Perf ---->| | + | | | | + | | | | + | | | | + | | | | + | | | | + | | | | + | | | | + | | | | + | | | | + Lowest non- | | | | + linear perf ------>+-----------------------+ +-----------------------+ + | | | | + | | Lowest perf ---->| | + | | | | + Lowest perf ------>+-----------------------+ +-----------------------+ + | | | | + | | | | + | | | | + 0 ------>+-----------------------+ +-----------------------+ + + AMD P-States Performance Scale + + +.. _perf_cap: + +AMD CPPC Performance Capability +-------------------------------- + +Highest Performance (RO) +......................... + +It is the absolute maximum performance an individual processor may reach, +assuming ideal conditions. This performance level may not be sustainable +for long durations and may only be achievable if other platform components +are in a specific state; for example, it may require other processors be in +an idle state. This would be equivalent to the highest frequencies +supported by the processor. + +Nominal (Guaranteed) Performance (RO) +...................................... + +It is the maximum sustained performance level of the processor, assuming +ideal operating conditions. In absence of an external constraint (power, +thermal, etc.) this is the performance level the processor is expected to +be able to maintain continuously. All cores/processors are expected to be +able to sustain their nominal performance state simultaneously. + +Lowest non-linear Performance (RO) +................................... + +It is the lowest performance level at which nonlinear power savings are +achieved, for example, due to the combined effects of voltage and frequency +scaling. Above this threshold, lower performance levels should be generally +more energy efficient than higher performance levels. This register +effectively conveys the most efficient performance level to ``amd-pstate``. + +Lowest Performance (RO) +........................ + +It is the absolute lowest performance level of the processor. Selecting a +performance level lower than the lowest nonlinear performance level may +cause an efficiency penalty but should reduce the instantaneous power +consumption of the processor. + +AMD CPPC Performance Control +------------------------------ + +``amd-pstate`` passes performance goals through these registers. The +register drives the behavior of the desired performance target. + +Minimum requested performance (RW) +................................... + +``amd-pstate`` specifies the minimum allowed performance level. + +Maximum requested performance (RW) +................................... + +``amd-pstate`` specifies a limit the maximum performance that is expected +to be supplied by the hardware. + +Desired performance target (RW) +................................... + +``amd-pstate`` specifies a desired target in the CPPC performance scale as +a relative number. This can be expressed as percentage of nominal +performance (infrastructure max). Below the nominal sustained performance +level, desired performance expresses the average performance level of the +processor subject to hardware. Above the nominal performance level, +processor must provide at least nominal performance requested and go higher +if current operating conditions allow. + +Energy Performance Preference (EPP) (RW) +......................................... + +Provides a hint to the hardware if software wants to bias toward performance +(0x0) or energy efficiency (0xff). + + +Key Governors Support +======================= + +``amd-pstate`` can be used with all the (generic) scaling governors listed +by the ``scaling_available_governors`` policy attribute in ``sysfs``. Then, +it is responsible for the configuration of policy objects corresponding to +CPUs and provides the ``CPUFreq`` core (and the scaling governors attached +to the policy objects) with accurate information on the maximum and minimum +operating frequencies supported by the hardware. Users can check the +``scaling_cur_freq`` information comes from the ``CPUFreq`` core. + +``amd-pstate`` mainly supports ``schedutil`` and ``ondemand`` for dynamic +frequency control. It is to fine tune the processor configuration on +``amd-pstate`` to the ``schedutil`` with CPU CFS scheduler. ``amd-pstate`` +registers adjust_perf callback to implement the CPPC similar performance +update behavior. It is initialized by ``sugov_start`` and then populate the +CPU's update_util_data pointer to assign ``sugov_update_single_perf`` as +the utilization update callback function in CPU scheduler. CPU scheduler +will call ``cpufreq_update_util`` and assign the target performance +according to the ``struct sugov_cpu`` that utilization update belongs to. +Then ``amd-pstate`` updates the desired performance according to the CPU +scheduler assigned. + + +Processor Support +======================= + +The ``amd-pstate`` initialization will fail if the _CPC in ACPI SBIOS is +not existed at the detected processor, and it uses ``acpi_cpc_valid`` to +check the _CPC existence. All Zen based processors support legacy ACPI +hardware P-States function, so while the ``amd-pstate`` fails to be +initialized, the kernel will fall back to initialize ``acpi-cpufreq`` +driver. + +There are two types of hardware implementations for ``amd-pstate``: one is +`Full MSR Support `_ and another is `Shared Memory Support +`_. It can use :c:macro:`X86_FEATURE_AMD_CPPC` feature flag (for +details refer to Processor Programming Reference (PPR) for AMD Family +19h Model 21h, Revision B0 Processors [3]_) to indicate the different +types. ``amd-pstate`` is to register different ``amd_pstate_perf_funcs`` +instances for different hardware implementations. + +Currently, some of Zen2 and Zen3 processors support ``amd-pstate``. In the +future, it will be supported on more and more AMD processors. + +Full MSR Support +----------------- + +Some new Zen3 processors such as Cezanne provide the MSR registers directly +while the :c:macro:`X86_FEATURE_AMD_CPPC` CPU feature flag is set. +``amd-pstate`` can handle the MSR register to implement the fast switch +function in ``CPUFreq`` that can shrink latency of frequency control on the +interrupt context. + +Shared Memory Support +---------------------- + +If :c:macro:`X86_FEATURE_AMD_CPPC` CPU feature flag is not set, that means +the processor supports shared memory solution. In this case, ``amd-pstate`` +uses the ``cppc_acpi`` helper methods to implement the callback functions +of ``amd_pstate_perf_funcs``. + + +AMD P-States and ACPI hardware P-States always can be supported in one +processor. But AMD P-States has the higher priority and if it is enabled +with :c:macro:`MSR_AMD_CPPC_ENABLE` or ``cppc_set_enable``, it will respond +to the request from AMD P-States. + + +User Space Interface in ``sysfs`` +================================== + +``amd-pstate`` exposes several global attributes (files) in ``sysfs`` to +control its functionality at the system level. They located in the +``/sys/devices/system/cpu/cpufreq/policyX/`` directory and affect all CPUs. :: + + root@hr-test1:/home/ray# ls /sys/devices/system/cpu/cpufreq/policy0/*amd* + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_highest_perf + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_lowest_nonlinear_freq + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_lowest_nonlinear_perf + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_lowest_perf + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_max_freq + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_min_freq + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_nominal_freq + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_nominal_perf + + +``amd_pstate_highest_perf / amd_pstate_max_freq`` + +Maximum CPPC performance and CPU frequency that the driver is allowed to +set in percent of the maximum supported CPPC performance level (the highest +performance supported in `AMD CPPC Performance Capability `_). +This attribute is read-only. + +``amd_pstate_nominal_perf / amd_pstate_nominal_freq`` + +Nominal CPPC performance and CPU frequency that the driver is allowed to +set in percent of the maximum supported CPPC performance level (Please see +nominal performance in `AMD CPPC Performance Capability `_). +This attribute is read-only. + +``amd_pstate_lowest_nonlinear_perf / amd_pstate_lowest_nonlinear_freq`` + +The lowest non-linear CPPC performance and CPU frequency that the driver is +allowed to set in percent of the maximum supported CPPC performance level +(Please see the lowest non-linear performance in `AMD CPPC Performance +Capability `_). +This attribute is read-only. + +``amd_pstate_lowest_perf`` + +The lowest physical CPPC performance. The minimum CPU frequency can be read +back from ``cpuinfo`` member of ``cpufreq_policy``, so we won't expose it +here. +This attribute is read-only. + + +``amd-pstate`` vs ``acpi-cpufreq`` +====================================== + +On majority of AMD platforms supported by ``acpi-cpufreq``, the ACPI tables +provided by the platform firmware used for CPU performance scaling, but +only provides 3 P-states on AMD processors. +However, on modern AMD APU and CPU series, it provides the collaborative +processor performance control according to ACPI protocol and customize this +for AMD platforms. That is fine-grain and continuous frequency range +instead of the legacy hardware P-states. ``amd-pstate`` is the kernel +module which supports the new AMD P-States mechanism on most of future AMD +platforms. The AMD P-States mechanism will be the more performance and energy +efficiency frequency management method on AMD processors. + +``cpupower`` tool support for ``amd-pstate`` +=============================================== + +``amd-pstate`` is supported on ``cpupower`` tool that can be used to dump the frequency +information. And it is in progress to support more and more operations for new +``amd-pstate`` module with this tool. :: + + root@hr-test1:/home/ray# cpupower frequency-info + analyzing CPU 0: + driver: amd-pstate + CPUs which run at the same hardware frequency: 0 + CPUs which need to have their frequency coordinated by software: 0 + maximum transition latency: 131 us + hardware limits: 400 MHz - 4.68 GHz + available cpufreq governors: ondemand conservative powersave userspace performance schedutil + current policy: frequency should be within 400 MHz and 4.68 GHz. + The governor "schedutil" may decide which speed to use + within this range. + current CPU frequency: Unable to call hardware + current CPU frequency: 4.02 GHz (asserted by call to kernel) + boost state support: + Supported: yes + Active: yes + AMD PSTATE Highest Performance: 166. Maximum Frequency: 4.68 GHz. + AMD PSTATE Nominal Performance: 117. Nominal Frequency: 3.30 GHz. + AMD PSTATE Lowest Non-linear Performance: 39. Lowest Non-linear Frequency: 1.10 GHz. + AMD PSTATE Lowest Performance: 15. Lowest Frequency: 400 MHz. + + +Diagnostics and Tuning +======================= + +Trace Events +-------------- + +There are two static trace events that can be used for ``amd-pstate`` +diagnostics. One of them is the cpu_frequency trace event generally used +by ``CPUFreq``, and the other one is the ``amd_pstate_perf`` trace event +specific to ``amd-pstate``. The following sequence of shell commands can +be used to enable them and see their output (if the kernel is generally +configured to support event tracing). :: + + root@hr-test1:/home/ray# cd /sys/kernel/tracing/ + root@hr-test1:/sys/kernel/tracing# echo 1 > events/amd_cpu/enable + root@hr-test1:/sys/kernel/tracing# cat trace + # tracer: nop + # + # entries-in-buffer/entries-written: 47827/42233061 #P:2 + # + # _-----=> irqs-off + # / _----=> need-resched + # | / _---=> hardirq/softirq + # || / _--=> preempt-depth + # ||| / delay + # TASK-PID CPU# |||| TIMESTAMP FUNCTION + # | | | |||| | | + -0 [015] dN... 4995.979886: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=15 changed=false fast_switch=true + -0 [007] d.h.. 4995.979893: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=7 changed=false fast_switch=true + cat-2161 [000] d.... 4995.980841: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=0 changed=false fast_switch=true + sshd-2125 [004] d.s.. 4995.980968: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=4 changed=false fast_switch=true + -0 [007] d.s.. 4995.980968: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=7 changed=false fast_switch=true + -0 [003] d.s.. 4995.980971: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=3 changed=false fast_switch=true + -0 [011] d.s.. 4995.980996: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=11 changed=false fast_switch=true + +The cpu_frequency trace event will be triggered either by the ``schedutil`` scaling +governor (for the policies it is attached to), or by the ``CPUFreq`` core (for the +policies with other scaling governors). + + +Reference +=========== + +.. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming, + https://www.amd.com/system/files/TechDocs/24593.pdf + +.. [2] Advanced Configuration and Power Interface Specification, + https://uefi.org/sites/default/files/resources/ACPI_Spec_6_4_Jan22.pdf + +.. [3] Processor Programming Reference (PPR) for AMD Family 19h Model 21h, Revision B0 Processors + https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip + diff --git a/Documentation/admin-guide/pm/working-state.rst b/Documentation/admin-guide/pm/working-state.rst index f40994c422dc..5d2757e2de65 100644 --- a/Documentation/admin-guide/pm/working-state.rst +++ b/Documentation/admin-guide/pm/working-state.rst @@ -11,6 +11,7 @@ Working-State Power Management intel_idle cpufreq intel_pstate + amd-pstate cpufreq_drivers intel_epb intel-speed-select