From patchwork Sat Oct 30 14:40:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12594425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86ADFC433EF for ; Sat, 30 Oct 2021 14:40:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6645860F58 for ; Sat, 30 Oct 2021 14:40:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229585AbhJ3Omu (ORCPT ); Sat, 30 Oct 2021 10:42:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230392AbhJ3Omt (ORCPT ); Sat, 30 Oct 2021 10:42:49 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0EDF9C061570; Sat, 30 Oct 2021 07:40:19 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id b2-20020a1c8002000000b0032fb900951eso5811945wmd.4; Sat, 30 Oct 2021 07:40:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DToYAQHxf/EmU+9Qq/Jcp+BO8Gdd2Z8qCSR2az0OK88=; b=a53BaJ/pGJ3Hj01nFTpBqLr4jU05yNGuyqncmlBy+RmTLQrM8VbMFWJy+0rKgVVphe xfI0NfjE1wtNbyBsZgb4obty9Zk5A3uAB4n9NVtNVzn2vGK9y2+XSSQP74YhusdENAgY r19CnsOa7O/IechMMK3ivb/hI59eQc8XHWC4YdiqCDZDYhLV7V9V23eC60OklNAgL0Q5 QkpPnxH3Bsib1MJxv+xlxlhgoKY/cHtcbiA+ZhV/irtQdglsV6foMdCwaK6btX0L9kSq ELsgXG0weVSyJUJj6jOY62MlzsqPCZqEVRMO3kE9K+AtbAkf2/XDgSdUn9N9i8YXXZuN xi9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DToYAQHxf/EmU+9Qq/Jcp+BO8Gdd2Z8qCSR2az0OK88=; b=Iu4V2DvY9amLtPL8UmpbEb9fY3/AwuHcfRGCLinJwz9yodCg7ICIBcSEE7jJGzzaWc d5eI/BUIrQz9aeggBgwqqFxApWodBZ4h3q6l1t5KnnIkIJ1iTO0hascwHco06P2aCDp6 34JyMqBIktQKlTuLwSzoC6W/0Be0Nh12QJpndWt32/B0bntrreSD3OGnFtf9iIiKSf+B 8ODRnojs6SY0VfrbnSlbTKUlYmUvn23O+6eRY271c8ft0GRDpzrE7ikVTMoczO/XRyXl GVni1vTdUWN9o8r0vpZYCVMP3S8p3YfDYQok6gqcBCZpYgMHUNx5HmZ6B7HeBo8FHh0x JIOg== X-Gm-Message-State: AOAM531S4Blo9uJVbj/+X/arTbSbkmp1x/zhYaFYvVpQSWn5uQ7Or1Gt b3LjwpVFEfUoDV2hbxTsdHY= X-Google-Smtp-Source: ABdhPJzXEmb4NsKsRqQU3A4l8zsj0JrJBwWolog/9AGpwCkOKdzKsMv2kO2ecoDitQlKYo1XMHO3jw== X-Received: by 2002:a05:600c:4f81:: with SMTP id n1mr26909887wmq.63.1635604817623; Sat, 30 Oct 2021 07:40:17 -0700 (PDT) Received: from localhost.localdomain (252.red-83-54-181.dynamicip.rima-tde.net. [83.54.181.252]) by smtp.gmail.com with ESMTPSA id u19sm483602wmm.5.2021.10.30.07.40.16 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 30 Oct 2021 07:40:17 -0700 (PDT) From: Sergio Paracuellos To: sboyd@kernel.org Cc: linux-clk@vger.kernel.org, gregkh@linuxfoundation.org, linux-staging@lists.linux.dev, neil@brown.name, linux-kernel@vger.kernel.org, john@phrozen.org, Rob Herring Subject: [PATCH v4 1/4] dt-bindings: reset: add dt binding header for Mediatek MT7621 resets Date: Sat, 30 Oct 2021 16:40:11 +0200 Message-Id: <20211030144014.26315-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211030144014.26315-1-sergio.paracuellos@gmail.com> References: <20211030144014.26315-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add dt binding header for resets lines in Mediatek MT7621 SoCs. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/reset/mt7621-reset.h | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 include/dt-bindings/reset/mt7621-reset.h diff --git a/include/dt-bindings/reset/mt7621-reset.h b/include/dt-bindings/reset/mt7621-reset.h new file mode 100644 index 000000000000..7572c6b41453 --- /dev/null +++ b/include/dt-bindings/reset/mt7621-reset.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 Sergio Paracuellos + * Author: Sergio Paracuellos + */ + +#ifndef DT_BINDING_MT7621_RESET_H +#define DT_BINDING_MT7621_RESET_H + +#define MT7621_RST_SYS 0 +#define MT7621_RST_MCM 2 +#define MT7621_RST_HSDMA 5 +#define MT7621_RST_FE 6 +#define MT7621_RST_SPDIFTX 7 +#define MT7621_RST_TIMER 8 +#define MT7621_RST_INT 9 +#define MT7621_RST_MC 10 +#define MT7621_RST_PCM 11 +#define MT7621_RST_PIO 13 +#define MT7621_RST_GDMA 14 +#define MT7621_RST_NFI 15 +#define MT7621_RST_I2C 16 +#define MT7621_RST_I2S 17 +#define MT7621_RST_SPI 18 +#define MT7621_RST_UART1 19 +#define MT7621_RST_UART2 20 +#define MT7621_RST_UART3 21 +#define MT7621_RST_ETH 23 +#define MT7621_RST_PCIE0 24 +#define MT7621_RST_PCIE1 25 +#define MT7621_RST_PCIE2 26 +#define MT7621_RST_AUX_STCK 28 +#define MT7621_RST_CRYPTO 29 +#define MT7621_RST_SDXC 30 +#define MT7621_RST_PPE 31 + +#endif /* DT_BINDING_MT7621_RESET_H */ From patchwork Sat Oct 30 14:40:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12594427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89D3BC433EF for ; Sat, 30 Oct 2021 14:40:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 697AF61058 for ; Sat, 30 Oct 2021 14:40:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231911AbhJ3Omv (ORCPT ); Sat, 30 Oct 2021 10:42:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231421AbhJ3Omu (ORCPT ); Sat, 30 Oct 2021 10:42:50 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05DD5C061570; Sat, 30 Oct 2021 07:40:20 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id f7-20020a1c1f07000000b0032ee11917ceso5128932wmf.0; Sat, 30 Oct 2021 07:40:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OJp/wZiERGVBUU7HIuspGPpojRpXm2e3BfdSR6ZgDTc=; b=d5toudcTVdIEVYCVYXWFZjlG/GeMQ4BLjm/uq9/kHYBx/ZXd8GIMr2n/DGTWCGJ+9f PzR4W1+x84oIoruGgufXmG91NGKbaj85h94ZMW7tqrO7t+bBkbJQoxI7dd0+0w6Xok2e 5oj4Wo8+Jm5s8wcu1aK6L6gkKVzLSlK81RPk7V/5oCKLONIygzWkfveHW7E3Ob/e/YIO 40Ui1GAGSwtz/xsChZ/3pRdJCl3Jews/X05cxlVXXjTTJUzQ9w2J55KLdKj9D1RZ5GKy 7zuhmxQFW908SyOI22BYyT2fJrx2CgVcMJhh6n2HiEdj+ZzADR+LGEjDZG7kMsa/6WhS c3Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OJp/wZiERGVBUU7HIuspGPpojRpXm2e3BfdSR6ZgDTc=; b=a/KJeNdUX4wHS8MjRustIZ3B3ass6d2BXcdOMoyiDwd8GM70uIuTK2bBCa75RJd68+ jewnNhp2rj/eXgwADeM3+dI4ncthFvl6x3qYS0GusmkLbMz2/ShcdMGZvIW3mpndelug K02SWhUc9qtOEYZXEvIF5Yv77zUa7NGVRWXdQxJeb/x3Xixy1chPx8yU1HBCB5bxmmiR c8sUxqzTn2QuGTcJd4LLMMxkr7/6vhyKDUfEhzR33gYTHXbNQ8zn68ZuVxl4Nr8e+tIP bLOcwdaVKqtEmB5+WfiqgZHUx7ilJDW7++lneNfd/tQdorbf9KF8mllnjaEyIs7nJbk1 JJYg== X-Gm-Message-State: AOAM533yNjmKdb/UCgkmzU+gyGOoqYVlJZu4mN7bzqwD1VuXYXBpeStv SXv0MeRXYiIj981f+80sPFg= X-Google-Smtp-Source: ABdhPJziKvxTucgWl5y9YXjQAT3kxG1nEmAYfSWwkfmBh7bm7FI5+fEy15cyGehOUUzIzYPcRsvIdg== X-Received: by 2002:a7b:cc11:: with SMTP id f17mr19406047wmh.122.1635604818629; Sat, 30 Oct 2021 07:40:18 -0700 (PDT) Received: from localhost.localdomain (252.red-83-54-181.dynamicip.rima-tde.net. [83.54.181.252]) by smtp.gmail.com with ESMTPSA id u19sm483602wmm.5.2021.10.30.07.40.17 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 30 Oct 2021 07:40:18 -0700 (PDT) From: Sergio Paracuellos To: sboyd@kernel.org Cc: linux-clk@vger.kernel.org, gregkh@linuxfoundation.org, linux-staging@lists.linux.dev, neil@brown.name, linux-kernel@vger.kernel.org, john@phrozen.org, Rob Herring Subject: [PATCH v4 2/4] dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property Date: Sat, 30 Oct 2021 16:40:12 +0200 Message-Id: <20211030144014.26315-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211030144014.26315-1-sergio.paracuellos@gmail.com> References: <20211030144014.26315-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Make system controller a reset provider for all the peripherals in the MT7621 SoC adding '#reset-cells' property. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-sysc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml index 915f84efd763..0c0b0ae5e2ac 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml @@ -22,6 +22,11 @@ description: | The clocks are provided inside a system controller node. + This node is also a reset provider for all the peripherals. + + Reset related bits are defined in: + [2]: . + properties: compatible: items: @@ -37,6 +42,12 @@ properties: clocks. const: 1 + "#reset-cells": + description: + The first cell indicates the reset bit within the register, see + [2] for available resets. + const: 1 + ralink,memctl: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -61,6 +72,7 @@ examples: compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; #clock-cells = <1>; + #reset-cells = <1>; ralink,memctl = <&memc>; clock-output-names = "xtal", "cpu", "bus", "50m", "125m", "150m", From patchwork Sat Oct 30 14:40:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12594429 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2A4CC433FE for ; Sat, 30 Oct 2021 14:40:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BBCA460F58 for ; Sat, 30 Oct 2021 14:40:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231936AbhJ3Omx (ORCPT ); Sat, 30 Oct 2021 10:42:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231905AbhJ3Omv (ORCPT ); Sat, 30 Oct 2021 10:42:51 -0400 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24A9CC061714; Sat, 30 Oct 2021 07:40:21 -0700 (PDT) Received: by mail-wm1-x332.google.com with SMTP id 133so1056214wme.0; Sat, 30 Oct 2021 07:40:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4aD4ZDxJstzmt0vUvyM6aWTJh0HAiDU6XH10PQEfpns=; b=hIrR9xMEcdC+YPBpOd6ixrlZnuJrULr63EY47sIedWF8DTx0MQlREZklevogYvMCec JiQVkOrKoc5xxs9Gqe+k0LfS9jzXgnM/KuTqPgPgQ3bHR77uorAWsJzZQeAUzGhOEREE BpkYzCpOQppc8o6pctLj2g3sQtTAjowVMg+Ovd87h36iVWaMTOKfpqiFTrepfLXiYIEh N9KbUQf2tgM9PG9iVudJwkoCAdfepU69TnYjxrpFdU+BDdfWM3KmYbY1PH7zO06yyC4e 4vVUzMmYhg2QGfr8Y0vNv+nTUh8njm91YCKmSLYVHg8+nGYW3wPzRPUSVdoWihExmcro QnCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4aD4ZDxJstzmt0vUvyM6aWTJh0HAiDU6XH10PQEfpns=; b=BfcpsejSHdMyD646Q1OMR5qvOBN+Uaj7cfTbSR6CRgTp+VyBqXbgeclp0HApcFyeSo OodzkV+fLJhyKFqLFBtGLI8HWBUlux13UY66ggJmay0U8bbDNX7ztvdhbegQN3iZJYTx tkIoCe/pzKQmbdg5LPcbr+LRtzFBS+VwfkDRzMM2b9TlDCJChufhsM5o5xHVvZv9bgKx S8XQ38YxYPf41pVEXXa1t3A5SwxirYZ4oxgAKSJrbkHb9iFlEYMSQhEL7qdVAAQ48LaU 7ictTQIq9edDI5KNMpoaKHlpUOkctJTaPdL3IW/BNTc/6XOWKDQCBXYERFlJVTTbjvGk tiVw== X-Gm-Message-State: AOAM530gATZHyj/IODkRXHOM1Oo56qMxSOrck7jDeJRPpNpH1oceoEvI BxQ0S5X/2wpaDp2OhFWuE2M= X-Google-Smtp-Source: ABdhPJxvshz4oCCeQtluyBCzudW5xIP2lz7qm0UTxXAh8g++1F/BbK0mZVDu+n8QKLVNntLJfJSUZg== X-Received: by 2002:a05:600c:49a2:: with SMTP id h34mr5391253wmp.40.1635604819757; Sat, 30 Oct 2021 07:40:19 -0700 (PDT) Received: from localhost.localdomain (252.red-83-54-181.dynamicip.rima-tde.net. [83.54.181.252]) by smtp.gmail.com with ESMTPSA id u19sm483602wmm.5.2021.10.30.07.40.18 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 30 Oct 2021 07:40:19 -0700 (PDT) From: Sergio Paracuellos To: sboyd@kernel.org Cc: linux-clk@vger.kernel.org, gregkh@linuxfoundation.org, linux-staging@lists.linux.dev, neil@brown.name, linux-kernel@vger.kernel.org, john@phrozen.org Subject: [PATCH v4 3/4] clk: ralink: make system controller node a reset provider Date: Sat, 30 Oct 2021 16:40:13 +0200 Message-Id: <20211030144014.26315-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211030144014.26315-1-sergio.paracuellos@gmail.com> References: <20211030144014.26315-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org MT7621 system controller node is already providing the clocks for the whole system but must also serve as a reset provider. Hence, add reset controller related code to the clock driver itself. Signed-off-by: Sergio Paracuellos --- drivers/clk/ralink/clk-mt7621.c | 79 +++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c index a2c045390f00..328ebf746703 100644 --- a/drivers/clk/ralink/clk-mt7621.c +++ b/drivers/clk/ralink/clk-mt7621.c @@ -11,14 +11,17 @@ #include #include #include +#include #include #include +#include /* Configuration registers */ #define SYSC_REG_SYSTEM_CONFIG0 0x10 #define SYSC_REG_SYSTEM_CONFIG1 0x14 #define SYSC_REG_CLKCFG0 0x2c #define SYSC_REG_CLKCFG1 0x30 +#define SYSC_REG_RESET_CTRL 0x34 #define SYSC_REG_CUR_CLK_STS 0x44 #define MEMC_REG_CPU_PLL 0x648 @@ -398,6 +401,76 @@ static void __init mt7621_clk_init(struct device_node *node) } CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init); +struct mt7621_rst { + struct reset_controller_dev rcdev; + struct regmap *sysc; +}; + +static inline struct mt7621_rst *to_mt7621_rst(struct reset_controller_dev *dev) +{ + return container_of(dev, struct mt7621_rst, rcdev); +} + +static int mt7621_assert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + if (id == MT7621_RST_SYS) + return -EINVAL; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id)); +} + +static int mt7621_deassert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + if (id == MT7621_RST_SYS) + return -EINVAL; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0); +} + +static int mt7621_reset_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = mt7621_assert_device(rcdev, id); + if (ret < 0) + return ret; + + return mt7621_deassert_device(rcdev, id); +} + +static const struct reset_control_ops reset_ops = { + .reset = mt7621_reset_device, + .assert = mt7621_assert_device, + .deassert = mt7621_deassert_device +}; + +static int mt7621_reset_init(struct device *dev, struct regmap *sysc) +{ + struct mt7621_rst *rst_data; + + rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); + if (!rst_data) + return -ENOMEM; + + rst_data->sysc = sysc; + rst_data->rcdev.ops = &reset_ops; + rst_data->rcdev.owner = THIS_MODULE; + rst_data->rcdev.nr_resets = 32; + rst_data->rcdev.of_reset_n_cells = 1; + rst_data->rcdev.of_node = dev_of_node(dev); + + return devm_reset_controller_register(dev, &rst_data->rcdev); +} + static int mt7621_clk_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -424,6 +497,12 @@ static int mt7621_clk_probe(struct platform_device *pdev) return ret; } + ret = mt7621_reset_init(dev, priv->sysc); + if (ret) { + dev_err(dev, "Could not init reset controller\n"); + return ret; + } + count = ARRAY_SIZE(mt7621_clks_base) + ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates); clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count), From patchwork Sat Oct 30 14:40:14 2021 Content-Type: text/plain; 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[83.54.181.252]) by smtp.gmail.com with ESMTPSA id u19sm483602wmm.5.2021.10.30.07.40.19 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 30 Oct 2021 07:40:20 -0700 (PDT) From: Sergio Paracuellos To: sboyd@kernel.org Cc: linux-clk@vger.kernel.org, gregkh@linuxfoundation.org, linux-staging@lists.linux.dev, neil@brown.name, linux-kernel@vger.kernel.org, john@phrozen.org Subject: [PATCH v4 4/4] staging: mt7621-dts: align resets with binding documentation Date: Sat, 30 Oct 2021 16:40:14 +0200 Message-Id: <20211030144014.26315-5-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211030144014.26315-1-sergio.paracuellos@gmail.com> References: <20211030144014.26315-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Binding documentation for compatible 'mediatek,mt7621-sysc' has been updated to be used as a reset provider. Align reset related bits and system controller node with binding documentation along the dtsi file. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts/mt7621.dtsi | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 6d158e4f4b8c..2bf74468d495 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -2,6 +2,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -67,6 +68,7 @@ sysc: syscon@0 { compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; #clock-cells = <1>; + #reset-cells = <1>; ralink,memctl = <&memc>; clock-output-names = "xtal", "cpu", "bus", "50m", "125m", "150m", @@ -96,7 +98,7 @@ i2c: i2c@900 { clocks = <&sysc MT7621_CLK_I2C>; clock-names = "i2c"; - resets = <&rstctrl 16>; + resets = <&sysc MT7621_RST_I2C>; reset-names = "i2c"; #address-cells = <1>; @@ -137,7 +139,7 @@ spi0: spi@b00 { clocks = <&sysc MT7621_CLK_SPI>; clock-names = "spi"; - resets = <&rstctrl 18>; + resets = <&sysc MT7621_RST_SPI>; reset-names = "spi"; #address-cells = <1>; @@ -153,7 +155,7 @@ gdma: gdma@2800 { clocks = <&sysc MT7621_CLK_GDMA>; clock-names = "gdma"; - resets = <&rstctrl 14>; + resets = <&sysc MT7621_RST_GDMA>; reset-names = "dma"; interrupt-parent = <&gic>; @@ -172,7 +174,7 @@ hsdma: hsdma@7000 { clocks = <&sysc MT7621_CLK_HSDMA>; clock-names = "hsdma"; - resets = <&rstctrl 5>; + resets = <&sysc MT7621_RST_HSDMA>; reset-names = "hsdma"; interrupt-parent = <&gic>; @@ -272,11 +274,6 @@ pinmux { }; }; - rstctrl: rstctrl { - compatible = "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - sdhci: sdhci@1e130000 { status = "disabled"; @@ -355,7 +352,7 @@ ethernet: ethernet@1e100000 { #address-cells = <1>; #size-cells = <0>; - resets = <&rstctrl 6 &rstctrl 23>; + resets = <&sysc MT7621_CLK_FE &sysc MT7621_CLK_ETH>; reset-names = "fe", "eth"; interrupt-parent = <&gic>; @@ -400,7 +397,7 @@ switch0: switch0@0 { #size-cells = <0>; reg = <0>; mediatek,mcm; - resets = <&rstctrl 2>; + resets = <&sysc MT7621_RST_MCM>; reset-names = "mcm"; interrupt-controller; #interrupt-cells = <1>; @@ -486,7 +483,7 @@ pcie@0,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 24>; + resets = <&sysc MT7621_RST_PCIE0>; clocks = <&sysc MT7621_CLK_PCIE0>; phys = <&pcie0_phy 1>; phy-names = "pcie-phy0"; @@ -501,7 +498,7 @@ pcie@1,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 25>; + resets = <&sysc MT7621_RST_PCIE1>; clocks = <&sysc MT7621_CLK_PCIE1>; phys = <&pcie0_phy 1>; phy-names = "pcie-phy1"; @@ -516,7 +513,7 @@ pcie@2,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 26>; + resets = <&sysc MT7621_RST_PCIE2>; clocks = <&sysc MT7621_CLK_PCIE2>; phys = <&pcie2_phy 0>; phy-names = "pcie-phy2";