From patchwork Mon Dec 17 06:01:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Schaeckeler X-Patchwork-Id: 10732771 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B2CC713AD for ; Mon, 17 Dec 2018 06:04:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9E11428632 for ; Mon, 17 Dec 2018 06:04:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9210F28803; Mon, 17 Dec 2018 06:04:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A57B928632 for ; Mon, 17 Dec 2018 06:04:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=NHZFS2FGVqImZ9pValc33rsNv2SL1Ih6EBEPrwRyxjs=; b=gUdgH++l4vpDkLs2A9zIG2CqDq J+7WQLy/eupREVosN20iqeOxuSxI12mUBUeHSAWlQslXxytxkgCZXyEUk6uflFiFol4F3iJFjskJT oahWnIaxEniBRvMJY/3XDjdnwtY7Dr6q9rhsxWufrZg/9/Tj6I07xaKnxZfXU6Qr3WXjVFGALqrV3 jud6JSfFWt6xxavIUuePtl1dBnv0g+YLE0QmTXbpmNixOhEhO9nxplaTKqwPAyUIttv8/b/pkTCGD q5ZEpiD3aZDWlHllFq0KiCC4+R3D5zMCqmLE2uXSstwRWKSVIcJg7/Kck5M8xNY5Hlewfet3QBQVa idQdHUfw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gYm0q-0003Wh-Hf; Mon, 17 Dec 2018 06:04:20 +0000 Received: from mout.gmx.net ([212.227.15.19]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gYm0Q-00030T-Nj for linux-arm-kernel@lists.infradead.org; Mon, 17 Dec 2018 06:03:58 +0000 Received: from corona.crabdance.com ([173.228.106.209]) by mail.gmx.com (mrgmx002 [212.227.17.190]) with ESMTPSA (Nemesis) id 0LanoO-1hJ46T2Q1I-00kLrp; Mon, 17 Dec 2018 07:03:30 +0100 Received: by corona.crabdance.com (Postfix, from userid 1001) id 4A8956E85605; Sun, 16 Dec 2018 22:03:19 -0800 (PST) From: Stefan Schaeckeler To: Rob Herring , Mark Rutland , Joel Stanley , Andrew Jeffery , Borislav Petkov , Mauro Carvalho Chehab , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-edac@vger.kernel.org Subject: [PATCH 1/2] EDAC: Add Aspeed AST2500 EDAC driver Date: Sun, 16 Dec 2018 22:01:56 -0800 Message-Id: <1545026517-64069-2-git-send-email-schaecsn@gmx.net> X-Mailer: git-send-email 2.4.5 In-Reply-To: <1545026517-64069-1-git-send-email-schaecsn@gmx.net> References: <1545026517-64069-1-git-send-email-schaecsn@gmx.net> X-Provags-ID: V03:K1:lq9rUW5qXZPLF0L+W6uQB6KV7jL3hEe7kbkYJcvach9XCCa+3S5 kjnDtjZxA/fE8ir9ydn2os8l5QiKg9RVHHtO0EaReWmxful3LROzfqfadjXM2oG3GWbqIr+ 5wBlHKCKuty7kF8q73w17VVTpzIazV458BWmH7jn/IGvCx8JgdM36Mq4ZCnAjRoZXUvaFuh mDMwO156AK3JmarGjQh8Q== X-UI-Out-Filterresults: notjunk:1;V03:K0:VGbxVwVSGPQ=:p4K1tRuiCd77L+ij38XLD/ PYHblYZ5b4vf3JSRYdWGnSbU5gCj6H19QU30srxmrKbhhI0dZrd2ZaWXg4wE9vaLu2ffUgftF J51R5K5sYaRUS1RtrBEtHEMYHv8qtQ2/4Ra+qeBj/nPEpXe5MHGxiQTByxUGDj+wY4xn4rq5I ZYebADOG6gwny5UJfdTNivPuWvldi+WuqbgGddYDIy0Q755ozQxtZMvWcD4syxEwcYz9iPX+r u5UHk3u7oWYRi1R4Atf1E2lPh+czp6L8vKKcm2m+JxGmRlljyehY2AVfSTgvw12PBuJK1Ck0N 5UugjjzO2OuwBE6g8bF7uLnDiMohebBoQtu+nCr2wvx20B5oafC245JSjKrrjTLPpOewEN9Sx LIj1Q3NKUSM8vmIOYXd6px+8WthzXv+o5J0a2GpCkggpvL53+SlgQpwVviBWzn63er85xuNW3 MwrFmICDkdXvVpDov/BUaqUV0eqeD4/oE/pyFILYJaHCOk23LDm0ioqNrTgTLahZH7vnEUlXL 8m3bAGZnZJx5UYEPToDHohvOFFOse9GEZRGjuFZ6SM2MQ0y3vjfhha2gsbKeVX3ckiOCq7/0i LZ2kqgVOaQKM4D59p+xY+vb4MzK64c0hVYF7VPyfvqVOjcZ5e+iCpmzAs3VgoCKOqDCb1NGvb QIHkdPZQzO3JckP/ooP3XR6DLwZcPPM/0TE657LTR+VR0CkJsKuYr/mzixQN++VIp09h4ga9u Hc+rQ6EUKJ9YmnWBBusay7Mpjfo24chIYal6v9fnlsXhGkVXICzjAiSFwlGz/U42CN2q91KZt BaqnF/vnURj5kIK/vzNU6Kzz58TqrVweRdei5hXm3zDAtDLnA12pUWjaVP+rN7yubDT7LYM57 IkTjUQHhwN97sLWNaEaQbd7s9ExDJ4XsdQbFqe6kg= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181216_220355_256819_4B0855C1 X-CRM114-Status: GOOD ( 22.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan M Schaeckeler MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Stefan M Schaeckeler Add support for the Aspeed AST2500 SoC EDAC driver. Signed-off-by: Stefan M Schaeckeler --- MAINTAINERS | 6 + arch/arm/boot/dts/aspeed-g5.dtsi | 7 + drivers/edac/Kconfig | 7 + drivers/edac/Makefile | 1 + drivers/edac/aspeed_edac.c | 457 +++++++++++++++++++++++++++++++ 5 files changed, 478 insertions(+) create mode 100644 drivers/edac/aspeed_edac.c diff --git a/MAINTAINERS b/MAINTAINERS index 3318f30903b2..1feb92b14029 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5315,6 +5315,12 @@ L: linux-edac@vger.kernel.org S: Maintained F: drivers/edac/amd64_edac* +EDAC-AST2500 +M: Stefan Schaeckeler +S: Supported +F: drivers/edac/aspeed_edac.c +F: Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt + EDAC-CALXEDA M: Robert Richter L: linux-edac@vger.kernel.org diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index d107459fc0f8..b4e479ab5a2d 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -47,6 +47,13 @@ reg = <0x80000000 0>; }; + edac: sdram@1e6e0000 { + compatible = "aspeed,ast2500-sdram-edac"; + reg = <0x1e6e0000 0x174>; + interrupts = <0>; + status = "disabled"; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 41c9ccdd20d6..67834430b0a1 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -475,4 +475,11 @@ config EDAC_QCOM For debugging issues having to do with stability and overall system health, you should probably say 'Y' here. +config EDAC_ASPEED + tristate "Aspeed AST 2500 SoC" + depends on MACH_ASPEED_G5 + help + Support for error detection and correction on the + Aspeed AST 2500 SoC. + endif # EDAC diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 716096d08ea0..e1f23d4ff860 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -78,3 +78,4 @@ obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o obj-$(CONFIG_EDAC_TI) += ti_edac.o obj-$(CONFIG_EDAC_QCOM) += qcom_edac.o +obj-$(CONFIG_EDAC_ASPEED) += aspeed_edac.o diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c new file mode 100644 index 000000000000..d6ed119909eb --- /dev/null +++ b/drivers/edac/aspeed_edac.c @@ -0,0 +1,457 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 Cisco Systems + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "edac_module.h" + + +#define DRV_NAME "aspeed-edac" + + +/* registers */ +#define ASPEED_MCR_PROT 0x00 /* protection key register */ +#define ASPEED_MCR_CONF 0x04 /* configuration register */ +#define ASPEED_MCR_INTR_CTRL 0x50 /* interrupt control/status register */ +#define ASPEED_MCR_ADDR_UNREC 0x58 /* address of first un-recoverable error */ +#define ASPEED_MCR_ADDR_REC 0x5c /* address of last recoverable error */ +#define ASPEED_MCR_LAST ASPEED_MCR_ADDR_REC + + +/* bits and masks */ +#define ASPEED_MCR_PROT_PASSWD 0xfc600309 +#define ASPEED_MCR_CONF_DRAM_TYPE BIT(4) +#define ASPEED_MCR_CONF_ECC BIT(7) +#define ASPEED_MCR_INTR_CTRL_CLEAR BIT(31) +#define ASPEED_MCR_INTR_CTRL_CNT_REC GENMASK(23, 16) +#define ASPEED_MCR_INTR_CTRL_CNT_UNREC GENMASK(15, 12) +#define ASPEED_MCR_INTR_CTRL_ENABLE (BIT(0) | BIT(1)) + + + +static int aspeed_edac_regmap_reg_write(void *context, unsigned int reg, + unsigned int val) +{ + void __iomem *regs = (void __iomem *)context; + + /* enable write to MCR register set */ + writel(ASPEED_MCR_PROT_PASSWD, regs + ASPEED_MCR_PROT); + + writel(val, regs + reg); + + /* disable write to MCR register set */ + writel(~ASPEED_MCR_PROT_PASSWD, regs + ASPEED_MCR_PROT); + + return 0; +} + + +static int aspeed_edac_regmap_reg_read(void *context, unsigned int reg, + unsigned int *val) +{ + void __iomem *regs = (void __iomem *)context; + + *val = readl(regs + reg); + + return 0; +} + +static bool aspeed_edac_regmap_is_volatile(struct device *dev, + unsigned int reg) +{ + switch (reg) { + case ASPEED_MCR_PROT: + case ASPEED_MCR_INTR_CTRL: + case ASPEED_MCR_ADDR_UNREC: + case ASPEED_MCR_ADDR_REC: + return true; + default: + return false; + } +} + + +static const struct regmap_config aspeed_edac_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = ASPEED_MCR_LAST, + .reg_write = aspeed_edac_regmap_reg_write, + .reg_read = aspeed_edac_regmap_reg_read, + .volatile_reg = aspeed_edac_regmap_is_volatile, + .fast_io = true, +}; + + +static struct regmap *aspeed_edac_regmap; + + +static void aspeed_edac_count_rec(struct mem_ctl_info *mci, + u8 rec_cnt, + u32 rec_addr) +{ + struct csrow_info *csrow = mci->csrows[0]; + u32 page, offset, syndrome; + + if (rec_cnt > 0) { + /* report first few errors (if there are) */ + /* note: no addresses are recorded */ + if (rec_cnt > 1) { + page = 0; /* not available */ + offset = 0; /* not available */ + syndrome = 0; /* not available */ + edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, + rec_cnt-1, page, offset, + syndrome, 0, 0, -1, + "address(es) not available", ""); + } + + /* report last error */ + /* note: rec_addr is the last recoverable error addr */ + page = rec_addr >> PAGE_SHIFT; + offset = rec_addr & ~PAGE_MASK; + syndrome = 0; /* not available */ + edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, + csrow->first_page + page, offset, syndrome, + 0, 0, -1, "", ""); + } +} + + +static void aspeed_edac_count_un_rec(struct mem_ctl_info *mci, + u8 un_rec_cnt, + u32 un_rec_addr) +{ + struct csrow_info *csrow = mci->csrows[0]; + u32 page, offset, syndrome; + + if (un_rec_cnt > 0) { + /* report 1. error */ + /* note: un_rec_addr is the first unrecoverable error addr */ + page = un_rec_addr >> PAGE_SHIFT; + offset = un_rec_addr & ~PAGE_MASK; + syndrome = 0; /* not available */ + edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, + csrow->first_page + page, offset, syndrome, + 0, 0, -1, "", ""); + + /* report further errors (if there are) */ + /* note: no addresses are recorded */ + if (un_rec_cnt > 1) { + page = 0; /* not available */ + offset = 0; /* not available */ + syndrome = 0; /* not available */ + edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, + un_rec_cnt-1, page, offset, + syndrome, 0, 0, -1, + "address(es) not available", ""); + } + } +} + + +static void aspeed_edac_enable_interrupts(void) +{ + + regmap_update_bits(aspeed_edac_regmap, ASPEED_MCR_INTR_CTRL, + ASPEED_MCR_INTR_CTRL_ENABLE, + ASPEED_MCR_INTR_CTRL_ENABLE); +} + + +static void aspeed_edac_disable_interrupts(void) +{ + regmap_update_bits(aspeed_edac_regmap, ASPEED_MCR_INTR_CTRL, + ASPEED_MCR_INTR_CTRL_ENABLE, 0); +} + + +static void aspeed_edac_clear_interrupts(void) +{ + regmap_update_bits(aspeed_edac_regmap, ASPEED_MCR_INTR_CTRL, + ASPEED_MCR_INTR_CTRL_CLEAR, + ASPEED_MCR_INTR_CTRL_CLEAR); + + regmap_update_bits(aspeed_edac_regmap, ASPEED_MCR_INTR_CTRL, + ASPEED_MCR_INTR_CTRL_CLEAR, 0); +} + + +static irqreturn_t aspeed_edac_isr(int irq, void *arg) +{ + u8 rec_cnt, un_rec_cnt; + u32 rec_addr, un_rec_addr; + struct mem_ctl_info *mci = arg; + u32 reg50, reg5c, reg58; + + regmap_read(aspeed_edac_regmap, ASPEED_MCR_INTR_CTRL, ®50); + dev_dbg(mci->pdev, "received edac interrupt w/ mmc register 50: 0x%x\n", + reg50); + + /* collect data about recoverable and unrecoverable errors */ + rec_cnt = (reg50 & ASPEED_MCR_INTR_CTRL_CNT_REC) >> 16; + un_rec_cnt = (reg50 & ASPEED_MCR_INTR_CTRL_CNT_UNREC) >> 12; + + dev_dbg(mci->pdev, "%d recoverable interrupts and %d unrecoverable interrupts\n", + rec_cnt, un_rec_cnt); + + regmap_read(aspeed_edac_regmap, ASPEED_MCR_ADDR_UNREC, ®58); + un_rec_addr = reg58 >> 4; + + regmap_read(aspeed_edac_regmap, ASPEED_MCR_ADDR_REC, ®5c); + rec_addr = reg5c >> 4; + + /* clear interrupt flags and error counters: */ + aspeed_edac_clear_interrupts(); + + /* process recoverable and unrecoverable errors */ + if (rec_cnt > 0) + aspeed_edac_count_rec(mci, rec_cnt, rec_addr); + + if (un_rec_cnt > 0) + aspeed_edac_count_un_rec(mci, un_rec_cnt, un_rec_addr); + + if ((rec_cnt == 0) && (un_rec_cnt == 0)) + dev_dbg(mci->pdev, "received edac interrupt, but did not find any ecc counters\n"); + + regmap_read(aspeed_edac_regmap, ASPEED_MCR_INTR_CTRL, ®50); + dev_dbg(mci->pdev, "edac interrupt handled. mmc reg 50 is now: 0x%x\n", + reg50); + + return IRQ_HANDLED; +} + + +static int aspeed_edac_config_irq(void *ctx, + struct platform_device *pdev) +{ + int irq; + int rc; + + /* register interrupt handler */ + + irq = platform_get_irq(pdev, 0); + dev_dbg(&pdev->dev, "got irq %d\n", irq); + if (!irq) + return -ENODEV; + + rc = devm_request_irq(&pdev->dev, irq, aspeed_edac_isr, + IRQF_TRIGGER_HIGH, DRV_NAME, ctx); + if (rc) { + dev_err(&pdev->dev, "unable to request irq %d\n", irq); + return rc; + } + + /* enable interrupts */ + aspeed_edac_enable_interrupts(); + + return 0; +} + + +static int aspeed_edac_init_csrows(struct mem_ctl_info *mci) +{ + struct csrow_info *csrow = mci->csrows[0]; + struct dimm_info *dimm; + struct device_node *np; + u32 nr_pages, dram_type; + struct resource r; + u32 reg04; + int rc; + + /* retrieve info about physical memory from device tree */ + np = of_find_node_by_path("/memory"); + + if (!np) { + dev_err(mci->pdev, "dt: missing /memory node\n"); + return -ENODEV; + }; + + rc = of_address_to_resource(np, 0, &r); + + of_node_put(np); + + if (rc) { + dev_err(mci->pdev, "dt: failed requesting resource for /memory node\n"); + return rc; + }; + + dev_dbg(mci->pdev, "dt: /memory node resources: first page r.start=0x%x, resource_size=0x%x, PAGE_SHIFT macro=0x%x\n", + r.start, resource_size(&r), PAGE_SHIFT); + + csrow->first_page = r.start >> PAGE_SHIFT; + nr_pages = resource_size(&r) >> PAGE_SHIFT; + csrow->last_page = csrow->first_page + nr_pages - 1; + + regmap_read(aspeed_edac_regmap, ASPEED_MCR_CONF, ®04); + dram_type = (reg04 & ASPEED_MCR_CONF_DRAM_TYPE) ? MEM_DDR4 : MEM_DDR3; + + dimm = csrow->channels[0]->dimm; + dimm->mtype = dram_type; + dimm->edac_mode = EDAC_SECDED; + dimm->nr_pages = nr_pages / csrow->nr_channels; + + dev_dbg(mci->pdev, "initialized dimm with first_page=0x%lx and nr_pages=0x%x\n", + csrow->first_page, nr_pages); + + return 0; +} + + +static int aspeed_edac_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + void __iomem *regs; + struct resource *res; + struct mem_ctl_info *mci; + struct edac_mc_layer layers[2]; + struct device_node *np; + u32 reg04; + int rc; + + /* setup regmap */ + np = dev->of_node; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENOENT; + + regs = devm_ioremap_resource(dev, res); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + aspeed_edac_regmap = devm_regmap_init(dev, NULL, (__force void *)regs, + &aspeed_edac_regmap_config); + if (IS_ERR(aspeed_edac_regmap)) + return PTR_ERR(aspeed_edac_regmap); + + /* bail out if ECC mode is not configured */ + regmap_read(aspeed_edac_regmap, ASPEED_MCR_CONF, ®04); + if (!(reg04 & ASPEED_MCR_CONF_ECC)) { + dev_err(&pdev->dev, "ECC mode is not configured in u-boot\n"); + return -EPERM; + } + + edac_op_state = EDAC_OPSTATE_INT; + + /* allocate & init EDAC MC data structure */ + layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; + layers[0].size = 1; + layers[0].is_virt_csrow = true; + layers[1].type = EDAC_MC_LAYER_CHANNEL; + layers[1].size = 1; + layers[1].is_virt_csrow = false; + + mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); + if (mci == NULL) + return -ENOMEM; + + mci->pdev = &pdev->dev; + mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR4; + mci->edac_ctl_cap = EDAC_FLAG_SECDED; + mci->edac_cap = EDAC_FLAG_SECDED; + mci->scrub_cap = SCRUB_FLAG_HW_SRC; + mci->scrub_mode = SCRUB_HW_SRC; + mci->mod_name = DRV_NAME; + mci->ctl_name = "MIC"; + mci->dev_name = dev_name(&pdev->dev); + + rc = aspeed_edac_init_csrows(mci); + if (rc) { + dev_err(&pdev->dev, "failed to init csrows\n"); + goto probe_exit02; + } + + platform_set_drvdata(pdev, mci); + + /* register with edac core */ + rc = edac_mc_add_mc(mci); + if (rc) { + dev_err(&pdev->dev, "failed to register with EDAC core\n"); + goto probe_exit02; + } + + /* register interrupt handler and enable interrupts */ + rc = aspeed_edac_config_irq(mci, pdev); + if (rc) { + dev_err(&pdev->dev, "failed setting up irq\n"); + goto probe_exit01; + } + + return 0; + +probe_exit01: + edac_mc_del_mc(&pdev->dev); +probe_exit02: + edac_mc_free(mci); + return rc; +} + + +static int aspeed_edac_remove(struct platform_device *pdev) +{ + struct mem_ctl_info *mci; + + /* disable interrupts */ + aspeed_edac_disable_interrupts(); + + /* free resources */ + mci = edac_mc_del_mc(&pdev->dev); + if (mci) + edac_mc_free(mci); + + return 0; +} + + +static const struct of_device_id aspeed_edac_of_match[] = { + { .compatible = "aspeed,ast2500-sdram-edac" }, + {}, +}; + + +static struct platform_driver aspeed_edac_driver = { + .driver = { + .name = DRV_NAME, + .of_match_table = aspeed_edac_of_match + }, + .probe = aspeed_edac_probe, + .remove = aspeed_edac_remove +}; + + +static int __init aspeed_edac_init(void) +{ + return platform_driver_register(&aspeed_edac_driver); +} + + +static void __exit aspeed_edac_exit(void) +{ + platform_driver_unregister(&aspeed_edac_driver); +} + + +module_init(aspeed_edac_init); +module_exit(aspeed_edac_exit); + + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Stefan Schaeckeler "); +MODULE_DESCRIPTION("Aspeed AST2500 EDAC driver"); +MODULE_VERSION("1.0"); From patchwork Mon Dec 17 06:01:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Schaeckeler X-Patchwork-Id: 10732769 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 000E2746 for ; Mon, 17 Dec 2018 06:04:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E29192841C for ; Mon, 17 Dec 2018 06:04:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D582D2853E; Mon, 17 Dec 2018 06:04:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7C8642841C for ; Mon, 17 Dec 2018 06:04:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=gaCjjViIrImGyNK9STjkWAz3Rujv1wqBagQYWPNxizk=; b=f7pY/QOCsfzVp7nUl9LRB50qqK BiErqRKKuvSJRa13Xds81vcYzG3Yl0atLzvA7L/CiA68/hQg4mxWx+OGCkiWlZ5oZnGUg/0nTgxES 0F4+9fiK0nVXH0+W1dxiLNK+yoZ4XBnMOxlK5YiwDTVnfEuhf6WCjadgSTC96KKzbu7c3/ud1D6oW 7fFKXQF42blJwwl2fNrjAMlJV/6WFqUEmnncHwgDkVKglqw/skJrfkfvMdBQwkRCazivUcMijpV/s XaCnBKJ2Y7dFeo6NcDeTFfDHUB2M4p9T7R+OGktj4h4BYv4aXg8DXCexBVZSFIvFNta7r7npnkZp8 CgpImwUA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gYm0V-0003FG-Se; Mon, 17 Dec 2018 06:03:59 +0000 Received: from mout.gmx.net ([212.227.17.22]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gYm0R-00030W-R6 for linux-arm-kernel@lists.infradead.org; Mon, 17 Dec 2018 06:03:57 +0000 Received: from corona.crabdance.com ([173.228.106.209]) by mail.gmx.com (mrgmx103 [212.227.17.168]) with ESMTPSA (Nemesis) id 0MUHbK-1gyes32odu-00R3oy; Mon, 17 Dec 2018 07:03:34 +0100 Received: by corona.crabdance.com (Postfix, from userid 1001) id 9C5116E85602; Sun, 16 Dec 2018 22:03:25 -0800 (PST) From: Stefan Schaeckeler To: Rob Herring , Mark Rutland , Joel Stanley , Andrew Jeffery , Borislav Petkov , Mauro Carvalho Chehab , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-edac@vger.kernel.org Subject: [PATCH 2/2] dt-bindings: edac: Aspeed AST2500 Date: Sun, 16 Dec 2018 22:01:57 -0800 Message-Id: <1545026517-64069-3-git-send-email-schaecsn@gmx.net> X-Mailer: git-send-email 2.4.5 In-Reply-To: <1545026517-64069-1-git-send-email-schaecsn@gmx.net> References: <1545026517-64069-1-git-send-email-schaecsn@gmx.net> X-Provags-ID: V03:K1:MyWwx3gGskanIwe0jDsnK8d7E2zY9k8gWtJXmZkccmuO4erj1bH ymZXIVv4zZXpdrndTR4X72/n37JJ7qxeGnMdaZG4/fVSami207jaxTziuxlinSR8sDrUcF+ qKRYixdG0GW3xr/0FGpi6FP2BYOHcxwtaDMW6wQfyTxWkZ+cpE8bNLAufo1ijQLUwRizkoq srDURXm9mVvzm8OBLovwA== X-UI-Out-Filterresults: notjunk:1;V03:K0:mbv8/CNPiQ4=:2oOK6ayD7ROsSVujygy+HQ 6F30PoDWGXHg97XU6G0IiIlb11FWywQLBMm6Zf5fCydDRb/bN/7AwxDU5gIeSlvKFQNHp9w5Z rmjsksZ4fURMxYA2OsKAKG3vTulI01MUVPYiZIVKxrGKULhAI91F6bOaM9OFIZa9GbFRzvPzB rcoFH9fazKYB/AAdy6WRh0umLYti8ruvmq2wrRQ8Rp53Q5MiIcF/e8HxLbme1ftrFaUoge69i DM70+TmOG2dkrMlhu1voDtQtkuQ5nRRPJ4M1wJ2JEcavk8R/cervefy/u4arZBKHEyB86dtSb JwzUWnBSHqrRPWlK20qKQnZ1FBSIcz67aRXNFOKRPTWeva7M80DhkN1mlHuEuj6RudB922/ez IHTu/YEO2psNtLz1NZSWXuHM4TC5KsZnTNqVEUJ/yOnR++JpDMAOmkV8+kO6jklN6nru0dpAB xVh9dPPMdn8smoJPobSHGcRtBzlYVN9gAS9KqWUu09L5SMpVnHIJFFD/cEppEADq4xcppQkxu Rt7No3xclgzmKjhpDDXOGw9LIr0/QPokHSU92U5EEr+tb6fA5MLuecx7io4NB85NOufJ35mNl fGaOVPmpW3ATBeJOSqbiAjQJ9zMik4urt9zMRCPwHept1x4x5QhMaaCpoO1o266CxitV+pBO3 vzDMBKcL1YIq+l8eu8U+twqpWHa2enXRb/cCwa6DZEhw+PdVMXwVOpEWD98ICeMe3iHCsnzlP VlT0Dx7GVeYX08nSQ0A00IuRQF+ifq9UQVPnbgPxqP9Q6pC7XUdu2ULY35vfwacMjEaNgKKGg O+GYfD4A1+Lct4AMxdNNr5GjT3PdqO4RwuNmPu0EKv0LBE+ZBDem3R/oN8O3gx7DY1u1mD4Cl DbqIhhvoRm5UaoQvilgfVnhjDRxIxNKS4fpDv1ag4= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181216_220356_238534_8EE80E3E X-CRM114-Status: GOOD ( 12.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan M Schaeckeler MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Stefan M Schaeckeler Add support for the Aspeed AST2500 SoC EDAC driver. Signed-off-by: Stefan M Schaeckeler --- .../bindings/edac/aspeed-sdram-edac.txt | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt new file mode 100644 index 000000000000..57ba852883c7 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt @@ -0,0 +1,34 @@ +Aspeed AST2500 SoC EDAC device driver + +The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error +correction check). + +The memory controller supports SECDED (single bit error correction, double bit +error detection) and single bit error auto scrubbing by reserving 8 bits for +every 64 bit word (effectively reducing available memory to 8/9). + +First, ECC must be configured in u-boot. Then, this driver will expose error +counters via the edac kernel framework. + +A note on memory organization in ECC mode: every 512 bytes are followed by 64 +bytes of ECC codes. The address remapping is done in hardware and is fully +transparent to firmware and software. Because of this, ECC mode must be +configured in u-boot as part of the memory initialization as one can not switch +from one mode to another when executing in memory. + + + +Required properties: +- compatible: should be "aspeed,ast2500-sdram-edac" +- reg: sdram controller register set should be <0x1e6e0000 0x174> +- interrupts: should be AVIC interrupt #0 + + +Example: + + edac: sdram@1e6e0000 { + compatible = "aspeed,ast2500-sdram-edac"; + reg = <0x1e6e0000 0x174>; + interrupts = <0>; + status = "okay"; + };