From patchwork Thu Nov 4 14:45:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12603261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AD9EC433EF for ; Thu, 4 Nov 2021 14:45:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B544C611C4 for ; Thu, 4 Nov 2021 14:45:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B544C611C4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 025676E3B2; Thu, 4 Nov 2021 14:45:30 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8D2D06E3B2 for ; Thu, 4 Nov 2021 14:45:29 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10157"; a="230433954" X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="230433954" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2021 07:45:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="497973356" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga007.fm.intel.com with SMTP; 04 Nov 2021 07:45:24 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 04 Nov 2021 16:45:23 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Nov 2021 16:45:04 +0200 Message-Id: <20211104144520.22605-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com> References: <20211104144520.22605-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 01/17] drm/i915/fbc: Exract snb_fbc_program_fence() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä We have two identical copies of the snb+ system agent CPU fence programming code. Extract into a helper. Also there's no real point in insisting that we program 0 into DPFC_CPU_FENCE_OFFSET when the fence is disabled. So just always stick the computed Y offset there whether or not the fence is actually used or not. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 39 ++++++++++++------------ 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 834eb4cc7c10..6bd952a37901 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -307,6 +307,18 @@ static void intel_fbc_recompress(struct drm_i915_private *dev_priv) i8xx_fbc_recompress(dev_priv); } +static void snb_fbc_program_fence(struct drm_i915_private *i915) +{ + const struct intel_fbc_reg_params *params = &i915->fbc.params; + u32 ctl = 0; + + if (params->fence_id >= 0) + ctl = SNB_CPU_FENCE_ENABLE | params->fence_id; + + intel_de_write(i915, SNB_DPFC_CTL_SA, ctl); + intel_de_write(i915, DPFC_CPU_FENCE_OFFSET, params->fence_y_offset); +} + static void ilk_fbc_activate(struct drm_i915_private *dev_priv) { struct intel_fbc_reg_params *params = &dev_priv->fbc.params; @@ -320,19 +332,11 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv) dpfc_ctl |= DPFC_CTL_FENCE_EN; if (IS_IRONLAKE(dev_priv)) dpfc_ctl |= params->fence_id; - if (IS_SANDYBRIDGE(dev_priv)) { - intel_de_write(dev_priv, SNB_DPFC_CTL_SA, - SNB_CPU_FENCE_ENABLE | params->fence_id); - intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, - params->fence_y_offset); - } - } else { - if (IS_SANDYBRIDGE(dev_priv)) { - intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0); - intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0); - } } + if (IS_SANDYBRIDGE(dev_priv)) + snb_fbc_program_fence(dev_priv); + intel_de_write(dev_priv, ILK_DPFC_FENCE_YOFF, params->fence_y_offset); /* enable it... */ @@ -389,20 +393,15 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) dpfc_ctl |= g4x_dpfc_ctl_limit(dev_priv); - if (params->fence_id >= 0) { + if (params->fence_id >= 0) dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; - intel_de_write(dev_priv, SNB_DPFC_CTL_SA, - SNB_CPU_FENCE_ENABLE | params->fence_id); - intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, - params->fence_y_offset); - } else if (dev_priv->ggtt.num_fences) { - intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0); - intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0); - } if (dev_priv->fbc.false_color) dpfc_ctl |= FBC_CTL_FALSE_COLOR; + if (dev_priv->ggtt.num_fences) + snb_fbc_program_fence(dev_priv); + intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); } From patchwork Thu Nov 4 14:45:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12603263 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80A8FC433FE for ; Thu, 4 Nov 2021 14:45:32 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 26D67611C4 for ; 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04 Nov 2021 07:45:27 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 04 Nov 2021 16:45:26 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Nov 2021 16:45:05 +0200 Message-Id: <20211104144520.22605-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com> References: <20211104144520.22605-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 02/17] drm/i915/fbc: Extract {skl, glk}_fbc_program_cfb_stride() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Declutter gen7_fbc_activate() by sucking the override stride programming stuff into helpers. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 53 +++++++++++++++--------- 1 file changed, 33 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 6bd952a37901..c95a32f1985a 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -360,32 +360,45 @@ static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv) return intel_de_read(dev_priv, ILK_DPFC_CONTROL) & DPFC_CTL_EN; } +static void glk_fbc_program_cfb_stride(struct drm_i915_private *i915) +{ + struct intel_fbc *fbc = &i915->fbc; + const struct intel_fbc_reg_params *params = &fbc->params; + u32 val = 0; + + if (params->override_cfb_stride) + val |= FBC_STRIDE_OVERRIDE | + FBC_STRIDE(params->override_cfb_stride / fbc->limit); + + intel_de_write(i915, GLK_FBC_STRIDE, val); +} + +static void skl_fbc_program_cfb_stride(struct drm_i915_private *i915) +{ + struct intel_fbc *fbc = &i915->fbc; + const struct intel_fbc_reg_params *params = &fbc->params; + u32 val = 0; + + /* Display WA #0529: skl, kbl, bxt. */ + if (params->override_cfb_stride) + val |= CHICKEN_FBC_STRIDE_OVERRIDE | + CHICKEN_FBC_STRIDE(params->override_cfb_stride / fbc->limit); + + intel_de_rmw(i915, CHICKEN_MISC_4, + CHICKEN_FBC_STRIDE_OVERRIDE | + CHICKEN_FBC_STRIDE_MASK, val); +} + static void gen7_fbc_activate(struct drm_i915_private *dev_priv) { struct intel_fbc *fbc = &dev_priv->fbc; const struct intel_fbc_reg_params *params = &fbc->params; u32 dpfc_ctl; - if (DISPLAY_VER(dev_priv) >= 10) { - u32 val = 0; - - if (params->override_cfb_stride) - val |= FBC_STRIDE_OVERRIDE | - FBC_STRIDE(params->override_cfb_stride / fbc->limit); - - intel_de_write(dev_priv, GLK_FBC_STRIDE, val); - } else if (DISPLAY_VER(dev_priv) == 9) { - u32 val = 0; - - /* Display WA #0529: skl, kbl, bxt. */ - if (params->override_cfb_stride) - val |= CHICKEN_FBC_STRIDE_OVERRIDE | - CHICKEN_FBC_STRIDE(params->override_cfb_stride / fbc->limit); - - intel_de_rmw(dev_priv, CHICKEN_MISC_4, - CHICKEN_FBC_STRIDE_OVERRIDE | - CHICKEN_FBC_STRIDE_MASK, val); - } + if (DISPLAY_VER(dev_priv) >= 10) + glk_fbc_program_cfb_stride(dev_priv); + else if (DISPLAY_VER(dev_priv) == 9) + skl_fbc_program_cfb_stride(dev_priv); dpfc_ctl = 0; if (IS_IVYBRIDGE(dev_priv)) From patchwork Thu Nov 4 14:45:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12603267 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69681C433FE for ; Thu, 4 Nov 2021 14:45:37 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 35F9C611EE for ; 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04 Nov 2021 07:45:30 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 04 Nov 2021 16:45:29 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Nov 2021 16:45:06 +0200 Message-Id: <20211104144520.22605-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com> References: <20211104144520.22605-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 03/17] drm/i915/fbc: Just use params->fence_y_offset always X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä No need to tiptoe around programming DPFC_FENCE_YOFF with params->fence_y_offset vs. 0. If the fence is not enabled it doesn't even matter what we program here. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index c95a32f1985a..8f51af2b4ebc 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -235,13 +235,11 @@ static void g4x_fbc_activate(struct drm_i915_private *dev_priv) dpfc_ctl |= g4x_dpfc_ctl_limit(dev_priv); - if (params->fence_id >= 0) { + if (params->fence_id >= 0) dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fence_id; - intel_de_write(dev_priv, DPFC_FENCE_YOFF, - params->fence_y_offset); - } else { - intel_de_write(dev_priv, DPFC_FENCE_YOFF, 0); - } + + intel_de_write(dev_priv, DPFC_FENCE_YOFF, + params->fence_y_offset); /* enable it... */ intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); From patchwork Thu Nov 4 14:45:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12603269 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF944C433F5 for ; Thu, 4 Nov 2021 14:45:38 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8BEDB611EE for ; Thu, 4 Nov 2021 14:45:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 8BEDB611EE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 93B066E439; Thu, 4 Nov 2021 14:45:37 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id C475D6E432 for ; Thu, 4 Nov 2021 14:45:35 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10157"; a="212463175" X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="212463175" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2021 07:45:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="489982263" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga007.jf.intel.com with SMTP; 04 Nov 2021 07:45:33 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 04 Nov 2021 16:45:32 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Nov 2021 16:45:07 +0200 Message-Id: <20211104144520.22605-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com> References: <20211104144520.22605-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 04/17] drm/i915/fbc: Introduce intel_fbc_is_compressing() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Move the direct FBC status register reads from the debugfs code behind an abstract api. Signed-off-by: Ville Syrjälä --- .../drm/i915/display/intel_display_debugfs.c | 23 +++--------- drivers/gpu/drm/i915/display/intel_fbc.c | 36 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_fbc.h | 1 + 3 files changed, 41 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index d7d6dde518a3..19bc148e168c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -52,27 +52,12 @@ static int i915_fbc_status(struct seq_file *m, void *unused) wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); mutex_lock(&fbc->lock); - if (intel_fbc_is_active(dev_priv)) + if (intel_fbc_is_active(dev_priv)) { seq_puts(m, "FBC enabled\n"); - else + seq_printf(m, "Compressing: %s\n", + yesno(intel_fbc_is_compressing(dev_priv))); + } else { seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason); - - if (intel_fbc_is_active(dev_priv)) { - u32 mask; - - if (DISPLAY_VER(dev_priv) >= 8) - mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK; - else if (DISPLAY_VER(dev_priv) >= 7) - mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; - else if (DISPLAY_VER(dev_priv) >= 5) - mask = intel_de_read(dev_priv, ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK; - else if (IS_G4X(dev_priv)) - mask = intel_de_read(dev_priv, DPFC_STATUS) & DPFC_COMP_SEG_MASK; - else - mask = intel_de_read(dev_priv, FBC_STATUS) & - (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED); - - seq_printf(m, "Compressing: %s\n", yesno(mask)); } mutex_unlock(&fbc->lock); diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 8f51af2b4ebc..4d7b156e46db 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -211,6 +211,12 @@ static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv) return intel_de_read(dev_priv, FBC_CONTROL) & FBC_CTL_EN; } +static bool i8xx_fbc_is_compressing(struct drm_i915_private *i915) +{ + return intel_de_read(i915, FBC_STATUS) & + (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED); +} + static u32 g4x_dpfc_ctl_limit(struct drm_i915_private *i915) { switch (i915->fbc.limit) { @@ -262,6 +268,11 @@ static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv) return intel_de_read(dev_priv, DPFC_CONTROL) & DPFC_CTL_EN; } +static bool g4x_fbc_is_compressing(struct drm_i915_private *i915) +{ + return intel_de_read(i915, DPFC_STATUS) & DPFC_COMP_SEG_MASK; +} + static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv) { struct intel_fbc_reg_params *params = &dev_priv->fbc.params; @@ -358,6 +369,11 @@ static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv) return intel_de_read(dev_priv, ILK_DPFC_CONTROL) & DPFC_CTL_EN; } +static bool ilk_fbc_is_compressing(struct drm_i915_private *i915) +{ + return intel_de_read(i915, ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK; +} + static void glk_fbc_program_cfb_stride(struct drm_i915_private *i915) { struct intel_fbc *fbc = &i915->fbc; @@ -416,6 +432,14 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); } +static bool gen7_fbc_is_compressing(struct drm_i915_private *i915) +{ + if (DISPLAY_VER(i915) >= 8) + return intel_de_read(i915, IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK; + else + return intel_de_read(i915, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; +} + static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv) { if (DISPLAY_VER(dev_priv) >= 5) @@ -461,6 +485,18 @@ static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv) i8xx_fbc_deactivate(dev_priv); } +bool intel_fbc_is_compressing(struct drm_i915_private *i915) +{ + if (DISPLAY_VER(i915) >= 7) + return gen7_fbc_is_compressing(i915); + else if (DISPLAY_VER(i915) >= 5) + return ilk_fbc_is_compressing(i915); + else if (IS_G4X(i915)) + return g4x_fbc_is_compressing(i915); + else + return i8xx_fbc_is_compressing(i915); +} + /** * intel_fbc_is_active - Is FBC active? * @dev_priv: i915 device instance diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h index b97d908738e6..b2c9e441edbd 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.h +++ b/drivers/gpu/drm/i915/display/intel_fbc.h @@ -19,6 +19,7 @@ struct intel_plane_state; void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, struct intel_atomic_state *state); bool intel_fbc_is_active(struct drm_i915_private *dev_priv); +bool intel_fbc_is_compressing(struct drm_i915_private *dev_priv); bool intel_fbc_pre_update(struct intel_atomic_state *state, struct intel_crtc *crtc); void intel_fbc_post_update(struct intel_atomic_state *state, From patchwork Thu Nov 4 14:45:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12603271 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FFE6C433EF for ; Thu, 4 Nov 2021 14:45:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2745B611EF for ; Thu, 4 Nov 2021 14:45:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2745B611EF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7579E6E49C; Thu, 4 Nov 2021 14:45:40 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4FB7C6E455 for ; Thu, 4 Nov 2021 14:45:39 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10157"; a="212463184" X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="212463184" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2021 07:45:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="450222732" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga006.jf.intel.com with SMTP; 04 Nov 2021 07:45:36 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 04 Nov 2021 16:45:35 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Nov 2021 16:45:08 +0200 Message-Id: <20211104144520.22605-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com> References: <20211104144520.22605-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 05/17] drm/i915/fbc: Extract helpers to compute FBC control register values X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Declutter the *_fbc_activate() functions by pulling all the control register value computations into helpers. I left the enable bit in *_fbc_activate() in the hopes of maybe using the helpers in the *_fbc_deactivate() paths as well instead of the current rmw approach. That won't be possible at least quite yet since we clobber the fbc->params before deactivating FBC so we could end up changing some of the values live, which given FBC's lack of/poor double buffering would likely not go so well. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 162 +++++++++++++---------- 1 file changed, 94 insertions(+), 68 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 4d7b156e46db..fbb96f6aaacd 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -142,6 +142,48 @@ static unsigned int intel_fbc_cfb_size(struct drm_i915_private *dev_priv, return lines * intel_fbc_cfb_stride(dev_priv, cache); } +static u32 i8xx_fbc_ctl(struct drm_i915_private *i915) +{ + struct intel_fbc *fbc = &i915->fbc; + const struct intel_fbc_reg_params *params = &fbc->params; + unsigned int cfb_stride; + u32 fbc_ctl; + + cfb_stride = params->cfb_stride / fbc->limit; + + /* FBC_CTL wants 32B or 64B units */ + if (DISPLAY_VER(i915) == 2) + cfb_stride = (cfb_stride / 32) - 1; + else + cfb_stride = (cfb_stride / 64) - 1; + + fbc_ctl = FBC_CTL_PERIODIC | + FBC_CTL_INTERVAL(params->interval) | + FBC_CTL_STRIDE(cfb_stride); + + if (IS_I945GM(i915)) + fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ + + if (params->fence_id >= 0) + fbc_ctl |= FBC_CTL_FENCENO(params->fence_id); + + return fbc_ctl; +} + +static u32 i965_fbc_ctl2(struct drm_i915_private *i915) +{ + const struct intel_fbc_reg_params *params = &i915->fbc.params; + u32 fbc_ctl2; + + fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | + FBC_CTL_PLANE(params->crtc.i9xx_plane); + + if (params->fence_id >= 0) + fbc_ctl2 |= FBC_CTL_CPU_FENCE; + + return fbc_ctl2; +} + static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv) { u32 fbc_ctl; @@ -166,44 +208,21 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) { struct intel_fbc *fbc = &dev_priv->fbc; const struct intel_fbc_reg_params *params = &fbc->params; - int cfb_pitch; int i; - u32 fbc_ctl; - - cfb_pitch = params->cfb_stride / fbc->limit; - - /* FBC_CTL wants 32B or 64B units */ - if (DISPLAY_VER(dev_priv) == 2) - cfb_pitch = (cfb_pitch / 32) - 1; - else - cfb_pitch = (cfb_pitch / 64) - 1; /* Clear old tags */ for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) intel_de_write(dev_priv, FBC_TAG(i), 0); if (DISPLAY_VER(dev_priv) == 4) { - u32 fbc_ctl2; - - /* Set it up... */ - fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM; - fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.i9xx_plane); - if (params->fence_id >= 0) - fbc_ctl2 |= FBC_CTL_CPU_FENCE; - intel_de_write(dev_priv, FBC_CONTROL2, fbc_ctl2); + intel_de_write(dev_priv, FBC_CONTROL2, + i965_fbc_ctl2(dev_priv)); intel_de_write(dev_priv, FBC_FENCE_OFF, params->fence_y_offset); } - /* enable it... */ - fbc_ctl = FBC_CTL_INTERVAL(params->interval); - fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; - if (IS_I945GM(dev_priv)) - fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ - fbc_ctl |= FBC_CTL_STRIDE(cfb_pitch & 0xff); - if (params->fence_id >= 0) - fbc_ctl |= FBC_CTL_FENCENO(params->fence_id); - intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl); + intel_de_write(dev_priv, FBC_CONTROL, + FBC_CTL_EN | i8xx_fbc_ctl(dev_priv)); } static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv) @@ -232,23 +251,36 @@ static u32 g4x_dpfc_ctl_limit(struct drm_i915_private *i915) } } +static u32 g4x_dpfc_ctl(struct drm_i915_private *i915) +{ + const struct intel_fbc_reg_params *params = &i915->fbc.params; + u32 dpfc_ctl; + + dpfc_ctl = g4x_dpfc_ctl_limit(i915) | + DPFC_CTL_PLANE(params->crtc.i9xx_plane); + + if (IS_G4X(i915)) + dpfc_ctl |= DPFC_SR_EN; + + if (params->fence_id >= 0) { + dpfc_ctl |= DPFC_CTL_FENCE_EN; + + if (DISPLAY_VER(i915) < 6) + dpfc_ctl |= params->fence_id; + } + + return dpfc_ctl; +} + static void g4x_fbc_activate(struct drm_i915_private *dev_priv) { - struct intel_fbc_reg_params *params = &dev_priv->fbc.params; - u32 dpfc_ctl; - - dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN; - - dpfc_ctl |= g4x_dpfc_ctl_limit(dev_priv); - - if (params->fence_id >= 0) - dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fence_id; + const struct intel_fbc_reg_params *params = &dev_priv->fbc.params; intel_de_write(dev_priv, DPFC_FENCE_YOFF, params->fence_y_offset); - /* enable it... */ - intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); + intel_de_write(dev_priv, DPFC_CONTROL, + DPFC_CTL_EN | g4x_dpfc_ctl(dev_priv)); } static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv) @@ -331,25 +363,15 @@ static void snb_fbc_program_fence(struct drm_i915_private *i915) static void ilk_fbc_activate(struct drm_i915_private *dev_priv) { struct intel_fbc_reg_params *params = &dev_priv->fbc.params; - u32 dpfc_ctl; - - dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane); - - dpfc_ctl |= g4x_dpfc_ctl_limit(dev_priv); - - if (params->fence_id >= 0) { - dpfc_ctl |= DPFC_CTL_FENCE_EN; - if (IS_IRONLAKE(dev_priv)) - dpfc_ctl |= params->fence_id; - } if (IS_SANDYBRIDGE(dev_priv)) snb_fbc_program_fence(dev_priv); intel_de_write(dev_priv, ILK_DPFC_FENCE_YOFF, params->fence_y_offset); - /* enable it... */ - intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); + + intel_de_write(dev_priv, ILK_DPFC_CONTROL, + DPFC_CTL_EN | g4x_dpfc_ctl(dev_priv)); } static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv) @@ -403,33 +425,37 @@ static void skl_fbc_program_cfb_stride(struct drm_i915_private *i915) CHICKEN_FBC_STRIDE_MASK, val); } +static u32 gen7_dpfc_ctl(struct drm_i915_private *i915) +{ + const struct intel_fbc_reg_params *params = &i915->fbc.params; + u32 dpfc_ctl; + + dpfc_ctl = g4x_dpfc_ctl_limit(i915); + + if (IS_IVYBRIDGE(i915)) + dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane); + + if (params->fence_id >= 0) + dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; + + if (i915->fbc.false_color) + dpfc_ctl |= FBC_CTL_FALSE_COLOR; + + return dpfc_ctl; +} + static void gen7_fbc_activate(struct drm_i915_private *dev_priv) { - struct intel_fbc *fbc = &dev_priv->fbc; - const struct intel_fbc_reg_params *params = &fbc->params; - u32 dpfc_ctl; - if (DISPLAY_VER(dev_priv) >= 10) glk_fbc_program_cfb_stride(dev_priv); else if (DISPLAY_VER(dev_priv) == 9) skl_fbc_program_cfb_stride(dev_priv); - dpfc_ctl = 0; - if (IS_IVYBRIDGE(dev_priv)) - dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane); - - dpfc_ctl |= g4x_dpfc_ctl_limit(dev_priv); - - if (params->fence_id >= 0) - dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; - - if (dev_priv->fbc.false_color) - dpfc_ctl |= FBC_CTL_FALSE_COLOR; - if (dev_priv->ggtt.num_fences) snb_fbc_program_fence(dev_priv); - intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); + intel_de_write(dev_priv, ILK_DPFC_CONTROL, + DPFC_CTL_EN | gen7_dpfc_ctl(dev_priv)); } static bool gen7_fbc_is_compressing(struct drm_i915_private *i915) From patchwork Thu Nov 4 14:45:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12603273 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04D0EC433F5 for ; Thu, 4 Nov 2021 14:45:44 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C7581611C4 for ; Thu, 4 Nov 2021 14:45:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C7581611C4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3B4D96E4AF; Thu, 4 Nov 2021 14:45:43 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 662316E4AF for ; Thu, 4 Nov 2021 14:45:42 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10157"; a="218618369" X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="218618369" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2021 07:45:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="532287757" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga001.jf.intel.com with SMTP; 04 Nov 2021 07:45:39 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 04 Nov 2021 16:45:39 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Nov 2021 16:45:09 +0200 Message-Id: <20211104144520.22605-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com> References: <20211104144520.22605-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 06/17] drm/i915/fbc: Introduce intel_fbc_funcs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Replace the "if-ladders everywhere" approach with vfuncs. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 80 +++++++++++++++--------- drivers/gpu/drm/i915/i915_drv.h | 3 + 2 files changed, 55 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index fbb96f6aaacd..a2e09b6d21c7 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -48,6 +48,13 @@ #include "intel_fbc.h" #include "intel_frontbuffer.h" +struct intel_fbc_funcs { + void (*activate)(struct drm_i915_private *i915); + void (*deactivate)(struct drm_i915_private *i915); + bool (*is_active)(struct drm_i915_private *i915); + bool (*is_compressing)(struct drm_i915_private *i915); +}; + /* * For SKL+, the plane source size used by the hardware is based on the value we * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value @@ -236,6 +243,13 @@ static bool i8xx_fbc_is_compressing(struct drm_i915_private *i915) (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED); } +static const struct intel_fbc_funcs i8xx_fbc_funcs = { + .activate = i8xx_fbc_activate, + .deactivate = i8xx_fbc_deactivate, + .is_active = i8xx_fbc_is_active, + .is_compressing = i8xx_fbc_is_compressing, +}; + static u32 g4x_dpfc_ctl_limit(struct drm_i915_private *i915) { switch (i915->fbc.limit) { @@ -305,6 +319,13 @@ static bool g4x_fbc_is_compressing(struct drm_i915_private *i915) return intel_de_read(i915, DPFC_STATUS) & DPFC_COMP_SEG_MASK; } +static const struct intel_fbc_funcs g4x_fbc_funcs = { + .activate = g4x_fbc_activate, + .deactivate = g4x_fbc_deactivate, + .is_active = g4x_fbc_is_active, + .is_compressing = g4x_fbc_is_compressing, +}; + static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv) { struct intel_fbc_reg_params *params = &dev_priv->fbc.params; @@ -396,6 +417,13 @@ static bool ilk_fbc_is_compressing(struct drm_i915_private *i915) return intel_de_read(i915, ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK; } +static const struct intel_fbc_funcs ilk_fbc_funcs = { + .activate = ilk_fbc_activate, + .deactivate = ilk_fbc_deactivate, + .is_active = ilk_fbc_is_active, + .is_compressing = ilk_fbc_is_compressing, +}; + static void glk_fbc_program_cfb_stride(struct drm_i915_private *i915) { struct intel_fbc *fbc = &i915->fbc; @@ -466,14 +494,18 @@ static bool gen7_fbc_is_compressing(struct drm_i915_private *i915) return intel_de_read(i915, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; } +static const struct intel_fbc_funcs gen7_fbc_funcs = { + .activate = gen7_fbc_activate, + .deactivate = ilk_fbc_deactivate, + .is_active = ilk_fbc_is_active, + .is_compressing = gen7_fbc_is_compressing, +}; + static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv) { - if (DISPLAY_VER(dev_priv) >= 5) - return ilk_fbc_is_active(dev_priv); - else if (IS_GM45(dev_priv)) - return g4x_fbc_is_active(dev_priv); - else - return i8xx_fbc_is_active(dev_priv); + struct intel_fbc *fbc = &dev_priv->fbc; + + return fbc->funcs->is_active(dev_priv); } static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv) @@ -485,14 +517,7 @@ static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv) fbc->active = true; fbc->activated = true; - if (DISPLAY_VER(dev_priv) >= 7) - gen7_fbc_activate(dev_priv); - else if (DISPLAY_VER(dev_priv) >= 5) - ilk_fbc_activate(dev_priv); - else if (IS_GM45(dev_priv)) - g4x_fbc_activate(dev_priv); - else - i8xx_fbc_activate(dev_priv); + fbc->funcs->activate(dev_priv); } static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv) @@ -503,24 +528,14 @@ static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv) fbc->active = false; - if (DISPLAY_VER(dev_priv) >= 5) - ilk_fbc_deactivate(dev_priv); - else if (IS_GM45(dev_priv)) - g4x_fbc_deactivate(dev_priv); - else - i8xx_fbc_deactivate(dev_priv); + fbc->funcs->deactivate(dev_priv); } bool intel_fbc_is_compressing(struct drm_i915_private *i915) { - if (DISPLAY_VER(i915) >= 7) - return gen7_fbc_is_compressing(i915); - else if (DISPLAY_VER(i915) >= 5) - return ilk_fbc_is_compressing(i915); - else if (IS_G4X(i915)) - return g4x_fbc_is_compressing(i915); - else - return i8xx_fbc_is_compressing(i915); + struct intel_fbc *fbc = &i915->fbc; + + return fbc->funcs->is_compressing(i915); } /** @@ -1650,6 +1665,15 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) return; } + if (DISPLAY_VER(dev_priv) >= 7) + fbc->funcs = &gen7_fbc_funcs; + else if (DISPLAY_VER(dev_priv) >= 5) + fbc->funcs = &ilk_fbc_funcs; + else if (IS_G4X(dev_priv)) + fbc->funcs = &g4x_fbc_funcs; + else + fbc->funcs = &i8xx_fbc_funcs; + /* We still don't have any sort of hardware state readout for FBC, so * deactivate it in case the BIOS activated it to make sure software * matches the hardware state. */ diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e967cd08f23e..e5d57c2a8506 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -409,10 +409,13 @@ struct drm_i915_display_funcs { void (*commit_modeset_enables)(struct intel_atomic_state *state); }; +struct intel_fbc_funcs; #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ struct intel_fbc { + const struct intel_fbc_funcs *funcs; + /* This is always the inner lock when overlapping with struct_mutex and * it's the outer lock when overlapping with stolen_lock. */ struct mutex lock; From patchwork Thu Nov 4 14:45:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12603275 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FE9EC433EF for ; Thu, 4 Nov 2021 14:45:47 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 18DD7611EE for ; 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04 Nov 2021 07:45:42 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 04 Nov 2021 16:45:42 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Nov 2021 16:45:10 +0200 Message-Id: <20211104144520.22605-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com> References: <20211104144520.22605-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 07/17] drm/i915/fbc: Introduce .nuke() vfunc X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Eliminate yet another if-ladder by adding .nuke() vfunc. We also rename all *_recompress() stuff to *_nuke() since that's the terminology the spec uses. Also "recompress" is a bit confusing by perhaps implying that this triggers an immediate recompression. Depending on the hardware that may definitely not be the case, and in general we don't specifically know when the hardware decides to compress. So all we do is "nuke" the current compressed framebuffer and leave it up to the hardware to recompress later if it so chooses. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 145 +++++++++++++---------- 1 file changed, 84 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index a2e09b6d21c7..be89404840d2 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -53,6 +53,7 @@ struct intel_fbc_funcs { void (*deactivate)(struct drm_i915_private *i915); bool (*is_active)(struct drm_i915_private *i915); bool (*is_compressing)(struct drm_i915_private *i915); + void (*nuke)(struct drm_i915_private *i915); }; /* @@ -243,11 +244,42 @@ static bool i8xx_fbc_is_compressing(struct drm_i915_private *i915) (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED); } +static void i8xx_fbc_nuke(struct drm_i915_private *dev_priv) +{ + struct intel_fbc_reg_params *params = &dev_priv->fbc.params; + enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane; + + spin_lock_irq(&dev_priv->uncore.lock); + intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), + intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane))); + spin_unlock_irq(&dev_priv->uncore.lock); +} + static const struct intel_fbc_funcs i8xx_fbc_funcs = { .activate = i8xx_fbc_activate, .deactivate = i8xx_fbc_deactivate, .is_active = i8xx_fbc_is_active, .is_compressing = i8xx_fbc_is_compressing, + .nuke = i8xx_fbc_nuke, +}; + +static void i965_fbc_nuke(struct drm_i915_private *dev_priv) +{ + struct intel_fbc_reg_params *params = &dev_priv->fbc.params; + enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane; + + spin_lock_irq(&dev_priv->uncore.lock); + intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), + intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane))); + spin_unlock_irq(&dev_priv->uncore.lock); +} + +static const struct intel_fbc_funcs i965_fbc_funcs = { + .activate = i8xx_fbc_activate, + .deactivate = i8xx_fbc_deactivate, + .is_active = i8xx_fbc_is_active, + .is_compressing = i8xx_fbc_is_compressing, + .nuke = i965_fbc_nuke, }; static u32 g4x_dpfc_ctl_limit(struct drm_i915_private *i915) @@ -324,70 +356,13 @@ static const struct intel_fbc_funcs g4x_fbc_funcs = { .deactivate = g4x_fbc_deactivate, .is_active = g4x_fbc_is_active, .is_compressing = g4x_fbc_is_compressing, + .nuke = i965_fbc_nuke, }; -static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv) -{ - struct intel_fbc_reg_params *params = &dev_priv->fbc.params; - enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane; - - spin_lock_irq(&dev_priv->uncore.lock); - intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), - intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane))); - spin_unlock_irq(&dev_priv->uncore.lock); -} - -static void i965_fbc_recompress(struct drm_i915_private *dev_priv) -{ - struct intel_fbc_reg_params *params = &dev_priv->fbc.params; - enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane; - - spin_lock_irq(&dev_priv->uncore.lock); - intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), - intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane))); - spin_unlock_irq(&dev_priv->uncore.lock); -} - -/* This function forces a CFB recompression through the nuke operation. */ -static void snb_fbc_recompress(struct drm_i915_private *dev_priv) -{ - intel_de_write(dev_priv, MSG_FBC_REND_STATE, FBC_REND_NUKE); - intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE); -} - -static void intel_fbc_recompress(struct drm_i915_private *dev_priv) -{ - struct intel_fbc *fbc = &dev_priv->fbc; - - trace_intel_fbc_nuke(fbc->crtc); - - if (DISPLAY_VER(dev_priv) >= 6) - snb_fbc_recompress(dev_priv); - else if (DISPLAY_VER(dev_priv) >= 4) - i965_fbc_recompress(dev_priv); - else - i8xx_fbc_recompress(dev_priv); -} - -static void snb_fbc_program_fence(struct drm_i915_private *i915) -{ - const struct intel_fbc_reg_params *params = &i915->fbc.params; - u32 ctl = 0; - - if (params->fence_id >= 0) - ctl = SNB_CPU_FENCE_ENABLE | params->fence_id; - - intel_de_write(i915, SNB_DPFC_CTL_SA, ctl); - intel_de_write(i915, DPFC_CPU_FENCE_OFFSET, params->fence_y_offset); -} - static void ilk_fbc_activate(struct drm_i915_private *dev_priv) { struct intel_fbc_reg_params *params = &dev_priv->fbc.params; - if (IS_SANDYBRIDGE(dev_priv)) - snb_fbc_program_fence(dev_priv); - intel_de_write(dev_priv, ILK_DPFC_FENCE_YOFF, params->fence_y_offset); @@ -422,6 +397,40 @@ static const struct intel_fbc_funcs ilk_fbc_funcs = { .deactivate = ilk_fbc_deactivate, .is_active = ilk_fbc_is_active, .is_compressing = ilk_fbc_is_compressing, + .nuke = i965_fbc_nuke, +}; + +static void snb_fbc_program_fence(struct drm_i915_private *i915) +{ + const struct intel_fbc_reg_params *params = &i915->fbc.params; + u32 ctl = 0; + + if (params->fence_id >= 0) + ctl = SNB_CPU_FENCE_ENABLE | params->fence_id; + + intel_de_write(i915, SNB_DPFC_CTL_SA, ctl); + intel_de_write(i915, DPFC_CPU_FENCE_OFFSET, params->fence_y_offset); +} + +static void snb_fbc_activate(struct drm_i915_private *dev_priv) +{ + snb_fbc_program_fence(dev_priv); + + ilk_fbc_activate(dev_priv); +} + +static void snb_fbc_nuke(struct drm_i915_private *dev_priv) +{ + intel_de_write(dev_priv, MSG_FBC_REND_STATE, FBC_REND_NUKE); + intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE); +} + +static const struct intel_fbc_funcs snb_fbc_funcs = { + .activate = snb_fbc_activate, + .deactivate = ilk_fbc_deactivate, + .is_active = ilk_fbc_is_active, + .is_compressing = ilk_fbc_is_compressing, + .nuke = snb_fbc_nuke, }; static void glk_fbc_program_cfb_stride(struct drm_i915_private *i915) @@ -499,6 +508,7 @@ static const struct intel_fbc_funcs gen7_fbc_funcs = { .deactivate = ilk_fbc_deactivate, .is_active = ilk_fbc_is_active, .is_compressing = gen7_fbc_is_compressing, + .nuke = snb_fbc_nuke, }; static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv) @@ -538,6 +548,15 @@ bool intel_fbc_is_compressing(struct drm_i915_private *i915) return fbc->funcs->is_compressing(i915); } +static void intel_fbc_nuke(struct drm_i915_private *i915) +{ + struct intel_fbc *fbc = &i915->fbc; + + trace_intel_fbc_nuke(fbc->crtc); + + fbc->funcs->nuke(i915); +} + /** * intel_fbc_is_active - Is FBC active? * @dev_priv: i915 device instance @@ -555,7 +574,7 @@ bool intel_fbc_is_active(struct drm_i915_private *dev_priv) static void intel_fbc_activate(struct drm_i915_private *dev_priv) { intel_fbc_hw_activate(dev_priv); - intel_fbc_recompress(dev_priv); + intel_fbc_nuke(dev_priv); } static void intel_fbc_deactivate(struct drm_i915_private *dev_priv, @@ -1318,7 +1337,7 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv, if (!fbc->busy_bits && fbc->crtc && (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) { if (fbc->active) - intel_fbc_recompress(dev_priv); + intel_fbc_nuke(dev_priv); else if (!fbc->flip_pending) __intel_fbc_post_update(fbc->crtc); } @@ -1667,10 +1686,14 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) if (DISPLAY_VER(dev_priv) >= 7) fbc->funcs = &gen7_fbc_funcs; - else if (DISPLAY_VER(dev_priv) >= 5) + else if (DISPLAY_VER(dev_priv) == 6) + fbc->funcs = &snb_fbc_funcs; + else if (DISPLAY_VER(dev_priv) == 5) fbc->funcs = &ilk_fbc_funcs; else if (IS_G4X(dev_priv)) fbc->funcs = &g4x_fbc_funcs; + else if (DISPLAY_VER(dev_priv) == 4) + fbc->funcs = &i965_fbc_funcs; else fbc->funcs = &i8xx_fbc_funcs; From patchwork Thu Nov 4 14:45:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12603277 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A897FC433F5 for ; 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d="scan'208";a="231663954" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2021 07:45:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="578609607" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by FMSMGA003.fm.intel.com with SMTP; 04 Nov 2021 07:45:45 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 04 Nov 2021 16:45:45 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Nov 2021 16:45:11 +0200 Message-Id: <20211104144520.22605-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com> References: <20211104144520.22605-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 08/17] drm/i915/fbc: s/gen7/ivb/ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä "gen7" in display code is not really sensible. We shall call these things "ivb". Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index be89404840d2..1df5a08d3457 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -462,7 +462,7 @@ static void skl_fbc_program_cfb_stride(struct drm_i915_private *i915) CHICKEN_FBC_STRIDE_MASK, val); } -static u32 gen7_dpfc_ctl(struct drm_i915_private *i915) +static u32 ivb_dpfc_ctl(struct drm_i915_private *i915) { const struct intel_fbc_reg_params *params = &i915->fbc.params; u32 dpfc_ctl; @@ -481,7 +481,7 @@ static u32 gen7_dpfc_ctl(struct drm_i915_private *i915) return dpfc_ctl; } -static void gen7_fbc_activate(struct drm_i915_private *dev_priv) +static void ivb_fbc_activate(struct drm_i915_private *dev_priv) { if (DISPLAY_VER(dev_priv) >= 10) glk_fbc_program_cfb_stride(dev_priv); @@ -492,10 +492,10 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) snb_fbc_program_fence(dev_priv); intel_de_write(dev_priv, ILK_DPFC_CONTROL, - DPFC_CTL_EN | gen7_dpfc_ctl(dev_priv)); + DPFC_CTL_EN | ivb_dpfc_ctl(dev_priv)); } -static bool gen7_fbc_is_compressing(struct drm_i915_private *i915) +static bool ivb_fbc_is_compressing(struct drm_i915_private *i915) { if (DISPLAY_VER(i915) >= 8) return intel_de_read(i915, IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK; @@ -503,11 +503,11 @@ static bool gen7_fbc_is_compressing(struct drm_i915_private *i915) return intel_de_read(i915, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; } -static const struct intel_fbc_funcs gen7_fbc_funcs = { - .activate = gen7_fbc_activate, +static const struct intel_fbc_funcs ivb_fbc_funcs = { + .activate = ivb_fbc_activate, .deactivate = ilk_fbc_deactivate, .is_active = ilk_fbc_is_active, - .is_compressing = gen7_fbc_is_compressing, + .is_compressing = ivb_fbc_is_compressing, .nuke = snb_fbc_nuke, }; @@ -1685,7 +1685,7 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) } if (DISPLAY_VER(dev_priv) >= 7) - fbc->funcs = &gen7_fbc_funcs; + fbc->funcs = &ivb_fbc_funcs; else if (DISPLAY_VER(dev_priv) == 6) fbc->funcs = &snb_fbc_funcs; else if (DISPLAY_VER(dev_priv) == 5) From patchwork Thu Nov 4 14:45:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12603279 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76EC1C433F5 for ; Thu, 4 Nov 2021 14:45:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 48B58611C4 for ; Thu, 4 Nov 2021 14:45:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 48B58611C4 Authentication-Results: mail.kernel.org; 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Thu, 04 Nov 2021 16:45:47 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Nov 2021 16:45:12 +0200 Message-Id: <20211104144520.22605-10-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com> References: <20211104144520.22605-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 09/17] drm/i915/fbc: Introduce .program_cfb() vfunc X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Eliminate the last if-ladder by pulling the CFB/LLB programming into a vfunc as well. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 56 ++++++++++++++++-------- 1 file changed, 37 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 1df5a08d3457..0cbd0e302320 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -54,6 +54,7 @@ struct intel_fbc_funcs { bool (*is_active)(struct drm_i915_private *i915); bool (*is_compressing)(struct drm_i915_private *i915); void (*nuke)(struct drm_i915_private *i915); + void (*program_cfb)(struct drm_i915_private *i915); }; /* @@ -255,12 +256,28 @@ static void i8xx_fbc_nuke(struct drm_i915_private *dev_priv) spin_unlock_irq(&dev_priv->uncore.lock); } +static void i8xx_fbc_program_cfb(struct drm_i915_private *i915) +{ + struct intel_fbc *fbc = &i915->fbc; + + GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start, + fbc->compressed_fb.start, U32_MAX)); + GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start, + fbc->compressed_llb.start, U32_MAX)); + + intel_de_write(i915, FBC_CFB_BASE, + i915->dsm.start + fbc->compressed_fb.start); + intel_de_write(i915, FBC_LL_BASE, + i915->dsm.start + fbc->compressed_llb.start); +} + static const struct intel_fbc_funcs i8xx_fbc_funcs = { .activate = i8xx_fbc_activate, .deactivate = i8xx_fbc_deactivate, .is_active = i8xx_fbc_is_active, .is_compressing = i8xx_fbc_is_compressing, .nuke = i8xx_fbc_nuke, + .program_cfb = i8xx_fbc_program_cfb, }; static void i965_fbc_nuke(struct drm_i915_private *dev_priv) @@ -280,6 +297,7 @@ static const struct intel_fbc_funcs i965_fbc_funcs = { .is_active = i8xx_fbc_is_active, .is_compressing = i8xx_fbc_is_compressing, .nuke = i965_fbc_nuke, + .program_cfb = i8xx_fbc_program_cfb, }; static u32 g4x_dpfc_ctl_limit(struct drm_i915_private *i915) @@ -351,12 +369,20 @@ static bool g4x_fbc_is_compressing(struct drm_i915_private *i915) return intel_de_read(i915, DPFC_STATUS) & DPFC_COMP_SEG_MASK; } +static void g4x_fbc_program_cfb(struct drm_i915_private *i915) +{ + struct intel_fbc *fbc = &i915->fbc; + + intel_de_write(i915, DPFC_CB_BASE, fbc->compressed_fb.start); +} + static const struct intel_fbc_funcs g4x_fbc_funcs = { .activate = g4x_fbc_activate, .deactivate = g4x_fbc_deactivate, .is_active = g4x_fbc_is_active, .is_compressing = g4x_fbc_is_compressing, .nuke = i965_fbc_nuke, + .program_cfb = g4x_fbc_program_cfb, }; static void ilk_fbc_activate(struct drm_i915_private *dev_priv) @@ -392,12 +418,20 @@ static bool ilk_fbc_is_compressing(struct drm_i915_private *i915) return intel_de_read(i915, ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK; } +static void ilk_fbc_program_cfb(struct drm_i915_private *i915) +{ + struct intel_fbc *fbc = &i915->fbc; + + intel_de_write(i915, ILK_DPFC_CB_BASE, fbc->compressed_fb.start); +} + static const struct intel_fbc_funcs ilk_fbc_funcs = { .activate = ilk_fbc_activate, .deactivate = ilk_fbc_deactivate, .is_active = ilk_fbc_is_active, .is_compressing = ilk_fbc_is_compressing, .nuke = i965_fbc_nuke, + .program_cfb = ilk_fbc_program_cfb, }; static void snb_fbc_program_fence(struct drm_i915_private *i915) @@ -431,6 +465,7 @@ static const struct intel_fbc_funcs snb_fbc_funcs = { .is_active = ilk_fbc_is_active, .is_compressing = ilk_fbc_is_compressing, .nuke = snb_fbc_nuke, + .program_cfb = ilk_fbc_program_cfb, }; static void glk_fbc_program_cfb_stride(struct drm_i915_private *i915) @@ -509,6 +544,7 @@ static const struct intel_fbc_funcs ivb_fbc_funcs = { .is_active = ilk_fbc_is_active, .is_compressing = ivb_fbc_is_compressing, .nuke = snb_fbc_nuke, + .program_cfb = ilk_fbc_program_cfb, }; static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv) @@ -704,25 +740,7 @@ static void intel_fbc_program_cfb(struct drm_i915_private *dev_priv) { struct intel_fbc *fbc = &dev_priv->fbc; - if (DISPLAY_VER(dev_priv) >= 5) { - intel_de_write(dev_priv, ILK_DPFC_CB_BASE, - fbc->compressed_fb.start); - } else if (IS_GM45(dev_priv)) { - intel_de_write(dev_priv, DPFC_CB_BASE, - fbc->compressed_fb.start); - } else { - GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start, - fbc->compressed_fb.start, - U32_MAX)); - GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start, - fbc->compressed_llb.start, - U32_MAX)); - - intel_de_write(dev_priv, FBC_CFB_BASE, - dev_priv->dsm.start + fbc->compressed_fb.start); - intel_de_write(dev_priv, FBC_LL_BASE, - dev_priv->dsm.start + fbc->compressed_llb.start); - } + fbc->funcs->program_cfb(dev_priv); } static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) From patchwork Thu Nov 4 14:45:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12603281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A88FDC433F5 for ; Thu, 4 Nov 2021 14:45:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7CD2F611EE for ; Thu, 4 Nov 2021 14:45:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 7CD2F611EE Authentication-Results: mail.kernel.org; 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Thu, 04 Nov 2021 16:45:50 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Nov 2021 16:45:13 +0200 Message-Id: <20211104144520.22605-11-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com> References: <20211104144520.22605-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 10/17] drm/i915/fbc: Introduce intel_fbc_set_false_color() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Pull the direct FBC register frobbing out from the debugfs code into the fbc code. Also add a vfunc for this so we don't need extra platforms checks. Signed-off-by: Ville Syrjälä --- .../drm/i915/display/intel_display_debugfs.c | 18 +------------ drivers/gpu/drm/i915/display/intel_fbc.c | 27 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_fbc.h | 2 ++ 3 files changed, 30 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 19bc148e168c..1a9210739727 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -70,9 +70,6 @@ static int i915_fbc_false_color_get(void *data, u64 *val) { struct drm_i915_private *dev_priv = data; - if (DISPLAY_VER(dev_priv) < 7 || !HAS_FBC(dev_priv)) - return -ENODEV; - *val = dev_priv->fbc.false_color; return 0; @@ -81,21 +78,8 @@ static int i915_fbc_false_color_get(void *data, u64 *val) static int i915_fbc_false_color_set(void *data, u64 val) { struct drm_i915_private *dev_priv = data; - u32 reg; - if (DISPLAY_VER(dev_priv) < 7 || !HAS_FBC(dev_priv)) - return -ENODEV; - - mutex_lock(&dev_priv->fbc.lock); - - reg = intel_de_read(dev_priv, ILK_DPFC_CONTROL); - dev_priv->fbc.false_color = val; - - intel_de_write(dev_priv, ILK_DPFC_CONTROL, - val ? (reg | FBC_CTL_FALSE_COLOR) : (reg & ~FBC_CTL_FALSE_COLOR)); - - mutex_unlock(&dev_priv->fbc.lock); - return 0; + return intel_fbc_set_false_color(dev_priv, val); } DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops, diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 0cbd0e302320..b13a776cb3dc 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -55,6 +55,7 @@ struct intel_fbc_funcs { bool (*is_compressing)(struct drm_i915_private *i915); void (*nuke)(struct drm_i915_private *i915); void (*program_cfb)(struct drm_i915_private *i915); + void (*set_false_color)(struct drm_i915_private *i915, bool enable); }; /* @@ -538,6 +539,13 @@ static bool ivb_fbc_is_compressing(struct drm_i915_private *i915) return intel_de_read(i915, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; } +static void ivb_fbc_set_false_color(struct drm_i915_private *i915, + bool enable) +{ + intel_de_rmw(i915, ILK_DPFC_CONTROL, + FBC_CTL_FALSE_COLOR, enable ? FBC_CTL_FALSE_COLOR : 0); +} + static const struct intel_fbc_funcs ivb_fbc_funcs = { .activate = ivb_fbc_activate, .deactivate = ilk_fbc_deactivate, @@ -545,6 +553,7 @@ static const struct intel_fbc_funcs ivb_fbc_funcs = { .is_compressing = ivb_fbc_is_compressing, .nuke = snb_fbc_nuke, .program_cfb = ilk_fbc_program_cfb, + .set_false_color = ivb_fbc_set_false_color, }; static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv) @@ -593,6 +602,24 @@ static void intel_fbc_nuke(struct drm_i915_private *i915) fbc->funcs->nuke(i915); } +int intel_fbc_set_false_color(struct drm_i915_private *i915, bool enable) +{ + struct intel_fbc *fbc = &i915->fbc; + + if (!fbc->funcs || !fbc->funcs->set_false_color) + return -ENODEV; + + mutex_lock(&fbc->lock); + + fbc->false_color = enable; + + fbc->funcs->set_false_color(i915, enable); + + mutex_unlock(&fbc->lock); + + return 0; +} + /** * intel_fbc_is_active - Is FBC active? * @dev_priv: i915 device instance diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h index b2c9e441edbd..4d1f2a76ccb4 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.h +++ b/drivers/gpu/drm/i915/display/intel_fbc.h @@ -37,5 +37,7 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv, void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv); void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv); int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv); +int intel_fbc_set_false_color(struct drm_i915_private *i915, + bool enable); #endif /* __INTEL_FBC_H__ */ From patchwork Thu Nov 4 14:45:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12603283 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4148AC433EF for ; Thu, 4 Nov 2021 14:45:59 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 049BD611C4 for ; Thu, 4 Nov 2021 14:45:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 049BD611C4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5DC138979F; Thu, 4 Nov 2021 14:45:58 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id B025589491 for ; Thu, 4 Nov 2021 14:45:56 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10157"; a="295162067" X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="295162067" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2021 07:45:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="497973483" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga007.fm.intel.com with SMTP; 04 Nov 2021 07:45:54 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 04 Nov 2021 16:45:53 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Nov 2021 16:45:14 +0200 Message-Id: <20211104144520.22605-12-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com> References: <20211104144520.22605-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 11/17] drm/i915/fbc: Nuke BDW_FBC_COMP_SEG_MASK X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Just use a same mask for ivb/hsw as for bdw+. The extra bit in the bdw mask is mbz on ivb/hsw anyway so this is just pointless complexity. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 5 +---- drivers/gpu/drm/i915/i915_reg.h | 3 +-- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index b13a776cb3dc..1193e86690e5 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -533,10 +533,7 @@ static void ivb_fbc_activate(struct drm_i915_private *dev_priv) static bool ivb_fbc_is_compressing(struct drm_i915_private *i915) { - if (DISPLAY_VER(i915) >= 8) - return intel_de_read(i915, IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK; - else - return intel_de_read(i915, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; + return intel_de_read(i915, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; } static void ivb_fbc_set_false_color(struct drm_i915_private *i915, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b456920555b7..1e99fe8dc253 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3382,8 +3382,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define ILK_DPFC_STATUS _MMIO(0x43210) #define ILK_DPFC_COMP_SEG_MASK 0x7ff #define IVB_FBC_STATUS2 _MMIO(0x43214) -#define IVB_FBC_COMP_SEG_MASK 0x7ff -#define BDW_FBC_COMP_SEG_MASK 0xfff +#define IVB_FBC_COMP_SEG_MASK 0xfff #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218) #define ILK_DPFC_CHICKEN _MMIO(0x43224) #define ILK_DPFC_DISABLE_DUMMY0 (1 << 8) From patchwork Thu Nov 4 14:45:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12603285 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81D8AC433EF for ; Thu, 4 Nov 2021 14:46:03 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4E3B7611C4 for ; Thu, 4 Nov 2021 14:46:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4E3B7611C4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 79C3D89BCD; Thu, 4 Nov 2021 14:46:02 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 22B7289B45 for ; Thu, 4 Nov 2021 14:46:00 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10157"; a="231564002" X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="231564002" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2021 07:45:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="639365023" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga001.fm.intel.com with SMTP; 04 Nov 2021 07:45:56 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 04 Nov 2021 16:45:56 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Nov 2021 16:45:15 +0200 Message-Id: <20211104144520.22605-13-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com> References: <20211104144520.22605-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 12/17] drm/i915/fbc: Clean up all register defines X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The FBC register defines are a mess: - namespace changes between DPFC_, FBC_, and some platform specific prefix at a whim - ilk+ reuses most g4x bits but still has some separate bit defines elsewhere - it's not clear from the defines that the bit defines are shared So let's clean it up: - both g4x and ilk register share the same defines now - only defines which conflict have a _PLATFORM suffix, everyone else just gets comments to indicate which platforms do what - namespace is consistent DPFC_ now - SNB system agent fence registers also get a consistent namespace - REG_BIT() & co. for everything Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 24 +++---- drivers/gpu/drm/i915/i915_reg.h | 85 ++++++++++++------------ drivers/gpu/drm/i915/intel_pm.c | 14 ++-- 3 files changed, 62 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 1193e86690e5..1c9ada22b4de 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -322,16 +322,16 @@ static u32 g4x_dpfc_ctl(struct drm_i915_private *i915) u32 dpfc_ctl; dpfc_ctl = g4x_dpfc_ctl_limit(i915) | - DPFC_CTL_PLANE(params->crtc.i9xx_plane); + DPFC_CTL_PLANE_G4X(params->crtc.i9xx_plane); if (IS_G4X(i915)) - dpfc_ctl |= DPFC_SR_EN; + dpfc_ctl |= DPFC_CTL_SR_EN; if (params->fence_id >= 0) { - dpfc_ctl |= DPFC_CTL_FENCE_EN; + dpfc_ctl |= DPFC_CTL_FENCE_EN_G4X; if (DISPLAY_VER(i915) < 6) - dpfc_ctl |= params->fence_id; + dpfc_ctl |= DPFC_CTL_FENCENO(params->fence_id); } return dpfc_ctl; @@ -416,7 +416,7 @@ static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv) static bool ilk_fbc_is_compressing(struct drm_i915_private *i915) { - return intel_de_read(i915, ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK; + return intel_de_read(i915, ILK_DPFC_STATUS) & DPFC_COMP_SEG_MASK; } static void ilk_fbc_program_cfb(struct drm_i915_private *i915) @@ -441,10 +441,10 @@ static void snb_fbc_program_fence(struct drm_i915_private *i915) u32 ctl = 0; if (params->fence_id >= 0) - ctl = SNB_CPU_FENCE_ENABLE | params->fence_id; + ctl = SNB_DPFC_FENCE_EN | SNB_DPFC_FENCENO(params->fence_id); intel_de_write(i915, SNB_DPFC_CTL_SA, ctl); - intel_de_write(i915, DPFC_CPU_FENCE_OFFSET, params->fence_y_offset); + intel_de_write(i915, SNB_DPFC_CPU_FENCE_OFFSET, params->fence_y_offset); } static void snb_fbc_activate(struct drm_i915_private *dev_priv) @@ -506,13 +506,13 @@ static u32 ivb_dpfc_ctl(struct drm_i915_private *i915) dpfc_ctl = g4x_dpfc_ctl_limit(i915); if (IS_IVYBRIDGE(i915)) - dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane); + dpfc_ctl |= DPFC_CTL_PLANE_IVB(params->crtc.i9xx_plane); if (params->fence_id >= 0) - dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; + dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB; if (i915->fbc.false_color) - dpfc_ctl |= FBC_CTL_FALSE_COLOR; + dpfc_ctl |= DPFC_CTL_FALSE_COLOR; return dpfc_ctl; } @@ -533,14 +533,14 @@ static void ivb_fbc_activate(struct drm_i915_private *dev_priv) static bool ivb_fbc_is_compressing(struct drm_i915_private *i915) { - return intel_de_read(i915, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; + return intel_de_read(i915, ILK_DPFC_STATUS2) & DPFC_COMP_SEG_MASK_IVB; } static void ivb_fbc_set_false_color(struct drm_i915_private *i915, bool enable) { intel_de_rmw(i915, ILK_DPFC_CONTROL, - FBC_CTL_FALSE_COLOR, enable ? FBC_CTL_FALSE_COLOR : 0); + DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0); } static const struct intel_fbc_funcs ivb_fbc_funcs = { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1e99fe8dc253..d937958e7a6b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3345,56 +3345,55 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) /* Framebuffer compression for GM45+ */ #define DPFC_CB_BASE _MMIO(0x3200) +#define ILK_DPFC_CB_BASE _MMIO(0x43200) #define DPFC_CONTROL _MMIO(0x3208) -#define DPFC_CTL_EN (1 << 31) -#define DPFC_CTL_PLANE(plane) ((plane) << 30) -#define IVB_DPFC_CTL_PLANE(plane) ((plane) << 29) -#define DPFC_CTL_FENCE_EN (1 << 29) -#define IVB_DPFC_CTL_FENCE_EN (1 << 28) -#define DPFC_CTL_PERSISTENT_MODE (1 << 25) -#define DPFC_SR_EN (1 << 10) -#define DPFC_CTL_LIMIT_1X (0 << 6) -#define DPFC_CTL_LIMIT_2X (1 << 6) -#define DPFC_CTL_LIMIT_4X (2 << 6) +#define ILK_DPFC_CONTROL _MMIO(0x43208) +#define DPFC_CTL_EN REG_BIT(31) +#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */ +#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane)) +#define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */ +#define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */ +#define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane)) +#define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */ +#define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */ +#define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */ +#define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */ +#define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */ +#define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6) +#define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0) +#define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1) +#define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2) +#define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0) +#define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence)) #define DPFC_RECOMP_CTL _MMIO(0x320c) -#define DPFC_RECOMP_STALL_EN (1 << 27) -#define DPFC_RECOMP_STALL_WM_SHIFT (16) -#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) -#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) -#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) +#define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c) +#define DPFC_RECOMP_STALL_EN REG_BIT(27) +#define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16) +#define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0) #define DPFC_STATUS _MMIO(0x3210) -#define DPFC_INVAL_SEG_SHIFT (16) -#define DPFC_INVAL_SEG_MASK (0x07ff0000) -#define DPFC_COMP_SEG_SHIFT (0) -#define DPFC_COMP_SEG_MASK (0x000007ff) +#define ILK_DPFC_STATUS _MMIO(0x43210) +#define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16) +#define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0) #define DPFC_STATUS2 _MMIO(0x3214) +#define ILK_DPFC_STATUS2 _MMIO(0x43214) +#define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0) #define DPFC_FENCE_YOFF _MMIO(0x3218) -#define DPFC_CHICKEN _MMIO(0x3224) -#define DPFC_HT_MODIFY (1 << 31) - -/* Framebuffer compression for Ironlake */ -#define ILK_DPFC_CB_BASE _MMIO(0x43200) -#define ILK_DPFC_CONTROL _MMIO(0x43208) -#define FBC_CTL_FALSE_COLOR (1 << 10) -/* The bit 28-8 is reserved */ -#define DPFC_RESERVED (0x1FFFFF00) -#define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c) -#define ILK_DPFC_STATUS _MMIO(0x43210) -#define ILK_DPFC_COMP_SEG_MASK 0x7ff -#define IVB_FBC_STATUS2 _MMIO(0x43214) -#define IVB_FBC_COMP_SEG_MASK 0xfff #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218) +#define DPFC_CHICKEN _MMIO(0x3224) #define ILK_DPFC_CHICKEN _MMIO(0x43224) -#define ILK_DPFC_DISABLE_DUMMY0 (1 << 8) -#define ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL (1 << 14) -#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1 << 23) +#define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */ +#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */ +#define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */ +#define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */ + #define GLK_FBC_STRIDE _MMIO(0x43228) #define FBC_STRIDE_OVERRIDE REG_BIT(15) #define FBC_STRIDE_MASK REG_GENMASK(14, 0) #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x)) + #define ILK_FBC_RT_BASE _MMIO(0x2128) -#define ILK_FBC_RT_VALID (1 << 0) -#define SNB_FBC_FRONT_BUFFER (1 << 1) +#define ILK_FBC_RT_VALID REG_BIT(0) +#define SNB_FBC_FRONT_BUFFER REG_BIT(1) #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) #define ILK_FBCQ_DIS (1 << 22) @@ -3418,8 +3417,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) * The following two registers are of type GTTMMADR */ #define SNB_DPFC_CTL_SA _MMIO(0x100100) -#define SNB_CPU_FENCE_ENABLE (1 << 29) -#define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) +#define SNB_DPFC_FENCE_EN REG_BIT(29) +#define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0) +#define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence)) +#define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) /* Framebuffer compression for Ivybridge */ #define IVB_FBC_RT_BASE _MMIO(0x7020) @@ -3429,8 +3430,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define IPS_ENABLE (1 << 31) #define MSG_FBC_REND_STATE _MMIO(0x50380) -#define FBC_REND_NUKE (1 << 2) -#define FBC_REND_CACHE_CLEAN (1 << 1) +#define FBC_REND_NUKE REG_BIT(2) +#define FBC_REND_CACHE_CLEAN REG_BIT(1) /* * GPIO regs diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 59adf0ce6719..a64f3b195448 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -161,7 +161,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) * Display WA #0883: bxt */ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) | - ILK_DPFC_DISABLE_DUMMY0); + DPFC_DISABLE_DUMMY0); } static void glk_init_clock_gating(struct drm_i915_private *dev_priv) @@ -7435,7 +7435,7 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv) { /* Wa_1409120013:icl,ehl */ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, - ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL); + DPFC_CHICKEN_COMP_DUMMY_PIXEL); /*Wa_14010594013:icl, ehl */ intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1, @@ -7448,7 +7448,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, - ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL); + DPFC_CHICKEN_COMP_DUMMY_PIXEL); /* Wa_1409825376:tgl (pre-prod)*/ if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) @@ -7510,7 +7510,7 @@ static void cfl_init_clock_gating(struct drm_i915_private *dev_priv) * Display WA #0873: cfl */ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) | - ILK_DPFC_NUKE_ON_ANY_MODIFICATION); + DPFC_NUKE_ON_ANY_MODIFICATION); } static void kbl_init_clock_gating(struct drm_i915_private *dev_priv) @@ -7543,7 +7543,7 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv) * Display WA #0873: kbl */ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) | - ILK_DPFC_NUKE_ON_ANY_MODIFICATION); + DPFC_NUKE_ON_ANY_MODIFICATION); } static void skl_init_clock_gating(struct drm_i915_private *dev_priv) @@ -7570,14 +7570,14 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv) * Display WA #0873: skl */ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) | - ILK_DPFC_NUKE_ON_ANY_MODIFICATION); + DPFC_NUKE_ON_ANY_MODIFICATION); /* * WaFbcHighMemBwCorruptionAvoidance:skl * Display WA #0883: skl */ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) | - ILK_DPFC_DISABLE_DUMMY0); + DPFC_DISABLE_DUMMY0); } static void bdw_init_clock_gating(struct drm_i915_private *dev_priv) From patchwork Thu Nov 4 14:45:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12603287 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5557DC433F5 for ; Thu, 4 Nov 2021 14:46:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 28D67611EE for ; Thu, 4 Nov 2021 14:46:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 28D67611EE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3F65289C07; Thu, 4 Nov 2021 14:46:04 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 835CC89C07 for ; Thu, 4 Nov 2021 14:46:02 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10157"; a="211768122" X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="211768122" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2021 07:46:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="501566647" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga008.jf.intel.com with SMTP; 04 Nov 2021 07:45:59 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 04 Nov 2021 16:45:59 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Nov 2021 16:45:16 +0200 Message-Id: <20211104144520.22605-14-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com> References: <20211104144520.22605-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 13/17] drm/i915/fbc: Finish polishing FBC1 registers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Switch all the FBC1 registers over to REG_BTT()/etc. And while at it add a few more registers/bits that escaped the net previously. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 62 ++++++++++++++---------- 2 files changed, 37 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 1c9ada22b4de..888ee814e8bb 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -189,7 +189,7 @@ static u32 i965_fbc_ctl2(struct drm_i915_private *i915) FBC_CTL_PLANE(params->crtc.i9xx_plane); if (params->fence_id >= 0) - fbc_ctl2 |= FBC_CTL_CPU_FENCE; + fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN; return fbc_ctl2; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d937958e7a6b..3463853e4a6d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3309,34 +3309,44 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ #define FBC_CONTROL _MMIO(0x3208) -#define FBC_CTL_EN REG_BIT(31) -#define FBC_CTL_PERIODIC REG_BIT(30) -#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16) -#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) -#define FBC_CTL_STOP_ON_MOD REG_BIT(15) -#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ -#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm */ -#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) -#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) -#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) -#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) +#define FBC_CTL_EN REG_BIT(31) +#define FBC_CTL_PERIODIC REG_BIT(30) +#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16) +#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) +#define FBC_CTL_STOP_ON_MOD REG_BIT(15) +#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ +#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */ +#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) +#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) +#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) +#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) #define FBC_COMMAND _MMIO(0x320c) -#define FBC_CMD_COMPRESS (1 << 0) +#define FBC_CMD_COMPRESS REG_BIT(0) #define FBC_STATUS _MMIO(0x3210) -#define FBC_STAT_COMPRESSING (1 << 31) -#define FBC_STAT_COMPRESSED (1 << 30) -#define FBC_STAT_MODIFIED (1 << 29) -#define FBC_STAT_CURRENT_LINE_SHIFT (0) -#define FBC_CONTROL2 _MMIO(0x3214) -#define FBC_CTL_FENCE_DBL (0 << 4) -#define FBC_CTL_IDLE_IMM (0 << 2) -#define FBC_CTL_IDLE_FULL (1 << 2) -#define FBC_CTL_IDLE_LINE (2 << 2) -#define FBC_CTL_IDLE_DEBUG (3 << 2) -#define FBC_CTL_CPU_FENCE (1 << 1) -#define FBC_CTL_PLANE(plane) ((plane) << 0) -#define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */ -#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) +#define FBC_STAT_COMPRESSING REG_BIT(31) +#define FBC_STAT_COMPRESSED REG_BIT(30) +#define FBC_STAT_MODIFIED REG_BIT(29) +#define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0) +#define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */ +#define FBC_CTL_FENCE_DBL REG_BIT(4) +#define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2) +#define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0) +#define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1) +#define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2) +#define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3) +#define FBC_CTL_CPU_FENCE_EN REG_BIT(1) +#define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0) +#define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane)) +#define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */ +#define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */ +#define FBC_MOD_NUM_MASK REG_GENMASK(31, 1) +#define FBC_MOD_NUM_VALID REG_BIT(0) +#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */ +#define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */ +#define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0) +#define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1) +#define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2) +#define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3) #define FBC_LL_SIZE (1536) From patchwork Thu Nov 4 14:45:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12603289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 764A3C433EF for ; Thu, 4 Nov 2021 14:46:07 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4219F611EE for ; Thu, 4 Nov 2021 14:46:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4219F611EE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C08BD89CE1; Thu, 4 Nov 2021 14:46:06 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 835A789CE1 for ; Thu, 4 Nov 2021 14:46:05 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10157"; a="317919059" X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="317919059" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2021 07:46:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="489982365" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga007.jf.intel.com with SMTP; 04 Nov 2021 07:46:02 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 04 Nov 2021 16:46:02 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Nov 2021 16:45:17 +0200 Message-Id: <20211104144520.22605-15-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com> References: <20211104144520.22605-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 14/17] drm/i915: Relocate FBC_LLC_READ_CTRL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä In the case of FBC_LLC_READ_CTRL the "FBC" stands for frame buffer _caching_, not frame buffer compression. Move the register definition out from the middle of the frame buffer compression register definitions. Let's just stick it somewhere with similar looking register offsets. And while at it switch it over to REG_BIT(). Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_reg.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3463853e4a6d..07d6cf76c389 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -371,6 +371,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define VLV_G3DCTL _MMIO(0x9024) #define VLV_GSCKGCTL _MMIO(0x9028) +#define FBC_LLC_READ_CTRL _MMIO(0x9044) +#define FBC_LLC_FULLY_OPEN REG_BIT(30) + #define GEN6_MBCTL _MMIO(0x0907c) #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) @@ -3350,9 +3353,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define FBC_LL_SIZE (1536) -#define FBC_LLC_READ_CTRL _MMIO(0x9044) -#define FBC_LLC_FULLY_OPEN (1 << 30) - /* Framebuffer compression for GM45+ */ #define DPFC_CB_BASE _MMIO(0x3200) #define ILK_DPFC_CB_BASE _MMIO(0x43200) From patchwork Thu Nov 4 14:45:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12603291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 498D8C433F5 for ; Thu, 4 Nov 2021 14:46:10 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1BAF7611EE for ; Thu, 4 Nov 2021 14:46:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1BAF7611EE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B6CB389D86; Thu, 4 Nov 2021 14:46:09 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3A4C589D86 for ; Thu, 4 Nov 2021 14:46:08 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10157"; a="317919063" X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="317919063" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2021 07:46:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="450222788" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga006.jf.intel.com with SMTP; 04 Nov 2021 07:46:05 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 04 Nov 2021 16:46:05 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Nov 2021 16:45:18 +0200 Message-Id: <20211104144520.22605-16-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com> References: <20211104144520.22605-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 15/17] drm/i915/fbc: s/dev_priv/i915/ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Rename 'dev_priv' to 'i915' to match modern style. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 526 +++++++++++------------ 1 file changed, 263 insertions(+), 263 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 888ee814e8bb..ea3968001c4b 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -139,17 +139,17 @@ static unsigned int intel_fbc_cfb_stride(struct drm_i915_private *i915, return stride; } -static unsigned int intel_fbc_cfb_size(struct drm_i915_private *dev_priv, +static unsigned int intel_fbc_cfb_size(struct drm_i915_private *i915, const struct intel_fbc_state_cache *cache) { int lines = cache->plane.src_h; - if (DISPLAY_VER(dev_priv) == 7) + if (DISPLAY_VER(i915) == 7) lines = min(lines, 2048); - else if (DISPLAY_VER(dev_priv) >= 8) + else if (DISPLAY_VER(i915) >= 8) lines = min(lines, 2560); - return lines * intel_fbc_cfb_stride(dev_priv, cache); + return lines * intel_fbc_cfb_stride(i915, cache); } static u32 i8xx_fbc_ctl(struct drm_i915_private *i915) @@ -194,50 +194,50 @@ static u32 i965_fbc_ctl2(struct drm_i915_private *i915) return fbc_ctl2; } -static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv) +static void i8xx_fbc_deactivate(struct drm_i915_private *i915) { u32 fbc_ctl; /* Disable compression */ - fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL); + fbc_ctl = intel_de_read(i915, FBC_CONTROL); if ((fbc_ctl & FBC_CTL_EN) == 0) return; fbc_ctl &= ~FBC_CTL_EN; - intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl); + intel_de_write(i915, FBC_CONTROL, fbc_ctl); /* Wait for compressing bit to clear */ - if (intel_de_wait_for_clear(dev_priv, FBC_STATUS, + if (intel_de_wait_for_clear(i915, FBC_STATUS, FBC_STAT_COMPRESSING, 10)) { - drm_dbg_kms(&dev_priv->drm, "FBC idle timed out\n"); + drm_dbg_kms(&i915->drm, "FBC idle timed out\n"); return; } } -static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) +static void i8xx_fbc_activate(struct drm_i915_private *i915) { - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; const struct intel_fbc_reg_params *params = &fbc->params; int i; /* Clear old tags */ for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) - intel_de_write(dev_priv, FBC_TAG(i), 0); + intel_de_write(i915, FBC_TAG(i), 0); - if (DISPLAY_VER(dev_priv) == 4) { - intel_de_write(dev_priv, FBC_CONTROL2, - i965_fbc_ctl2(dev_priv)); - intel_de_write(dev_priv, FBC_FENCE_OFF, + if (DISPLAY_VER(i915) == 4) { + intel_de_write(i915, FBC_CONTROL2, + i965_fbc_ctl2(i915)); + intel_de_write(i915, FBC_FENCE_OFF, params->fence_y_offset); } - intel_de_write(dev_priv, FBC_CONTROL, - FBC_CTL_EN | i8xx_fbc_ctl(dev_priv)); + intel_de_write(i915, FBC_CONTROL, + FBC_CTL_EN | i8xx_fbc_ctl(i915)); } -static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv) +static bool i8xx_fbc_is_active(struct drm_i915_private *i915) { - return intel_de_read(dev_priv, FBC_CONTROL) & FBC_CTL_EN; + return intel_de_read(i915, FBC_CONTROL) & FBC_CTL_EN; } static bool i8xx_fbc_is_compressing(struct drm_i915_private *i915) @@ -337,32 +337,32 @@ static u32 g4x_dpfc_ctl(struct drm_i915_private *i915) return dpfc_ctl; } -static void g4x_fbc_activate(struct drm_i915_private *dev_priv) +static void g4x_fbc_activate(struct drm_i915_private *i915) { - const struct intel_fbc_reg_params *params = &dev_priv->fbc.params; + const struct intel_fbc_reg_params *params = &i915->fbc.params; - intel_de_write(dev_priv, DPFC_FENCE_YOFF, + intel_de_write(i915, DPFC_FENCE_YOFF, params->fence_y_offset); - intel_de_write(dev_priv, DPFC_CONTROL, - DPFC_CTL_EN | g4x_dpfc_ctl(dev_priv)); + intel_de_write(i915, DPFC_CONTROL, + DPFC_CTL_EN | g4x_dpfc_ctl(i915)); } -static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv) +static void g4x_fbc_deactivate(struct drm_i915_private *i915) { u32 dpfc_ctl; /* Disable compression */ - dpfc_ctl = intel_de_read(dev_priv, DPFC_CONTROL); + dpfc_ctl = intel_de_read(i915, DPFC_CONTROL); if (dpfc_ctl & DPFC_CTL_EN) { dpfc_ctl &= ~DPFC_CTL_EN; - intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl); + intel_de_write(i915, DPFC_CONTROL, dpfc_ctl); } } -static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv) +static bool g4x_fbc_is_active(struct drm_i915_private *i915) { - return intel_de_read(dev_priv, DPFC_CONTROL) & DPFC_CTL_EN; + return intel_de_read(i915, DPFC_CONTROL) & DPFC_CTL_EN; } static bool g4x_fbc_is_compressing(struct drm_i915_private *i915) @@ -386,32 +386,32 @@ static const struct intel_fbc_funcs g4x_fbc_funcs = { .program_cfb = g4x_fbc_program_cfb, }; -static void ilk_fbc_activate(struct drm_i915_private *dev_priv) +static void ilk_fbc_activate(struct drm_i915_private *i915) { - struct intel_fbc_reg_params *params = &dev_priv->fbc.params; + struct intel_fbc_reg_params *params = &i915->fbc.params; - intel_de_write(dev_priv, ILK_DPFC_FENCE_YOFF, + intel_de_write(i915, ILK_DPFC_FENCE_YOFF, params->fence_y_offset); - intel_de_write(dev_priv, ILK_DPFC_CONTROL, - DPFC_CTL_EN | g4x_dpfc_ctl(dev_priv)); + intel_de_write(i915, ILK_DPFC_CONTROL, + DPFC_CTL_EN | g4x_dpfc_ctl(i915)); } -static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv) +static void ilk_fbc_deactivate(struct drm_i915_private *i915) { u32 dpfc_ctl; /* Disable compression */ - dpfc_ctl = intel_de_read(dev_priv, ILK_DPFC_CONTROL); + dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL); if (dpfc_ctl & DPFC_CTL_EN) { dpfc_ctl &= ~DPFC_CTL_EN; - intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl); + intel_de_write(i915, ILK_DPFC_CONTROL, dpfc_ctl); } } -static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv) +static bool ilk_fbc_is_active(struct drm_i915_private *i915) { - return intel_de_read(dev_priv, ILK_DPFC_CONTROL) & DPFC_CTL_EN; + return intel_de_read(i915, ILK_DPFC_CONTROL) & DPFC_CTL_EN; } static bool ilk_fbc_is_compressing(struct drm_i915_private *i915) @@ -447,17 +447,17 @@ static void snb_fbc_program_fence(struct drm_i915_private *i915) intel_de_write(i915, SNB_DPFC_CPU_FENCE_OFFSET, params->fence_y_offset); } -static void snb_fbc_activate(struct drm_i915_private *dev_priv) +static void snb_fbc_activate(struct drm_i915_private *i915) { - snb_fbc_program_fence(dev_priv); + snb_fbc_program_fence(i915); - ilk_fbc_activate(dev_priv); + ilk_fbc_activate(i915); } -static void snb_fbc_nuke(struct drm_i915_private *dev_priv) +static void snb_fbc_nuke(struct drm_i915_private *i915) { - intel_de_write(dev_priv, MSG_FBC_REND_STATE, FBC_REND_NUKE); - intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE); + intel_de_write(i915, MSG_FBC_REND_STATE, FBC_REND_NUKE); + intel_de_posting_read(i915, MSG_FBC_REND_STATE); } static const struct intel_fbc_funcs snb_fbc_funcs = { @@ -517,18 +517,18 @@ static u32 ivb_dpfc_ctl(struct drm_i915_private *i915) return dpfc_ctl; } -static void ivb_fbc_activate(struct drm_i915_private *dev_priv) +static void ivb_fbc_activate(struct drm_i915_private *i915) { - if (DISPLAY_VER(dev_priv) >= 10) - glk_fbc_program_cfb_stride(dev_priv); - else if (DISPLAY_VER(dev_priv) == 9) - skl_fbc_program_cfb_stride(dev_priv); + if (DISPLAY_VER(i915) >= 10) + glk_fbc_program_cfb_stride(i915); + else if (DISPLAY_VER(i915) == 9) + skl_fbc_program_cfb_stride(i915); - if (dev_priv->ggtt.num_fences) - snb_fbc_program_fence(dev_priv); + if (i915->ggtt.num_fences) + snb_fbc_program_fence(i915); - intel_de_write(dev_priv, ILK_DPFC_CONTROL, - DPFC_CTL_EN | ivb_dpfc_ctl(dev_priv)); + intel_de_write(i915, ILK_DPFC_CONTROL, + DPFC_CTL_EN | ivb_dpfc_ctl(i915)); } static bool ivb_fbc_is_compressing(struct drm_i915_private *i915) @@ -553,34 +553,34 @@ static const struct intel_fbc_funcs ivb_fbc_funcs = { .set_false_color = ivb_fbc_set_false_color, }; -static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv) +static bool intel_fbc_hw_is_active(struct drm_i915_private *i915) { - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; - return fbc->funcs->is_active(dev_priv); + return fbc->funcs->is_active(i915); } -static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv) +static void intel_fbc_hw_activate(struct drm_i915_private *i915) { - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; trace_intel_fbc_activate(fbc->crtc); fbc->active = true; fbc->activated = true; - fbc->funcs->activate(dev_priv); + fbc->funcs->activate(i915); } -static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv) +static void intel_fbc_hw_deactivate(struct drm_i915_private *i915) { - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; trace_intel_fbc_deactivate(fbc->crtc); fbc->active = false; - fbc->funcs->deactivate(dev_priv); + fbc->funcs->deactivate(i915); } bool intel_fbc_is_compressing(struct drm_i915_private *i915) @@ -619,33 +619,33 @@ int intel_fbc_set_false_color(struct drm_i915_private *i915, bool enable) /** * intel_fbc_is_active - Is FBC active? - * @dev_priv: i915 device instance + * @i915: i915 device instance * * This function is used to verify the current state of FBC. * * FIXME: This should be tracked in the plane config eventually * instead of queried at runtime for most callers. */ -bool intel_fbc_is_active(struct drm_i915_private *dev_priv) +bool intel_fbc_is_active(struct drm_i915_private *i915) { - return dev_priv->fbc.active; + return i915->fbc.active; } -static void intel_fbc_activate(struct drm_i915_private *dev_priv) +static void intel_fbc_activate(struct drm_i915_private *i915) { - intel_fbc_hw_activate(dev_priv); - intel_fbc_nuke(dev_priv); + intel_fbc_hw_activate(i915); + intel_fbc_nuke(i915); } -static void intel_fbc_deactivate(struct drm_i915_private *dev_priv, +static void intel_fbc_deactivate(struct drm_i915_private *i915, const char *reason) { - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; - drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock)); + drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock)); if (fbc->active) - intel_fbc_hw_deactivate(dev_priv); + intel_fbc_hw_deactivate(i915); fbc->no_fbc_reason = reason; } @@ -658,7 +658,7 @@ static u64 intel_fbc_cfb_base_max(struct drm_i915_private *i915) return BIT_ULL(32); } -static u64 intel_fbc_stolen_end(struct drm_i915_private *dev_priv) +static u64 intel_fbc_stolen_end(struct drm_i915_private *i915) { u64 end; @@ -666,13 +666,13 @@ static u64 intel_fbc_stolen_end(struct drm_i915_private *dev_priv) * reserved range size, so it always assumes the maximum (8mb) is used. * If we enable FBC using a CFB on that memory range we'll get FIFO * underruns, even if that range is not reserved by the BIOS. */ - if (IS_BROADWELL(dev_priv) || (DISPLAY_VER(dev_priv) == 9 && - !IS_BROXTON(dev_priv))) - end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024; + if (IS_BROADWELL(i915) || + (DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915))) + end = resource_size(&i915->dsm) - 8 * 1024 * 1024; else end = U64_MAX; - return min(end, intel_fbc_cfb_base_max(dev_priv)); + return min(end, intel_fbc_cfb_base_max(i915)); } static int intel_fbc_min_limit(int fb_cpp) @@ -680,10 +680,10 @@ static int intel_fbc_min_limit(int fb_cpp) return fb_cpp == 2 ? 2 : 1; } -static int intel_fbc_max_limit(struct drm_i915_private *dev_priv) +static int intel_fbc_max_limit(struct drm_i915_private *i915) { /* WaFbcOnly1to1Ratio:ctg */ - if (IS_G4X(dev_priv)) + if (IS_G4X(i915)) return 1; /* @@ -693,23 +693,23 @@ static int intel_fbc_max_limit(struct drm_i915_private *dev_priv) return 4; } -static int find_compression_limit(struct drm_i915_private *dev_priv, +static int find_compression_limit(struct drm_i915_private *i915, unsigned int size, int min_limit) { - struct intel_fbc *fbc = &dev_priv->fbc; - u64 end = intel_fbc_stolen_end(dev_priv); + struct intel_fbc *fbc = &i915->fbc; + u64 end = intel_fbc_stolen_end(i915); int ret, limit = min_limit; size /= limit; /* Try to over-allocate to reduce reallocations and fragmentation. */ - ret = i915_gem_stolen_insert_node_in_range(dev_priv, &fbc->compressed_fb, + ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb, size <<= 1, 4096, 0, end); if (ret == 0) return limit; - for (; limit <= intel_fbc_max_limit(dev_priv); limit <<= 1) { - ret = i915_gem_stolen_insert_node_in_range(dev_priv, &fbc->compressed_fb, + for (; limit <= intel_fbc_max_limit(i915); limit <<= 1) { + ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb, size >>= 1, 4096, 0, end); if (ret == 0) return limit; @@ -718,34 +718,34 @@ static int find_compression_limit(struct drm_i915_private *dev_priv, return 0; } -static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, +static int intel_fbc_alloc_cfb(struct drm_i915_private *i915, unsigned int size, int min_limit) { - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; int ret; - drm_WARN_ON(&dev_priv->drm, + drm_WARN_ON(&i915->drm, drm_mm_node_allocated(&fbc->compressed_fb)); - drm_WARN_ON(&dev_priv->drm, + drm_WARN_ON(&i915->drm, drm_mm_node_allocated(&fbc->compressed_llb)); - if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) { - ret = i915_gem_stolen_insert_node(dev_priv, &fbc->compressed_llb, + if (DISPLAY_VER(i915) < 5 && !IS_G4X(i915)) { + ret = i915_gem_stolen_insert_node(i915, &fbc->compressed_llb, 4096, 4096); if (ret) goto err; } - ret = find_compression_limit(dev_priv, size, min_limit); + ret = find_compression_limit(i915, size, min_limit); if (!ret) goto err_llb; else if (ret > min_limit) - drm_info_once(&dev_priv->drm, + drm_info_once(&i915->drm, "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); fbc->limit = ret; - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(&i915->drm, "reserved %llu bytes of contiguous stolen space for FBC, limit: %d\n", fbc->compressed_fb.size, fbc->limit); @@ -753,64 +753,64 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, err_llb: if (drm_mm_node_allocated(&fbc->compressed_llb)) - i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_llb); + i915_gem_stolen_remove_node(i915, &fbc->compressed_llb); err: - if (drm_mm_initialized(&dev_priv->mm.stolen)) - drm_info_once(&dev_priv->drm, "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); + if (drm_mm_initialized(&i915->mm.stolen)) + drm_info_once(&i915->drm, "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); return -ENOSPC; } -static void intel_fbc_program_cfb(struct drm_i915_private *dev_priv) +static void intel_fbc_program_cfb(struct drm_i915_private *i915) { - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; - fbc->funcs->program_cfb(dev_priv); + fbc->funcs->program_cfb(i915); } -static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) +static void __intel_fbc_cleanup_cfb(struct drm_i915_private *i915) { - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; - if (WARN_ON(intel_fbc_hw_is_active(dev_priv))) + if (WARN_ON(intel_fbc_hw_is_active(i915))) return; if (drm_mm_node_allocated(&fbc->compressed_llb)) - i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_llb); + i915_gem_stolen_remove_node(i915, &fbc->compressed_llb); if (drm_mm_node_allocated(&fbc->compressed_fb)) - i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb); + i915_gem_stolen_remove_node(i915, &fbc->compressed_fb); } -void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) +void intel_fbc_cleanup_cfb(struct drm_i915_private *i915) { - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; - if (!HAS_FBC(dev_priv)) + if (!HAS_FBC(i915)) return; mutex_lock(&fbc->lock); - __intel_fbc_cleanup_cfb(dev_priv); + __intel_fbc_cleanup_cfb(i915); mutex_unlock(&fbc->lock); } -static bool stride_is_valid(struct drm_i915_private *dev_priv, +static bool stride_is_valid(struct drm_i915_private *i915, u64 modifier, unsigned int stride) { /* This should have been caught earlier. */ - if (drm_WARN_ON_ONCE(&dev_priv->drm, (stride & (64 - 1)) != 0)) + if (drm_WARN_ON_ONCE(&i915->drm, (stride & (64 - 1)) != 0)) return false; /* Below are the additional FBC restrictions. */ if (stride < 512) return false; - if (DISPLAY_VER(dev_priv) == 2 || DISPLAY_VER(dev_priv) == 3) + if (DISPLAY_VER(i915) == 2 || DISPLAY_VER(i915) == 3) return stride == 4096 || stride == 8192; - if (DISPLAY_VER(dev_priv) == 4 && !IS_G4X(dev_priv) && stride < 2048) + if (DISPLAY_VER(i915) == 4 && !IS_G4X(i915) && stride < 2048) return false; /* Display WA #1105: skl,bxt,kbl,cfl,glk */ - if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) && + if ((DISPLAY_VER(i915) == 9 || IS_GEMINILAKE(i915)) && modifier == DRM_FORMAT_MOD_LINEAR && stride & 511) return false; @@ -820,7 +820,7 @@ static bool stride_is_valid(struct drm_i915_private *dev_priv, return true; } -static bool pixel_format_is_valid(struct drm_i915_private *dev_priv, +static bool pixel_format_is_valid(struct drm_i915_private *i915, u32 pixel_format) { switch (pixel_format) { @@ -830,10 +830,10 @@ static bool pixel_format_is_valid(struct drm_i915_private *dev_priv, case DRM_FORMAT_XRGB1555: case DRM_FORMAT_RGB565: /* 16bpp not supported on gen2 */ - if (DISPLAY_VER(dev_priv) == 2) + if (DISPLAY_VER(i915) == 2) return false; /* WaFbcOnly1to1Ratio:ctg */ - if (IS_G4X(dev_priv)) + if (IS_G4X(i915)) return false; return true; default: @@ -841,13 +841,13 @@ static bool pixel_format_is_valid(struct drm_i915_private *dev_priv, } } -static bool rotation_is_valid(struct drm_i915_private *dev_priv, +static bool rotation_is_valid(struct drm_i915_private *i915, u32 pixel_format, unsigned int rotation) { - if (DISPLAY_VER(dev_priv) >= 9 && pixel_format == DRM_FORMAT_RGB565 && + if (DISPLAY_VER(i915) >= 9 && pixel_format == DRM_FORMAT_RGB565 && drm_rotation_90_or_270(rotation)) return false; - else if (DISPLAY_VER(dev_priv) <= 4 && !IS_G4X(dev_priv) && + else if (DISPLAY_VER(i915) <= 4 && !IS_G4X(i915) && rotation != DRM_MODE_ROTATE_0) return false; @@ -862,17 +862,17 @@ static bool rotation_is_valid(struct drm_i915_private *dev_priv, */ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_fbc *fbc = &dev_priv->fbc; + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_fbc *fbc = &i915->fbc; unsigned int effective_w, effective_h, max_w, max_h; - if (DISPLAY_VER(dev_priv) >= 10) { + if (DISPLAY_VER(i915) >= 10) { max_w = 5120; max_h = 4096; - } else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) { + } else if (DISPLAY_VER(i915) >= 8 || IS_HASWELL(i915)) { max_w = 4096; max_h = 4096; - } else if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) { + } else if (IS_G4X(i915) || DISPLAY_VER(i915) >= 5) { max_w = 4096; max_h = 2048; } else { @@ -888,14 +888,14 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) return effective_w <= max_w && effective_h <= max_h; } -static bool tiling_is_valid(struct drm_i915_private *dev_priv, +static bool tiling_is_valid(struct drm_i915_private *i915, u64 modifier) { switch (modifier) { case DRM_FORMAT_MOD_LINEAR: case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: - return DISPLAY_VER(dev_priv) >= 9; + return DISPLAY_VER(i915) >= 9; case I915_FORMAT_MOD_X_TILED: return true; default: @@ -907,8 +907,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_fbc *fbc = &dev_priv->fbc; + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_fbc *fbc = &i915->fbc; struct intel_fbc_state_cache *cache = &fbc->state_cache; struct drm_framebuffer *fb = plane_state->hw.fb; @@ -917,7 +917,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, return; cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags; - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) + if (IS_HASWELL(i915) || IS_BROADWELL(i915)) cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate; cache->plane.rotation = plane_state->hw.rotation; @@ -942,7 +942,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, cache->fence_y_offset = intel_plane_fence_y_offset(plane_state); - drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE && + drm_WARN_ON(&i915->drm, plane_state->flags & PLANE_HAS_FENCE && !plane_state->ggtt_vma->fence); if (plane_state->flags & PLANE_HAS_FENCE && @@ -954,19 +954,19 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, cache->psr2_active = crtc_state->has_psr2; } -static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv) +static bool intel_fbc_cfb_size_changed(struct drm_i915_private *i915) { - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; - return intel_fbc_cfb_size(dev_priv, &fbc->state_cache) > + return intel_fbc_cfb_size(i915, &fbc->state_cache) > fbc->compressed_fb.size * fbc->limit; } -static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *dev_priv, +static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *i915, const struct intel_fbc_state_cache *cache) { unsigned int stride = _intel_fbc_cfb_stride(cache); - unsigned int stride_aligned = intel_fbc_cfb_stride(dev_priv, cache); + unsigned int stride_aligned = intel_fbc_cfb_stride(i915, cache); /* * Override stride in 64 byte units per 4 line segment. @@ -976,23 +976,23 @@ static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *dev_priv, * we always need to use the override there. */ if (stride != stride_aligned || - (DISPLAY_VER(dev_priv) == 9 && + (DISPLAY_VER(i915) == 9 && cache->fb.modifier == DRM_FORMAT_MOD_LINEAR)) return stride_aligned * 4 / 64; return 0; } -static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv) +static bool intel_fbc_can_enable(struct drm_i915_private *i915) { - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; - if (intel_vgpu_active(dev_priv)) { + if (intel_vgpu_active(i915)) { fbc->no_fbc_reason = "VGPU is active"; return false; } - if (!dev_priv->params.enable_fbc) { + if (!i915->params.enable_fbc) { fbc->no_fbc_reason = "disabled per module param or by default"; return false; } @@ -1007,11 +1007,11 @@ static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv) static bool intel_fbc_can_activate(struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_fbc *fbc = &dev_priv->fbc; + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_fbc *fbc = &i915->fbc; struct intel_fbc_state_cache *cache = &fbc->state_cache; - if (!intel_fbc_can_enable(dev_priv)) + if (!intel_fbc_can_enable(i915)) return false; if (!cache->plane.visible) { @@ -1054,28 +1054,28 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) * For now this will effectively disable FBC with 90/270 degree * rotation. */ - if (DISPLAY_VER(dev_priv) < 9 && cache->fence_id < 0) { + if (DISPLAY_VER(i915) < 9 && cache->fence_id < 0) { fbc->no_fbc_reason = "framebuffer not tiled or fenced"; return false; } - if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) { + if (!pixel_format_is_valid(i915, cache->fb.format->format)) { fbc->no_fbc_reason = "pixel format is invalid"; return false; } - if (!rotation_is_valid(dev_priv, cache->fb.format->format, + if (!rotation_is_valid(i915, cache->fb.format->format, cache->plane.rotation)) { fbc->no_fbc_reason = "rotation unsupported"; return false; } - if (!tiling_is_valid(dev_priv, cache->fb.modifier)) { + if (!tiling_is_valid(i915, cache->fb.modifier)) { fbc->no_fbc_reason = "tiling unsupported"; return false; } - if (!stride_is_valid(dev_priv, cache->fb.modifier, + if (!stride_is_valid(i915, cache->fb.modifier, cache->fb.stride * cache->fb.format->cpp[0])) { fbc->no_fbc_reason = "framebuffer stride not supported"; return false; @@ -1088,8 +1088,8 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) } /* WaFbcExceedCdClockThreshold:hsw,bdw */ - if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && - cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) { + if ((IS_HASWELL(i915) || IS_BROADWELL(i915)) && + cache->crtc.hsw_bdw_pixel_rate >= i915->cdclk.hw.cdclk * 95 / 100) { fbc->no_fbc_reason = "pixel rate is too big"; return false; } @@ -1104,7 +1104,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) * we didn't get any invalidate/deactivate calls, but this would require * a lot of tracking just for a specific case. If we conclude it's an * important case, we can implement it later. */ - if (intel_fbc_cfb_size_changed(dev_priv)) { + if (intel_fbc_cfb_size_changed(i915)) { fbc->no_fbc_reason = "CFB requirements changed"; return false; } @@ -1114,14 +1114,14 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) * having a Y offset that isn't divisible by 4 causes FIFO underrun * and screen flicker. */ - if (DISPLAY_VER(dev_priv) >= 9 && + if (DISPLAY_VER(i915) >= 9 && (fbc->state_cache.plane.adjusted_y & 3)) { fbc->no_fbc_reason = "plane Y offset is misaligned"; return false; } /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */ - if (DISPLAY_VER(dev_priv) >= 11 && + if (DISPLAY_VER(i915) >= 11 && (cache->plane.src_h + cache->plane.adjusted_y) % 4) { fbc->no_fbc_reason = "plane height + offset is non-modulo of 4"; return false; @@ -1132,7 +1132,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) * Recommendation is to keep this combination disabled * Bspec: 50422 HSD: 14010260002 */ - if (fbc->state_cache.psr2_active && DISPLAY_VER(dev_priv) >= 12) { + if (fbc->state_cache.psr2_active && DISPLAY_VER(i915) >= 12) { fbc->no_fbc_reason = "not supported with PSR2"; return false; } @@ -1143,8 +1143,8 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) static void intel_fbc_get_reg_params(struct intel_crtc *crtc, struct intel_fbc_reg_params *params) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_fbc *fbc = &dev_priv->fbc; + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_fbc *fbc = &i915->fbc; struct intel_fbc_state_cache *cache = &fbc->state_cache; /* Since all our fields are integer types, use memset here so the @@ -1164,9 +1164,9 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc, params->fb.modifier = cache->fb.modifier; params->fb.stride = cache->fb.stride; - params->cfb_stride = intel_fbc_cfb_stride(dev_priv, cache); - params->cfb_size = intel_fbc_cfb_size(dev_priv, cache); - params->override_cfb_stride = intel_fbc_override_cfb_stride(dev_priv, cache); + params->cfb_stride = intel_fbc_cfb_stride(i915, cache); + params->cfb_size = intel_fbc_cfb_size(i915, cache); + params->override_cfb_stride = intel_fbc_override_cfb_stride(i915, cache); params->plane_visible = cache->plane.visible; } @@ -1174,8 +1174,8 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc, static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - const struct intel_fbc *fbc = &dev_priv->fbc; + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + const struct intel_fbc *fbc = &i915->fbc; const struct intel_fbc_state_cache *cache = &fbc->state_cache; const struct intel_fbc_reg_params *params = &fbc->params; @@ -1197,13 +1197,13 @@ static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state) if (params->fb.stride != cache->fb.stride) return false; - if (params->cfb_stride != intel_fbc_cfb_stride(dev_priv, cache)) + if (params->cfb_stride != intel_fbc_cfb_stride(i915, cache)) return false; - if (params->cfb_size != intel_fbc_cfb_size(dev_priv, cache)) + if (params->cfb_size != intel_fbc_cfb_size(i915, cache)) return false; - if (params->override_cfb_stride != intel_fbc_override_cfb_stride(dev_priv, cache)) + if (params->override_cfb_stride != intel_fbc_override_cfb_stride(i915, cache)) return false; return true; @@ -1217,8 +1217,8 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); const struct intel_plane_state *plane_state = intel_atomic_get_new_plane_state(state, plane); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_fbc *fbc = &dev_priv->fbc; + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_fbc *fbc = &i915->fbc; const char *reason = "update pending"; bool need_vblank_wait = false; @@ -1234,7 +1234,7 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state, fbc->flip_pending = true; if (!intel_fbc_can_flip_nuke(crtc_state)) { - intel_fbc_deactivate(dev_priv, reason); + intel_fbc_deactivate(i915, reason); /* * Display WA #1198: glk+ @@ -1250,7 +1250,7 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state, * if at least one frame has already passed. */ if (fbc->activated && - DISPLAY_VER(dev_priv) >= 10) + DISPLAY_VER(i915) >= 10) need_vblank_wait = true; fbc->activated = false; } @@ -1262,43 +1262,43 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state, /** * __intel_fbc_disable - disable FBC - * @dev_priv: i915 device instance + * @i915: i915 device instance * * This is the low level function that actually disables FBC. Callers should * grab the FBC lock. */ -static void __intel_fbc_disable(struct drm_i915_private *dev_priv) +static void __intel_fbc_disable(struct drm_i915_private *i915) { - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; struct intel_crtc *crtc = fbc->crtc; - drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock)); - drm_WARN_ON(&dev_priv->drm, !fbc->crtc); - drm_WARN_ON(&dev_priv->drm, fbc->active); + drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock)); + drm_WARN_ON(&i915->drm, !fbc->crtc); + drm_WARN_ON(&i915->drm, fbc->active); - drm_dbg_kms(&dev_priv->drm, "Disabling FBC on pipe %c\n", + drm_dbg_kms(&i915->drm, "Disabling FBC on pipe %c\n", pipe_name(crtc->pipe)); - __intel_fbc_cleanup_cfb(dev_priv); + __intel_fbc_cleanup_cfb(i915); fbc->crtc = NULL; } static void __intel_fbc_post_update(struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_fbc *fbc = &dev_priv->fbc; + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_fbc *fbc = &i915->fbc; - drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock)); + drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock)); if (fbc->crtc != crtc) return; fbc->flip_pending = false; - if (!dev_priv->params.enable_fbc) { - intel_fbc_deactivate(dev_priv, "disabled at runtime per module param"); - __intel_fbc_disable(dev_priv); + if (!i915->params.enable_fbc) { + intel_fbc_deactivate(i915, "disabled at runtime per module param"); + __intel_fbc_disable(i915); return; } @@ -1309,19 +1309,19 @@ static void __intel_fbc_post_update(struct intel_crtc *crtc) return; if (!fbc->busy_bits) - intel_fbc_activate(dev_priv); + intel_fbc_activate(i915); else - intel_fbc_deactivate(dev_priv, "frontbuffer write"); + intel_fbc_deactivate(i915, "frontbuffer write"); } void intel_fbc_post_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_plane *plane = to_intel_plane(crtc->base.primary); const struct intel_plane_state *plane_state = intel_atomic_get_new_plane_state(state, plane); - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; if (!plane->has_fbc || !plane_state) return; @@ -1339,13 +1339,13 @@ static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc) return fbc->possible_framebuffer_bits; } -void intel_fbc_invalidate(struct drm_i915_private *dev_priv, +void intel_fbc_invalidate(struct drm_i915_private *i915, unsigned int frontbuffer_bits, enum fb_op_origin origin) { - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; - if (!HAS_FBC(dev_priv)) + if (!HAS_FBC(i915)) return; if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE) @@ -1356,17 +1356,17 @@ void intel_fbc_invalidate(struct drm_i915_private *dev_priv, fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits; if (fbc->crtc && fbc->busy_bits) - intel_fbc_deactivate(dev_priv, "frontbuffer write"); + intel_fbc_deactivate(i915, "frontbuffer write"); mutex_unlock(&fbc->lock); } -void intel_fbc_flush(struct drm_i915_private *dev_priv, +void intel_fbc_flush(struct drm_i915_private *i915, unsigned int frontbuffer_bits, enum fb_op_origin origin) { - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; - if (!HAS_FBC(dev_priv)) + if (!HAS_FBC(i915)) return; mutex_lock(&fbc->lock); @@ -1379,7 +1379,7 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv, if (!fbc->busy_bits && fbc->crtc && (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) { if (fbc->active) - intel_fbc_nuke(dev_priv); + intel_fbc_nuke(i915); else if (!fbc->flip_pending) __intel_fbc_post_update(fbc->crtc); } @@ -1390,7 +1390,7 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv, /** * intel_fbc_choose_crtc - select a CRTC to enable FBC on - * @dev_priv: i915 device instance + * @i915: i915 device instance * @state: the atomic state structure * * This function looks at the proposed state for CRTCs and planes, then chooses @@ -1398,12 +1398,12 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv, * true. * * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe - * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc. + * enable FBC for the chosen CRTC. If it does, it will set i915->fbc.crtc. */ -void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, +void intel_fbc_choose_crtc(struct drm_i915_private *i915, struct intel_atomic_state *state) { - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; struct intel_plane *plane; struct intel_plane_state *plane_state; bool crtc_chosen = false; @@ -1416,7 +1416,7 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, !intel_atomic_get_new_crtc_state(state, fbc->crtc)) goto out; - if (!intel_fbc_can_enable(dev_priv)) + if (!intel_fbc_can_enable(i915)) goto out; /* Simply choose the first CRTC that is compatible and has a visible @@ -1460,13 +1460,13 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, static void intel_fbc_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_plane *plane = to_intel_plane(crtc->base.primary); const struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); const struct intel_plane_state *plane_state = intel_atomic_get_new_plane_state(state, plane); - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; struct intel_fbc_state_cache *cache = &fbc->state_cache; int min_limit; @@ -1483,13 +1483,13 @@ static void intel_fbc_enable(struct intel_atomic_state *state, goto out; if (fbc->limit >= min_limit && - !intel_fbc_cfb_size_changed(dev_priv)) + !intel_fbc_cfb_size_changed(i915)) goto out; - __intel_fbc_disable(dev_priv); + __intel_fbc_disable(i915); } - drm_WARN_ON(&dev_priv->drm, fbc->active); + drm_WARN_ON(&i915->drm, fbc->active); intel_fbc_update_state_cache(crtc, crtc_state, plane_state); @@ -1497,20 +1497,20 @@ static void intel_fbc_enable(struct intel_atomic_state *state, if (!cache->plane.visible) goto out; - if (intel_fbc_alloc_cfb(dev_priv, - intel_fbc_cfb_size(dev_priv, cache), min_limit)) { + if (intel_fbc_alloc_cfb(i915, + intel_fbc_cfb_size(i915, cache), min_limit)) { cache->plane.visible = false; fbc->no_fbc_reason = "not enough stolen memory"; goto out; } - drm_dbg_kms(&dev_priv->drm, "Enabling FBC on pipe %c\n", + drm_dbg_kms(&i915->drm, "Enabling FBC on pipe %c\n", pipe_name(crtc->pipe)); fbc->no_fbc_reason = "FBC enabled but not active yet\n"; fbc->crtc = crtc; - intel_fbc_program_cfb(dev_priv); + intel_fbc_program_cfb(i915); out: mutex_unlock(&fbc->lock); } @@ -1523,16 +1523,16 @@ static void intel_fbc_enable(struct intel_atomic_state *state, */ void intel_fbc_disable(struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_plane *plane = to_intel_plane(crtc->base.primary); - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; if (!plane->has_fbc) return; mutex_lock(&fbc->lock); if (fbc->crtc == crtc) - __intel_fbc_disable(dev_priv); + __intel_fbc_disable(i915); mutex_unlock(&fbc->lock); } @@ -1560,30 +1560,30 @@ void intel_fbc_update(struct intel_atomic_state *state, /** * intel_fbc_global_disable - globally disable FBC - * @dev_priv: i915 device instance + * @i915: i915 device instance * * This function disables FBC regardless of which CRTC is associated with it. */ -void intel_fbc_global_disable(struct drm_i915_private *dev_priv) +void intel_fbc_global_disable(struct drm_i915_private *i915) { - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; - if (!HAS_FBC(dev_priv)) + if (!HAS_FBC(i915)) return; mutex_lock(&fbc->lock); if (fbc->crtc) { - drm_WARN_ON(&dev_priv->drm, fbc->crtc->active); - __intel_fbc_disable(dev_priv); + drm_WARN_ON(&i915->drm, fbc->crtc->active); + __intel_fbc_disable(i915); } mutex_unlock(&fbc->lock); } static void intel_fbc_underrun_work_fn(struct work_struct *work) { - struct drm_i915_private *dev_priv = + struct drm_i915_private *i915 = container_of(work, struct drm_i915_private, fbc.underrun_work); - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; mutex_lock(&fbc->lock); @@ -1591,46 +1591,46 @@ static void intel_fbc_underrun_work_fn(struct work_struct *work) if (fbc->underrun_detected || !fbc->crtc) goto out; - drm_dbg_kms(&dev_priv->drm, "Disabling FBC due to FIFO underrun.\n"); + drm_dbg_kms(&i915->drm, "Disabling FBC due to FIFO underrun.\n"); fbc->underrun_detected = true; - intel_fbc_deactivate(dev_priv, "FIFO underrun"); + intel_fbc_deactivate(i915, "FIFO underrun"); out: mutex_unlock(&fbc->lock); } /* * intel_fbc_reset_underrun - reset FBC fifo underrun status. - * @dev_priv: i915 device instance + * @i915: i915 device instance * * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we * want to re-enable FBC after an underrun to increase test coverage. */ -int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv) +int intel_fbc_reset_underrun(struct drm_i915_private *i915) { int ret; - cancel_work_sync(&dev_priv->fbc.underrun_work); + cancel_work_sync(&i915->fbc.underrun_work); - ret = mutex_lock_interruptible(&dev_priv->fbc.lock); + ret = mutex_lock_interruptible(&i915->fbc.lock); if (ret) return ret; - if (dev_priv->fbc.underrun_detected) { - drm_dbg_kms(&dev_priv->drm, + if (i915->fbc.underrun_detected) { + drm_dbg_kms(&i915->drm, "Re-allowing FBC after fifo underrun\n"); - dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared"; + i915->fbc.no_fbc_reason = "FIFO underrun cleared"; } - dev_priv->fbc.underrun_detected = false; - mutex_unlock(&dev_priv->fbc.lock); + i915->fbc.underrun_detected = false; + mutex_unlock(&i915->fbc.lock); return 0; } /** * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun - * @dev_priv: i915 device instance + * @i915: i915 device instance * * Without FBC, most underruns are harmless and don't really cause too many * problems, except for an annoying message on dmesg. With FBC, underruns can @@ -1642,11 +1642,11 @@ int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv) * * This function is called from the IRQ handler. */ -void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv) +void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915) { - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; - if (!HAS_FBC(dev_priv)) + if (!HAS_FBC(i915)) return; /* There's no guarantee that underrun_detected won't be set to true @@ -1670,26 +1670,26 @@ void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv) * space to change the value during runtime without sanitizing it again. IGT * relies on being able to change i915.enable_fbc at runtime. */ -static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv) +static int intel_sanitize_fbc_option(struct drm_i915_private *i915) { - if (dev_priv->params.enable_fbc >= 0) - return !!dev_priv->params.enable_fbc; + if (i915->params.enable_fbc >= 0) + return !!i915->params.enable_fbc; - if (!HAS_FBC(dev_priv)) + if (!HAS_FBC(i915)) return 0; - if (IS_BROADWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 9) + if (IS_BROADWELL(i915) || DISPLAY_VER(i915) >= 9) return 1; return 0; } -static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv) +static bool need_fbc_vtd_wa(struct drm_i915_private *i915) { /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */ if (intel_vtd_active() && - (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) { - drm_info(&dev_priv->drm, + (IS_SKYLAKE(i915) || IS_BROXTON(i915))) { + drm_info(&i915->drm, "Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n"); return true; } @@ -1699,42 +1699,42 @@ static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv) /** * intel_fbc_init - Initialize FBC - * @dev_priv: the i915 device + * @i915: the i915 device * * This function might be called during PM init process. */ -void intel_fbc_init(struct drm_i915_private *dev_priv) +void intel_fbc_init(struct drm_i915_private *i915) { - struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc *fbc = &i915->fbc; INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn); mutex_init(&fbc->lock); fbc->active = false; - if (!drm_mm_initialized(&dev_priv->mm.stolen)) - mkwrite_device_info(dev_priv)->display.has_fbc = false; + if (!drm_mm_initialized(&i915->mm.stolen)) + mkwrite_device_info(i915)->display.has_fbc = false; - if (need_fbc_vtd_wa(dev_priv)) - mkwrite_device_info(dev_priv)->display.has_fbc = false; + if (need_fbc_vtd_wa(i915)) + mkwrite_device_info(i915)->display.has_fbc = false; - dev_priv->params.enable_fbc = intel_sanitize_fbc_option(dev_priv); - drm_dbg_kms(&dev_priv->drm, "Sanitized enable_fbc value: %d\n", - dev_priv->params.enable_fbc); + i915->params.enable_fbc = intel_sanitize_fbc_option(i915); + drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n", + i915->params.enable_fbc); - if (!HAS_FBC(dev_priv)) { + if (!HAS_FBC(i915)) { fbc->no_fbc_reason = "unsupported by this chipset"; return; } - if (DISPLAY_VER(dev_priv) >= 7) + if (DISPLAY_VER(i915) >= 7) fbc->funcs = &ivb_fbc_funcs; - else if (DISPLAY_VER(dev_priv) == 6) + else if (DISPLAY_VER(i915) == 6) fbc->funcs = &snb_fbc_funcs; - else if (DISPLAY_VER(dev_priv) == 5) + else if (DISPLAY_VER(i915) == 5) fbc->funcs = &ilk_fbc_funcs; - else if (IS_G4X(dev_priv)) + else if (IS_G4X(i915)) fbc->funcs = &g4x_fbc_funcs; - else if (DISPLAY_VER(dev_priv) == 4) + else if (DISPLAY_VER(i915) == 4) fbc->funcs = &i965_fbc_funcs; else fbc->funcs = &i8xx_fbc_funcs; @@ -1742,6 +1742,6 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) /* We still don't have any sort of hardware state readout for FBC, so * deactivate it in case the BIOS activated it to make sure software * matches the hardware state. */ - if (intel_fbc_hw_is_active(dev_priv)) - intel_fbc_hw_deactivate(dev_priv); + if (intel_fbc_hw_is_active(i915)) + intel_fbc_hw_deactivate(i915); } From patchwork Thu Nov 4 14:45:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12603293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25CA4C433FE for ; Thu, 4 Nov 2021 14:46:13 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E65BC611EF for ; Thu, 4 Nov 2021 14:46:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org E65BC611EF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A42489FBC; Thu, 4 Nov 2021 14:46:12 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id B082789F6F for ; Thu, 4 Nov 2021 14:46:11 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10157"; a="212463261" X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="212463261" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2021 07:46:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="532287833" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga001.jf.intel.com with SMTP; 04 Nov 2021 07:46:08 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 04 Nov 2021 16:46:07 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Nov 2021 16:45:19 +0200 Message-Id: <20211104144520.22605-17-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com> References: <20211104144520.22605-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 16/17] drm/i915/fbc: Start passing around intel_fbc X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä In preparation for multiple FBC instances start passing around intel_fbc pointers rather than i915 pointers. And once there are multiple of these we can't rely on container_of() to get back to the i915, so we toss in a fbc->i915 pointer already. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- .../drm/i915/display/intel_display_debugfs.c | 8 +- drivers/gpu/drm/i915/display/intel_fbc.c | 379 +++++++++--------- drivers/gpu/drm/i915/display/intel_fbc.h | 14 +- .../drm/i915/display/intel_fifo_underrun.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 2 +- 7 files changed, 200 insertions(+), 208 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 29392dfc46c8..3be82f075655 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -10837,7 +10837,7 @@ void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) destroy_workqueue(i915->flip_wq); destroy_workqueue(i915->modeset_wq); - intel_fbc_cleanup_cfb(i915); + intel_fbc_cleanup(i915); } /* part #3: call after gem init */ diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 1a9210739727..3f5a5e1b1c41 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -52,10 +52,10 @@ static int i915_fbc_status(struct seq_file *m, void *unused) wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); mutex_lock(&fbc->lock); - if (intel_fbc_is_active(dev_priv)) { + if (intel_fbc_is_active(fbc)) { seq_puts(m, "FBC enabled\n"); seq_printf(m, "Compressing: %s\n", - yesno(intel_fbc_is_compressing(dev_priv))); + yesno(intel_fbc_is_compressing(fbc))); } else { seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason); } @@ -79,7 +79,7 @@ static int i915_fbc_false_color_set(void *data, u64 val) { struct drm_i915_private *dev_priv = data; - return intel_fbc_set_false_color(dev_priv, val); + return intel_fbc_set_false_color(&dev_priv->fbc, val); } DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops, @@ -2063,7 +2063,7 @@ i915_fifo_underrun_reset_write(struct file *filp, return ret; } - ret = intel_fbc_reset_underrun(dev_priv); + ret = intel_fbc_reset_underrun(&dev_priv->fbc); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index ea3968001c4b..e8235d55e76a 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -49,13 +49,13 @@ #include "intel_frontbuffer.h" struct intel_fbc_funcs { - void (*activate)(struct drm_i915_private *i915); - void (*deactivate)(struct drm_i915_private *i915); - bool (*is_active)(struct drm_i915_private *i915); - bool (*is_compressing)(struct drm_i915_private *i915); - void (*nuke)(struct drm_i915_private *i915); - void (*program_cfb)(struct drm_i915_private *i915); - void (*set_false_color)(struct drm_i915_private *i915, bool enable); + void (*activate)(struct intel_fbc *fbc); + void (*deactivate)(struct intel_fbc *fbc); + bool (*is_active)(struct intel_fbc *fbc); + bool (*is_compressing)(struct intel_fbc *fbc); + void (*nuke)(struct intel_fbc *fbc); + void (*program_cfb)(struct intel_fbc *fbc); + void (*set_false_color)(struct intel_fbc *fbc, bool enable); }; /* @@ -94,9 +94,10 @@ static unsigned int _intel_fbc_cfb_stride(const struct intel_fbc_state_cache *ca } /* minimum acceptable cfb stride in bytes, assuming 1:1 compression limit */ -static unsigned int skl_fbc_min_cfb_stride(struct drm_i915_private *i915, +static unsigned int skl_fbc_min_cfb_stride(struct intel_fbc *fbc, const struct intel_fbc_state_cache *cache) { + struct drm_i915_private *i915 = fbc->i915; unsigned int limit = 4; /* 1:4 compression limit is the worst case */ unsigned int cpp = 4; /* FBC always 4 bytes per pixel */ unsigned int height = 4; /* FBC segment is 4 lines */ @@ -123,9 +124,10 @@ static unsigned int skl_fbc_min_cfb_stride(struct drm_i915_private *i915, } /* properly aligned cfb stride in bytes, assuming 1:1 compression limit */ -static unsigned int intel_fbc_cfb_stride(struct drm_i915_private *i915, +static unsigned int intel_fbc_cfb_stride(struct intel_fbc *fbc, const struct intel_fbc_state_cache *cache) { + struct drm_i915_private *i915 = fbc->i915; unsigned int stride = _intel_fbc_cfb_stride(cache); /* @@ -134,14 +136,15 @@ static unsigned int intel_fbc_cfb_stride(struct drm_i915_private *i915, * that regardless of the compression limit we choose later. */ if (DISPLAY_VER(i915) >= 9) - return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(i915, cache)); + return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(fbc, cache)); else return stride; } -static unsigned int intel_fbc_cfb_size(struct drm_i915_private *i915, +static unsigned int intel_fbc_cfb_size(struct intel_fbc *fbc, const struct intel_fbc_state_cache *cache) { + struct drm_i915_private *i915 = fbc->i915; int lines = cache->plane.src_h; if (DISPLAY_VER(i915) == 7) @@ -149,13 +152,13 @@ static unsigned int intel_fbc_cfb_size(struct drm_i915_private *i915, else if (DISPLAY_VER(i915) >= 8) lines = min(lines, 2560); - return lines * intel_fbc_cfb_stride(i915, cache); + return lines * intel_fbc_cfb_stride(fbc, cache); } -static u32 i8xx_fbc_ctl(struct drm_i915_private *i915) +static u32 i8xx_fbc_ctl(struct intel_fbc *fbc) { - struct intel_fbc *fbc = &i915->fbc; const struct intel_fbc_reg_params *params = &fbc->params; + struct drm_i915_private *i915 = fbc->i915; unsigned int cfb_stride; u32 fbc_ctl; @@ -180,9 +183,9 @@ static u32 i8xx_fbc_ctl(struct drm_i915_private *i915) return fbc_ctl; } -static u32 i965_fbc_ctl2(struct drm_i915_private *i915) +static u32 i965_fbc_ctl2(struct intel_fbc *fbc) { - const struct intel_fbc_reg_params *params = &i915->fbc.params; + const struct intel_fbc_reg_params *params = &fbc->params; u32 fbc_ctl2; fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | @@ -194,8 +197,9 @@ static u32 i965_fbc_ctl2(struct drm_i915_private *i915) return fbc_ctl2; } -static void i8xx_fbc_deactivate(struct drm_i915_private *i915) +static void i8xx_fbc_deactivate(struct intel_fbc *fbc) { + struct drm_i915_private *i915 = fbc->i915; u32 fbc_ctl; /* Disable compression */ @@ -214,10 +218,10 @@ static void i8xx_fbc_deactivate(struct drm_i915_private *i915) } } -static void i8xx_fbc_activate(struct drm_i915_private *i915) +static void i8xx_fbc_activate(struct intel_fbc *fbc) { - struct intel_fbc *fbc = &i915->fbc; const struct intel_fbc_reg_params *params = &fbc->params; + struct drm_i915_private *i915 = fbc->i915; int i; /* Clear old tags */ @@ -226,30 +230,31 @@ static void i8xx_fbc_activate(struct drm_i915_private *i915) if (DISPLAY_VER(i915) == 4) { intel_de_write(i915, FBC_CONTROL2, - i965_fbc_ctl2(i915)); + i965_fbc_ctl2(fbc)); intel_de_write(i915, FBC_FENCE_OFF, params->fence_y_offset); } intel_de_write(i915, FBC_CONTROL, - FBC_CTL_EN | i8xx_fbc_ctl(i915)); + FBC_CTL_EN | i8xx_fbc_ctl(fbc)); } -static bool i8xx_fbc_is_active(struct drm_i915_private *i915) +static bool i8xx_fbc_is_active(struct intel_fbc *fbc) { - return intel_de_read(i915, FBC_CONTROL) & FBC_CTL_EN; + return intel_de_read(fbc->i915, FBC_CONTROL) & FBC_CTL_EN; } -static bool i8xx_fbc_is_compressing(struct drm_i915_private *i915) +static bool i8xx_fbc_is_compressing(struct intel_fbc *fbc) { - return intel_de_read(i915, FBC_STATUS) & + return intel_de_read(fbc->i915, FBC_STATUS) & (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED); } -static void i8xx_fbc_nuke(struct drm_i915_private *dev_priv) +static void i8xx_fbc_nuke(struct intel_fbc *fbc) { - struct intel_fbc_reg_params *params = &dev_priv->fbc.params; + struct intel_fbc_reg_params *params = &fbc->params; enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane; + struct drm_i915_private *dev_priv = fbc->i915; spin_lock_irq(&dev_priv->uncore.lock); intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), @@ -257,9 +262,9 @@ static void i8xx_fbc_nuke(struct drm_i915_private *dev_priv) spin_unlock_irq(&dev_priv->uncore.lock); } -static void i8xx_fbc_program_cfb(struct drm_i915_private *i915) +static void i8xx_fbc_program_cfb(struct intel_fbc *fbc) { - struct intel_fbc *fbc = &i915->fbc; + struct drm_i915_private *i915 = fbc->i915; GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start, fbc->compressed_fb.start, U32_MAX)); @@ -281,10 +286,11 @@ static const struct intel_fbc_funcs i8xx_fbc_funcs = { .program_cfb = i8xx_fbc_program_cfb, }; -static void i965_fbc_nuke(struct drm_i915_private *dev_priv) +static void i965_fbc_nuke(struct intel_fbc *fbc) { - struct intel_fbc_reg_params *params = &dev_priv->fbc.params; + struct intel_fbc_reg_params *params = &fbc->params; enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane; + struct drm_i915_private *dev_priv = fbc->i915; spin_lock_irq(&dev_priv->uncore.lock); intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), @@ -301,11 +307,11 @@ static const struct intel_fbc_funcs i965_fbc_funcs = { .program_cfb = i8xx_fbc_program_cfb, }; -static u32 g4x_dpfc_ctl_limit(struct drm_i915_private *i915) +static u32 g4x_dpfc_ctl_limit(struct intel_fbc *fbc) { - switch (i915->fbc.limit) { + switch (fbc->limit) { default: - MISSING_CASE(i915->fbc.limit); + MISSING_CASE(fbc->limit); fallthrough; case 1: return DPFC_CTL_LIMIT_1X; @@ -316,12 +322,13 @@ static u32 g4x_dpfc_ctl_limit(struct drm_i915_private *i915) } } -static u32 g4x_dpfc_ctl(struct drm_i915_private *i915) +static u32 g4x_dpfc_ctl(struct intel_fbc *fbc) { - const struct intel_fbc_reg_params *params = &i915->fbc.params; + const struct intel_fbc_reg_params *params = &fbc->params; + struct drm_i915_private *i915 = fbc->i915; u32 dpfc_ctl; - dpfc_ctl = g4x_dpfc_ctl_limit(i915) | + dpfc_ctl = g4x_dpfc_ctl_limit(fbc) | DPFC_CTL_PLANE_G4X(params->crtc.i9xx_plane); if (IS_G4X(i915)) @@ -337,19 +344,21 @@ static u32 g4x_dpfc_ctl(struct drm_i915_private *i915) return dpfc_ctl; } -static void g4x_fbc_activate(struct drm_i915_private *i915) +static void g4x_fbc_activate(struct intel_fbc *fbc) { - const struct intel_fbc_reg_params *params = &i915->fbc.params; + const struct intel_fbc_reg_params *params = &fbc->params; + struct drm_i915_private *i915 = fbc->i915; intel_de_write(i915, DPFC_FENCE_YOFF, params->fence_y_offset); intel_de_write(i915, DPFC_CONTROL, - DPFC_CTL_EN | g4x_dpfc_ctl(i915)); + DPFC_CTL_EN | g4x_dpfc_ctl(fbc)); } -static void g4x_fbc_deactivate(struct drm_i915_private *i915) +static void g4x_fbc_deactivate(struct intel_fbc *fbc) { + struct drm_i915_private *i915 = fbc->i915; u32 dpfc_ctl; /* Disable compression */ @@ -360,19 +369,19 @@ static void g4x_fbc_deactivate(struct drm_i915_private *i915) } } -static bool g4x_fbc_is_active(struct drm_i915_private *i915) +static bool g4x_fbc_is_active(struct intel_fbc *fbc) { - return intel_de_read(i915, DPFC_CONTROL) & DPFC_CTL_EN; + return intel_de_read(fbc->i915, DPFC_CONTROL) & DPFC_CTL_EN; } -static bool g4x_fbc_is_compressing(struct drm_i915_private *i915) +static bool g4x_fbc_is_compressing(struct intel_fbc *fbc) { - return intel_de_read(i915, DPFC_STATUS) & DPFC_COMP_SEG_MASK; + return intel_de_read(fbc->i915, DPFC_STATUS) & DPFC_COMP_SEG_MASK; } -static void g4x_fbc_program_cfb(struct drm_i915_private *i915) +static void g4x_fbc_program_cfb(struct intel_fbc *fbc) { - struct intel_fbc *fbc = &i915->fbc; + struct drm_i915_private *i915 = fbc->i915; intel_de_write(i915, DPFC_CB_BASE, fbc->compressed_fb.start); } @@ -386,19 +395,21 @@ static const struct intel_fbc_funcs g4x_fbc_funcs = { .program_cfb = g4x_fbc_program_cfb, }; -static void ilk_fbc_activate(struct drm_i915_private *i915) +static void ilk_fbc_activate(struct intel_fbc *fbc) { - struct intel_fbc_reg_params *params = &i915->fbc.params; + struct intel_fbc_reg_params *params = &fbc->params; + struct drm_i915_private *i915 = fbc->i915; intel_de_write(i915, ILK_DPFC_FENCE_YOFF, params->fence_y_offset); intel_de_write(i915, ILK_DPFC_CONTROL, - DPFC_CTL_EN | g4x_dpfc_ctl(i915)); + DPFC_CTL_EN | g4x_dpfc_ctl(fbc)); } -static void ilk_fbc_deactivate(struct drm_i915_private *i915) +static void ilk_fbc_deactivate(struct intel_fbc *fbc) { + struct drm_i915_private *i915 = fbc->i915; u32 dpfc_ctl; /* Disable compression */ @@ -409,19 +420,19 @@ static void ilk_fbc_deactivate(struct drm_i915_private *i915) } } -static bool ilk_fbc_is_active(struct drm_i915_private *i915) +static bool ilk_fbc_is_active(struct intel_fbc *fbc) { - return intel_de_read(i915, ILK_DPFC_CONTROL) & DPFC_CTL_EN; + return intel_de_read(fbc->i915, ILK_DPFC_CONTROL) & DPFC_CTL_EN; } -static bool ilk_fbc_is_compressing(struct drm_i915_private *i915) +static bool ilk_fbc_is_compressing(struct intel_fbc *fbc) { - return intel_de_read(i915, ILK_DPFC_STATUS) & DPFC_COMP_SEG_MASK; + return intel_de_read(fbc->i915, ILK_DPFC_STATUS) & DPFC_COMP_SEG_MASK; } -static void ilk_fbc_program_cfb(struct drm_i915_private *i915) +static void ilk_fbc_program_cfb(struct intel_fbc *fbc) { - struct intel_fbc *fbc = &i915->fbc; + struct drm_i915_private *i915 = fbc->i915; intel_de_write(i915, ILK_DPFC_CB_BASE, fbc->compressed_fb.start); } @@ -435,9 +446,10 @@ static const struct intel_fbc_funcs ilk_fbc_funcs = { .program_cfb = ilk_fbc_program_cfb, }; -static void snb_fbc_program_fence(struct drm_i915_private *i915) +static void snb_fbc_program_fence(struct intel_fbc *fbc) { - const struct intel_fbc_reg_params *params = &i915->fbc.params; + const struct intel_fbc_reg_params *params = &fbc->params; + struct drm_i915_private *i915 = fbc->i915; u32 ctl = 0; if (params->fence_id >= 0) @@ -447,15 +459,17 @@ static void snb_fbc_program_fence(struct drm_i915_private *i915) intel_de_write(i915, SNB_DPFC_CPU_FENCE_OFFSET, params->fence_y_offset); } -static void snb_fbc_activate(struct drm_i915_private *i915) +static void snb_fbc_activate(struct intel_fbc *fbc) { - snb_fbc_program_fence(i915); + snb_fbc_program_fence(fbc); - ilk_fbc_activate(i915); + ilk_fbc_activate(fbc); } -static void snb_fbc_nuke(struct drm_i915_private *i915) +static void snb_fbc_nuke(struct intel_fbc *fbc) { + struct drm_i915_private *i915 = fbc->i915; + intel_de_write(i915, MSG_FBC_REND_STATE, FBC_REND_NUKE); intel_de_posting_read(i915, MSG_FBC_REND_STATE); } @@ -469,10 +483,10 @@ static const struct intel_fbc_funcs snb_fbc_funcs = { .program_cfb = ilk_fbc_program_cfb, }; -static void glk_fbc_program_cfb_stride(struct drm_i915_private *i915) +static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc) { - struct intel_fbc *fbc = &i915->fbc; const struct intel_fbc_reg_params *params = &fbc->params; + struct drm_i915_private *i915 = fbc->i915; u32 val = 0; if (params->override_cfb_stride) @@ -482,10 +496,10 @@ static void glk_fbc_program_cfb_stride(struct drm_i915_private *i915) intel_de_write(i915, GLK_FBC_STRIDE, val); } -static void skl_fbc_program_cfb_stride(struct drm_i915_private *i915) +static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc) { - struct intel_fbc *fbc = &i915->fbc; const struct intel_fbc_reg_params *params = &fbc->params; + struct drm_i915_private *i915 = fbc->i915; u32 val = 0; /* Display WA #0529: skl, kbl, bxt. */ @@ -498,12 +512,13 @@ static void skl_fbc_program_cfb_stride(struct drm_i915_private *i915) CHICKEN_FBC_STRIDE_MASK, val); } -static u32 ivb_dpfc_ctl(struct drm_i915_private *i915) +static u32 ivb_dpfc_ctl(struct intel_fbc *fbc) { - const struct intel_fbc_reg_params *params = &i915->fbc.params; + const struct intel_fbc_reg_params *params = &fbc->params; + struct drm_i915_private *i915 = fbc->i915; u32 dpfc_ctl; - dpfc_ctl = g4x_dpfc_ctl_limit(i915); + dpfc_ctl = g4x_dpfc_ctl_limit(fbc); if (IS_IVYBRIDGE(i915)) dpfc_ctl |= DPFC_CTL_PLANE_IVB(params->crtc.i9xx_plane); @@ -511,35 +526,37 @@ static u32 ivb_dpfc_ctl(struct drm_i915_private *i915) if (params->fence_id >= 0) dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB; - if (i915->fbc.false_color) + if (fbc->false_color) dpfc_ctl |= DPFC_CTL_FALSE_COLOR; return dpfc_ctl; } -static void ivb_fbc_activate(struct drm_i915_private *i915) +static void ivb_fbc_activate(struct intel_fbc *fbc) { + struct drm_i915_private *i915 = fbc->i915; + if (DISPLAY_VER(i915) >= 10) - glk_fbc_program_cfb_stride(i915); + glk_fbc_program_cfb_stride(fbc); else if (DISPLAY_VER(i915) == 9) - skl_fbc_program_cfb_stride(i915); + skl_fbc_program_cfb_stride(fbc); if (i915->ggtt.num_fences) - snb_fbc_program_fence(i915); + snb_fbc_program_fence(fbc); intel_de_write(i915, ILK_DPFC_CONTROL, - DPFC_CTL_EN | ivb_dpfc_ctl(i915)); + DPFC_CTL_EN | ivb_dpfc_ctl(fbc)); } -static bool ivb_fbc_is_compressing(struct drm_i915_private *i915) +static bool ivb_fbc_is_compressing(struct intel_fbc *fbc) { - return intel_de_read(i915, ILK_DPFC_STATUS2) & DPFC_COMP_SEG_MASK_IVB; + return intel_de_read(fbc->i915, ILK_DPFC_STATUS2) & DPFC_COMP_SEG_MASK_IVB; } -static void ivb_fbc_set_false_color(struct drm_i915_private *i915, +static void ivb_fbc_set_false_color(struct intel_fbc *fbc, bool enable) { - intel_de_rmw(i915, ILK_DPFC_CONTROL, + intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL, DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0); } @@ -553,56 +570,44 @@ static const struct intel_fbc_funcs ivb_fbc_funcs = { .set_false_color = ivb_fbc_set_false_color, }; -static bool intel_fbc_hw_is_active(struct drm_i915_private *i915) +static bool intel_fbc_hw_is_active(struct intel_fbc *fbc) { - struct intel_fbc *fbc = &i915->fbc; - - return fbc->funcs->is_active(i915); + return fbc->funcs->is_active(fbc); } -static void intel_fbc_hw_activate(struct drm_i915_private *i915) +static void intel_fbc_hw_activate(struct intel_fbc *fbc) { - struct intel_fbc *fbc = &i915->fbc; - trace_intel_fbc_activate(fbc->crtc); fbc->active = true; fbc->activated = true; - fbc->funcs->activate(i915); + fbc->funcs->activate(fbc); } -static void intel_fbc_hw_deactivate(struct drm_i915_private *i915) +static void intel_fbc_hw_deactivate(struct intel_fbc *fbc) { - struct intel_fbc *fbc = &i915->fbc; - trace_intel_fbc_deactivate(fbc->crtc); fbc->active = false; - fbc->funcs->deactivate(i915); + fbc->funcs->deactivate(fbc); } -bool intel_fbc_is_compressing(struct drm_i915_private *i915) +bool intel_fbc_is_compressing(struct intel_fbc *fbc) { - struct intel_fbc *fbc = &i915->fbc; - - return fbc->funcs->is_compressing(i915); + return fbc->funcs->is_compressing(fbc); } -static void intel_fbc_nuke(struct drm_i915_private *i915) +static void intel_fbc_nuke(struct intel_fbc *fbc) { - struct intel_fbc *fbc = &i915->fbc; - trace_intel_fbc_nuke(fbc->crtc); - fbc->funcs->nuke(i915); + fbc->funcs->nuke(fbc); } -int intel_fbc_set_false_color(struct drm_i915_private *i915, bool enable) +int intel_fbc_set_false_color(struct intel_fbc *fbc, bool enable) { - struct intel_fbc *fbc = &i915->fbc; - if (!fbc->funcs || !fbc->funcs->set_false_color) return -ENODEV; @@ -610,7 +615,7 @@ int intel_fbc_set_false_color(struct drm_i915_private *i915, bool enable) fbc->false_color = enable; - fbc->funcs->set_false_color(i915, enable); + fbc->funcs->set_false_color(fbc, enable); mutex_unlock(&fbc->lock); @@ -626,26 +631,25 @@ int intel_fbc_set_false_color(struct drm_i915_private *i915, bool enable) * FIXME: This should be tracked in the plane config eventually * instead of queried at runtime for most callers. */ -bool intel_fbc_is_active(struct drm_i915_private *i915) +bool intel_fbc_is_active(struct intel_fbc *fbc) { - return i915->fbc.active; + return fbc->active; } -static void intel_fbc_activate(struct drm_i915_private *i915) +static void intel_fbc_activate(struct intel_fbc *fbc) { - intel_fbc_hw_activate(i915); - intel_fbc_nuke(i915); + intel_fbc_hw_activate(fbc); + intel_fbc_nuke(fbc); } -static void intel_fbc_deactivate(struct drm_i915_private *i915, - const char *reason) +static void intel_fbc_deactivate(struct intel_fbc *fbc, const char *reason) { - struct intel_fbc *fbc = &i915->fbc; + struct drm_i915_private *i915 = fbc->i915; drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock)); if (fbc->active) - intel_fbc_hw_deactivate(i915); + intel_fbc_hw_deactivate(fbc); fbc->no_fbc_reason = reason; } @@ -693,10 +697,10 @@ static int intel_fbc_max_limit(struct drm_i915_private *i915) return 4; } -static int find_compression_limit(struct drm_i915_private *i915, +static int find_compression_limit(struct intel_fbc *fbc, unsigned int size, int min_limit) { - struct intel_fbc *fbc = &i915->fbc; + struct drm_i915_private *i915 = fbc->i915; u64 end = intel_fbc_stolen_end(i915); int ret, limit = min_limit; @@ -718,10 +722,10 @@ static int find_compression_limit(struct drm_i915_private *i915, return 0; } -static int intel_fbc_alloc_cfb(struct drm_i915_private *i915, +static int intel_fbc_alloc_cfb(struct intel_fbc *fbc, unsigned int size, int min_limit) { - struct intel_fbc *fbc = &i915->fbc; + struct drm_i915_private *i915 = fbc->i915; int ret; drm_WARN_ON(&i915->drm, @@ -736,7 +740,7 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private *i915, goto err; } - ret = find_compression_limit(i915, size, min_limit); + ret = find_compression_limit(fbc, size, min_limit); if (!ret) goto err_llb; else if (ret > min_limit) @@ -760,18 +764,16 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private *i915, return -ENOSPC; } -static void intel_fbc_program_cfb(struct drm_i915_private *i915) +static void intel_fbc_program_cfb(struct intel_fbc *fbc) { - struct intel_fbc *fbc = &i915->fbc; - - fbc->funcs->program_cfb(i915); + fbc->funcs->program_cfb(fbc); } -static void __intel_fbc_cleanup_cfb(struct drm_i915_private *i915) +static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc) { - struct intel_fbc *fbc = &i915->fbc; + struct drm_i915_private *i915 = fbc->i915; - if (WARN_ON(intel_fbc_hw_is_active(i915))) + if (WARN_ON(intel_fbc_hw_is_active(fbc))) return; if (drm_mm_node_allocated(&fbc->compressed_llb)) @@ -780,7 +782,7 @@ static void __intel_fbc_cleanup_cfb(struct drm_i915_private *i915) i915_gem_stolen_remove_node(i915, &fbc->compressed_fb); } -void intel_fbc_cleanup_cfb(struct drm_i915_private *i915) +void intel_fbc_cleanup(struct drm_i915_private *i915) { struct intel_fbc *fbc = &i915->fbc; @@ -788,7 +790,7 @@ void intel_fbc_cleanup_cfb(struct drm_i915_private *i915) return; mutex_lock(&fbc->lock); - __intel_fbc_cleanup_cfb(i915); + __intel_fbc_cleanup_cfb(fbc); mutex_unlock(&fbc->lock); } @@ -860,10 +862,10 @@ static bool rotation_is_valid(struct drm_i915_private *i915, * the X and Y offset registers. That's why we include the src x/y offsets * instead of just looking at the plane size. */ -static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) +static bool intel_fbc_hw_tracking_covers_screen(struct intel_fbc *fbc, + struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); - struct intel_fbc *fbc = &i915->fbc; + struct drm_i915_private *i915 = fbc->i915; unsigned int effective_w, effective_h, max_w, max_h; if (DISPLAY_VER(i915) >= 10) { @@ -954,19 +956,17 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, cache->psr2_active = crtc_state->has_psr2; } -static bool intel_fbc_cfb_size_changed(struct drm_i915_private *i915) +static bool intel_fbc_cfb_size_changed(struct intel_fbc *fbc) { - struct intel_fbc *fbc = &i915->fbc; - - return intel_fbc_cfb_size(i915, &fbc->state_cache) > + return intel_fbc_cfb_size(fbc, &fbc->state_cache) > fbc->compressed_fb.size * fbc->limit; } -static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *i915, +static u16 intel_fbc_override_cfb_stride(struct intel_fbc *fbc, const struct intel_fbc_state_cache *cache) { unsigned int stride = _intel_fbc_cfb_stride(cache); - unsigned int stride_aligned = intel_fbc_cfb_stride(i915, cache); + unsigned int stride_aligned = intel_fbc_cfb_stride(fbc, cache); /* * Override stride in 64 byte units per 4 line segment. @@ -976,16 +976,16 @@ static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *i915, * we always need to use the override there. */ if (stride != stride_aligned || - (DISPLAY_VER(i915) == 9 && + (DISPLAY_VER(fbc->i915) == 9 && cache->fb.modifier == DRM_FORMAT_MOD_LINEAR)) return stride_aligned * 4 / 64; return 0; } -static bool intel_fbc_can_enable(struct drm_i915_private *i915) +static bool intel_fbc_can_enable(struct intel_fbc *fbc) { - struct intel_fbc *fbc = &i915->fbc; + struct drm_i915_private *i915 = fbc->i915; if (intel_vgpu_active(i915)) { fbc->no_fbc_reason = "VGPU is active"; @@ -1011,7 +1011,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) struct intel_fbc *fbc = &i915->fbc; struct intel_fbc_state_cache *cache = &fbc->state_cache; - if (!intel_fbc_can_enable(i915)) + if (!intel_fbc_can_enable(fbc)) return false; if (!cache->plane.visible) { @@ -1032,7 +1032,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) return false; } - if (!intel_fbc_hw_tracking_covers_screen(crtc)) { + if (!intel_fbc_hw_tracking_covers_screen(fbc, crtc)) { fbc->no_fbc_reason = "mode too large for compression"; return false; } @@ -1104,7 +1104,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) * we didn't get any invalidate/deactivate calls, but this would require * a lot of tracking just for a specific case. If we conclude it's an * important case, we can implement it later. */ - if (intel_fbc_cfb_size_changed(i915)) { + if (intel_fbc_cfb_size_changed(fbc)) { fbc->no_fbc_reason = "CFB requirements changed"; return false; } @@ -1140,12 +1140,11 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) return true; } -static void intel_fbc_get_reg_params(struct intel_crtc *crtc, - struct intel_fbc_reg_params *params) +static void intel_fbc_get_reg_params(struct intel_fbc *fbc, + struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); - struct intel_fbc *fbc = &i915->fbc; - struct intel_fbc_state_cache *cache = &fbc->state_cache; + const struct intel_fbc_state_cache *cache = &fbc->state_cache; + struct intel_fbc_reg_params *params = &fbc->params; /* Since all our fields are integer types, use memset here so the * comparison function can rely on memcmp because the padding will be @@ -1164,9 +1163,9 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc, params->fb.modifier = cache->fb.modifier; params->fb.stride = cache->fb.stride; - params->cfb_stride = intel_fbc_cfb_stride(i915, cache); - params->cfb_size = intel_fbc_cfb_size(i915, cache); - params->override_cfb_stride = intel_fbc_override_cfb_stride(i915, cache); + params->cfb_stride = intel_fbc_cfb_stride(fbc, cache); + params->cfb_size = intel_fbc_cfb_size(fbc, cache); + params->override_cfb_stride = intel_fbc_override_cfb_stride(fbc, cache); params->plane_visible = cache->plane.visible; } @@ -1175,7 +1174,7 @@ static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); - const struct intel_fbc *fbc = &i915->fbc; + struct intel_fbc *fbc = &i915->fbc; const struct intel_fbc_state_cache *cache = &fbc->state_cache; const struct intel_fbc_reg_params *params = &fbc->params; @@ -1197,13 +1196,13 @@ static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state) if (params->fb.stride != cache->fb.stride) return false; - if (params->cfb_stride != intel_fbc_cfb_stride(i915, cache)) + if (params->cfb_stride != intel_fbc_cfb_stride(fbc, cache)) return false; - if (params->cfb_size != intel_fbc_cfb_size(i915, cache)) + if (params->cfb_size != intel_fbc_cfb_size(fbc, cache)) return false; - if (params->override_cfb_stride != intel_fbc_override_cfb_stride(i915, cache)) + if (params->override_cfb_stride != intel_fbc_override_cfb_stride(fbc, cache)) return false; return true; @@ -1234,7 +1233,7 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state, fbc->flip_pending = true; if (!intel_fbc_can_flip_nuke(crtc_state)) { - intel_fbc_deactivate(i915, reason); + intel_fbc_deactivate(fbc, reason); /* * Display WA #1198: glk+ @@ -1260,16 +1259,9 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state, return need_vblank_wait; } -/** - * __intel_fbc_disable - disable FBC - * @i915: i915 device instance - * - * This is the low level function that actually disables FBC. Callers should - * grab the FBC lock. - */ -static void __intel_fbc_disable(struct drm_i915_private *i915) +static void __intel_fbc_disable(struct intel_fbc *fbc) { - struct intel_fbc *fbc = &i915->fbc; + struct drm_i915_private *i915 = fbc->i915; struct intel_crtc *crtc = fbc->crtc; drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock)); @@ -1279,7 +1271,7 @@ static void __intel_fbc_disable(struct drm_i915_private *i915) drm_dbg_kms(&i915->drm, "Disabling FBC on pipe %c\n", pipe_name(crtc->pipe)); - __intel_fbc_cleanup_cfb(i915); + __intel_fbc_cleanup_cfb(fbc); fbc->crtc = NULL; } @@ -1297,21 +1289,21 @@ static void __intel_fbc_post_update(struct intel_crtc *crtc) fbc->flip_pending = false; if (!i915->params.enable_fbc) { - intel_fbc_deactivate(i915, "disabled at runtime per module param"); - __intel_fbc_disable(i915); + intel_fbc_deactivate(fbc, "disabled at runtime per module param"); + __intel_fbc_disable(fbc); return; } - intel_fbc_get_reg_params(crtc, &fbc->params); + intel_fbc_get_reg_params(fbc, crtc); if (!intel_fbc_can_activate(crtc)) return; if (!fbc->busy_bits) - intel_fbc_activate(i915); + intel_fbc_activate(fbc); else - intel_fbc_deactivate(i915, "frontbuffer write"); + intel_fbc_deactivate(fbc, "frontbuffer write"); } void intel_fbc_post_update(struct intel_atomic_state *state, @@ -1356,7 +1348,7 @@ void intel_fbc_invalidate(struct drm_i915_private *i915, fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits; if (fbc->crtc && fbc->busy_bits) - intel_fbc_deactivate(i915, "frontbuffer write"); + intel_fbc_deactivate(fbc, "frontbuffer write"); mutex_unlock(&fbc->lock); } @@ -1379,7 +1371,7 @@ void intel_fbc_flush(struct drm_i915_private *i915, if (!fbc->busy_bits && fbc->crtc && (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) { if (fbc->active) - intel_fbc_nuke(i915); + intel_fbc_nuke(fbc); else if (!fbc->flip_pending) __intel_fbc_post_update(fbc->crtc); } @@ -1416,7 +1408,7 @@ void intel_fbc_choose_crtc(struct drm_i915_private *i915, !intel_atomic_get_new_crtc_state(state, fbc->crtc)) goto out; - if (!intel_fbc_can_enable(i915)) + if (!intel_fbc_can_enable(fbc)) goto out; /* Simply choose the first CRTC that is compatible and has a visible @@ -1483,10 +1475,10 @@ static void intel_fbc_enable(struct intel_atomic_state *state, goto out; if (fbc->limit >= min_limit && - !intel_fbc_cfb_size_changed(i915)) + !intel_fbc_cfb_size_changed(fbc)) goto out; - __intel_fbc_disable(i915); + __intel_fbc_disable(fbc); } drm_WARN_ON(&i915->drm, fbc->active); @@ -1497,8 +1489,7 @@ static void intel_fbc_enable(struct intel_atomic_state *state, if (!cache->plane.visible) goto out; - if (intel_fbc_alloc_cfb(i915, - intel_fbc_cfb_size(i915, cache), min_limit)) { + if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(fbc, cache), min_limit)) { cache->plane.visible = false; fbc->no_fbc_reason = "not enough stolen memory"; goto out; @@ -1510,7 +1501,7 @@ static void intel_fbc_enable(struct intel_atomic_state *state, fbc->crtc = crtc; - intel_fbc_program_cfb(i915); + intel_fbc_program_cfb(fbc); out: mutex_unlock(&fbc->lock); } @@ -1532,7 +1523,7 @@ void intel_fbc_disable(struct intel_crtc *crtc) mutex_lock(&fbc->lock); if (fbc->crtc == crtc) - __intel_fbc_disable(i915); + __intel_fbc_disable(fbc); mutex_unlock(&fbc->lock); } @@ -1574,7 +1565,7 @@ void intel_fbc_global_disable(struct drm_i915_private *i915) mutex_lock(&fbc->lock); if (fbc->crtc) { drm_WARN_ON(&i915->drm, fbc->crtc->active); - __intel_fbc_disable(i915); + __intel_fbc_disable(fbc); } mutex_unlock(&fbc->lock); } @@ -1594,7 +1585,7 @@ static void intel_fbc_underrun_work_fn(struct work_struct *work) drm_dbg_kms(&i915->drm, "Disabling FBC due to FIFO underrun.\n"); fbc->underrun_detected = true; - intel_fbc_deactivate(i915, "FIFO underrun"); + intel_fbc_deactivate(fbc, "FIFO underrun"); out: mutex_unlock(&fbc->lock); } @@ -1606,24 +1597,25 @@ static void intel_fbc_underrun_work_fn(struct work_struct *work) * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we * want to re-enable FBC after an underrun to increase test coverage. */ -int intel_fbc_reset_underrun(struct drm_i915_private *i915) +int intel_fbc_reset_underrun(struct intel_fbc *fbc) { + struct drm_i915_private *i915 = fbc->i915; int ret; - cancel_work_sync(&i915->fbc.underrun_work); + cancel_work_sync(&fbc->underrun_work); - ret = mutex_lock_interruptible(&i915->fbc.lock); + ret = mutex_lock_interruptible(&fbc->lock); if (ret) return ret; - if (i915->fbc.underrun_detected) { + if (fbc->underrun_detected) { drm_dbg_kms(&i915->drm, "Re-allowing FBC after fifo underrun\n"); - i915->fbc.no_fbc_reason = "FIFO underrun cleared"; + fbc->no_fbc_reason = "FIFO underrun cleared"; } - i915->fbc.underrun_detected = false; - mutex_unlock(&i915->fbc.lock); + fbc->underrun_detected = false; + mutex_unlock(&fbc->lock); return 0; } @@ -1642,11 +1634,9 @@ int intel_fbc_reset_underrun(struct drm_i915_private *i915) * * This function is called from the IRQ handler. */ -void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915) +void intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc) { - struct intel_fbc *fbc = &i915->fbc; - - if (!HAS_FBC(i915)) + if (!HAS_FBC(fbc->i915)) return; /* There's no guarantee that underrun_detected won't be set to true @@ -1707,6 +1697,7 @@ void intel_fbc_init(struct drm_i915_private *i915) { struct intel_fbc *fbc = &i915->fbc; + fbc->i915 = i915; INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn); mutex_init(&fbc->lock); fbc->active = false; @@ -1742,6 +1733,6 @@ void intel_fbc_init(struct drm_i915_private *i915) /* We still don't have any sort of hardware state readout for FBC, so * deactivate it in case the BIOS activated it to make sure software * matches the hardware state. */ - if (intel_fbc_hw_is_active(i915)) - intel_fbc_hw_deactivate(i915); + if (intel_fbc_hw_is_active(fbc)) + intel_fbc_hw_deactivate(fbc); } diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h index 4d1f2a76ccb4..ce48a22c5e9e 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.h +++ b/drivers/gpu/drm/i915/display/intel_fbc.h @@ -14,17 +14,19 @@ struct drm_i915_private; struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; +struct intel_fbc; struct intel_plane_state; void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, struct intel_atomic_state *state); -bool intel_fbc_is_active(struct drm_i915_private *dev_priv); -bool intel_fbc_is_compressing(struct drm_i915_private *dev_priv); +bool intel_fbc_is_active(struct intel_fbc *fbc); +bool intel_fbc_is_compressing(struct intel_fbc *fbc); bool intel_fbc_pre_update(struct intel_atomic_state *state, struct intel_crtc *crtc); void intel_fbc_post_update(struct intel_atomic_state *state, struct intel_crtc *crtc); void intel_fbc_init(struct drm_i915_private *dev_priv); +void intel_fbc_cleanup(struct drm_i915_private *dev_priv); void intel_fbc_update(struct intel_atomic_state *state, struct intel_crtc *crtc); void intel_fbc_disable(struct intel_crtc *crtc); @@ -34,10 +36,8 @@ void intel_fbc_invalidate(struct drm_i915_private *dev_priv, enum fb_op_origin origin); void intel_fbc_flush(struct drm_i915_private *dev_priv, unsigned int frontbuffer_bits, enum fb_op_origin origin); -void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv); -void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv); -int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv); -int intel_fbc_set_false_color(struct drm_i915_private *i915, - bool enable); +void intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc); +int intel_fbc_reset_underrun(struct intel_fbc *fbc); +int intel_fbc_set_false_color(struct intel_fbc *fbc, bool enable); #endif /* __INTEL_FBC_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c index eb841960840d..28d9eeb7b4f3 100644 --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c @@ -434,7 +434,7 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe)); } - intel_fbc_handle_fifo_underrun_irq(dev_priv); + intel_fbc_handle_fifo_underrun_irq(&dev_priv->fbc); } /** diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e5d57c2a8506..c8a06dc28db6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -414,6 +414,7 @@ struct intel_fbc_funcs; #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ struct intel_fbc { + struct drm_i915_private *i915; const struct intel_fbc_funcs *funcs; /* This is always the inner lock when overlapping with struct_mutex and diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a64f3b195448..b3d4710c6b25 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3375,7 +3375,7 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv, * enabled sometime later. */ if (DISPLAY_VER(dev_priv) == 5 && !merged->fbc_wm_enabled && - intel_fbc_is_active(dev_priv)) { + intel_fbc_is_active(&dev_priv->fbc)) { for (level = 2; level <= max_level; level++) { struct intel_wm_level *wm = &merged->wm[level]; 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Thu, 4 Nov 2021 14:46:15 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id EA99489FCC for ; Thu, 4 Nov 2021 14:46:13 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10157"; a="212463269" X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="212463269" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2021 07:46:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,209,1631602800"; d="scan'208";a="468484943" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga002.jf.intel.com with SMTP; 04 Nov 2021 07:46:11 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 04 Nov 2021 16:46:10 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Nov 2021 16:45:20 +0200 Message-Id: <20211104144520.22605-18-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211104144520.22605-1-ville.syrjala@linux.intel.com> References: <20211104144520.22605-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 17/17] drm/1915/fbc: Replace plane->has_fbc with a pointer to the fbc instance X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä With multiple fbc instances we need to find the right one for each plane. Rather than going looking for the right instance every time let's just replace the has_fbc boolean with a pointer that gets us there straight away. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/i9xx_plane.c | 10 ++++---- drivers/gpu/drm/i915/display/intel_display.c | 2 +- .../drm/i915/display/intel_display_types.h | 4 +++- drivers/gpu/drm/i915/display/intel_fbc.c | 24 +++++++++---------- .../drm/i915/display/skl_universal_plane.c | 10 ++++---- 5 files changed, 24 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index c8722771aa40..8a59fd0fd2ca 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -774,12 +774,10 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) plane->id = PLANE_PRIMARY; plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); - plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane); - if (plane->has_fbc) { - struct intel_fbc *fbc = &dev_priv->fbc; - - fbc->possible_framebuffer_bits |= plane->frontbuffer_bit; - } + if (i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane)) + plane->fbc = &dev_priv->fbc; + if (plane->fbc) + plane->fbc->possible_framebuffer_bits |= plane->frontbuffer_bit; if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { formats = vlv_primary_formats; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 3be82f075655..8118e65ec732 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -645,7 +645,7 @@ bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) struct drm_i915_private *dev_priv = to_i915(plane->base.dev); return DISPLAY_VER(dev_priv) < 4 || - (plane->has_fbc && + (plane->fbc && plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL); } diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index a174b0b83640..aa759999aac9 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -49,6 +49,7 @@ struct drm_printer; struct __intel_global_objs_state; struct intel_ddi_buf_trans; +struct intel_fbc; /* * Display related stuff @@ -1331,7 +1332,6 @@ struct intel_plane { enum i9xx_plane_id i9xx_plane; enum plane_id id; enum pipe pipe; - bool has_fbc; bool need_async_flip_disable_wa; u32 frontbuffer_bit; @@ -1339,6 +1339,8 @@ struct intel_plane { u32 base, cntl, size; } cursor; + struct intel_fbc *fbc; + /* * NOTE: Do not place new plane state fields here (e.g., when adding * new plane properties). New runtime state should now be placed in diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index e8235d55e76a..a7e0f79ceb63 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1217,11 +1217,11 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state, const struct intel_plane_state *plane_state = intel_atomic_get_new_plane_state(state, plane); struct drm_i915_private *i915 = to_i915(crtc->base.dev); - struct intel_fbc *fbc = &i915->fbc; + struct intel_fbc *fbc = plane->fbc; const char *reason = "update pending"; bool need_vblank_wait = false; - if (!plane->has_fbc || !plane_state) + if (!fbc || !plane_state) return need_vblank_wait; mutex_lock(&fbc->lock); @@ -1309,13 +1309,12 @@ static void __intel_fbc_post_update(struct intel_crtc *crtc) void intel_fbc_post_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_plane *plane = to_intel_plane(crtc->base.primary); const struct intel_plane_state *plane_state = intel_atomic_get_new_plane_state(state, plane); - struct intel_fbc *fbc = &i915->fbc; + struct intel_fbc *fbc = plane->fbc; - if (!plane->has_fbc || !plane_state) + if (!fbc || !plane_state) return; mutex_lock(&fbc->lock); @@ -1419,7 +1418,7 @@ void intel_fbc_choose_crtc(struct drm_i915_private *i915, struct intel_crtc_state *crtc_state; struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc); - if (!plane->has_fbc) + if (plane->fbc != fbc) continue; if (!plane_state->uapi.visible) @@ -1458,13 +1457,15 @@ static void intel_fbc_enable(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); const struct intel_plane_state *plane_state = intel_atomic_get_new_plane_state(state, plane); - struct intel_fbc *fbc = &i915->fbc; - struct intel_fbc_state_cache *cache = &fbc->state_cache; + struct intel_fbc *fbc = plane->fbc; + struct intel_fbc_state_cache *cache; int min_limit; - if (!plane->has_fbc || !plane_state) + if (!fbc || !plane_state) return; + cache = &fbc->state_cache; + min_limit = intel_fbc_min_limit(plane_state->hw.fb ? plane_state->hw.fb->format->cpp[0] : 0); @@ -1514,11 +1515,10 @@ static void intel_fbc_enable(struct intel_atomic_state *state, */ void intel_fbc_disable(struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_plane *plane = to_intel_plane(crtc->base.primary); - struct intel_fbc *fbc = &i915->fbc; + struct intel_fbc *fbc = plane->fbc; - if (!plane->has_fbc) + if (!fbc) return; mutex_lock(&fbc->lock); diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 91a79b1582c9..077a96c150d1 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2060,12 +2060,10 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->id = plane_id; plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id); - plane->has_fbc = skl_plane_has_fbc(dev_priv, pipe, plane_id); - if (plane->has_fbc) { - struct intel_fbc *fbc = &dev_priv->fbc; - - fbc->possible_framebuffer_bits |= plane->frontbuffer_bit; - } + if (skl_plane_has_fbc(dev_priv, pipe, plane_id)) + plane->fbc = &dev_priv->fbc; + if (plane->fbc) + plane->fbc->possible_framebuffer_bits |= plane->frontbuffer_bit; if (DISPLAY_VER(dev_priv) >= 11) { plane->min_width = icl_plane_min_width;