From patchwork Sun Nov 7 07:41:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12606713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5BE3C433FE for ; Sun, 7 Nov 2021 07:42:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CA41561425 for ; Sun, 7 Nov 2021 07:42:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234272AbhKGHot (ORCPT ); Sun, 7 Nov 2021 02:44:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234954AbhKGHor (ORCPT ); Sun, 7 Nov 2021 02:44:47 -0500 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44F33C061570; Sun, 7 Nov 2021 00:42:05 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id 133so10552677wme.0; Sun, 07 Nov 2021 00:42:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DToYAQHxf/EmU+9Qq/Jcp+BO8Gdd2Z8qCSR2az0OK88=; b=BjfScZc2zd9quVMZa3wEMSuXvKSHCRVVK90d9WoR/lxdnL61F2JY8RUh3j+indP+Sm jabTf1Ko+plMv+i+XSVBRkZ/fxXC4sKcSk8gInzMywSoCwOHtjO7vl0U8vNfLckn8qqZ r6MWdhnokaBciA8/99w/05kaKi9qPJwKvHj8qn6CBIx2FJQv6c665DKAJB6Y3Ng9BrMJ V1MSjpHTBCcg4ZXD3NyJF37aFJsyuYwQo1Ys+PKgYbQKNcEisP19NTofNVUV3Nxmj2+q SzrfTw0/LfAZuLhBvcnsBr1EMFDeyD7QKZ8akSQZyD0mGV61SM84pgobsqMsme3kPwiR BgrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DToYAQHxf/EmU+9Qq/Jcp+BO8Gdd2Z8qCSR2az0OK88=; b=MrsPzJkZvKMD8isgrx95t+YHpAtMlVXaga0iPOB9MRKpP0kocJDBaqhPKwXiP8IlH4 9+RCKbiXBx2iFAiYLer7sr+CsHqUdzXqpvRTKgy1TUzN2uWfqq9pZ8KhWKgmE3SpEnZy w4AD0bD5AQCoKICjk/4NrGAUblpqzxa3nE5geAJwobJyD+SRxkJSdw9PiLG58WgyGo// GjuT6hF6iLdOAsz067S5H0iNwR+bszACh1Uyz5wrJPi9wDO4fwWLs3cGMMZ3HpmToXel u6kZHlCu6GkopFsUpRcfSqnU2FRARm1696t7T8F+jyXHbL2HsQvToOia4qQm76H8cWao rEyA== X-Gm-Message-State: AOAM5319dijDB7AgtbiKqq1kg3N2gE6COoI4Xvlu8mHiP72KZv8X5AVz WR5U+/PiCiA33Kh7AkRnwEMSzHThY6Mmkg== X-Google-Smtp-Source: ABdhPJyvO3YtYJdhN5L0k0z4aFFIWsLR3XjcqqsSZ3lDac28EUXR5wX8KDVxFh2AUl/Ki9KDV2UexQ== X-Received: by 2002:a05:600c:a55:: with SMTP id c21mr43630210wmq.191.1636270923574; Sun, 07 Nov 2021 00:42:03 -0700 (PDT) Received: from localhost.localdomain (252.red-83-54-181.dynamicip.rima-tde.net. [83.54.181.252]) by smtp.gmail.com with ESMTPSA id e12sm15353352wrq.20.2021.11.07.00.42.02 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Nov 2021 00:42:03 -0700 (PDT) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org, sboyd@kernel.org, john@phrozen.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, Rob Herring Subject: [PATCH v5 1/4] dt-bindings: reset: add dt binding header for Mediatek MT7621 resets Date: Sun, 7 Nov 2021 08:41:57 +0100 Message-Id: <20211107074200.18911-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211107074200.18911-1-sergio.paracuellos@gmail.com> References: <20211107074200.18911-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add dt binding header for resets lines in Mediatek MT7621 SoCs. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/reset/mt7621-reset.h | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 include/dt-bindings/reset/mt7621-reset.h diff --git a/include/dt-bindings/reset/mt7621-reset.h b/include/dt-bindings/reset/mt7621-reset.h new file mode 100644 index 000000000000..7572c6b41453 --- /dev/null +++ b/include/dt-bindings/reset/mt7621-reset.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 Sergio Paracuellos + * Author: Sergio Paracuellos + */ + +#ifndef DT_BINDING_MT7621_RESET_H +#define DT_BINDING_MT7621_RESET_H + +#define MT7621_RST_SYS 0 +#define MT7621_RST_MCM 2 +#define MT7621_RST_HSDMA 5 +#define MT7621_RST_FE 6 +#define MT7621_RST_SPDIFTX 7 +#define MT7621_RST_TIMER 8 +#define MT7621_RST_INT 9 +#define MT7621_RST_MC 10 +#define MT7621_RST_PCM 11 +#define MT7621_RST_PIO 13 +#define MT7621_RST_GDMA 14 +#define MT7621_RST_NFI 15 +#define MT7621_RST_I2C 16 +#define MT7621_RST_I2S 17 +#define MT7621_RST_SPI 18 +#define MT7621_RST_UART1 19 +#define MT7621_RST_UART2 20 +#define MT7621_RST_UART3 21 +#define MT7621_RST_ETH 23 +#define MT7621_RST_PCIE0 24 +#define MT7621_RST_PCIE1 25 +#define MT7621_RST_PCIE2 26 +#define MT7621_RST_AUX_STCK 28 +#define MT7621_RST_CRYPTO 29 +#define MT7621_RST_SDXC 30 +#define MT7621_RST_PPE 31 + +#endif /* DT_BINDING_MT7621_RESET_H */ From patchwork Sun Nov 7 07:41:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12606715 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B2B8C433EF for ; Sun, 7 Nov 2021 07:42:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E296261452 for ; Sun, 7 Nov 2021 07:42:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235042AbhKGHot (ORCPT ); Sun, 7 Nov 2021 02:44:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235004AbhKGHos (ORCPT ); Sun, 7 Nov 2021 02:44:48 -0500 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F2FCC061570; Sun, 7 Nov 2021 00:42:06 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id 71so10491958wma.4; Sun, 07 Nov 2021 00:42:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OJp/wZiERGVBUU7HIuspGPpojRpXm2e3BfdSR6ZgDTc=; b=PP0yCHrPUsuBD3zKIXVoPdLYQJwcdFQrEACEv/HmWaSTnmRGe8xw3bBQFxKu0b7bVM NwhbsiTtmfhpQJqjjSeCdRpQVyFv3hXUgFIjkmrhqfuHGEOQcVT4IxYA1TN087pJjcve /bGSpiYgYrnscBv8HLgh8fa5tk7/7cOWIc0dKwm+ebIRp/h4+22jDt9O2SD+RjmYAOu2 ygI/iD9fBxr/YIpx8zDtbmdJ/861DXBC5wFg7kWcUYeL4SUOHbqQPnZ5ZZkN3oroe8LK IZgcT1GyPDXVgeJXGpWlUNAQMywhrtHXpg+zRB9hv9yyqEpd+gQZWLJsxZnf7/7mbGMv cJ3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OJp/wZiERGVBUU7HIuspGPpojRpXm2e3BfdSR6ZgDTc=; b=RMYG8G0Y7fXlIpNwaRsNHIFn59nHdLWEc4X9mJssLfrvCCtsJZkMeVD+9dYLjA/s34 SFTHDwzseN/nDInmxupazHe3VRu9x963tB4U+E4P09Y8nYbjsAEWSGauXhJU3qSGKD1U Jbx5ei8Qat3YWD0exYAjH+YV7BP/UlpF2Z4TH70ua8k+yVB03tb7LEoSufasNkfHOfGG 4BPWtWFtuv3hdb+fKMPfRKNOIgdDK/WPAHufzTd4HNCUPVLzxSleRTu0E9Cq7udjIga/ Ei2QIdoBpUR/Z+lt2IcEamEr23ZOQIDvaODAa7XkOUj+A9oYilxI1EIwl3HquwCbVtYJ +JuA== X-Gm-Message-State: AOAM530WkQzRy0QXYWsWUeA71S1xx/jQdYcnRZpHCcCA0t/Eu3zqasTP PvAiHkZlnH+EgFtsAjgJ+rFyquVH2AxiFw== X-Google-Smtp-Source: ABdhPJwFV2uyo9fINU7WHNoT0sKrZNhrhElgzc60E2wNGxZJG6LSejSb2gQx+gNvO4hNqJUXh4++TA== X-Received: by 2002:a7b:c084:: with SMTP id r4mr45972882wmh.117.1636270924550; Sun, 07 Nov 2021 00:42:04 -0700 (PDT) Received: from localhost.localdomain (252.red-83-54-181.dynamicip.rima-tde.net. [83.54.181.252]) by smtp.gmail.com with ESMTPSA id e12sm15353352wrq.20.2021.11.07.00.42.03 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Nov 2021 00:42:04 -0700 (PDT) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org, sboyd@kernel.org, john@phrozen.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, Rob Herring Subject: [PATCH v5 2/4] dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property Date: Sun, 7 Nov 2021 08:41:58 +0100 Message-Id: <20211107074200.18911-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211107074200.18911-1-sergio.paracuellos@gmail.com> References: <20211107074200.18911-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Make system controller a reset provider for all the peripherals in the MT7621 SoC adding '#reset-cells' property. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-sysc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml index 915f84efd763..0c0b0ae5e2ac 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml @@ -22,6 +22,11 @@ description: | The clocks are provided inside a system controller node. + This node is also a reset provider for all the peripherals. + + Reset related bits are defined in: + [2]: . + properties: compatible: items: @@ -37,6 +42,12 @@ properties: clocks. const: 1 + "#reset-cells": + description: + The first cell indicates the reset bit within the register, see + [2] for available resets. + const: 1 + ralink,memctl: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -61,6 +72,7 @@ examples: compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; #clock-cells = <1>; + #reset-cells = <1>; ralink,memctl = <&memc>; clock-output-names = "xtal", "cpu", "bus", "50m", "125m", "150m", From patchwork Sun Nov 7 07:41:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12606717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C6FDC433F5 for ; Sun, 7 Nov 2021 07:42:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6209A60E97 for ; Sun, 7 Nov 2021 07:42:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235136AbhKGHoy (ORCPT ); Sun, 7 Nov 2021 02:44:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235036AbhKGHot (ORCPT ); Sun, 7 Nov 2021 02:44:49 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 049FFC061570; Sun, 7 Nov 2021 00:42:07 -0700 (PDT) Received: by mail-wr1-x42b.google.com with SMTP id c4so21056231wrd.9; Sun, 07 Nov 2021 00:42:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x10IZirB5LB8RZRsT12IdJrVjqBTqx2EabDrhJCUln8=; b=W1swplioznskhYAQ1ZqCNQvi2fsHPXAhokpSmvufHZVx07Gvy69LzQTUeT3BrrJwQ+ cEGUdNof1JflZwCpj3rWZ1sFMz6qePAAlqrfcF5Rl6zvIYbOzBXyYu5zCEN0pFssXzpe KTftB8wQZ5OE9QZ4rwH1RLbwiDfVfYio/ItfcKwh4mClDtUKsX0u+NyGt+S2tWtweiab 6D2B4/tTRAbXpbw3Kh1j+UlsGOsuD2v+zso+X4Uj+CFF7dQt5ZhRQHI4Epadni1QIthG k7UlVntS0WFFLenHhKk6jYNDtNnQADal616xPCUxpPJf1tdDM8dp4kkDZVNImIVBMDXy cTNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x10IZirB5LB8RZRsT12IdJrVjqBTqx2EabDrhJCUln8=; b=AKErGuxNf+nRM7zTrr+zMngL1CGEJibevbmcUt+tak8mQmxKwTsDImchaxFyaTQ6a0 103ZjpHetfa5Sldzfm4mo0YMEtwbY2NBE5MBI03JezSiuFWNUuefjNUC3vOGl4qYwKgp ewYjfeojOwyoYESRjlOp1FrEsGRkZIhIfQBg0YOJ05R6P15bQBMf1Borzi/rdvasQBOX 2ZlE0U89/SoMseKRYyeL1bKIbPrY1bODOU3XhXE91h8MEtgVpyjJ5xfVqV7PZjs6K/ds xs7p1unWF8Rf7aXgn/7EI25RljZCk1hchFWkKRLGeVwF8mQLL+TjaqzXOaPravUZIGN5 B/yw== X-Gm-Message-State: AOAM5313eEBTnPLmpXaXY6gvfUjV4p/qduPe2a2vxaAgF7MqtdRro+tL vr03zcWdm8pPfh9g149StcS9Ju3Y/TnxRQ== X-Google-Smtp-Source: ABdhPJy75LeVj3e7rKYpSXW0JCBUnqe1MheUEqygdahEB/IjRYt1Pg4wLTfIvcAOBhhdkv7quCsSWA== X-Received: by 2002:a5d:4348:: with SMTP id u8mr27088940wrr.35.1636270925443; Sun, 07 Nov 2021 00:42:05 -0700 (PDT) Received: from localhost.localdomain (252.red-83-54-181.dynamicip.rima-tde.net. [83.54.181.252]) by smtp.gmail.com with ESMTPSA id e12sm15353352wrq.20.2021.11.07.00.42.04 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Nov 2021 00:42:05 -0700 (PDT) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org, sboyd@kernel.org, john@phrozen.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name Subject: [PATCH v5 3/4] clk: ralink: make system controller node a reset provider Date: Sun, 7 Nov 2021 08:41:59 +0100 Message-Id: <20211107074200.18911-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211107074200.18911-1-sergio.paracuellos@gmail.com> References: <20211107074200.18911-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org MT7621 system controller node is already providing the clocks for the whole system but must also serve as a reset provider. Hence, add reset controller related code to the clock driver itself. To get resets properly ready for the rest of the world we need to move platform driver initialization process to 'arch_initcall'. Signed-off-by: Sergio Paracuellos --- drivers/clk/ralink/clk-mt7621.c | 86 ++++++++++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 1 deletion(-) diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c index a2c045390f00..c725bf6e6e07 100644 --- a/drivers/clk/ralink/clk-mt7621.c +++ b/drivers/clk/ralink/clk-mt7621.c @@ -11,14 +11,17 @@ #include #include #include +#include #include #include +#include /* Configuration registers */ #define SYSC_REG_SYSTEM_CONFIG0 0x10 #define SYSC_REG_SYSTEM_CONFIG1 0x14 #define SYSC_REG_CLKCFG0 0x2c #define SYSC_REG_CLKCFG1 0x30 +#define SYSC_REG_RESET_CTRL 0x34 #define SYSC_REG_CUR_CLK_STS 0x44 #define MEMC_REG_CPU_PLL 0x648 @@ -398,6 +401,76 @@ static void __init mt7621_clk_init(struct device_node *node) } CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init); +struct mt7621_rst { + struct reset_controller_dev rcdev; + struct regmap *sysc; +}; + +static struct mt7621_rst *to_mt7621_rst(struct reset_controller_dev *dev) +{ + return container_of(dev, struct mt7621_rst, rcdev); +} + +static int mt7621_assert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + if (id == MT7621_RST_SYS) + return -EINVAL; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id)); +} + +static int mt7621_deassert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + if (id == MT7621_RST_SYS) + return -EINVAL; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0); +} + +static int mt7621_reset_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = mt7621_assert_device(rcdev, id); + if (ret < 0) + return ret; + + return mt7621_deassert_device(rcdev, id); +} + +static const struct reset_control_ops reset_ops = { + .reset = mt7621_reset_device, + .assert = mt7621_assert_device, + .deassert = mt7621_deassert_device +}; + +static int mt7621_reset_init(struct device *dev, struct regmap *sysc) +{ + struct mt7621_rst *rst_data; + + rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); + if (!rst_data) + return -ENOMEM; + + rst_data->sysc = sysc; + rst_data->rcdev.ops = &reset_ops; + rst_data->rcdev.owner = THIS_MODULE; + rst_data->rcdev.nr_resets = 32; + rst_data->rcdev.of_reset_n_cells = 1; + rst_data->rcdev.of_node = dev_of_node(dev); + + return devm_reset_controller_register(dev, &rst_data->rcdev); +} + static int mt7621_clk_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -424,6 +497,12 @@ static int mt7621_clk_probe(struct platform_device *pdev) return ret; } + ret = mt7621_reset_init(dev, priv->sysc); + if (ret) { + dev_err(dev, "Could not init reset controller\n"); + return ret; + } + count = ARRAY_SIZE(mt7621_clks_base) + ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates); clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count), @@ -485,4 +564,9 @@ static struct platform_driver mt7621_clk_driver = { .of_match_table = mt7621_clk_of_match, }, }; -builtin_platform_driver(mt7621_clk_driver); + +static int __init mt7621_clk_reset_init(void) +{ + return platform_driver_register(&mt7621_clk_driver); +} +arch_initcall(mt7621_clk_reset_init); From patchwork Sun Nov 7 07:42:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12606719 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 056E1C433FE for ; Sun, 7 Nov 2021 07:42:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D99E8613B3 for ; Sun, 7 Nov 2021 07:42:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235097AbhKGHoz (ORCPT ); Sun, 7 Nov 2021 02:44:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57716 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235091AbhKGHou (ORCPT ); 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[83.54.181.252]) by smtp.gmail.com with ESMTPSA id e12sm15353352wrq.20.2021.11.07.00.42.05 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Nov 2021 00:42:05 -0700 (PDT) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org, sboyd@kernel.org, john@phrozen.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name Subject: [PATCH v5 4/4] staging: mt7621-dts: align resets with binding documentation Date: Sun, 7 Nov 2021 08:42:00 +0100 Message-Id: <20211107074200.18911-5-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211107074200.18911-1-sergio.paracuellos@gmail.com> References: <20211107074200.18911-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Binding documentation for compatible 'mediatek,mt7621-sysc' has been updated to be used as a reset provider. Align reset related bits and system controller node with binding documentation along the dtsi file. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts/mt7621.dtsi | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 6d158e4f4b8c..2bf74468d495 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -2,6 +2,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -67,6 +68,7 @@ sysc: syscon@0 { compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; #clock-cells = <1>; + #reset-cells = <1>; ralink,memctl = <&memc>; clock-output-names = "xtal", "cpu", "bus", "50m", "125m", "150m", @@ -96,7 +98,7 @@ i2c: i2c@900 { clocks = <&sysc MT7621_CLK_I2C>; clock-names = "i2c"; - resets = <&rstctrl 16>; + resets = <&sysc MT7621_RST_I2C>; reset-names = "i2c"; #address-cells = <1>; @@ -137,7 +139,7 @@ spi0: spi@b00 { clocks = <&sysc MT7621_CLK_SPI>; clock-names = "spi"; - resets = <&rstctrl 18>; + resets = <&sysc MT7621_RST_SPI>; reset-names = "spi"; #address-cells = <1>; @@ -153,7 +155,7 @@ gdma: gdma@2800 { clocks = <&sysc MT7621_CLK_GDMA>; clock-names = "gdma"; - resets = <&rstctrl 14>; + resets = <&sysc MT7621_RST_GDMA>; reset-names = "dma"; interrupt-parent = <&gic>; @@ -172,7 +174,7 @@ hsdma: hsdma@7000 { clocks = <&sysc MT7621_CLK_HSDMA>; clock-names = "hsdma"; - resets = <&rstctrl 5>; + resets = <&sysc MT7621_RST_HSDMA>; reset-names = "hsdma"; interrupt-parent = <&gic>; @@ -272,11 +274,6 @@ pinmux { }; }; - rstctrl: rstctrl { - compatible = "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - sdhci: sdhci@1e130000 { status = "disabled"; @@ -355,7 +352,7 @@ ethernet: ethernet@1e100000 { #address-cells = <1>; #size-cells = <0>; - resets = <&rstctrl 6 &rstctrl 23>; + resets = <&sysc MT7621_CLK_FE &sysc MT7621_CLK_ETH>; reset-names = "fe", "eth"; interrupt-parent = <&gic>; @@ -400,7 +397,7 @@ switch0: switch0@0 { #size-cells = <0>; reg = <0>; mediatek,mcm; - resets = <&rstctrl 2>; + resets = <&sysc MT7621_RST_MCM>; reset-names = "mcm"; interrupt-controller; #interrupt-cells = <1>; @@ -486,7 +483,7 @@ pcie@0,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 24>; + resets = <&sysc MT7621_RST_PCIE0>; clocks = <&sysc MT7621_CLK_PCIE0>; phys = <&pcie0_phy 1>; phy-names = "pcie-phy0"; @@ -501,7 +498,7 @@ pcie@1,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 25>; + resets = <&sysc MT7621_RST_PCIE1>; clocks = <&sysc MT7621_CLK_PCIE1>; phys = <&pcie0_phy 1>; phy-names = "pcie-phy1"; @@ -516,7 +513,7 @@ pcie@2,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 26>; + resets = <&sysc MT7621_RST_PCIE2>; clocks = <&sysc MT7621_CLK_PCIE2>; phys = <&pcie2_phy 0>; phy-names = "pcie-phy2";