From patchwork Sun Nov 7 19:55:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12606965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FA21C433F5 for ; Sun, 7 Nov 2021 20:05:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DB43C6128E for ; Sun, 7 Nov 2021 20:05:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236390AbhKGUIF (ORCPT ); Sun, 7 Nov 2021 15:08:05 -0500 Received: from mx1.riseup.net ([198.252.153.129]:34688 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236381AbhKGUIF (ORCPT ); Sun, 7 Nov 2021 15:08:05 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HnQ325Yr3zDyXD; Sun, 7 Nov 2021 11:55:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636314942; bh=Zok29VGxLNbCS2SSOfCqSks7d0rR86LWsOTAyuVRHE4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nZoI5M+MJXYGLEeTGUxeF3O856MGXX5tlA5nfBJTKmOTrd2RJlvqLp9o2AziEoi5B UybxVVCN9brm04WNUAp/ZHp30MJWxX69eBjKPBRx08+JuXu3rej1xf0WdiYP6soX+N iyL3pnhZucQ2cTsqeAjIjj+phYiUIRHEYKX6IS7s= X-Riseup-User-ID: 77F8FC23B2FEF10E81837EA7EBDDE1057B514602D2BCBEF68C901B1AD7F827C2 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HnQ2z4N2wz5vj2; Sun, 7 Nov 2021 11:55:39 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, martin.botka@somainline.org, marijn.suijten@somainline.org, paul.bouchara@somainline.org, angelogioacchino.delregno@somainline.org Subject: [PATCH 1/7] arm64: dts: qcom: sdm630: Assign numbers to eMMC and SD Date: Mon, 8 Nov 2021 02:55:05 +0700 Message-Id: <20211107195511.3346734-2-danct12@riseup.net> In-Reply-To: <20211107195511.3346734-1-danct12@riseup.net> References: <20211107195511.3346734-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This makes eMMC/SD device number consistent. Signed-off-by: Dang Huynh Reviewed-by: Martin Botka --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 3e0165bb61c5..b75bb87ed290 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -19,6 +19,11 @@ / { #address-cells = <2>; #size-cells = <2>; + aliases { + mmc1 = &sdhc_1; + mmc2 = &sdhc_2; + }; + chosen { }; clocks { From patchwork Sun Nov 7 19:55:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12606969 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8CBAC43217 for ; Sun, 7 Nov 2021 20:05:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8AE8F6134F for ; Sun, 7 Nov 2021 20:05:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236401AbhKGUIG (ORCPT ); Sun, 7 Nov 2021 15:08:06 -0500 Received: from mx1.riseup.net ([198.252.153.129]:34872 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236382AbhKGUIF (ORCPT ); Sun, 7 Nov 2021 15:08:05 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HnQ3613WMzF3QB; Sun, 7 Nov 2021 11:55:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636314946; bh=nDzonL5LEgFhgGcgGohs5zybDh6agAh8DFjxFnPl3RU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NMhz//++7tX0LOrkgDnDu14/t1PuEa5euimuv10ruVJXyOIpjfZOdF2SVPP7C0g2+ 42eNuNcvAsTFpFhtPrsZh2UPwEh/bVYFVtSeFjdtavkNGit2zAQCnWUEYuno9RaxGf 2hasVnS9D5qfhToQn7JXrP0l1Z79mWcx7C4n5c4M= X-Riseup-User-ID: 13A89ECB5C0534F24E432FF1FEFE14E2DA5494CD72571E3A3847926574EB29F0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HnQ330dn2z5vj2; Sun, 7 Nov 2021 11:55:42 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, martin.botka@somainline.org, marijn.suijten@somainline.org, paul.bouchara@somainline.org, angelogioacchino.delregno@somainline.org Subject: [PATCH 2/7] arm64: dts: qcom: sdm660-xiaomi-lavender: Add RPM and fixed regulators Date: Mon, 8 Nov 2021 02:55:06 +0700 Message-Id: <20211107195511.3346734-3-danct12@riseup.net> In-Reply-To: <20211107195511.3346734-1-danct12@riseup.net> References: <20211107195511.3346734-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add most of the RPM PM660/PM660L regulators and the fixed ones, defining the common electrical part of this platform. Signed-off-by: Dang Huynh --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 294 ++++++++++++++++++ 1 file changed, 294 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 1edc53fd6941..365a03b56cde 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -1,11 +1,14 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020, Alexey Minnekhanov + * Copyright (c) 2021, Dang Huynh */ /dts-v1/; #include "sdm660.dtsi" +#include "pm660.dtsi" +#include "pm660l.dtsi" / { model = "Xiaomi Redmi Note 7"; @@ -20,6 +23,14 @@ chosen { stdout-path = "serial0:115200n8"; }; + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + + regulator-always-on; + regulator-boot-on; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -40,6 +51,289 @@ &blsp1_uart2 { status = "okay"; }; +&rpm_requests { + pm660l-regulators { + compatible = "qcom,rpm-pm660l-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>; + vdd_l2-supply = <&vreg_bob>; + vdd_l3_l5_l7_l8-supply = <&vreg_bob>; + vdd_l4_l6-supply = <&vreg_bob>; + vdd_bob-supply = <&vph_pwr>; + + vreg_s1b_1p125: s1 { + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_s2b_1p05: s2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + /* LDOs */ + vreg_l1b_0p925: l1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <925000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + // SDHCI 3.3V signal doesn't seem to be supported. + vreg_l2b_2p95: l2 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2696000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l3b_3p3: l3 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l4b_2p95: l4 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + + regulator-min-microamp = <200>; + regulator-max-microamp = <600000>; + regulator-system-load = <570000>; + regulator-allow-set-load; + }; + + /* + * Downstream specifies a range of 1721-3600mV, + * but the only assigned consumers are SDHCI2 VMMC + * and Coresight QPDI that both request pinned 2.95V. + * Tighten the range to 1.8-3.328 (closest to 3.3) to + * make the mmc driver happy. + */ + vreg_l5b_2p95: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3328000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + regulator-system-load = <800000>; + }; + + vreg_l7b_3p125: l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3125000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l8b_3p3: l8 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + regulator-enable-ramp-delay = <500>; + regulator-ramp-delay = <0>; + }; + }; + + pm660-regulators { + compatible = "qcom,rpm-pm660-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>; + vdd_l2_l3-supply = <&vreg_s2b_1p05>; + vdd_l5-supply = <&vreg_s2b_1p05>; + vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>; + vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>; + + /* + * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed + * by the Core Power Reduction hardened (CPRh) and the + * Operating State Manager (OSM) HW automatically. + */ + + vreg_s4a_2p04: s4 { + regulator-min-microvolt = <1805000>; + regulator-max-microvolt = <2040000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + vreg_s5a_1p35: s5 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1350000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_s6a_0p87: s6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <992000>; + regulator-enable-ramp-delay = <150>; + regulator-ramp-delay = <0>; + }; + + /* LDOs */ + vreg_l1a_1p225: l1 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l2a_1p0: l2 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l3a_1p0: l3 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l5a_0p848: l5 { + regulator-min-microvolt = <525000>; + regulator-max-microvolt = <950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l6a_1p3: l6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1370000>; + regulator-allow-set-load; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l7a_1p2: l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l8a_1p8: l8 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-system-load = <325000>; + regulator-allow-set-load; + }; + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l10a_1p8: l10 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l11a_1p8: l11 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l12a_1p8: l12 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + /* This gives power to the LPDDR4: never turn it off! */ + vreg_l13a_1p8: l13 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_l14a_1p8: l14 { + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l15a_1p8: l15 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l16a_2p7: l16 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + vreg_l17a_1p8: l17 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l19a_3p3: l19 { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + }; +}; + &tlmm { gpio-reserved-ranges = <8 4>; }; From patchwork Sun Nov 7 19:55:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12606967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA0D6C4332F for ; Sun, 7 Nov 2021 20:05:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B74986134F for ; Sun, 7 Nov 2021 20:05:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236395AbhKGUIG (ORCPT ); Sun, 7 Nov 2021 15:08:06 -0500 Received: from mx1.riseup.net ([198.252.153.129]:34618 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229548AbhKGUIF (ORCPT ); Sun, 7 Nov 2021 15:08:05 -0500 X-Greylist: delayed 582 seconds by postgrey-1.27 at vger.kernel.org; Sun, 07 Nov 2021 15:08:04 EST Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HnQ393zPSzDyS6; Sun, 7 Nov 2021 11:55:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636314949; bh=EvJNkWC7WStqzP8043NR3jmhKI30lKemFklLBeyCM64=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Zyzq5ZkRMswtDzA4nsAiWrA+gnEq/E5U/caDFLVm8/O9mecYHtDZ3QAh9oiishjLm ua2njmfhMTD95EdzZE5L61lMFPe5wG+q7r4QG8x7RlHWbRJNTQcmnqBq94cXdifunE aNKgrFUL6i/eNRAeCd/GGlM614Bct0Ii2IWWHISQ= X-Riseup-User-ID: 3CA882FE7982556A9D09C0A87ED279012AC4F6407DAFCB8E8B35535ACC62BECE Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HnQ363b9mz5vj2; Sun, 7 Nov 2021 11:55:46 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, martin.botka@somainline.org, marijn.suijten@somainline.org, paul.bouchara@somainline.org, angelogioacchino.delregno@somainline.org Subject: [PATCH 3/7] arm64: dts: qcom: sdm660-xiaomi-lavender: Add volume down button Date: Mon, 8 Nov 2021 02:55:07 +0700 Message-Id: <20211107195511.3346734-4-danct12@riseup.net> In-Reply-To: <20211107195511.3346734-1-danct12@riseup.net> References: <20211107195511.3346734-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This enables the volume down key. Signed-off-by: Dang Huynh Reviewed-by: Martin Botka --- arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 365a03b56cde..28408240735b 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -51,6 +51,16 @@ &blsp1_uart2 { status = "okay"; }; +&pon { + voldown { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; +}; + &rpm_requests { pm660l-regulators { compatible = "qcom,rpm-pm660l-regulators"; From patchwork Sun Nov 7 19:55:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12606977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A06EC433F5 for ; Sun, 7 Nov 2021 20:05:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4E35A6128E for ; Sun, 7 Nov 2021 20:05:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236437AbhKGUIN (ORCPT ); Sun, 7 Nov 2021 15:08:13 -0500 Received: from mx1.riseup.net ([198.252.153.129]:37434 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236385AbhKGUIH (ORCPT ); Sun, 7 Nov 2021 15:08:07 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HnQ3F0FJTzF43v; Sun, 7 Nov 2021 11:55:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636314953; bh=Mz2Y9Z3jJa5YdOET9mVHR82Zll7PFd5M8ER/5BHLkvw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cjGCALBnXt2Qp8jW89Voz2esWOJr+MI0SJ/m5lV1C+nOxE27Vu+UWlDo6OIUEkhvF XSxJ+dyhfcii0h2uPbNv6qwehVjUj4wKlEq5K2WRR4J7Y3Mk9KgS0/Yfw8we2/Q87T nOptwAuK2UxDBfEt8To0LtjEHCNXpP72205mw1Ss= X-Riseup-User-ID: CB7883D8C8B195857680B619F9C46094F400FF10FDACC8B442C9FB889B5A937E Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HnQ396ZmHz5vj2; Sun, 7 Nov 2021 11:55:49 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, martin.botka@somainline.org, marijn.suijten@somainline.org, paul.bouchara@somainline.org, angelogioacchino.delregno@somainline.org Subject: [PATCH 4/7] arm64: dts: qcom: sdm660-xiaomi-lavender: Add volume up button Date: Mon, 8 Nov 2021 02:55:08 +0700 Message-Id: <20211107195511.3346734-5-danct12@riseup.net> In-Reply-To: <20211107195511.3346734-1-danct12@riseup.net> References: <20211107195511.3346734-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This enables the volume up key. Signed-off-by: Dang Huynh Reviewed-by: Martin Botka --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 28408240735b..5e4682f54fbe 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -9,6 +9,9 @@ #include "sdm660.dtsi" #include "pm660.dtsi" #include "pm660l.dtsi" +#include +#include +#include / { model = "Xiaomi Redmi Note 7"; @@ -31,6 +34,23 @@ vph_pwr: vph-pwr-regulator { regulator-boot-on; }; + gpio_keys { + status = "okay"; + compatible = "gpio-keys"; + input-name = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + vol_up { + label = "Volume Up"; + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; From patchwork Sun Nov 7 19:55:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12606979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D63A4C43219 for ; Sun, 7 Nov 2021 20:05:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C2B0961351 for ; Sun, 7 Nov 2021 20:05:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236443AbhKGUIO (ORCPT ); Sun, 7 Nov 2021 15:08:14 -0500 Received: from mx1.riseup.net ([198.252.153.129]:37436 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236386AbhKGUIH (ORCPT ); Sun, 7 Nov 2021 15:08:07 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HnQ3J2xnYzF3g8; Sun, 7 Nov 2021 11:55:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636314956; bh=H8yazxf7HE6AfSXru1GfUz3uEeAH1qJLeml8PxMZ4Gs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PNkZb7XHRBBdkAyb1QC5jF8TxHf3iBOB+8m83chkP3NeMjgR3fhTOnGiL9vqywcZL 3A+DV1KwSJyadxZ9IdAaWuY8YMLYLR/8g50RQvtzGv481EudGToIP2JiuiB7uiwsjE HJ3vxT4h0e3pWNuylNECEvWAOVdfoLu2JLKwfXlU= X-Riseup-User-ID: 36824BF6AEE6CD861E6A323D570E8F1D099C9B848E7AEFA59E2F0C385FD77A3B Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HnQ3F2VcNz5vj2; Sun, 7 Nov 2021 11:55:53 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, martin.botka@somainline.org, marijn.suijten@somainline.org, paul.bouchara@somainline.org, angelogioacchino.delregno@somainline.org Subject: [PATCH 5/7] arm64: dts: qcom: sdm660-xiaomi-lavender: Add eMMC and SD Date: Mon, 8 Nov 2021 02:55:09 +0700 Message-Id: <20211107195511.3346734-6-danct12@riseup.net> In-Reply-To: <20211107195511.3346734-1-danct12@riseup.net> References: <20211107195511.3346734-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This commit enable the SD card slot and internal MMC. Signed-off-by: Dang Huynh --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 5e4682f54fbe..30e564927cd7 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -364,6 +364,25 @@ vreg_l19a_3p3: l19 { }; }; +&sdhc_1 { + status = "okay"; + supports-cqe; + + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + vmmc-supply = <&vreg_l4b_2p95>; + vqmmc-supply = <&vreg_l8a_1p8>; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&vreg_l5b_2p95>; + vqmmc-supply = <&vreg_l2b_2p95>; +}; + &tlmm { gpio-reserved-ranges = <8 4>; }; From patchwork Sun Nov 7 19:55:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12606973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94A35C4332F for ; Sun, 7 Nov 2021 20:05:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7E0D061354 for ; Sun, 7 Nov 2021 20:05:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236415AbhKGUII (ORCPT ); Sun, 7 Nov 2021 15:08:08 -0500 Received: from mx1.riseup.net ([198.252.153.129]:37442 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236387AbhKGUIH (ORCPT ); Sun, 7 Nov 2021 15:08:07 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HnQ3M60JbzF3gL; Sun, 7 Nov 2021 11:55:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636314959; bh=ddEC6H45Hu/66fHyjU3jKy0aj4quwFprpB3NaYBSfw4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bSTwb8ZwBIHlxZoUUiIlyBfDTsxKSalSD8ibIVLMxxFqPPqFsPZSyW+UT0hSXzn8d T8fi/sR1X2y7PAp//uAjaYSZRNa9UrFDBD3TuiujGLZA05QPKnxch/D6sClxF+IMHO HxvmvdkXQWg5wAbBOucIp2SXtyeFIbNHmrzo2Gl4= X-Riseup-User-ID: 75FA984DF7A6379CF0BF32107ABA5ED5580AAEA0763DF99F2B92FAA1DAFAF5B1 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HnQ3J5Vxhz5vj2; Sun, 7 Nov 2021 11:55:56 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, martin.botka@somainline.org, marijn.suijten@somainline.org, paul.bouchara@somainline.org, angelogioacchino.delregno@somainline.org Subject: [PATCH 6/7] arm64: dts: qcom: sdm660-xiaomi-lavender: Enable Simple Framebuffer Date: Mon, 8 Nov 2021 02:55:10 +0700 Message-Id: <20211107195511.3346734-7-danct12@riseup.net> In-Reply-To: <20211107195511.3346734-1-danct12@riseup.net> References: <20211107195511.3346734-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This lets the user sees the framebuffer console. Signed-off-by: Dang Huynh Reviewed-by: Martin Botka --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 30e564927cd7..d6599881f1ac 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -23,7 +23,21 @@ aliases { }; chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + stdout-path = "serial0:115200n8"; + + framebuffer0: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0 0x9d400000 0 (1080 * 2340 * 4)>; + width = <1080>; + height = <2340>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + status= "okay"; + }; }; vph_pwr: vph-pwr-regulator { @@ -64,6 +78,11 @@ ramoops@a0000000 { ftrace-size = <0x0>; pmsg-size = <0x20000>; }; + + cont_splash_mem: cont-splash-region@9d400000 { + reg = <0x0 0x9d400000 0x0 0x23ff000>; + no-map; + }; }; }; From patchwork Sun Nov 7 19:55:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12606971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 862E8C433F5 for ; Sun, 7 Nov 2021 20:05:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6BE856134F for ; Sun, 7 Nov 2021 20:05:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236404AbhKGUIH (ORCPT ); Sun, 7 Nov 2021 15:08:07 -0500 Received: from mx1.riseup.net ([198.252.153.129]:35010 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236383AbhKGUIF (ORCPT ); Sun, 7 Nov 2021 15:08:05 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HnQ3R21dpzDrhC; Sun, 7 Nov 2021 11:56:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636314963; bh=H5TSzC40aRVwGWGMaw5goomGgd7XGwJA1Z2Jw1JsVfA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Gd5EkgWt6tcv/dyxrwbZC63Gjhsx1naUDAPV3wPAvSGoKijXyD79UECXVD8p6H7KW 6/SIwAMqA0yI001oeRvtumTTraHruyA0F/Q8NPmmggo1zhOVhIzURUjoFfF3485bGr 0ErFj+T4MmMxkDyb+oib1L3WHJDfQTo3mYz0auc0= X-Riseup-User-ID: A90CA907D0BB05E5B3A226CB280CD9A0CDD45754D187F57A772E4E7AC55480D7 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HnQ3N1R98z5vkF; Sun, 7 Nov 2021 11:55:59 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, martin.botka@somainline.org, marijn.suijten@somainline.org, paul.bouchara@somainline.org, angelogioacchino.delregno@somainline.org Subject: [PATCH 7/7] arm64: dts: qcom: sdm660-xiaomi-lavender: Add USB Date: Mon, 8 Nov 2021 02:55:11 +0700 Message-Id: <20211107195511.3346734-8-danct12@riseup.net> In-Reply-To: <20211107195511.3346734-1-danct12@riseup.net> References: <20211107195511.3346734-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable and configure DWC3 and QUSB2 PHY to enable USB functionality on the Redmi Note 7. Signed-off-by: Dang Huynh --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index d6599881f1ac..b54191f1f152 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -84,6 +84,15 @@ cont_splash_mem: cont-splash-region@9d400000 { no-map; }; }; + + /* + * Until we hook up type-c detection, we + * have to stick with this. But it works. + */ + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + }; }; &blsp1_uart2 { @@ -100,6 +109,13 @@ voldown { }; }; +&qusb2phy { + status = "okay"; + + vdd-supply = <&vreg_l1b_0p925>; + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; +}; + &rpm_requests { pm660l-regulators { compatible = "qcom,rpm-pm660l-regulators"; @@ -405,3 +421,12 @@ &sdhc_2 { &tlmm { gpio-reserved-ranges = <8 4>; }; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; + extcon = <&extcon_usb>; +};