From patchwork Mon Nov 8 05:03:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12607821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 565B6C43219 for ; Mon, 8 Nov 2021 05:06:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 408BD61352 for ; Mon, 8 Nov 2021 05:06:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231767AbhKHFIv (ORCPT ); Mon, 8 Nov 2021 00:08:51 -0500 Received: from mx1.riseup.net ([198.252.153.129]:34818 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231238AbhKHFIu (ORCPT ); Mon, 8 Nov 2021 00:08:50 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HnfG56w55zF2Hd; Sun, 7 Nov 2021 21:06:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636347966; bh=Tb9BXhWjM8ETEr9rbF//OKUG6q3GkHqxrZkAdfraSgU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EVJef3BjMX85NLaJnpavwZ36fN19nTi+pumLR6OtGnQsAlRan5cx3ukS0+tkZhxs4 D9L3NVFz2eMaEUCNAW8tRQ2DUrx25lRdMz11nKV1hZwdEJoQD3lC0XQB4Znv3pP/5W gH5IybqPv41djUrQ7OodffDfUqRi4nWyk4G85CTo= X-Riseup-User-ID: 9AE33FBEF1815754132AFF61DA6028071E609353EB7373F4C84C48852C10E225 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HnfG243q5z5vj2; Sun, 7 Nov 2021 21:06:02 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, martin.botka@somainline.org, marijn.suijten@somainline.org, paul.bouchara@somainline.org, angelogioacchino.delregno@somainline.org, Caleb Connolly Subject: [PATCH v2 1/7] arm64: dts: qcom: sdm630: Assign numbers to eMMC and SD Date: Mon, 8 Nov 2021 12:03:30 +0700 Message-Id: <20211108050336.3404559-2-danct12@riseup.net> In-Reply-To: <20211108050336.3404559-1-danct12@riseup.net> References: <20211108050336.3404559-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This makes eMMC/SD device number consistent. Reviewed-by: Martin Botka Signed-off-by: Dang Huynh Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 3e0165bb61c5..b75bb87ed290 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -19,6 +19,11 @@ / { #address-cells = <2>; #size-cells = <2>; + aliases { + mmc1 = &sdhc_1; + mmc2 = &sdhc_2; + }; + chosen { }; clocks { From patchwork Mon Nov 8 05:03:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12607823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67AA1C433EF for ; Mon, 8 Nov 2021 05:06:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4E44F61503 for ; Mon, 8 Nov 2021 05:06:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231909AbhKHFIz (ORCPT ); Mon, 8 Nov 2021 00:08:55 -0500 Received: from mx1.riseup.net ([198.252.153.129]:38688 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232636AbhKHFIy (ORCPT ); Mon, 8 Nov 2021 00:08:54 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HnfG941p3zF401; Sun, 7 Nov 2021 21:06:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636347969; bh=jSY0qzpujg8K1X3d7R2Q+oibeez5KlF/lwGAGDy17hY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OK0AztyZoeuRdUj2TSEJNduKSNmEklY3xBzwfOR2O8jx9nS0FpLEwVvVam2cKZ9Dr qLgMwRDxz4M+GF79RuFRbUiG65KIpPV5LFs+jOmJjlD4+RtzgNTnXRe0XG3Y0XtpKS Ksprr9/ulnuZdBEHTzaypWV5n82L8fC556DNaXc0= X-Riseup-User-ID: F057E44C85A8B94457EC6A30375FAE02A5A597733E1D305ABA5CF53F417C0419 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HnfG61njKz5vj2; Sun, 7 Nov 2021 21:06:06 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, martin.botka@somainline.org, marijn.suijten@somainline.org, paul.bouchara@somainline.org, angelogioacchino.delregno@somainline.org, Caleb Connolly Subject: [PATCH v2 2/7] arm64: dts: qcom: sdm660-xiaomi-lavender: Add RPM and fixed regulators Date: Mon, 8 Nov 2021 12:03:31 +0700 Message-Id: <20211108050336.3404559-3-danct12@riseup.net> In-Reply-To: <20211108050336.3404559-1-danct12@riseup.net> References: <20211108050336.3404559-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add most of the RPM PM660/PM660L regulators and the fixed ones, defining the common electrical part of this platform. Reviewed-by: Caleb Connolly Signed-off-by: Dang Huynh --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 294 ++++++++++++++++++ 1 file changed, 294 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 1edc53fd6941..365a03b56cde 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -1,11 +1,14 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020, Alexey Minnekhanov + * Copyright (c) 2021, Dang Huynh */ /dts-v1/; #include "sdm660.dtsi" +#include "pm660.dtsi" +#include "pm660l.dtsi" / { model = "Xiaomi Redmi Note 7"; @@ -20,6 +23,14 @@ chosen { stdout-path = "serial0:115200n8"; }; + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + + regulator-always-on; + regulator-boot-on; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -40,6 +51,289 @@ &blsp1_uart2 { status = "okay"; }; +&rpm_requests { + pm660l-regulators { + compatible = "qcom,rpm-pm660l-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>; + vdd_l2-supply = <&vreg_bob>; + vdd_l3_l5_l7_l8-supply = <&vreg_bob>; + vdd_l4_l6-supply = <&vreg_bob>; + vdd_bob-supply = <&vph_pwr>; + + vreg_s1b_1p125: s1 { + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_s2b_1p05: s2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + /* LDOs */ + vreg_l1b_0p925: l1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <925000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + // SDHCI 3.3V signal doesn't seem to be supported. + vreg_l2b_2p95: l2 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2696000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l3b_3p3: l3 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l4b_2p95: l4 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + + regulator-min-microamp = <200>; + regulator-max-microamp = <600000>; + regulator-system-load = <570000>; + regulator-allow-set-load; + }; + + /* + * Downstream specifies a range of 1721-3600mV, + * but the only assigned consumers are SDHCI2 VMMC + * and Coresight QPDI that both request pinned 2.95V. + * Tighten the range to 1.8-3.328 (closest to 3.3) to + * make the mmc driver happy. + */ + vreg_l5b_2p95: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3328000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + regulator-system-load = <800000>; + }; + + vreg_l7b_3p125: l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3125000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l8b_3p3: l8 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + regulator-enable-ramp-delay = <500>; + regulator-ramp-delay = <0>; + }; + }; + + pm660-regulators { + compatible = "qcom,rpm-pm660-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>; + vdd_l2_l3-supply = <&vreg_s2b_1p05>; + vdd_l5-supply = <&vreg_s2b_1p05>; + vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>; + vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>; + + /* + * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed + * by the Core Power Reduction hardened (CPRh) and the + * Operating State Manager (OSM) HW automatically. + */ + + vreg_s4a_2p04: s4 { + regulator-min-microvolt = <1805000>; + regulator-max-microvolt = <2040000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + vreg_s5a_1p35: s5 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1350000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_s6a_0p87: s6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <992000>; + regulator-enable-ramp-delay = <150>; + regulator-ramp-delay = <0>; + }; + + /* LDOs */ + vreg_l1a_1p225: l1 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l2a_1p0: l2 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l3a_1p0: l3 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l5a_0p848: l5 { + regulator-min-microvolt = <525000>; + regulator-max-microvolt = <950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l6a_1p3: l6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1370000>; + regulator-allow-set-load; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l7a_1p2: l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l8a_1p8: l8 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-system-load = <325000>; + regulator-allow-set-load; + }; + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l10a_1p8: l10 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l11a_1p8: l11 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l12a_1p8: l12 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + /* This gives power to the LPDDR4: never turn it off! */ + vreg_l13a_1p8: l13 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_l14a_1p8: l14 { + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l15a_1p8: l15 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l16a_2p7: l16 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + vreg_l17a_1p8: l17 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l19a_3p3: l19 { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + }; +}; + &tlmm { gpio-reserved-ranges = <8 4>; }; From patchwork Mon Nov 8 05:03:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12607825 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D054FC433FE for ; Mon, 8 Nov 2021 05:06:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BC69261208 for ; Mon, 8 Nov 2021 05:06:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237636AbhKHFJK (ORCPT ); Mon, 8 Nov 2021 00:09:10 -0500 Received: from mx1.riseup.net ([198.252.153.129]:42314 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231947AbhKHFI5 (ORCPT ); Mon, 8 Nov 2021 00:08:57 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HnfGF14QPzF3K9; Sun, 7 Nov 2021 21:06:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636347973; bh=Bc10+pHBcFMLLVxlXuOSikB0TKg9+cWYR/znkPfiBU4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C2rDVBK++G+kEVXaIqoAg1iB50DUgYV5CVCPp/nqAlCAA0rO+jf38tQMGja4i8mfv yB+DKNkUG3VSPa+0J/ry15aq0hpClXDYnk5OxgQdOnpqDSwJl6C4pKnF3uuC8JC4k/ esuzWpYwIJUl/5hwZC+eUz+Awuzpn/3Q6tW5WMmE= X-Riseup-User-ID: 10E61440B16203EEFCA1E22B595C6255A6334DD061B45B45BD2DFE572E3957D3 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HnfG96Gd0z5vj2; Sun, 7 Nov 2021 21:06:09 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, martin.botka@somainline.org, marijn.suijten@somainline.org, paul.bouchara@somainline.org, angelogioacchino.delregno@somainline.org, Caleb Connolly Subject: [PATCH v2 3/7] arm64: dts: qcom: sdm660-xiaomi-lavender: Add volume down button Date: Mon, 8 Nov 2021 12:03:32 +0700 Message-Id: <20211108050336.3404559-4-danct12@riseup.net> In-Reply-To: <20211108050336.3404559-1-danct12@riseup.net> References: <20211108050336.3404559-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This enables the volume down key. Reviewed-by: Caleb Connolly Reviewed-by: Martin Botka Signed-off-by: Dang Huynh --- arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 365a03b56cde..28408240735b 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -51,6 +51,16 @@ &blsp1_uart2 { status = "okay"; }; +&pon { + voldown { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; +}; + &rpm_requests { pm660l-regulators { compatible = "qcom,rpm-pm660l-regulators"; From patchwork Mon Nov 8 05:03:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12607831 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A484C4332F for ; Mon, 8 Nov 2021 05:06:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 82460613D3 for ; Mon, 8 Nov 2021 05:06:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237606AbhKHFJV (ORCPT ); Mon, 8 Nov 2021 00:09:21 -0500 Received: from mx1.riseup.net ([198.252.153.129]:45986 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237610AbhKHFJD (ORCPT ); Mon, 8 Nov 2021 00:09:03 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HnfGJ5pHvzF2Hd; Sun, 7 Nov 2021 21:06:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636347976; bh=tioFDJfzihGLbumRH4c/w9cEfNW3tVsiU1fbw/gL4K8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=r104rRT3hhcUAv7e51qtK6+Xi7iwM0GAMCeE8HGtQ3Cx+TXMBEFjJXWELHN8PPaxt DFL3oJWCc8FW7R8mAZG+4T+1y7ReqYgAZjlnQ5Eq/I7TO3ql7Dtou3MyCGLU0A1TYx 8gZ0cbcNIVfgkD0wJeKRylpR/R6lRX1jwP7yttEM= X-Riseup-User-ID: 8712C061C11082B3840CEA5672B1879E3D63A98BA7AD4CE4754C7E9D1838E39A Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HnfGF3gTvz5vj2; Sun, 7 Nov 2021 21:06:13 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, martin.botka@somainline.org, marijn.suijten@somainline.org, paul.bouchara@somainline.org, angelogioacchino.delregno@somainline.org, Caleb Connolly Subject: [PATCH v2 4/7] arm64: dts: qcom: sdm660-xiaomi-lavender: Add volume up button Date: Mon, 8 Nov 2021 12:03:33 +0700 Message-Id: <20211108050336.3404559-5-danct12@riseup.net> In-Reply-To: <20211108050336.3404559-1-danct12@riseup.net> References: <20211108050336.3404559-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This enables the volume up key. Reviewed-by: Caleb Connolly Reviewed-by: Martin Botka Signed-off-by: Dang Huynh --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 28408240735b..ab814dc8a875 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -9,6 +9,9 @@ #include "sdm660.dtsi" #include "pm660.dtsi" #include "pm660l.dtsi" +#include +#include +#include / { model = "Xiaomi Redmi Note 7"; @@ -31,6 +34,21 @@ vph_pwr: vph-pwr-regulator { regulator-boot-on; }; + gpio_keys { + status = "okay"; + compatible = "gpio-keys"; + input-name = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + vol_up { + label = "Volume Up"; + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; From patchwork Mon Nov 8 05:03:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12607827 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41CC9C433FE for ; Mon, 8 Nov 2021 05:06:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2585761350 for ; Mon, 8 Nov 2021 05:06:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237640AbhKHFJN (ORCPT ); Mon, 8 Nov 2021 00:09:13 -0500 Received: from mx1.riseup.net ([198.252.153.129]:49040 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237622AbhKHFJE (ORCPT ); Mon, 8 Nov 2021 00:09:04 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HnfGN35fKzF43l; Sun, 7 Nov 2021 21:06:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636347980; bh=rq6wlb+rwlCGlsNlbNPlJC7Dd9i447YFd/T7vPgDiCw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VXfHvL234SZ2VankqbBdk/7wJLMAIj7xacM8AAz1S4JHrGOByDQqfM7aOMv+RAXCI YK1M1Uwpk5DZZrBUQNWh7bFz4DAjqfVb2PRBmIIWvX/RdolUd7y8pwezqGoHB/Uzod WuKEUzsOfc0aA20+mndaxRqEzeeJHm42ksuLH/78= X-Riseup-User-ID: AC3783CCB4B5A571438A1ED7EEA85EDD00F54B255541A44BE900D85461F8280D Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HnfGK14tlz5vj2; Sun, 7 Nov 2021 21:06:16 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, martin.botka@somainline.org, marijn.suijten@somainline.org, paul.bouchara@somainline.org, angelogioacchino.delregno@somainline.org, Caleb Connolly Subject: [PATCH v2 5/7] arm64: dts: qcom: sdm660-xiaomi-lavender: Add eMMC and SD Date: Mon, 8 Nov 2021 12:03:34 +0700 Message-Id: <20211108050336.3404559-6-danct12@riseup.net> In-Reply-To: <20211108050336.3404559-1-danct12@riseup.net> References: <20211108050336.3404559-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This commit enable the SD card slot and internal MMC. Reviewed-by: Caleb Connolly Signed-off-by: Dang Huynh --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index ab814dc8a875..8fd4d1732d94 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -362,6 +362,25 @@ vreg_l19a_3p3: l19 { }; }; +&sdhc_1 { + status = "okay"; + supports-cqe; + + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + vmmc-supply = <&vreg_l4b_2p95>; + vqmmc-supply = <&vreg_l8a_1p8>; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&vreg_l5b_2p95>; + vqmmc-supply = <&vreg_l2b_2p95>; +}; + &tlmm { gpio-reserved-ranges = <8 4>; }; From patchwork Mon Nov 8 05:03:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12607829 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00817C433F5 for ; Mon, 8 Nov 2021 05:06:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DAD5561208 for ; Mon, 8 Nov 2021 05:06:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237633AbhKHFJU (ORCPT ); Mon, 8 Nov 2021 00:09:20 -0500 Received: from mx1.riseup.net ([198.252.153.129]:51784 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237591AbhKHFJN (ORCPT ); Mon, 8 Nov 2021 00:09:13 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HnfGS0X77zDyXD; Sun, 7 Nov 2021 21:06:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636347984; bh=K5vDMa0Ne6mTpxBaAxuZyyGfLLkx3Tc6wlKfMsZa1U4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XSGGKqpl6b8KTAQz6QEc2hvQaCKsKh5FqSUhGTtlfYzQflQZ+5rnSMFhNZPX6p/NC IcXc9VLzk4nuW2Y6v/kZ4XmH/EGLrFHCHr88pN/oqFjiQU+wQ51OLZwNx5vnRTrECW R3CQ5boDGLSHKjNhpgaWcDXdi+3/3z5aI2BozsCw= X-Riseup-User-ID: 1899880FAC68F45CD3A6AF87F87BA411A9EE06C59302762C6587E83DAEB5C927 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HnfGN5cWvz5vj2; Sun, 7 Nov 2021 21:06:20 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, martin.botka@somainline.org, marijn.suijten@somainline.org, paul.bouchara@somainline.org, angelogioacchino.delregno@somainline.org, Caleb Connolly Subject: [PATCH v2 6/7] arm64: dts: qcom: sdm660-xiaomi-lavender: Enable Simple Framebuffer Date: Mon, 8 Nov 2021 12:03:35 +0700 Message-Id: <20211108050336.3404559-7-danct12@riseup.net> In-Reply-To: <20211108050336.3404559-1-danct12@riseup.net> References: <20211108050336.3404559-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This lets the user sees the framebuffer console. Reviewed-by: Caleb Connolly Reviewed-by: Martin Botka Signed-off-by: Dang Huynh --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 8fd4d1732d94..122b487f197b 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -23,7 +23,21 @@ aliases { }; chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + stdout-path = "serial0:115200n8"; + + framebuffer0: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0 0x9d400000 0 (1080 * 2340 * 4)>; + width = <1080>; + height = <2340>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + status= "okay"; + }; }; vph_pwr: vph-pwr-regulator { @@ -62,6 +76,11 @@ ramoops@a0000000 { ftrace-size = <0x0>; pmsg-size = <0x20000>; }; + + framebuffer_mem: memory@9d400000 { + reg = <0x0 0x9d400000 0x0 0x23ff000>; + no-map; + }; }; }; From patchwork Mon Nov 8 05:03:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12607833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78153C43217 for ; Mon, 8 Nov 2021 05:06:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 613D36162E for ; Mon, 8 Nov 2021 05:06:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237631AbhKHFJW (ORCPT ); Mon, 8 Nov 2021 00:09:22 -0500 Received: from mx1.riseup.net ([198.252.153.129]:55570 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237638AbhKHFJO (ORCPT ); Mon, 8 Nov 2021 00:09:14 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HnfGW4rQwzF3K9; Sun, 7 Nov 2021 21:06:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636347987; bh=F2q5E8Qn4Ne5vZ3VtvcvBFAEC8rtQNkSMlH8Ci6joyU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OZubvlMTmL5F8AcRGdwTNv76eKaCA8W6OQqdvOTb3rpr38ij63KbcT/8SO2j9dIk0 rDyivIjMj6n4pIxRWMwKooL226OpNx4Z0EMCY7OQK7bI0vPq+pZ3hMEVjYgW/VBzVy EqSGCefpX4I+QPaRkN9BjD4q42zktTZw8pIMuF1U= X-Riseup-User-ID: 8E9E742E70D9B4256ACE2F1FB7293BF8B30C92B3D3217CDF4250889B2F989CBA Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HnfGS2ytkz5vj2; Sun, 7 Nov 2021 21:06:24 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, martin.botka@somainline.org, marijn.suijten@somainline.org, paul.bouchara@somainline.org, angelogioacchino.delregno@somainline.org, Caleb Connolly Subject: [PATCH v2 7/7] arm64: dts: qcom: sdm660-xiaomi-lavender: Add USB Date: Mon, 8 Nov 2021 12:03:36 +0700 Message-Id: <20211108050336.3404559-8-danct12@riseup.net> In-Reply-To: <20211108050336.3404559-1-danct12@riseup.net> References: <20211108050336.3404559-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable and configure DWC3 and QUSB2 PHY to enable USB functionality on the Redmi Note 7. Signed-off-by: Dang Huynh --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 122b487f197b..a34812e91160 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -82,6 +82,15 @@ framebuffer_mem: memory@9d400000 { no-map; }; }; + + /* + * Until we hook up type-c detection, we + * have to stick with this. But it works. + */ + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + }; }; &blsp1_uart2 { @@ -98,6 +107,13 @@ voldown { }; }; +&qusb2phy { + status = "okay"; + + vdd-supply = <&vreg_l1b_0p925>; + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; +}; + &rpm_requests { pm660l-regulators { compatible = "qcom,rpm-pm660l-regulators"; @@ -403,3 +419,12 @@ &sdhc_2 { &tlmm { gpio-reserved-ranges = <8 4>; }; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; + extcon = <&extcon_usb>; +};