From patchwork Mon Nov 8 15:05:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12608573 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D112C433EF for ; Mon, 8 Nov 2021 15:06:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8841661101 for ; Mon, 8 Nov 2021 15:06:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240672AbhKHPJR (ORCPT ); Mon, 8 Nov 2021 10:09:17 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:21223 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240677AbhKHPJQ (ORCPT ); Mon, 8 Nov 2021 10:09:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1636383991; x=1667919991; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7TY70StaNQYPEo0JEGXnyDaaE5FyFeTJVVklhVpDOHY=; b=lgUQBoOQUks1+prlWNgwNnYy4deDNQinwI6ZnzLJzwhxTEBp9He8pir6 K/FurHtRtVLmtPqAqAWjFpIAuRYoipBaE0kkxvTLq7Ev4S1Ue9kz+TmlD QD2+dnfQsdG7V2gX4rtpfg1JksKZhPWTeI5Fgf6SUshNnEi1uYl709ucG 8l+2tU0mpu5cu2GffZ0opft4/m2zuyUPcDl2lfDeZvNxBXGel7dni+P/s SMQ06b8P0QrYuLAOTRdQdDV7OWK5RXsEsA/VhQ9gIbzung4Etpg2Sw8bs I+AofXhy0TdKY7cvcHHcvVYfteK8/WUaN5gTGvCnKF1HcuJO7S23qWzj0 g==; IronPort-SDR: Ntpp7n7MAYiBTQIALHMCUvFJeiU9D0S3cSUihj8H2Sa1PKofHXa5Gm6uzyYdUBtTVmZMiTI+Sm vRDvfd1ceVeyhMLRROFAT+SbZ16pWvUkc/6oIoCs9eQjuUWH5X2drqxkHzS6kVLG6ohPaRsNSw NVJc/UVeOeX3slZ4M2Dn3UhYi4z7ff4vWlQeU+CvEYtEU63f5CDX3kUZi2ib0F77+olpUP7SzH Ympz8b39z6uxj37N56/MHAj3IfQLiUDBbdaUkAC8pnGE2EaUvJz88DKXK/+WPwpvYko+phXh7C xL3ENJMyKEdgW2jyYgfUm/mn X-IronPort-AV: E=Sophos;i="5.87,218,1631602800"; d="scan'208";a="75727030" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Nov 2021 08:06:30 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 8 Nov 2021 08:06:25 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Mon, 8 Nov 2021 08:06:20 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH 01/13] dt-bindings: interrupt-controller: create a header for RISC-V interrupts Date: Mon, 8 Nov 2021 15:05:42 +0000 Message-ID: <20211108150554.4457-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211108150554.4457-1-conor.dooley@microchip.com> References: <20211108150554.4457-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Ivan Griffin Provide named identifiers for device tree for RISC-V interrupts. Licensed under GPL and MIT, as this file may be useful to any OS that uses device tree. Signed-off-by: Ivan Griffin Signed-off-by: Conor Dooley Acked-by: Rob Herring --- .../interrupt-controller/riscv-hart.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h diff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h b/include/dt-bindings/interrupt-controller/riscv-hart.h new file mode 100644 index 000000000000..e1c32f6090ac --- /dev/null +++ b/include/dt-bindings/interrupt-controller/riscv-hart.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2021 Microchip Technology Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H + +#define HART_INT_U_SOFT 0 +#define HART_INT_S_SOFT 1 +#define HART_INT_M_SOFT 3 +#define HART_INT_U_TIMER 4 +#define HART_INT_S_TIMER 5 +#define HART_INT_M_TIMER 7 +#define HART_INT_U_EXT 8 +#define HART_INT_S_EXT 9 +#define HART_INT_M_EXT 11 + +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */ From patchwork Mon Nov 8 15:05:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12608575 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 600E2C433FE for ; Mon, 8 Nov 2021 15:06:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 475DA61390 for ; Mon, 8 Nov 2021 15:06:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240711AbhKHPJj (ORCPT ); Mon, 8 Nov 2021 10:09:39 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:1626 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240713AbhKHPJ1 (ORCPT ); Mon, 8 Nov 2021 10:09:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1636384003; x=1667920003; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BN4mDvCXCNqjJLbkYo2UnAm38U+/IvQVORj+MpQsb2s=; b=HkLPkoF3zsR6yzmhuyqOSo26nFDnd/qPa+5D3+6rTCq8/SSC74kCadCE 4zr7HnJy5hhzWlEexHq/TN1KZoIdU1YJFMSmgJS67qlOuUUjXaVAbIvth rF5QEzlP4F1jcvaGnBWMXAEmGO8XZzOq3g9MuDmdeSfNi5das8eF7LRWM rW8hL7stRNQMUOceNlh8fBwvl+U5f/N/6XmxN8qasUTbcyQwXEqVmu2MQ y8u0yuAqx89uZ2MDlC2jZaBUWf/+iuNsqn+HBoCH91bcXAImuZ56ctfLj R1Q60GjNz7kAfyoKO5SlLp0oRXEEkxlU5DZMRnzO05EKvg7KU2jTIGyKc w==; IronPort-SDR: hYEsGNvlMkycxQH+Bhj6UhhxbcFwNZqm2s9a0At7/+ZEvNQhqruJH8y/DR4exZETVNT2ve+v5O 5gspF6U++90UPhJqREFzqkAA6Qbwl1dHPV+tH59gjUU88GIZ3WBGkYn8SwidMVjDSduMcbUscu y1obcgDYcXBeXx6odyCN9yr56BxAGwFpeez5rGFH8cKOFsOOWzqN6p65oI4kYr5VzOrcmVU1Tp iCfs1einVdgD3iRQ/nO1snNUMTHiy246qf0dt+lquZ0OFJg63m2yNrLXMvw/XzoRPmM8+irzEt wygNAGK7QCH8uFtdLGwBXOpt X-IronPort-AV: E=Sophos;i="5.87,218,1631602800"; d="scan'208";a="142601826" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Nov 2021 08:06:42 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 8 Nov 2021 08:06:40 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Mon, 8 Nov 2021 08:06:36 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH 02/13] dt-bindings: interrupt-controller: add defines for mpfs-plic Date: Mon, 8 Nov 2021 15:05:43 +0000 Message-ID: <20211108150554.4457-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211108150554.4457-1-conor.dooley@microchip.com> References: <20211108150554.4457-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Ivan Griffin Add device tree bindings for the Microchip Polarfire Soc interrupt controller Signed-off-by: Conor Dooley Signed-off-by: Ivan Griffin --- .../microchip,mpfs-plic.h | 199 ++++++++++++++++++ 1 file changed, 199 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/microchip,mpfs-plic.h diff --git a/include/dt-bindings/interrupt-controller/microchip,mpfs-plic.h b/include/dt-bindings/interrupt-controller/microchip,mpfs-plic.h new file mode 100644 index 000000000000..81c8cd02abd8 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/microchip,mpfs-plic.h @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2021 Microchip Technology Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H + +#define PLIC_INT_INVALID 0 +#define PLIC_INT_L2_METADATA_CORR 1 +#define PLIC_INT_L2_METADAT_UNCORR 2 +#define PLIC_INT_L2_DATA_CORR 3 +#define PLIC_INT_L2_DATA_UNCORR 4 +#define PLIC_INT_DMA_CH0_DONE 5 +#define PLIC_INT_DMA_CH0_ERR 6 +#define PLIC_INT_DMA_CH1_DONE 7 +#define PLIC_INT_DMA_CH1_ERR 8 +#define PLIC_INT_DMA_CH2_DONE 9 +#define PLIC_INT_DMA_CH2_ERR 10 +#define PLIC_INT_DMA_CH3_DONE 11 +#define PLIC_INT_DMA_CH3_ERR 12 + +#define PLIC_INT_GPIO0_BIT0_OR_GPIO2_BIT0 13 +#define PLIC_INT_GPIO0_BIT1_OR_GPIO2_BIT1 14 +#define PLIC_INT_GPIO0_BIT2_OR_GPIO2_BIT2 15 +#define PLIC_INT_GPIO0_BIT3_OR_GPIO2_BIT3 16 +#define PLIC_INT_GPIO0_BIT4_OR_GPIO2_BIT4 17 +#define PLIC_INT_GPIO0_BIT5_OR_GPIO2_BIT5 18 +#define PLIC_INT_GPIO0_BIT6_OR_GPIO2_BIT6 19 +#define PLIC_INT_GPIO0_BIT7_OR_GPIO2_BIT7 20 +#define PLIC_INT_GPIO0_BIT8_OR_GPIO2_BIT8 21 +#define PLIC_INT_GPIO0_BIT9_OR_GPIO2_BIT9 22 +#define PLIC_INT_GPIO0_BIT10_OR_GPIO2_BIT10 23 +#define PLIC_INT_GPIO0_BIT11_OR_GPIO2_BIT11 24 +#define PLIC_INT_GPIO0_BIT12_OR_GPIO2_BIT12 25 +#define PLIC_INT_GPIO0_BIT13_OR_GPIO2_BIT13 26 +#define PLIC_INT_GPIO1_BIT0_OR_GPIO2_BIT14 27 +#define PLIC_INT_GPIO1_BIT1_OR_GPIO2_BIT15 28 +#define PLIC_INT_GPIO1_BIT2_OR_GPIO2_BIT16 29 +#define PLIC_INT_GPIO1_BIT3_OR_GPIO2_BIT17 30 +#define PLIC_INT_GPIO1_BIT4_OR_GPIO2_BIT18 31 +#define PLIC_INT_GPIO1_BIT5_OR_GPIO2_BIT19 32 +#define PLIC_INT_GPIO1_BIT6_OR_GPIO2_BIT20 33 +#define PLIC_INT_GPIO1_BIT7_OR_GPIO2_BIT21 34 +#define PLIC_INT_GPIO1_BIT8_OR_GPIO2_BIT22 35 +#define PLIC_INT_GPIO1_BIT9_OR_GPIO2_BIT23 36 +#define PLIC_INT_GPIO1_BIT10_OR_GPIO2_BIT24 37 +#define PLIC_INT_GPIO1_BIT11_OR_GPIO2_BIT25 38 +#define PLIC_INT_GPIO1_BIT12_OR_GPIO2_BIT26 39 +#define PLIC_INT_GPIO1_BIT13_OR_GPIO2_BIT27 40 +#define PLIC_INT_GPIO1_BIT14_OR_GPIO2_BIT28 41 +#define PLIC_INT_GPIO1_BIT15_OR_GPIO2_BIT29 42 +#define PLIC_INT_GPIO1_BIT16_OR_GPIO2_BIT30 43 +#define PLIC_INT_GPIO1_BIT17_OR_GPIO2_BIT31 44 +#define PLIC_INT_GPIO1_BIT18 45 +#define PLIC_INT_GPIO1_BIT19 46 +#define PLIC_INT_GPIO1_BIT20 47 +#define PLIC_INT_GPIO1_BIT21 48 +#define PLIC_INT_GPIO1_BIT22 49 +#define PLIC_INT_GPIO1_BIT23 50 +#define PLIC_INT_GPIO0_NON_DIRECT 51 +#define PLIC_INT_GPIO1_NON_DIRECT 52 +#define PLIC_INT_GPIO2_NON_DIRECT 53 +#define PLIC_INT_SPI0 54 +#define PLIC_INT_SPI1 55 +#define PLIC_INT_CAN0 56 +#define PLIC_INT_CAN1 57 +#define PLIC_INT_I2C0_MAIN 58 +#define PLIC_INT_I2C0_ALERT 59 +#define PLIC_INT_I2C0_SUS 60 +#define PLIC_INT_I2C1_MAIN 61 +#define PLIC_INT_I2C1_ALERT 62 +#define PLIC_INT_I2C1_SUS 63 +#define PLIC_INT_MAC0_INT 64 +#define PLIC_INT_MAC0_QUEUE1 65 +#define PLIC_INT_MAC0_QUEUE2 66 +#define PLIC_INT_MAC0_QUEUE3 67 +#define PLIC_INT_MAC0_EMAC 68 +#define PLIC_INT_MAC0_MMSL 69 +#define PLIC_INT_MAC1_INT 70 +#define PLIC_INT_MAC1_QUEUE1 71 +#define PLIC_INT_MAC1_QUEUE2 72 +#define PLIC_INT_MAC1_QUEUE3 73 +#define PLIC_INT_MAC1_EMAC 74 +#define PLIC_INT_MAC1_MMSL 75 +#define PLIC_INT_DDRC_TRAIN 76 +#define PLIC_INT_SCB_INTERRUPT 77 +#define PLIC_INT_ECC_ERROR 78 +#define PLIC_INT_ECC_CORRECT 79 +#define PLIC_INT_RTC_WAKEUP 80 +#define PLIC_INT_RTC_MATCH 81 +#define PLIC_INT_TIMER1 82 +#define PLIC_INT_TIMER2 83 +#define PLIC_INT_ENVM 84 +#define PLIC_INT_QSPI 85 +#define PLIC_INT_USB_DMA 86 +#define PLIC_INT_USB_MC 87 +#define PLIC_INT_MMC_MAIN 88 +#define PLIC_INT_MMC_WAKEUP 89 +#define PLIC_INT_MMUART0 90 +#define PLIC_INT_MMUART1 91 +#define PLIC_INT_MMUART2 92 +#define PLIC_INT_MMUART3 93 +#define PLIC_INT_MMUART4 94 +#define PLIC_INT_G5C_DEVRST 95 +#define PLIC_INT_G5C_MESSAGE 96 +#define PLIC_INT_USOC_VC_INTERRUPT 97 +#define PLIC_INT_USOC_SMB_INTERRUPT 98 +#define PLIC_INT_E51_0_MAINTENACE 99 +#define PLIC_INT_WDOG0_MRVP 100 +#define PLIC_INT_WDOG1_MRVP 101 +#define PLIC_INT_WDOG2_MRVP 102 +#define PLIC_INT_WDOG3_MRVP 103 +#define PLIC_INT_WDOG4_MRVP 104 +#define PLIC_INT_WDOG0_TOUT 105 +#define PLIC_INT_WDOG1_TOUT 106 +#define PLIC_INT_WDOG2_TOUT 107 +#define PLIC_INT_WDOG3_TOUT 108 +#define PLIC_INT_WDOG4_TOUT 109 +#define PLIC_INT_G5C_MSS_SPI 110 +#define PLIC_INT_VOLT_TEMP_ALARM 111 +#define PLIC_INT_ATHENA_COMPLETE 112 +#define PLIC_INT_ATHENA_ALARM 113 +#define PLIC_INT_ATHENA_BUS_ERROR 114 +#define PLIC_INT_USOC_AXIC_US 115 +#define PLIC_INT_USOC_AXIC_DS 116 +#define PLIC_INT_SPARE 117 + +#define PLIC_INT_FABRIC_F2H_0 118 +#define PLIC_INT_FABRIC_F2H_1 119 +#define PLIC_INT_FABRIC_F2H_2 120 +#define PLIC_INT_FABRIC_F2H_3 121 +#define PLIC_INT_FABRIC_F2H_4 122 +#define PLIC_INT_FABRIC_F2H_5 123 +#define PLIC_INT_FABRIC_F2H_6 124 +#define PLIC_INT_FABRIC_F2H_7 125 +#define PLIC_INT_FABRIC_F2H_8 126 +#define PLIC_INT_FABRIC_F2H_9 127 +#define PLIC_INT_FABRIC_F2H_10 128 +#define PLIC_INT_FABRIC_F2H_11 129 +#define PLIC_INT_FABRIC_F2H_12 130 +#define PLIC_INT_FABRIC_F2H_13 131 +#define PLIC_INT_FABRIC_F2H_14 132 +#define PLIC_INT_FABRIC_F2H_15 133 +#define PLIC_INT_FABRIC_F2H_16 134 +#define PLIC_INT_FABRIC_F2H_17 135 +#define PLIC_INT_FABRIC_F2H_18 136 +#define PLIC_INT_FABRIC_F2H_19 137 +#define PLIC_INT_FABRIC_F2H_20 138 +#define PLIC_INT_FABRIC_F2H_21 139 +#define PLIC_INT_FABRIC_F2H_22 140 +#define PLIC_INT_FABRIC_F2H_23 141 +#define PLIC_INT_FABRIC_F2H_24 142 +#define PLIC_INT_FABRIC_F2H_25 143 +#define PLIC_INT_FABRIC_F2H_26 144 +#define PLIC_INT_FABRIC_F2H_27 145 +#define PLIC_INT_FABRIC_F2H_28 146 +#define PLIC_INT_FABRIC_F2H_29 147 +#define PLIC_INT_FABRIC_F2H_30 148 +#define PLIC_INT_FABRIC_F2H_31 149 +#define PLIC_INT_FABRIC_F2H_32 150 +#define PLIC_INT_FABRIC_F2H_33 151 +#define PLIC_INT_FABRIC_F2H_34 152 +#define PLIC_INT_FABRIC_F2H_35 153 +#define PLIC_INT_FABRIC_F2H_36 154 +#define PLIC_INT_FABRIC_F2H_37 155 +#define PLIC_INT_FABRIC_F2H_38 156 +#define PLIC_INT_FABRIC_F2H_39 157 +#define PLIC_INT_FABRIC_F2H_40 158 +#define PLIC_INT_FABRIC_F2H_41 159 +#define PLIC_INT_FABRIC_F2H_42 160 +#define PLIC_INT_FABRIC_F2H_43 161 +#define PLIC_INT_FABRIC_F2H_44 162 +#define PLIC_INT_FABRIC_F2H_45 163 +#define PLIC_INT_FABRIC_F2H_46 164 +#define PLIC_INT_FABRIC_F2H_47 165 +#define PLIC_INT_FABRIC_F2H_48 166 +#define PLIC_INT_FABRIC_F2H_49 167 +#define PLIC_INT_FABRIC_F2H_50 168 +#define PLIC_INT_FABRIC_F2H_51 169 +#define PLIC_INT_FABRIC_F2H_52 170 +#define PLIC_INT_FABRIC_F2H_53 171 +#define PLIC_INT_FABRIC_F2H_54 172 +#define PLIC_INT_FABRIC_F2H_55 173 +#define PLIC_INT_FABRIC_F2H_56 174 +#define PLIC_INT_FABRIC_F2H_57 175 +#define PLIC_INT_FABRIC_F2H_58 176 +#define PLIC_INT_FABRIC_F2H_59 177 +#define PLIC_INT_FABRIC_F2H_60 178 +#define PLIC_INT_FABRIC_F2H_61 179 +#define PLIC_INT_FABRIC_F2H_62 180 +#define PLIC_INT_FABRIC_F2H_63 181 +#define PLIC_INT_BUS_ERROR_UNIT_HART_0 182 +#define PLIC_INT_BUS_ERROR_UNIT_HART_1 183 +#define PLIC_INT_BUS_ERROR_UNIT_HART_2 184 +#define PLIC_INT_BUS_ERROR_UNIT_HART_3 185 +#define PLIC_INT_BUS_ERROR_UNIT_HART_4 186 + +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H */ From patchwork Mon Nov 8 15:05:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12608577 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 093B6C433EF for ; Mon, 8 Nov 2021 15:07:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E228861053 for ; Mon, 8 Nov 2021 15:07:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240736AbhKHPJ4 (ORCPT ); Mon, 8 Nov 2021 10:09:56 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:21281 "EHLO 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Date: Mon, 8 Nov 2021 15:05:44 +0000 Message-ID: <20211108150554.4457-4-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211108150554.4457-1-conor.dooley@microchip.com> References: <20211108150554.4457-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Conor Dooley Update 'compatible' strings for system controller drivers to the approved Microchip name. Signed-off-by: Conor Dooley --- .../bindings/mailbox/microchip,polarfire-soc-mailbox.yaml | 4 +++- .../soc/microchip/microchip,polarfire-soc-sys-controller.yaml | 4 +++- drivers/mailbox/mailbox-mpfs.c | 1 + 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml index bbb173ea483c..b08c8a158eea 100644 --- a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml @@ -11,7 +11,9 @@ maintainers: properties: compatible: - const: microchip,polarfire-soc-mailbox + enum: + - microchip,polarfire-soc-mailbox + - microchip,mpfs-mailbox reg: items: diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml index 2cd3bc6bd8d6..d6c953cd154b 100644 --- a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml @@ -19,7 +19,9 @@ properties: maxItems: 1 compatible: - const: microchip,polarfire-soc-sys-controller + enum: + - microchip,polarfire-soc-sys-controller + - microchip,mpfs-sys-controller required: - compatible diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c index 0d6e2231a2c7..9d5e558a6ee6 100644 --- a/drivers/mailbox/mailbox-mpfs.c +++ b/drivers/mailbox/mailbox-mpfs.c @@ -233,6 +233,7 @@ static int mpfs_mbox_probe(struct platform_device *pdev) static const struct of_device_id mpfs_mbox_of_match[] = { {.compatible = "microchip,polarfire-soc-mailbox", }, + {.compatible = "microchip,mpfs-mailbox", }, {}, }; MODULE_DEVICE_TABLE(of, mpfs_mbox_of_match); From patchwork Mon Nov 8 15:05:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12608579 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F124C4332F for ; Mon, 8 Nov 2021 15:07:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8B68461207 for ; Mon, 8 Nov 2021 15:07:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240716AbhKHPKV (ORCPT ); Mon, 8 Nov 2021 10:10:21 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:21310 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240749AbhKHPJn (ORCPT ); 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d="scan'208";a="75727206" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Nov 2021 08:06:57 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 8 Nov 2021 08:06:55 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Mon, 8 Nov 2021 08:06:51 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH 04/13] dt-bindings: riscv: update microchip polarfire binds Date: Mon, 8 Nov 2021 15:05:45 +0000 Message-ID: <20211108150554.4457-5-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211108150554.4457-1-conor.dooley@microchip.com> References: <20211108150554.4457-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Conor Dooley Add mpfs-soc to clear undocumented binding warning Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/microchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 3f981e897126..1ff7a5224bbc 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -21,6 +21,7 @@ properties: - enum: - microchip,mpfs-icicle-kit - const: microchip,mpfs + - const: microchip,mpfs-soc additionalProperties: true From patchwork Mon Nov 8 15:05:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12608581 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B765C433FE for ; Mon, 8 Nov 2021 15:07:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F31AD6113A for ; Mon, 8 Nov 2021 15:07:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240815AbhKHPK0 (ORCPT ); Mon, 8 Nov 2021 10:10:26 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:21335 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240769AbhKHPJt (ORCPT ); Mon, 8 Nov 2021 10:09:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; 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08 Nov 2021 08:07:04 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 8 Nov 2021 08:07:03 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Mon, 8 Nov 2021 08:06:59 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH 05/13] dt-bindings: i2c: add bindings for microchip mpfs i2c Date: Mon, 8 Nov 2021 15:05:46 +0000 Message-ID: <20211108150554.4457-6-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211108150554.4457-1-conor.dooley@microchip.com> References: <20211108150554.4457-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Conor Dooley Add device tree bindings for the i2c controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley Signed-off-by: Daire McNamara --- .../bindings/i2c/microchip,mpfs-i2c.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml diff --git a/Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml b/Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml new file mode 100644 index 000000000000..bc4ea4498d35 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/microchip,mpfs-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip MPFS I2C Controller Device Tree Bindings + +maintainers: + - Daire McNamara + +description: | + This I2C controller is found on the Microchip PolarFire SoC. + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + enum: + - microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + description: Phandle of the clock feeding the I2C controller. + minItems: 1 + + clock-frequency: + description: | + Desired I2C bus clock frequency in Hz. As only Standard and Fast + modes are supported, possible values are 100000 and 400000. + enum: [100000, 400000] + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + i2c@2010a000 { + compatible = "microchip,mpfs-i2c"; + reg = <0 0x2010a000 0 0x1000>; + interrupts = <58>; + clock-frequency = <100000>; + clocks = <&clkcfg CLK_I2C0>; + }; + }; + - | + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + i2c@2010b000 { + compatible = "microchip,mpfs-i2c"; + reg = <0 0x2010b000 0 0x1000>; + interrupts = <61>; + clock-frequency = <100000>; + clocks = <&clkcfg CLK_I2C1>; + }; + }; +... From patchwork Mon Nov 8 15:05:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12608583 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3032BC433F5 for ; Mon, 8 Nov 2021 15:07:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1A75461053 for ; Mon, 8 Nov 2021 15:07:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240728AbhKHPKb (ORCPT ); Mon, 8 Nov 2021 10:10:31 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:20358 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240779AbhKHPJy (ORCPT ); Mon, 8 Nov 2021 10:09:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1636384030; x=1667920030; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RnzRJe2j8YUJD/3ju4Zm4B76UxmFkkmN8AGI+FaOFNU=; b=q0om1p1V3kq/jjkHmCrMXPBs9zm8L7an7vU2kPTfmWftyWwaqceqKiVd v3olxGDNqs4hShKqhvOs0EtAp+EDBrxh1gVPKEBp/kItSSYLMW2xOLGT+ nqjQKcLbRIPBswaalhr+HsyfNZITHJHgwYCwBLKVHbr1+cuGntmC2OITT StfdIBdR0DwXD0ZErB2+7rcx31vlcqQ7iHlYNVQ59fBfBLGWuv+ISR8L4 Hr4KX38ZwEAulGPHZzPKyQqEn5s4Ne0KjsUjSEA1cDUVGGJIi58YRTXfG WdE0iCcxof+s6DN+9sO6MO38JSM7ELPNWsF4OjekS3J4WPqwIA4qTPqtn Q==; IronPort-SDR: gRM9iGd4Z5kToPIKmNPXQJXDF74gHh3Qo/SQy68lOs7xfksj32OLdrRet39IwAnqbcxVpWSF1x Om/cp2zzU/XZeZT32IWIF6eXbpTio0E2wGCnnNZiQD2j1RprcGHR6fQE3QnnYFNc/0+/7GgOIg flFvtFBBEmrN2e22JogEyWkClpz//rA0ip/1RYhkteMHHOvSpAQflRaXk3QmZlH/6q4iwPTpHK wraOZ/noYzF6L6qkLTvBJch64MSkn4v6UL61drg0xlUuSAkfGJWjOrq1LvuqRldaFOO4IiKETQ PcIJ0sR1bKLCGofpRBaG7huf X-IronPort-AV: E=Sophos;i="5.87,218,1631602800"; d="scan'208";a="143179818" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Nov 2021 08:07:08 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 8 Nov 2021 08:07:08 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Mon, 8 Nov 2021 08:07:04 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH 06/13] dt-bindings: rng: add bindings for microchip mpfs rng Date: Mon, 8 Nov 2021 15:05:47 +0000 Message-ID: <20211108150554.4457-7-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211108150554.4457-1-conor.dooley@microchip.com> References: <20211108150554.4457-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Conor Dooley Add device tree bindings for the hardware rng device accessed via the system services on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- .../bindings/rng/microchip,mpfs-rng.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml diff --git a/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml new file mode 100644 index 000000000000..e8ecb3538a86 --- /dev/null +++ b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/rng/microchip,mpfs-rng.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip MPFS random number generator + +maintainers: + - Conor Dooley + +properties: + compatible: + const: microchip,polarfire-soc-rng + + syscontroller: + maxItems: 1 + description: name of the system controller device node + +required: + - compatible + - "syscontroller" + +additionalProperties: false + +examples: + - | + hwrandom: hwrandom { + compatible = "microchip,polarfire-soc-rng"; + syscontroller = <&syscontroller>; + }; From patchwork Mon Nov 8 15:05:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12608585 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D6F6C4332F for ; Mon, 8 Nov 2021 15:07:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0BC6A61361 for ; Mon, 8 Nov 2021 15:07:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240871AbhKHPKi (ORCPT ); Mon, 8 Nov 2021 10:10:38 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:21281 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240781AbhKHPKA (ORCPT ); Mon, 8 Nov 2021 10:10:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1636384036; x=1667920036; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2bunDyf7QdoO97mJxTZcNYPQXz2FP977/gYahndmmno=; b=s9Y2LfChTje/zvt0SStTGRBC8E1NGyQTWKbhedh9j1kwax/ZjJA+4EWG X1ZUddQ3SnEXpPw+93bsFvagnG3PcADWJ9jAQN2949ovgVVSZEvMq5vVe rvAf5hJQ8c7IYFdseMeN1cQsTaz0PsOAQ/F1LnF+rdW5zRMMxk6gRb1B7 XVFYUsX/X5ScBGrHKV/hnlvIuR3NhaAlrsIbV8mvw3hyGDehy/orh3G3C W0U2r7QKGgYNgtWfCy+v+7zFZX47XfozB0AAUEznAC9LuA6zlAuzend07 YQUEBv620DmYXvDFoSBQ5+JEa6/4gvIAP5N+FuP+zTYHz9XW1UzMobOjt Q==; IronPort-SDR: J/W+WCXDkghFIAGAt5mOOrNV0DnRs7aFzNyIDg3V/oa+LvgnNE+h5CPqNTLdb7A6YoTZ6mIEp7 ipxyL3AlrNVwdKccME4qlf7pvp26kpglWgNh0okRmn3SHI1/aWYjjQ+Tl9xnH/k4cUqzmm7Ibc KGzpx1N8EKxjss94+Ns1LRhIkrmGJ4l0oHWIcWS9kB2U+59mEjUomaZP4HyjRYBxxhBPtq/bp2 NszeqTvHA1NTbFRe9qlGUdN4tnFHjiCsWNIYiKX2bpqfzgbjWMLQSwF92UmOWEMWS71ztartWo om3KGbOZbiW8yci3tXjX9PJA X-IronPort-AV: E=Sophos;i="5.87,218,1631602800"; d="scan'208";a="75727263" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Nov 2021 08:07:14 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 8 Nov 2021 08:07:14 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Mon, 8 Nov 2021 08:07:10 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH 07/13] dt-bindings: rtc: add bindings for microchip mpfs rtc Date: Mon, 8 Nov 2021 15:05:48 +0000 Message-ID: <20211108150554.4457-8-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211108150554.4457-1-conor.dooley@microchip.com> References: <20211108150554.4457-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Conor Dooley Add device tree bindings for the real time clock on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley Signed-off-by: Daire McNamara --- .../bindings/rtc/microchip,mfps-rtc.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml new file mode 100644 index 000000000000..c82b3e7351e0 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml# + +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings + +allOf: + - $ref: "rtc.yaml#" + +maintainers: + - Daire McNamara + - Lewis Hanly + +properties: + compatible: + enum: + - microchip,mpfs-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + prescaler: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: rtc + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + rtc@20124000 { + compatible = "microchip,mpfs-rtc"; + reg = <0 0x20124000 0 0x1000>; + clocks = <&clkcfg CLK_RTC>; + clock-names = "rtc"; + interrupts = <80>; + }; + }; +... From patchwork Mon Nov 8 15:05:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12608589 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59374C433F5 for ; Mon, 8 Nov 2021 15:08:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 42B9F61053 for ; Mon, 8 Nov 2021 15:08:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240875AbhKHPKj (ORCPT ); Mon, 8 Nov 2021 10:10:39 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:1701 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240743AbhKHPKG (ORCPT ); Mon, 8 Nov 2021 10:10:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1636384042; x=1667920042; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=F223P+LHyG+a0gJr80sI/UE2JykLqh7/ehIIfBDOW8g=; b=h9tlJiIo/GPA2PWEUbDFdi4/myeNdsHSgQtt7PFD/JiQouY+9SWNPTj+ iJ7XB0En7nie/bj+WM1/Y8gAXOJgvQwuJGgMmriUvyNX7nVs7RRoqq2yS wOL9PeFFhix2nsigfoFEh5EXKN6VS8fjCs5PjFUetR1oMFAi5cLVPlxYR Mw8Ci5nqq9/ulLyA53qxLN8JkN+h146Tu3OHxldS8bDMJwVUFnDKFk0oT s4s9hAGXxmh3ksGHGlmEDSqzfSwMbbyRPS1JURTTpUcv1Nd37Aa/t3rZa vf2wjuyBc1CFW4R8XEh7jHlya0sp2VGN1mVpdcXmna6QKxlykVqw328GS w==; IronPort-SDR: LotEgQwU7ZY6BNm4ah1XgQEO/UjY+3RM6gsVefFeUIFWBJan6unqHZ2yffCijMkI00ptRI6Gau x73O72vNDJ/Mma+7XTsUdFdoZqL69pl1NfPDOdFYULoGQmOEbDi0OSOYUHSvtf9zVaRKozCqV/ UdJK1U2tAHbIlFrjUt31zeqSqQ2StvODqQbz96Me3GmV6366fLwQIRgeKds1Dj/sQFdFWnNfP9 IdXABMSaKz7swchhprsDNraKlVO1SlKxrIYhD4BP5g0DdWAEhgkVcmIkiGPmLfnlDuGUNePSLF PUoDQOSoLOdvYFMhx+VDLUpq X-IronPort-AV: E=Sophos;i="5.87,218,1631602800"; d="scan'208";a="142601885" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Nov 2021 08:07:21 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 8 Nov 2021 08:07:20 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Mon, 8 Nov 2021 08:07:16 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH 08/13] dt-bindings: soc/microchip: add bindings for mpfs system services Date: Mon, 8 Nov 2021 15:05:49 +0000 Message-ID: <20211108150554.4457-9-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211108150554.4457-1-conor.dooley@microchip.com> References: <20211108150554.4457-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Conor Dooley Add device tree bindings for the services provided by the system controller directly on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- .../microchip,mpfs-generic-service.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml new file mode 100644 index 000000000000..f89d3a74c059 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs-generic-service.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip MPFS system services + +maintainers: + - Conor Dooley + +properties: + compatible: + const: microchip,mpfs-generic-service + + syscontroller: + maxItems: 1 + description: name of the system controller device node + +required: + - compatible + - "syscontroller" + +additionalProperties: false + +examples: + - | + sysserv: sysserv { + compatible = "microchip,mpfs-generic-service"; + syscontroller = <&syscontroller>; + }; From patchwork Mon Nov 8 15:05:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12608587 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F48DC433FE for ; Mon, 8 Nov 2021 15:08:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4EE8C61215 for ; Mon, 8 Nov 2021 15:08:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240886AbhKHPKk (ORCPT ); Mon, 8 Nov 2021 10:10:40 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:21310 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240790AbhKHPKL (ORCPT ); Mon, 8 Nov 2021 10:10:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1636384047; x=1667920047; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+3o7Ep3ggxTrUD7AgFLSIjR7aDwUI0lZ+wyKLhTBdoE=; b=KD9ui0EEYxiZOXVzMA4UIYafMzde8JQ1YwQ/PbVv3v+M/6kuUZjtOoOc 3l8eY7R2Z62W5dtAEX5fdVh2y+tw62UYM+uBCJff2BaNetHFqS/sNkfYx NWrbFVaUw9f+Q7lAxsAV2y0RBfV+BlgXAIAvVPk6Hg4L0UXt4Zk3STVjl cwJ3EcPIDRAk5sdJwCQz9P7PBeNy0XtHBmBcM6h/3qG0o4U2t9XYFOgZC p4xXRYQJuOQjFWMxinfVXDD/U/ezoOqSwBh+azI0d0eJX28kjJ55N4CyD K0ed034IHG4JHskDzOS5rZuozcV7M40WW+TbWfaC9MyMUmxTkhBOtd+xY Q==; IronPort-SDR: H9KfRQVr29ONAOeeKwJ4wRdtbGxcj6WZeG6xFYv1D17i+Ca/aaVz3NYOw4ZardmietpTLl/i1k S6yB6OefoUQE/gizhfNvPBMwJCRmUtnGmcJha77xZVAucMOlIy6XD4p74aCWucthXMW7AlqC/Y AzByZPuIPZnvS/Or7/Lkpdqr9HKuL02nWqPDOCIh+0qYbnMCx7cjrq04XcPNISnt6RLmFrajLQ 6IREsZIdtlYpaNSCV1lyhVZ7cQsWcGz7VVCNSlOqczhG4oxWiAMOfHdsoBKa3Lw7ADczEQSY7n 2baBAcVBhdMyQBrJGh2eNsB6 X-IronPort-AV: E=Sophos;i="5.87,218,1631602800"; d="scan'208";a="75727291" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Nov 2021 08:07:25 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 8 Nov 2021 08:07:25 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Mon, 8 Nov 2021 08:07:21 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH 09/13] dt-bindings: gpio: add bindings for microchip mpfs gpio Date: Mon, 8 Nov 2021 15:05:50 +0000 Message-ID: <20211108150554.4457-10-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211108150554.4457-1-conor.dooley@microchip.com> References: <20211108150554.4457-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Conor Dooley Add device tree bindings for the gpio controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- .../bindings/gpio/microchip,mpfs-gpio.yaml | 108 ++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml new file mode 100644 index 000000000000..067019ddc1f7 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip MPFS GPIO Controller Device Tree Bindings + +maintainers: + - Conor Dooley + +description: | + This GPIO controller is found on the Microchip PolarFire SoC. + +properties: + compatible: + items: + - enum: + - microchip,mpfs-gpio + - microsemi,ms-pf-mss-gpio + + reg: + maxItems: 1 + + interrupts: + description: + Interrupt mapping, one per GPIO. Maximum 32 GPIOs. + minItems: 1 + maxItems: 32 + + interrupt-controller: true + + clocks: + maxItems: 1 + + "#gpio-cells": + const: 2 + + ngpios: + description: + The number of GPIOs available. + minimum: 1 + maximum: 32 + default: 32 + + gpio-controller: true + +required: + - compatible + - reg + - interrupts + - "#interrupt-cells" + - "#gpio-cells" + - gpio-controller + - clocks + +additionalProperties: false + +examples: + - | + #include "dt-bindings/clock/microchip,mpfs-clock.h" + #include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h" + soc { + #address-cells = <2>; + #size-cells = <2>; + gpio2: gpio@20122000 { + compatible = "microchip,mpfs-gpio"; + reg = <0x0 0x20122000 0x0 0x1000>; + clocks = <&clkcfg CLK_GPIO2>; + interrupt-parent = <&plic>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + }; +... From patchwork Mon Nov 8 15:05:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12608685 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A296C433EF for ; Mon, 8 Nov 2021 15:08:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 640DE6113A for ; Mon, 8 Nov 2021 15:08:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238151AbhKHPLZ (ORCPT ); Mon, 8 Nov 2021 10:11:25 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:39196 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240713AbhKHPKV (ORCPT ); Mon, 8 Nov 2021 10:10:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1636384056; x=1667920056; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gPBDUHEHryuXddDlP+HH2IgvmB76SJ44PJ4f76bXn7A=; b=rQp6h8oxxSQ4Hcu/QSri1D4aWEr42QIuT965+o9jygxFtttAovIRX2FA 7lXVDOdgtOc6N242SFMjsgWb2uoI4Se/AsszzMHuxuqn/++yVbnt+TfbP mffJGLCxyYOvyctVYdn8VfJ9uEE9r0WP27BOIFqsVW14IrpXsZBLToadf hPyEBnxu+HRopGFH0d4xrzoaZjyVt7LNbriq2g4mOgduYJgcrC9m6qC6I EafT5U/ZeUSOvd9rHla6BITR2pSlXgUqnVsL9kOwtmGASAR/9hWDpt8ZF l5OnGsTRqt+n0sq95ucizw0zh/PYk/m92/mAJsQZz4Ssxyy7YJVFwctw1 w==; IronPort-SDR: GijAFQ3AR/eI2hQHdOazGp7fs6k3h/fM6DoGTF3/PI9F5jaeI+mLWWaA5/+heeXk/zOAI36I/5 AyIIlzaiFz1zAj/XndPfJmSaVnWQyd264KIV1Ad7CnjoAmXbCajbGQl4dVtrN1OQfwiSMJIp+t PINcl39dudouAPo+ZM3734ygn59wCQZ3BKzZXyoQX4Nlp50uc8zxD0hWmFizPO9ZGXwmKq/nYh VbPAcJa5QLqcBdhJJxZY8tZlj5UK0vn4TYzdXHZnzsolTjOH2ZUVXYuD7rF1OY/prqRp6vAgLe W0s+ZMBC32dHW3/httigaMOp X-IronPort-AV: E=Sophos;i="5.87,218,1631602800"; d="scan'208";a="151131546" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Nov 2021 08:07:35 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 8 Nov 2021 08:07:32 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Mon, 8 Nov 2021 08:07:28 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH 10/13] dt-bindings: spi: add bindings for microchip mpfs spi Date: Mon, 8 Nov 2021 15:05:51 +0000 Message-ID: <20211108150554.4457-11-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211108150554.4457-1-conor.dooley@microchip.com> References: <20211108150554.4457-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Conor Dooley Add device tree bindings for the {q,}spi controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- .../bindings/spi/microchip,mpfs-spi.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml new file mode 100644 index 000000000000..efed145ad029 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip MPFS {Q,}SPI Controller Device Tree Bindings + +maintainers: + - Conor Dooley + +description: | + This {Q,}SPI controller is found on the Microchip PolarFire SoC. + +allOf: + - $ref: "spi-controller.yaml#" + +properties: + compatible: + enum: + - microchip,mpfs-spi + - microsemi,ms-pf-mss-spi + - microchip,mpfs-qspi + - microsemi,ms-pf-mss-qspi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + maxItems: 1 + + clocks: + maxItems: 2 + + num-cs: + description: | + Number of chip selects used. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 8 + default: 8 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include "dt-bindings/clock/microchip,mpfs-clock.h" + #include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h" + soc { + #address-cells = <2>; + #size-cells = <2>; + spi0: spi@20108000 { + compatible = "microchip,mpfs-spi"; + reg = <0x0 0x20108000 0x0 0x1000>; + clocks = <&clkcfg CLK_SPI0>; + interrupt-parent = <&plic>; + interrupts = ; + spi-max-frequency = <25000000>; + num-cs = <8>; + status = "disabled"; + }; + }; +... From patchwork Mon Nov 8 15:05:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12608687 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 712EAC433F5 for ; Mon, 8 Nov 2021 15:08:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 57AFF61027 for ; Mon, 8 Nov 2021 15:08:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240772AbhKHPL3 (ORCPT ); Mon, 8 Nov 2021 10:11:29 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:21335 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240767AbhKHPK0 (ORCPT ); Mon, 8 Nov 2021 10:10:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1636384062; x=1667920062; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2n9GIVVmCiRGA0iC1L+MwladkBD7mqRRs9RpfrJ5md4=; b=w3Qox3vV4dvClLAM8u1N0ci2WzXmENBBNBnHG4mjPOyE5ryVJeK5+9LA F1R8O1nREJWp3KyskbHZkXsO2/7OIaJTu6Q+8uE5ciCDPzC3ycge6xWBB Fq7HK86V8buMHlFAO9JyDOtwKZ1brTvaGdpXvIl2z8NXmQnCcPMRdiXHa 1xTlWFb+Ubp+wvyn4yuWuYWr/4EOvKSJP88Gr21PJY8fW/pQmqXycbVFo gRoExPi+XEbhGL5CSjU2U0lZWvXsqJm9GNKt9vJ80kCG6q+QGg/4vntd2 OHoNIdsjNzuPJdnATkOxcuuf1VWptq5JWE9YoVXZdQMzgRoWb83BYuD+g w==; IronPort-SDR: r7HbJwr7nexggEpFJSRbMyvcbV+vuw7mdk4Dwj6UvhaaU2wF6vXwT3vPJ2zpHGbF9DMntkXnF6 RjqpXDvVlyM26NG5XITgpyj2WgYyz5vGsg1IWIfN1RywZ+Uu5qj50VKZ4K5KBnYZfA9OZKpWb4 j8170KXE3xPHqfFiitgen3YtXWjmwdLwXtC1gAnadV6MyXUTgFk3to8aKPboYGqaMtRWVUzB4J W78+mRWg/ZGo5kBCaldVWbaMWti3jiQeK9OcyQ1oDC0hmvl+ac+o2eYChkEhZrPXrPH6M0+Dhm icZlJxTAE3IZwvz1+5V++bT6 X-IronPort-AV: E=Sophos;i="5.87,218,1631602800"; d="scan'208";a="75727308" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Nov 2021 08:07:38 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 8 Nov 2021 08:07:38 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Mon, 8 Nov 2021 08:07:34 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH 11/13] dt-bindings: usb: add bindings for microchip mpfs musb Date: Mon, 8 Nov 2021 15:05:52 +0000 Message-ID: <20211108150554.4457-12-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211108150554.4457-1-conor.dooley@microchip.com> References: <20211108150554.4457-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Conor Dooley Add device tree bindings for the usb controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- .../bindings/usb/microchip,mpfs-usb-host.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.yaml diff --git a/Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.yaml b/Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.yaml new file mode 100644 index 000000000000..b867f49e7d70 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/microchip,mpfs-usb-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip MPFS USB Controller Device Tree Bindings + +maintainers: + - Conor Dooley + +description: | + This USB controller is found on the Microchip PolarFire SoC. + +properties: + compatible: + enum: + - microchip,mpfs-usb-host + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + minItems: 2 + items: + - const: dma + - const: mc + + clocks: + maxItems: 1 + + dr_mode: + enum: + - host + - otg + - peripheral + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - dr_mode + +additionalProperties: false + +examples: + - | + #include "dt-bindings/clock/microchip,mpfs-clock.h" + #include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h" + soc { + #address-cells = <2>; + #size-cells = <2>; + usb: usb@20201000 { + compatible = "microchip,mpfs-usb-host"; + reg = <0x0 0x20201000 0x0 0x1000>; + clocks = <&clkcfg CLK_USB>; + interrupt-parent = <&plic>; + interrupts = ; + interrupt-names = "dma","mc"; + dr_mode = "host"; + status = "disabled"; + }; + }; + +... From patchwork Mon Nov 8 15:05:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12608689 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3020CC4332F for ; Mon, 8 Nov 2021 15:09:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1A13B61378 for ; Mon, 8 Nov 2021 15:09:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238764AbhKHPLo (ORCPT ); Mon, 8 Nov 2021 10:11:44 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:23970 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240847AbhKHPKb (ORCPT ); Mon, 8 Nov 2021 10:10:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1636384067; x=1667920067; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4/7M3z76kv/YIpEtNq9m5VDAc2/s3Mft4/JhKERxudg=; b=dGs1vT+8yzApQa0WeOnLOB143QK4lo8Cj569DCNQr/e1ADcoemCgHuLf TtBKjVoctVwWWTNRJzFlBXxWG3WRjajVm80Atw3YHXjXerVpfCUBXOh5b fo4DjdFxU1LgAOT4BFO905Ul4Ljhy+hwuMgtUwv1N0tt92qHcBGvt3qxA 0t5/NIXsKgKecbfYAiIL6kbIfdbgCl8hvMUVw20nMXeHlzpRhMmX77FHs OZOAZBQJgee6vrz8mcLT9b1SqdtLOogoxaBY3DiZmjitWbIZdejYmI3lH BO+dqUHHY5EOtlnk2C+mGWO2DNnINbj7l7SXG6nAAQZCY3pwiZRZrklvf g==; IronPort-SDR: YN2AR1VoMRvQBh188H0EcEz8m9Hn1Wq0xii8FddSzHY7Ls1iEjaqT+4ASvsR9qp40rF+ZyJKMi P4KouHnUqGS3tb9eIy6A70VhdZoweMmPeleigmq7+4UQVh16gaVdzuBeVx8V7y4rcT3oGfqhmo flMCuR1OMs1L9B5uKvg8gJUanhKz+mFmbuxn5PXcRjbTjrujOWuS78H631V6KimfaLQ9QkCt1p Ns8R3TIWHuXElVSNs2J0b03e5JqOzBaaFR32jx6Fyzb4LYpOmwNj3+N39cAeT+thVilF3e/zLS O9eqEO9BK+6J+wcETh0PEbvh X-IronPort-AV: E=Sophos;i="5.87,218,1631602800"; d="scan'208";a="138382851" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Nov 2021 08:07:45 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 8 Nov 2021 08:07:43 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Mon, 8 Nov 2021 08:07:39 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH 12/13] riscv: icicle-kit: update microchip icicle kit device tree Date: Mon, 8 Nov 2021 15:05:53 +0000 Message-ID: <20211108150554.4457-13-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211108150554.4457-1-conor.dooley@microchip.com> References: <20211108150554.4457-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Conor Dooley Update the device tree for the icicle kit by splitting it into a third part, which contains peripherals in the fpga fabric, add new peripherals (spi, qspi, gpio, rtc, pcie, system services, i2c), update parts of the memory map which have been changed. Signed-off-by: Conor Dooley --- .../dts/microchip/microchip-mpfs-fabric.dtsi | 21 ++ .../microchip/microchip-mpfs-icicle-kit.dts | 159 +++++++-- .../boot/dts/microchip/microchip-mpfs.dtsi | 333 ++++++++++++++---- 3 files changed, 428 insertions(+), 85 deletions(-) create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi new file mode 100644 index 000000000000..8fa3356494f1 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2021 Microchip Technology Inc */ + +/ { + fpgadma: fpgadma@60020000 { + compatible = "microchip,mpfs-fpga-dma-uio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x60020000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = ; + status = "okay"; + }; + + fpgalsram: fpga_lsram@61000000 { + compatible = "generic-uio"; + reg = <0x0 0x61000000 0x0 0x0001000 + 0x14 0x00000000 0x0 0x00010000>; + status = "okay"; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index fc1e5869df1b..4212129fcdf1 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2020 Microchip Technology Inc */ +/* Copyright (c) 2020-2021 Microchip Technology Inc */ /dts-v1/; @@ -13,72 +13,187 @@ / { compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; aliases { - ethernet0 = &emac1; - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; + mmuart0 = &mmuart0; + mmuart1 = &mmuart1; + mmuart2 = &mmuart2; + mmuart3 = &mmuart3; + mmuart4 = &mmuart4; }; chosen { - stdout-path = "serial0:115200n8"; + stdout-path = "mmuart1:115200n8"; }; cpus { timebase-frequency = ; }; - memory@80000000 { + ddrc_cache_lo: memory@80000000 { device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x40000000>; - clocks = <&clkcfg 26>; + reg = <0x0 0x80000000 0x0 0x2e000000>; + clocks = <&clkcfg CLK_DDRC>; + status = "okay"; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type = "memory"; + reg = <0x10 0x0 0x0 0x40000000>; + clocks = <&clkcfg CLK_DDRC>; + status = "okay"; }; }; -&serial0 { +&mmuart1 { status = "okay"; }; -&serial1 { +&mmuart2 { status = "okay"; }; -&serial2 { +&mmuart3 { status = "okay"; }; -&serial3 { +&mmuart4 { status = "okay"; }; &mmc { status = "okay"; - bus-width = <4>; disable-wp; cap-sd-highspeed; + cap-mmc-highspeed; card-detect-delay = <200>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; sd-uhs-sdr104; }; -&emac0 { +&spi0 { + status = "okay"; + spidev@0 { + compatible = "spidev"; + reg = <0>; /* CS 0 */ + spi-max-frequency = <10000000>; + status = "okay"; + }; +}; + +&spi1 { + status = "okay"; +}; + +&qspi { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + pac193x: pac193x@10 { + compatible = "microchip,pac1934"; + reg = <0x10>; + samp-rate = <64>; + status = "okay"; + ch0: channel0 { + uohms-shunt-res = <10000>; + rail-name = "VDDREG"; + channel_enabled; + }; + ch1: channel1 { + uohms-shunt-res = <10000>; + rail-name = "VDDA25"; + channel_enabled; + }; + ch2: channel2 { + uohms-shunt-res = <10000>; + rail-name = "VDD25"; + channel_enabled; + }; + ch3: channel3 { + uohms-shunt-res = <10000>; + rail-name = "VDDA_REG"; + channel_enabled; + }; + }; +}; + +&mac0 { + status = "okay"; phy-mode = "sgmii"; phy-handle = <&phy0>; - phy0: ethernet-phy@8 { - reg = <8>; - ti,fifo-depth = <0x01>; - }; }; -&emac1 { +&mac1 { status = "okay"; phy-mode = "sgmii"; phy-handle = <&phy1>; phy1: ethernet-phy@9 { reg = <9>; - ti,fifo-depth = <0x01>; + ti,fifo-depth = <0x1>; + }; + phy0: ethernet-phy@8 { + reg = <8>; + ti,fifo-depth = <0x1>; }; }; + +&gpio2 { + interrupts = ; + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&mbox { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index c9f6d205d2ba..805e07f0169e 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -1,7 +1,10 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2020 Microchip Technology Inc */ +/* Copyright (c) 2020-2021 Microchip Technology Inc */ -/dts-v1/; +#include "dt-bindings/clock/microchip,mpfs-clock.h" +#include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h" +#include "dt-bindings/interrupt-controller/riscv-hart.h" +#include "microchip-mpfs-fabric.dtsi" / { #address-cells = <2>; @@ -16,8 +19,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { - clock-frequency = <0>; + cpu0: cpu@0 { compatible = "sifive,e51", "sifive,rocket0", "riscv"; device_type = "cpu"; i-cache-block-size = <64>; @@ -25,6 +27,7 @@ cpu@0 { i-cache-size = <16384>; reg = <0>; riscv,isa = "rv64imac"; + clocks = <&clkcfg CLK_CPU>; status = "disabled"; cpu0_intc: interrupt-controller { @@ -34,8 +37,7 @@ cpu0_intc: interrupt-controller { }; }; - cpu@1 { - clock-frequency = <0>; + cpu1: cpu@1 { compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -51,6 +53,7 @@ cpu@1 { mmu-type = "riscv,sv39"; reg = <1>; riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; tlb-split; status = "okay"; @@ -61,8 +64,7 @@ cpu1_intc: interrupt-controller { }; }; - cpu@2 { - clock-frequency = <0>; + cpu2: cpu@2 { compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -78,6 +80,7 @@ cpu@2 { mmu-type = "riscv,sv39"; reg = <2>; riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; tlb-split; status = "okay"; @@ -88,8 +91,7 @@ cpu2_intc: interrupt-controller { }; }; - cpu@3 { - clock-frequency = <0>; + cpu3: cpu@3 { compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -105,6 +107,7 @@ cpu@3 { mmu-type = "riscv,sv39"; reg = <3>; riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; tlb-split; status = "okay"; @@ -115,8 +118,7 @@ cpu3_intc: interrupt-controller { }; }; - cpu@4 { - clock-frequency = <0>; + cpu4: cpu@4 { compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -132,8 +134,10 @@ cpu@4 { mmu-type = "riscv,sv39"; reg = <4>; riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; tlb-split; status = "okay"; + cpu4_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -145,49 +149,55 @@ cpu4_intc: interrupt-controller { soc { #address-cells = <2>; #size-cells = <2>; - compatible = "simple-bus"; + compatible = "microchip,mpfs-soc", "simple-bus"; ranges; - cache-controller@2010000 { + cctrllr: cache-controller@2010000 { compatible = "sifive,fu540-c000-ccache", "cache"; + reg = <0x0 0x2010000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = ; cache-block-size = <64>; cache-level = <2>; cache-sets = <1024>; cache-size = <2097152>; cache-unified; - interrupt-parent = <&plic>; - interrupts = <1 2 3>; - reg = <0x0 0x2010000 0x0 0x1000>; }; - clint@2000000 { + clint: clint@2000000 { compatible = "sifive,fu540-c000-clint", "sifive,clint0"; reg = <0x0 0x2000000 0x0 0xC000>; - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7 - &cpu2_intc 3 &cpu2_intc 7 - &cpu3_intc 3 &cpu3_intc 7 - &cpu4_intc 3 &cpu4_intc 7>; + interrupts-extended = + <&cpu0_intc HART_INT_M_SOFT &cpu0_intc HART_INT_M_TIMER + &cpu1_intc HART_INT_M_SOFT &cpu1_intc HART_INT_M_TIMER + &cpu2_intc HART_INT_M_SOFT &cpu2_intc HART_INT_M_TIMER + &cpu3_intc HART_INT_M_SOFT &cpu3_intc HART_INT_M_TIMER + &cpu4_intc HART_INT_M_SOFT &cpu4_intc HART_INT_M_TIMER>; }; plic: interrupt-controller@c000000 { - #interrupt-cells = <1>; - compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; + compatible = "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; + #interrupt-cells = <1>; riscv,ndev = <186>; interrupt-controller; - interrupts-extended = <&cpu0_intc 11 - &cpu1_intc 11 &cpu1_intc 9 - &cpu2_intc 11 &cpu2_intc 9 - &cpu3_intc 11 &cpu3_intc 9 - &cpu4_intc 11 &cpu4_intc 9>; + interrupts-extended = <&cpu0_intc HART_INT_M_EXT + &cpu1_intc HART_INT_M_EXT &cpu1_intc HART_INT_S_EXT + &cpu2_intc HART_INT_M_EXT &cpu2_intc HART_INT_S_EXT + &cpu3_intc HART_INT_M_EXT &cpu3_intc HART_INT_S_EXT + &cpu4_intc HART_INT_M_EXT &cpu4_intc HART_INT_S_EXT>; }; - dma@3000000 { - compatible = "sifive,fu540-c000-pdma"; + pdma: pdma@3000000 { + compatible = "microchip,mpfs-pdma-uio"; reg = <0x0 0x3000000 0x0 0x8000>; interrupt-parent = <&plic>; - interrupts = <23 24 25 26 27 28 29 30>; + interrupts = ; #dma-cells = <1>; }; @@ -205,7 +215,7 @@ clkcfg: clkcfg@20002000 { clocks = <&refclk>; #clock-cells = <1>; clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ - "mac0", "mac1", "mmc", "timer", /* 4-7 */ + "mac0", "mac1", "mmc", "timer", /* 4-7 */ "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ "i2c1", "can0", "can1", "usb", /* 16-19 */ @@ -214,90 +224,287 @@ clkcfg: clkcfg@20002000 { "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ }; - serial0: serial@20000000 { + mmuart0: serial@20000000 { compatible = "ns16550a"; reg = <0x0 0x20000000 0x0 0x400>; reg-io-width = <4>; reg-shift = <2>; + clocks = <&clkcfg CLK_MMUART0>; interrupt-parent = <&plic>; - interrupts = <90>; + interrupts = ; current-speed = <115200>; - clocks = <&clkcfg 8>; - status = "disabled"; + status = "disabled"; /* Reserved for the HSS */ }; - serial1: serial@20100000 { + mmuart1: serial@20100000 { compatible = "ns16550a"; reg = <0x0 0x20100000 0x0 0x400>; reg-io-width = <4>; reg-shift = <2>; + clocks = <&clkcfg CLK_MMUART1>; interrupt-parent = <&plic>; - interrupts = <91>; + interrupts = ; current-speed = <115200>; - clocks = <&clkcfg 9>; status = "disabled"; }; - serial2: serial@20102000 { + mmuart2: serial@20102000 { compatible = "ns16550a"; reg = <0x0 0x20102000 0x0 0x400>; reg-io-width = <4>; reg-shift = <2>; + clocks = <&clkcfg CLK_MMUART2>; interrupt-parent = <&plic>; - interrupts = <92>; + interrupts = ; current-speed = <115200>; - clocks = <&clkcfg 10>; status = "disabled"; }; - serial3: serial@20104000 { + mmuart3: serial@20104000 { compatible = "ns16550a"; reg = <0x0 0x20104000 0x0 0x400>; reg-io-width = <4>; reg-shift = <2>; + clocks = <&clkcfg CLK_MMUART3>; + interrupt-parent = <&plic>; + interrupts = ; + current-speed = <115200>; + status = "disabled"; + }; + + mmuart4: serial@20106000 { + compatible = "ns16550a"; + reg = <0x0 0x20106000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&clkcfg CLK_MMUART4>; interrupt-parent = <&plic>; - interrupts = <93>; + interrupts = ; current-speed = <115200>; - clocks = <&clkcfg 11>; status = "disabled"; }; - /* Common node entry for emmc/sd */ - mmc: mmc@20008000 { + mmc: mmc@20008000 { /* Common node entry for emmc/sd */ compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; reg = <0x0 0x20008000 0x0 0x1000>; + clocks = <&clkcfg CLK_MMC>; interrupt-parent = <&plic>; - interrupts = <88 89>; - clocks = <&clkcfg 6>; + interrupts = ; max-frequency = <200000000>; status = "disabled"; }; - emac0: ethernet@20110000 { - compatible = "cdns,macb"; - reg = <0x0 0x20110000 0x0 0x2000>; + spi0: spi@20108000 { + compatible = "microchip,mpfs-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20108000 0x0 0x1000>; + clocks = <&clkcfg CLK_SPI0>; interrupt-parent = <&plic>; - interrupts = <64 65 66 67>; - local-mac-address = [00 00 00 00 00 00]; - clocks = <&clkcfg 4>, <&clkcfg 2>; - clock-names = "pclk", "hclk"; + interrupts = ; + spi-max-frequency = <25000000>; + num-cs = <8>; + status = "disabled"; + }; + + spi1: spi@20109000 { + compatible = "microchip,mpfs-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20109000 0x0 0x1000>; + clocks = <&clkcfg CLK_SPI1>; + interrupt-parent = <&plic>; + interrupts = ; + spi-max-frequency = <25000000>; + num-cs = <8>; + status = "disabled"; + }; + + qspi: qspi@21000000 { + compatible = "microchip,mpfs-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21000000 0x0 0x1000>; + clocks = <&clkcfg CLK_QSPI>; + interrupt-parent = <&plic>; + interrupts = ; + spi-max-frequency = <25000000>; + num-cs = <8>; + status = "disabled"; + }; + + i2c0: i2c@2010a000 { + compatible = "microchip,mpfs-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010a000 0x0 0x1000>; + clocks = <&clkcfg CLK_I2C0>; + interrupt-parent = <&plic>; + interrupts = ; + clock-frequency = <100000>; status = "disabled"; + }; + + i2c1: i2c@2010b000 { + compatible = "microchip,mpfs-i2c"; #address-cells = <1>; #size-cells = <0>; + reg = <0x0 0x2010b000 0x0 0x1000>; + clocks = <&clkcfg CLK_I2C1>; + interrupt-parent = <&plic>; + interrupts = ; + clock-frequency = <100000>; + status = "disabled"; }; - emac1: ethernet@20112000 { + mac0: ethernet@20110000 { compatible = "cdns,macb"; - reg = <0x0 0x20112000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20110000 0x0 0x2000>; + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; + clock-names = "pclk", "hclk"; interrupt-parent = <&plic>; - interrupts = <70 71 72 73>; - local-mac-address = [00 00 00 00 00 00]; - clocks = <&clkcfg 5>, <&clkcfg 2>; + interrupts = ; + mac-address = [56 34 12 00 FC 01]; status = "disabled"; + }; + + mac1: ethernet@20112000 { + compatible = "cdns,macb"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20112000 0x0 0x2000>; + clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; clock-names = "pclk", "hclk"; + interrupt-parent = <&plic>; + interrupts = ; + mac-address = [56 34 12 00 FC 02]; + status = "disabled"; + }; + + gpio0: gpio@20120000 { + compatible = "microchip,mpfs-gpio"; + reg = <0x0 0x20120000 0x0 0x1000>; + clocks = <&clkcfg CLK_GPIO0>; + interrupt-parent = <&plic>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpio1: gpio@20121000 { + compatible = "microchip,mpfs-gpio"; + reg = <000 0x20121000 0x0 0x1000>; + clocks = <&clkcfg CLK_GPIO1>; + interrupt-parent = <&plic>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpio2: gpio@20122000 { + compatible = "microchip,mpfs-gpio"; + reg = <0x0 0x20122000 0x0 0x1000>; + clocks = <&clkcfg CLK_GPIO2>; + interrupt-parent = <&plic>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + rtc: rtc@20124000 { + compatible = "microchip,mpfs-rtc"; #address-cells = <1>; #size-cells = <0>; + reg = <0x0 0x20124000 0x0 0x1000>; + clocks = <&clkcfg CLK_RTC>; + clock-names = "rtc"; + interrupt-parent = <&plic>; + interrupts = ; + status = "disabled"; }; + usb: usb@20201000 { + compatible = "microchip,mpfs-usb-host"; + reg = <0x0 0x20201000 0x0 0x1000>; + reg-names = "mc","control"; + clocks = <&clkcfg CLK_USB>; + interrupt-parent = <&plic>; + interrupts = ; + interrupt-names = "dma","mc"; + dr_mode = "host"; + status = "disabled"; + }; + + mbox: mailbox@37020000 { + compatible = "microchip,mpfs-mailbox"; + reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; + interrupt-parent = <&plic>; + interrupts = ; + #mbox-cells = <1>; + status = "disabled"; + }; + + pcie: pcie@2000000000 { + compatible = "microchip,pcie-host-1.0"; + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + device_type = "pci"; + reg = <0x20 0x0 0x0 0x8000000 0x0 0x43000000 0x0 0x10000>; + reg-names = "cfg", "apb"; + clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>; + clock-names = "fic0", "fic1", "fic3"; + bus-range = <0x0 0x7f>; + interrupt-parent = <&plic>; + interrupts = ; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent = <&pcie>; + msi-controller; + mchp,axi-m-atr0 = <0x10 0x0>; + status = "disabled"; + pcie_intc: legacy-interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + syscontroller: syscontroller { + compatible = "microchip,mpfs-sys-controller"; + #address-cells = <1>; + #size-cells = <1>; + mboxes = <&mbox 0>; + }; + + hwrandom: hwrandom { + compatible = "microchip,mpfs-rng"; + #address-cells = <1>; + #size-cells = <1>; + syscontroller = <&syscontroller>; + }; + + sysserv: sysserv { + compatible = "microchip,mpfs-generic-service"; + #address-cells = <1>; + #size-cells = <1>; + syscontroller = <&syscontroller>; + }; }; }; From patchwork Mon Nov 8 15:05:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12608691 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9859BC4321E for ; Mon, 8 Nov 2021 15:09:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 850DF6105A for ; Mon, 8 Nov 2021 15:09:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240877AbhKHPLu (ORCPT ); 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d="scan'208";a="138382872" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Nov 2021 08:07:50 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 8 Nov 2021 08:07:49 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Mon, 8 Nov 2021 08:07:45 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH 13/13] MAINTAINERS: update riscv/microchip entry Date: Mon, 8 Nov 2021 15:05:54 +0000 Message-ID: <20211108150554.4457-14-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211108150554.4457-1-conor.dooley@microchip.com> References: <20211108150554.4457-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Conor Dooley Update the riscv/microchip entry by adding the microchip dts directory and myself as maintainer Signed-off-by: Conor Dooley --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index ca6d6fde85cf..a0000ddd02fd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16077,8 +16077,10 @@ K: riscv RISC-V/MICROCHIP POLARFIRE SOC SUPPORT M: Lewis Hanly +M: Conor Dooley L: linux-riscv@lists.infradead.org S: Supported +F: arch/riscv/boot/dts/microchip/ F: drivers/mailbox/mailbox-mpfs.c F: drivers/soc/microchip/ F: include/soc/microchip/mpfs.h