From patchwork Wed Nov 10 19:15:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DC23C433EF for ; Wed, 10 Nov 2021 19:16:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 856BB6117A for ; Wed, 10 Nov 2021 19:16:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232769AbhKJTTJ (ORCPT ); Wed, 10 Nov 2021 14:19:09 -0500 Received: from www.zeus03.de ([194.117.254.33]:54970 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232707AbhKJTTI (ORCPT ); Wed, 10 Nov 2021 14:19:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=vF1Wsj/PEwKkfb w8YWFv/x2ThhwK4/iSmPZ0sryZuYI=; b=DxK+sTe/mwIUkIkejBdmI08IZBDwtz GMkHbangNcB1/k9Klix60gsU4HA50AUjjD3GaPeslcWeAls2UzVoIxHJF3Z7YHlE 0Rb2cnbvEBdzbMUEa3/yEW8tFO+8i7CCA7Hzsd3IbW5R67xr7tj2k7YRyP51FyR6 0bzxmTCLSwE5U= Received: (qmail 722332 invoked from network); 10 Nov 2021 20:16:19 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:19 +0100 X-UD-Smtp-Session: l3s3148p1@sE2KD3TQ0JogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 01/21] clk: renesas: rcar-gen3: add dummy SDnH clock Date: Wed, 10 Nov 2021 20:15:50 +0100 Message-Id: <20211110191610.5664-2-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Currently, SDnH is handled together with SDn. This caused lots of problems, so we want SDnH as a separate clock. Introduce a dummy SDnH type here which creates a fixed-factor clock with factor 1. That allows us to convert the per-SoC CPG drivers while keeping the old behaviour for now. A later patch then will add the proper functionality. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- Changes since RFC v1: * fixed typo in commit message * added tag from Geert drivers/clk/renesas/rcar-cpg-lib.c | 9 +++++++++ drivers/clk/renesas/rcar-cpg-lib.h | 4 ++++ drivers/clk/renesas/rcar-gen3-cpg.c | 4 ++++ drivers/clk/renesas/rcar-gen3-cpg.h | 4 ++++ 4 files changed, 21 insertions(+) diff --git a/drivers/clk/renesas/rcar-cpg-lib.c b/drivers/clk/renesas/rcar-cpg-lib.c index 5678768ee1f2..351cb9c04f5c 100644 --- a/drivers/clk/renesas/rcar-cpg-lib.c +++ b/drivers/clk/renesas/rcar-cpg-lib.c @@ -65,6 +65,15 @@ void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, /* * SDn Clock */ + +struct clk * __init cpg_sdh_clk_register(const char *name, + void __iomem *sdnckcr, const char *parent_name, + struct raw_notifier_head *notifiers) +{ + /* placeholder during transition */ + return clk_register_fixed_factor(NULL, name, parent_name, 0, 1, 1); +} + #define CPG_SD_STP_HCK BIT(9) #define CPG_SD_STP_CK BIT(8) diff --git a/drivers/clk/renesas/rcar-cpg-lib.h b/drivers/clk/renesas/rcar-cpg-lib.h index d00c91b116ca..548cb9562f35 100644 --- a/drivers/clk/renesas/rcar-cpg-lib.h +++ b/drivers/clk/renesas/rcar-cpg-lib.h @@ -26,6 +26,10 @@ void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set); +struct clk * __init cpg_sdh_clk_register(const char *name, + void __iomem *sdnckcr, const char *parent_name, + struct raw_notifier_head *notifiers); + struct clk * __init cpg_sd_clk_register(const char *name, void __iomem *base, unsigned int offset, const char *parent_name, struct raw_notifier_head *notifiers, bool skip_first); diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 558191c99b48..182b189bc8f4 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -486,6 +486,10 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, mult *= 2; break; + case CLK_TYPE_GEN3_SDH: + return cpg_sdh_clk_register(core->name, base + core->offset, + __clk_get_name(parent), notifiers); + case CLK_TYPE_GEN3_SD: return cpg_sd_clk_register(core->name, base, core->offset, __clk_get_name(parent), notifiers, diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 3d949c4a3244..2bc0afadf604 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -17,6 +17,7 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_PLL2, CLK_TYPE_GEN3_PLL3, CLK_TYPE_GEN3_PLL4, + CLK_TYPE_GEN3_SDH, CLK_TYPE_GEN3_SD, CLK_TYPE_GEN3_R, CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */ @@ -32,6 +33,9 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_SOC_BASE, }; +#define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset) + #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) From patchwork Wed Nov 10 19:15:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F15C2C4332F for ; Wed, 10 Nov 2021 19:16:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DC39F6117A for ; Wed, 10 Nov 2021 19:16:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232707AbhKJTTJ (ORCPT ); Wed, 10 Nov 2021 14:19:09 -0500 Received: from www.zeus03.de ([194.117.254.33]:54982 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232711AbhKJTTI (ORCPT ); Wed, 10 Nov 2021 14:19:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=dewpILHujTjgRL 66LWunFEQH8RiTbff22kNE4pyJ4+g=; b=SCnKOy1WLwfhn7Nwr9+8F+KzdpzI0D H6EmmqWyo0caS16A29FTIjiQIDm0rDnKu2tWD/bgcXam4WRy66AIXhV+tR1tz5Bn YaJd1NK+gRv1gC/Dio8KvJM7D0v2Svdh8QR1MSY4v48uv0oMMM9TkQw0SvGlE213 XfGlb9pq3Mxz0= Received: (qmail 722365 invoked from network); 10 Nov 2021 20:16:19 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:19 +0100 X-UD-Smtp-Session: l3s3148p1@D+OQD3TQ0pogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 02/21] clk: renesas: rcar-gen3: add SDnH clock Date: Wed, 10 Nov 2021 20:15:51 +0100 Message-Id: <20211110191610.5664-3-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Currently a pass-through clock but we will make it a real divider clock in the next patches. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- Changes since RFC v1: * fixed subject prefix * fixed whitespace issues * added tag from Geert drivers/clk/renesas/r8a774a1-cpg-mssr.c | 12 ++++++++---- drivers/clk/renesas/r8a774b1-cpg-mssr.c | 12 ++++++++---- drivers/clk/renesas/r8a774c0-cpg-mssr.c | 9 ++++++--- drivers/clk/renesas/r8a774e1-cpg-mssr.c | 12 ++++++++---- drivers/clk/renesas/r8a7795-cpg-mssr.c | 12 ++++++++---- drivers/clk/renesas/r8a7796-cpg-mssr.c | 12 ++++++++---- drivers/clk/renesas/r8a77965-cpg-mssr.c | 12 ++++++++---- drivers/clk/renesas/r8a77980-cpg-mssr.c | 3 ++- drivers/clk/renesas/r8a77990-cpg-mssr.c | 9 ++++++--- drivers/clk/renesas/r8a77995-cpg-mssr.c | 3 ++- 10 files changed, 64 insertions(+), 32 deletions(-) diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index 39b185d8e957..804f3362763c 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -100,10 +100,14 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { DEF_FIXED("s3d2", R8A774A1_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A774A1_CLK_S3D4, CLK_S3, 4, 1), - DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, CLK_SDSRC, 0x074), - DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078), - DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268), - DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c), + DEF_GEN3_SDH("sd0h", R8A774A1_CLK_SD0H, CLK_SDSRC, 0x074), + DEF_GEN3_SD( "sd0", R8A774A1_CLK_SD0, R8A774A1_CLK_SD0H, 0x074), + DEF_GEN3_SDH("sd1h", R8A774A1_CLK_SD1H, CLK_SDSRC, 0x078), + DEF_GEN3_SD( "sd1", R8A774A1_CLK_SD1, R8A774A1_CLK_SD1H, 0x078), + DEF_GEN3_SDH("sd2h", R8A774A1_CLK_SD2H, CLK_SDSRC, 0x268), + DEF_GEN3_SD( "sd2", R8A774A1_CLK_SD2, R8A774A1_CLK_SD2H, 0x268), + DEF_GEN3_SDH("sd3h", R8A774A1_CLK_SD3H, CLK_SDSRC, 0x26c), + DEF_GEN3_SD( "sd3", R8A774A1_CLK_SD3, R8A774A1_CLK_SD3H, 0x26c), DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1), diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c index af602d83c8ce..97fe5d2227fe 100644 --- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c @@ -97,10 +97,14 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = { DEF_FIXED("s3d2", R8A774B1_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A774B1_CLK_S3D4, CLK_S3, 4, 1), - DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, CLK_SDSRC, 0x074), - DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, CLK_SDSRC, 0x078), - DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, CLK_SDSRC, 0x268), - DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, CLK_SDSRC, 0x26c), + DEF_GEN3_SDH("sd0h", R8A774B1_CLK_SD0H, CLK_SDSRC, 0x074), + DEF_GEN3_SD( "sd0", R8A774B1_CLK_SD0, R8A774B1_CLK_SD0H, 0x074), + DEF_GEN3_SDH("sd1h", R8A774B1_CLK_SD1H, CLK_SDSRC, 0x078), + DEF_GEN3_SD( "sd1", R8A774B1_CLK_SD1, R8A774B1_CLK_SD1H, 0x078), + DEF_GEN3_SDH("sd2h", R8A774B1_CLK_SD2H, CLK_SDSRC, 0x268), + DEF_GEN3_SD( "sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268), + DEF_GEN3_SDH("sd3h", R8A774B1_CLK_SD3H, CLK_SDSRC, 0x26c), + DEF_GEN3_SD( "sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c), DEF_FIXED("cl", R8A774B1_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A774B1_CLK_CP, CLK_EXTAL, 2, 1), diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c index 5b938eb2df25..cef676c6b04e 100644 --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c @@ -108,9 +108,12 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { DEF_FIXED("s3d2", R8A774C0_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A774C0_CLK_S3D4, CLK_S3, 4, 1), - DEF_GEN3_SD("sd0", R8A774C0_CLK_SD0, CLK_SDSRC, 0x0074), - DEF_GEN3_SD("sd1", R8A774C0_CLK_SD1, CLK_SDSRC, 0x0078), - DEF_GEN3_SD("sd3", R8A774C0_CLK_SD3, CLK_SDSRC, 0x026c), + DEF_GEN3_SDH("sd0h", R8A774C0_CLK_SD0H, CLK_SDSRC, 0x0074), + DEF_GEN3_SD( "sd0", R8A774C0_CLK_SD0, R8A774C0_CLK_SD0H, 0x0074), + DEF_GEN3_SDH("sd1h", R8A774C0_CLK_SD1H, CLK_SDSRC, 0x0078), + DEF_GEN3_SD( "sd1", R8A774C0_CLK_SD1, R8A774C0_CLK_SD1H, 0x0078), + DEF_GEN3_SDH("sd3h", R8A774C0_CLK_SD3H, CLK_SDSRC, 0x026c), + DEF_GEN3_SD( "sd3", R8A774C0_CLK_SD3, R8A774C0_CLK_SD3H, 0x026c), DEF_FIXED("cl", R8A774C0_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cp", R8A774C0_CLK_CP, CLK_EXTAL, 2, 1), diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c b/drivers/clk/renesas/r8a774e1-cpg-mssr.c index 40c71466df37..98beea6f4f6c 100644 --- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c @@ -100,10 +100,14 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = { DEF_FIXED("s3d2", R8A774E1_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A774E1_CLK_S3D4, CLK_S3, 4, 1), - DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, CLK_SDSRC, 0x074), - DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, CLK_SDSRC, 0x078), - DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, CLK_SDSRC, 0x268), - DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, CLK_SDSRC, 0x26c), + DEF_GEN3_SDH("sd0h", R8A774E1_CLK_SD0H, CLK_SDSRC, 0x074), + DEF_GEN3_SD( "sd0", R8A774E1_CLK_SD0, R8A774E1_CLK_SD0H, 0x074), + DEF_GEN3_SDH("sd1h", R8A774E1_CLK_SD1H, CLK_SDSRC, 0x078), + DEF_GEN3_SD( "sd1", R8A774E1_CLK_SD1, R8A774E1_CLK_SD1H, 0x078), + DEF_GEN3_SDH("sd2h", R8A774E1_CLK_SD2H, CLK_SDSRC, 0x268), + DEF_GEN3_SD( "sd2", R8A774E1_CLK_SD2, R8A774E1_CLK_SD2H, 0x268), + DEF_GEN3_SDH("sd3h", R8A774E1_CLK_SD3H, CLK_SDSRC, 0x26c), + DEF_GEN3_SD( "sd3", R8A774E1_CLK_SD3, R8A774E1_CLK_SD3H, 0x26c), DEF_FIXED("cl", R8A774E1_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cr", R8A774E1_CLK_CR, CLK_PLL1_DIV4, 2, 1), diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index c32d2c678046..9ca26057e809 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -104,10 +104,14 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1), - DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074), - DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078), - DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268), - DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c), + DEF_GEN3_SDH("sd0h", R8A7795_CLK_SD0H, CLK_SDSRC, 0x074), + DEF_GEN3_SD( "sd0", R8A7795_CLK_SD0, R8A7795_CLK_SD0H, 0x074), + DEF_GEN3_SDH("sd1h", R8A7795_CLK_SD1H, CLK_SDSRC, 0x078), + DEF_GEN3_SD( "sd1", R8A7795_CLK_SD1, R8A7795_CLK_SD1H, 0x078), + DEF_GEN3_SDH("sd2h", R8A7795_CLK_SD2H, CLK_SDSRC, 0x268), + DEF_GEN3_SD( "sd2", R8A7795_CLK_SD2, R8A7795_CLK_SD2H, 0x268), + DEF_GEN3_SDH("sd3h", R8A7795_CLK_SD3H, CLK_SDSRC, 0x26c), + DEF_GEN3_SD( "sd3", R8A7795_CLK_SD3, R8A7795_CLK_SD3H, 0x26c), DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1), diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 41593c126faf..0dc0ba349a54 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -106,10 +106,14 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1), - DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074), - DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078), - DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268), - DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c), + DEF_GEN3_SDH("sd0h", R8A7796_CLK_SD0H, CLK_SDSRC, 0x074), + DEF_GEN3_SD( "sd0", R8A7796_CLK_SD0, R8A7796_CLK_SD0H, 0x074), + DEF_GEN3_SDH("sd1h", R8A7796_CLK_SD1H, CLK_SDSRC, 0x078), + DEF_GEN3_SD( "sd1", R8A7796_CLK_SD1, R8A7796_CLK_SD1H, 0x078), + DEF_GEN3_SDH("sd2h", R8A7796_CLK_SD2H, CLK_SDSRC, 0x268), + DEF_GEN3_SD( "sd2", R8A7796_CLK_SD2, R8A7796_CLK_SD2H, 0x268), + DEF_GEN3_SDH("sd3h", R8A7796_CLK_SD3H, CLK_SDSRC, 0x26c), + DEF_GEN3_SD( "sd3", R8A7796_CLK_SD3, R8A7796_CLK_SD3H, 0x26c), DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cr", R8A7796_CLK_CR, CLK_PLL1_DIV4, 2, 1), diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index bc1be8bcbbe4..d20a9a0fb3b8 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -101,10 +101,14 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { DEF_FIXED("s3d2", R8A77965_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A77965_CLK_S3D4, CLK_S3, 4, 1), - DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, CLK_SDSRC, 0x074), - DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, CLK_SDSRC, 0x078), - DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268), - DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c), + DEF_GEN3_SDH("sd0h", R8A77965_CLK_SD0H, CLK_SDSRC, 0x074), + DEF_GEN3_SD( "sd0", R8A77965_CLK_SD0, R8A77965_CLK_SD0H, 0x074), + DEF_GEN3_SDH("sd1h", R8A77965_CLK_SD1H, CLK_SDSRC, 0x078), + DEF_GEN3_SD( "sd1", R8A77965_CLK_SD1, R8A77965_CLK_SD1H, 0x078), + DEF_GEN3_SDH("sd2h", R8A77965_CLK_SD2H, CLK_SDSRC, 0x268), + DEF_GEN3_SD( "sd2", R8A77965_CLK_SD2, R8A77965_CLK_SD2H, 0x268), + DEF_GEN3_SDH("sd3h", R8A77965_CLK_SD3H, CLK_SDSRC, 0x26c), + DEF_GEN3_SD( "sd3", R8A77965_CLK_SD3, R8A77965_CLK_SD3H, 0x26c), DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cr", R8A77965_CLK_CR, CLK_PLL1_DIV4, 2, 1), diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c index 9fe372286c1e..4ff2abad1de0 100644 --- a/drivers/clk/renesas/r8a77980-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c @@ -96,7 +96,8 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { DEF_FIXED("s3d2", R8A77980_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A77980_CLK_S3D4, CLK_S3, 4, 1), - DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, CLK_SDSRC, 0x0074), + DEF_GEN3_SDH("sd0h", R8A77980_CLK_SD0H, CLK_SDSRC, 0x0074), + DEF_GEN3_SD( "sd0", R8A77980_CLK_SD0, R8A77980_CLK_SD0H, 0x0074), DEF_FIXED("cl", R8A77980_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A77980_CLK_CP, CLK_EXTAL, 2, 1), diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index a582f2ec3294..637c3f062fae 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -100,9 +100,12 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { DEF_FIXED("s3d2", R8A77990_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A77990_CLK_S3D4, CLK_S3, 4, 1), - DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, CLK_SDSRC, 0x0074), - DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078), - DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c), + DEF_GEN3_SDH("sd0h", R8A77990_CLK_SD0H, CLK_SDSRC, 0x0074), + DEF_GEN3_SD( "sd0", R8A77990_CLK_SD0, R8A77990_CLK_SD0H, 0x0074), + DEF_GEN3_SDH("sd1h", R8A77990_CLK_SD1H, CLK_SDSRC, 0x0078), + DEF_GEN3_SD( "sd1", R8A77990_CLK_SD1, R8A77990_CLK_SD1H, 0x0078), + DEF_GEN3_SDH("sd3h", R8A77990_CLK_SD3H, CLK_SDSRC, 0x026c), + DEF_GEN3_SD( "sd3", R8A77990_CLK_SD3, R8A77990_CLK_SD3H, 0x026c), DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cr", R8A77990_CLK_CR, CLK_PLL1D2, 2, 1), diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index 81c0bc1e78af..007f6fda1db4 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -103,7 +103,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2), DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4), - DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268), + DEF_GEN3_SDH("sd0h", R8A77995_CLK_SD0H, CLK_SDSRC, 0x268), + DEF_GEN3_SD( "sd0", R8A77995_CLK_SD0, R8A77995_CLK_SD0H, 0x268), DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244), DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014), From patchwork Wed Nov 10 19:15:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612695 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8778BC4167B for ; Wed, 10 Nov 2021 19:16:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 750E961186 for ; Wed, 10 Nov 2021 19:16:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232813AbhKJTTK (ORCPT ); Wed, 10 Nov 2021 14:19:10 -0500 Received: from www.zeus03.de ([194.117.254.33]:54998 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232744AbhKJTTJ (ORCPT ); Wed, 10 Nov 2021 14:19:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=a5uQcQa9lL5lZS irCGvck0DoBoIRueZn4XJM2bgbYPI=; b=3LG+fFLVUvlJmSF6vanAgSozumsjCV YqQuxbwqf0kzbtfYioDOKHxiEUpykRk6x19riypGPj4gebxP1MGjukYost2t6NaK Q4HhQPOogbWLSs8N+9V3t0FAqMWcOhrfrZp0tlhmHttNcUYbkmivw3oiL0p2qKjY YpjPT6VF4rLhY= Received: (qmail 722398 invoked from network); 10 Nov 2021 20:16:20 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:20 +0100 X-UD-Smtp-Session: l3s3148p1@ytSWD3TQ1JogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 03/21] clk: renesas: r8a779a0: add SDnH clock to V3U Date: Wed, 10 Nov 2021 20:15:52 +0100 Message-Id: <20211110191610.5664-4-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Currently a pass-through clock but we will make it a real divider clock in the next patches. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- Changes since RFC v1: * added tag from Geert drivers/clk/renesas/r8a779a0-cpg-mssr.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index f16d125ca009..fb7f0cf2654a 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -33,6 +33,7 @@ enum rcar_r8a779a0_clk_types { CLK_TYPE_R8A779A0_PLL1, CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */ CLK_TYPE_R8A779A0_PLL5, + CLK_TYPE_R8A779A0_SDH, CLK_TYPE_R8A779A0_SD, CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */ CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */ @@ -84,6 +85,9 @@ enum clk_ids { DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \ .offset = _offset) +#define DEF_SDH(_name, _id, _parent, _offset) \ + DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SDH, _parent, .offset = _offset) + #define DEF_SD(_name, _id, _parent, _offset) \ DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset) @@ -145,7 +149,8 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1), - DEF_SD("sd0", R8A779A0_CLK_SD0, CLK_SDSRC, 0x870), + DEF_SDH("sdh0", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870), + DEF_SD( "sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870), DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), @@ -293,6 +298,10 @@ static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev, div = cpg_pll_config->pll5_div; break; + case CLK_TYPE_R8A779A0_SDH: + return cpg_sdh_clk_register(core->name, base + core->offset, + __clk_get_name(parent), notifiers); + case CLK_TYPE_R8A779A0_SD: return cpg_sd_clk_register(core->name, base, core->offset, __clk_get_name(parent), notifiers, From patchwork Wed Nov 10 19:15:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612697 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B70CC433F5 for ; Wed, 10 Nov 2021 19:16:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1798B61186 for ; Wed, 10 Nov 2021 19:16:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232881AbhKJTTL (ORCPT ); Wed, 10 Nov 2021 14:19:11 -0500 Received: from www.zeus03.de ([194.117.254.33]:55008 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232761AbhKJTTJ (ORCPT ); Wed, 10 Nov 2021 14:19:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=3cAKb61YVdDf4Z evDZUPD2d/F5+aJA+U/Ya2IG3i5Xg=; b=j9dDJ9uku+xIDfW03CpAIOXx/OaNh2 wO2xVFkCtlNNYOsO58zwVesm+uSic5/4M5SSKMt19HiMF1GMGD+pnPwWUlW0nHlP 8adk91riI8Ha012hC7ntlkSW6ifR92vA/4hWD2mZ/+xjv+MWXcVFo0TmBmB1gxld wwMt1ZLEZbVPk= Received: (qmail 722432 invoked from network); 10 Nov 2021 20:16:20 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:20 +0100 X-UD-Smtp-Session: l3s3148p1@612cD3TQ1pogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 04/21] mmc: sdhi: internal_dmac: flag non-standard SDnH handling for V3M Date: Wed, 10 Nov 2021 20:15:53 +0100 Message-Id: <20211110191610.5664-5-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org V3M handles SDnH differently than other Gen3 SoCs, so let's add a separate entry for that. This will allow better SDnH handling in the future. Signed-off-by: Wolfram Sang Acked-by: Ulf Hansson Reviewed-by: Geert Uytterhoeven --- Changes since RFC v1: * new patch drivers/mmc/host/renesas_sdhi.h | 3 +++ drivers/mmc/host/renesas_sdhi_internal_dmac.c | 21 +++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdhi.h index 0c45e82ff0de..cd82420677cc 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -18,6 +18,8 @@ struct renesas_sdhi_scc { u32 tap_hs400_4tap; /* sampling clock position for HS400 (4 TAP) */ }; +#define SDHI_FLAG_NEED_CLKH_FALLBACK BIT(0) + struct renesas_sdhi_of_data { unsigned long tmio_flags; u32 tmio_ocr_mask; @@ -31,6 +33,7 @@ struct renesas_sdhi_of_data { int taps_num; unsigned int max_blk_count; unsigned short max_segs; + unsigned long sdhi_flags; }; #define SDHI_CALIB_TABLE_MAX 32 diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c index 7660f7ea74dd..9d2c600fd4ce 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -125,6 +125,22 @@ static const struct renesas_sdhi_of_data of_data_rcar_gen3 = { /* DMAC can handle 32bit blk count but only 1 segment */ .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, .max_segs = 1, + .sdhi_flags = SDHI_FLAG_NEED_CLKH_FALLBACK, +}; + +static const struct renesas_sdhi_of_data of_data_rcar_gen3_no_fallback = { + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | + TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, + .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | + MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, + .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, + .bus_shift = 2, + .scc_offset = 0x1000, + .taps = rcar_gen3_scc_taps, + .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), + /* DMAC can handle 32bit blk count but only 1 segment */ + .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, + .max_segs = 1, }; static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = { @@ -214,6 +230,10 @@ static const struct renesas_sdhi_of_data_with_quirks of_r8a77965_compatible = { .quirks = &sdhi_quirks_r8a77965, }; +static const struct renesas_sdhi_of_data_with_quirks of_r8a77970_compatible = { + .of_data = &of_data_rcar_gen3_no_fallback, +}; + static const struct renesas_sdhi_of_data_with_quirks of_r8a77980_compatible = { .of_data = &of_data_rcar_gen3, .quirks = &sdhi_quirks_nohs400, @@ -235,6 +255,7 @@ static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = { { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, }, { .compatible = "renesas,sdhi-r8a77961", .data = &of_r8a77961_compatible, }, { .compatible = "renesas,sdhi-r8a77965", .data = &of_r8a77965_compatible, }, + { .compatible = "renesas,sdhi-r8a77970", .data = &of_r8a77970_compatible, }, { .compatible = "renesas,sdhi-r8a77980", .data = &of_r8a77980_compatible, }, { .compatible = "renesas,sdhi-r8a77990", .data = &of_r8a77990_compatible, }, { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, From patchwork Wed Nov 10 19:15:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8F41C433EF for ; Wed, 10 Nov 2021 19:16:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CFC03611C9 for ; Wed, 10 Nov 2021 19:16:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232888AbhKJTTM (ORCPT ); Wed, 10 Nov 2021 14:19:12 -0500 Received: from www.zeus03.de ([194.117.254.33]:55020 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232797AbhKJTTK (ORCPT ); Wed, 10 Nov 2021 14:19:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=K5OM1by4C3vrdU agVLEmvQSbNICRKhHQledmhFLsyx0=; b=CPTLsdlwP7CHLUTmEE978A7jEJJJlW 0c29JRWjOkAGBzmEbGyIUoa64aCJ/NMeizbmrA0PRCwBE/cBz88Dr2DjzQeVrOat cVC83B4OF87DQvvBb2BdlvvOPxWUJgQxLr7o3kkmesGO7hICtehtZ7myx7F89n0G GV21f5r361PRw= Received: (qmail 722462 invoked from network); 10 Nov 2021 20:16:20 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:20 +0100 X-UD-Smtp-Session: l3s3148p1@5naiD3TQ2JogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 05/21] clk: renesas: rcar-gen3: switch to new SD clock handling Date: Wed, 10 Nov 2021 20:15:54 +0100 Message-Id: <20211110191610.5664-6-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The old SD handling code was huge and could not handle all the details which showed up on R-Car Gen3 SoCs meanwhile. It is time to switch to another design. Have SDnH a separate clock, use the existing divider clocks and move the errata handling from the clock driver to the SDHI driver where it belongs. This patch removes the old SD handling code and switch to the new one. This updates the SDHI driver at the same time. Because the SDHI driver can only communicate with the clock driver via clk_set_rate(), I don't see an alternative to this flag-day-approach, so we cross subsystems here. The patch sadly looks messy for the CPG lib, but it is basically a huge chunk of code removed and smaller chunks added. It looks much better when you just view the resulting source file. Signed-off-by: Wolfram Sang Acked-by: Ulf Hansson # For MMC Reviewed-by: Geert Uytterhoeven --- Changes since RFC v1: * fixed typos in commit message * switched to a flag instead of checking compatible for the fallback mechanisam * used bitshift instead of multiplication for the clkh factor * fixed a memleak * simplified an if condition * fixed the subject prefix drivers/clk/renesas/r8a779a0-cpg-mssr.c | 6 +- drivers/clk/renesas/rcar-cpg-lib.c | 220 +++--------------------- drivers/clk/renesas/rcar-cpg-lib.h | 3 +- drivers/clk/renesas/rcar-gen3-cpg.c | 5 +- drivers/mmc/host/renesas_sdhi.h | 1 + drivers/mmc/host/renesas_sdhi_core.c | 28 ++- 6 files changed, 56 insertions(+), 207 deletions(-) diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index fb7f0cf2654a..6531f23a4bea 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -303,10 +303,8 @@ static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev, __clk_get_name(parent), notifiers); case CLK_TYPE_R8A779A0_SD: - return cpg_sd_clk_register(core->name, base, core->offset, - __clk_get_name(parent), notifiers, - false); - break; + return cpg_sd_clk_register(core->name, base + core->offset, + __clk_get_name(parent)); case CLK_TYPE_R8A779A0_MDSEL: /* diff --git a/drivers/clk/renesas/rcar-cpg-lib.c b/drivers/clk/renesas/rcar-cpg-lib.c index 351cb9c04f5c..bec8358b599c 100644 --- a/drivers/clk/renesas/rcar-cpg-lib.c +++ b/drivers/clk/renesas/rcar-cpg-lib.c @@ -66,214 +66,48 @@ void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, * SDn Clock */ -struct clk * __init cpg_sdh_clk_register(const char *name, - void __iomem *sdnckcr, const char *parent_name, - struct raw_notifier_head *notifiers) -{ - /* placeholder during transition */ - return clk_register_fixed_factor(NULL, name, parent_name, 0, 1, 1); -} - -#define CPG_SD_STP_HCK BIT(9) -#define CPG_SD_STP_CK BIT(8) - -#define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK) -#define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0) - -#define CPG_SD_DIV_TABLE_DATA(stp_hck, sd_srcfc, sd_fc, sd_div) \ -{ \ - .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \ - ((sd_srcfc) << 2) | \ - ((sd_fc) << 0), \ - .div = (sd_div), \ -} - -struct sd_div_table { - u32 val; - unsigned int div; -}; +#define SDnSRCFC_SHIFT 2 +#define STPnHCK BIT(9 - SDnSRCFC_SHIFT) -struct sd_clock { - struct clk_hw hw; - const struct sd_div_table *div_table; - struct cpg_simple_notifier csn; - unsigned int div_num; - unsigned int cur_div_idx; -}; - -/* SDn divider - * sd_srcfc sd_fc div - * stp_hck (div) (div) = sd_srcfc x sd_fc - *--------------------------------------------------------- - * 0 0 (1) 1 (4) 4 : SDR104 / HS200 / HS400 (8 TAP) - * 0 1 (2) 1 (4) 8 : SDR50 - * 1 2 (4) 1 (4) 16 : HS / SDR25 - * 1 3 (8) 1 (4) 32 : NS / SDR12 - * 1 4 (16) 1 (4) 64 - * 0 0 (1) 0 (2) 2 - * 0 1 (2) 0 (2) 4 : SDR104 / HS200 / HS400 (4 TAP) - * 1 2 (4) 0 (2) 8 - * 1 3 (8) 0 (2) 16 - * 1 4 (16) 0 (2) 32 - * - * NOTE: There is a quirk option to ignore the first row of the dividers - * table when searching for suitable settings. This is because HS400 on - * early ES versions of H3 and M3-W requires a specific setting to work. - */ -static const struct sd_div_table cpg_sd_div_table[] = { -/* CPG_SD_DIV_TABLE_DATA(stp_hck, sd_srcfc, sd_fc, sd_div) */ - CPG_SD_DIV_TABLE_DATA(0, 0, 1, 4), - CPG_SD_DIV_TABLE_DATA(0, 1, 1, 8), - CPG_SD_DIV_TABLE_DATA(1, 2, 1, 16), - CPG_SD_DIV_TABLE_DATA(1, 3, 1, 32), - CPG_SD_DIV_TABLE_DATA(1, 4, 1, 64), - CPG_SD_DIV_TABLE_DATA(0, 0, 0, 2), - CPG_SD_DIV_TABLE_DATA(0, 1, 0, 4), - CPG_SD_DIV_TABLE_DATA(1, 2, 0, 8), - CPG_SD_DIV_TABLE_DATA(1, 3, 0, 16), - CPG_SD_DIV_TABLE_DATA(1, 4, 0, 32), +static const struct clk_div_table cpg_sdh_div_table[] = { + { 0, 1 }, { 1, 2 }, { STPnHCK | 2, 4 }, { STPnHCK | 3, 8 }, + { STPnHCK | 4, 16 }, { 0, 0 }, }; -#define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw) - -static int cpg_sd_clock_enable(struct clk_hw *hw) -{ - struct sd_clock *clock = to_sd_clock(hw); - - cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK, - clock->div_table[clock->cur_div_idx].val & - CPG_SD_STP_MASK); - - return 0; -} - -static void cpg_sd_clock_disable(struct clk_hw *hw) -{ - struct sd_clock *clock = to_sd_clock(hw); - - cpg_reg_modify(clock->csn.reg, 0, CPG_SD_STP_MASK); -} - -static int cpg_sd_clock_is_enabled(struct clk_hw *hw) -{ - struct sd_clock *clock = to_sd_clock(hw); - - return !(readl(clock->csn.reg) & CPG_SD_STP_MASK); -} - -static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) +struct clk * __init cpg_sdh_clk_register(const char *name, + void __iomem *sdnckcr, const char *parent_name, + struct raw_notifier_head *notifiers) { - struct sd_clock *clock = to_sd_clock(hw); - - return DIV_ROUND_CLOSEST(parent_rate, - clock->div_table[clock->cur_div_idx].div); -} + struct cpg_simple_notifier *csn; + struct clk *clk; -static int cpg_sd_clock_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - unsigned long best_rate = ULONG_MAX, diff_min = ULONG_MAX; - struct sd_clock *clock = to_sd_clock(hw); - unsigned long calc_rate, diff; - unsigned int i; + csn = kzalloc(sizeof(*csn), GFP_KERNEL); + if (!csn) + return ERR_PTR(-ENOMEM); - for (i = 0; i < clock->div_num; i++) { - calc_rate = DIV_ROUND_CLOSEST(req->best_parent_rate, - clock->div_table[i].div); - if (calc_rate < req->min_rate || calc_rate > req->max_rate) - continue; + csn->reg = sdnckcr; - diff = calc_rate > req->rate ? calc_rate - req->rate - : req->rate - calc_rate; - if (diff < diff_min) { - best_rate = calc_rate; - diff_min = diff; - } + clk = clk_register_divider_table(NULL, name, parent_name, 0, sdnckcr, + SDnSRCFC_SHIFT, 8, 0, cpg_sdh_div_table, + &cpg_lock); + if (IS_ERR(clk)) { + kfree(csn); + return clk; } - if (best_rate == ULONG_MAX) - return -EINVAL; - - req->rate = best_rate; - return 0; -} - -static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct sd_clock *clock = to_sd_clock(hw); - unsigned int i; - - for (i = 0; i < clock->div_num; i++) - if (rate == DIV_ROUND_CLOSEST(parent_rate, - clock->div_table[i].div)) - break; - - if (i >= clock->div_num) - return -EINVAL; - - clock->cur_div_idx = i; - - cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK | CPG_SD_FC_MASK, - clock->div_table[i].val & - (CPG_SD_STP_MASK | CPG_SD_FC_MASK)); - - return 0; + cpg_simple_notifier_register(notifiers, csn); + return clk; } -static const struct clk_ops cpg_sd_clock_ops = { - .enable = cpg_sd_clock_enable, - .disable = cpg_sd_clock_disable, - .is_enabled = cpg_sd_clock_is_enabled, - .recalc_rate = cpg_sd_clock_recalc_rate, - .determine_rate = cpg_sd_clock_determine_rate, - .set_rate = cpg_sd_clock_set_rate, +static const struct clk_div_table cpg_sd_div_table[] = { + { 0, 2 }, { 1, 4 }, { 0, 0 }, }; struct clk * __init cpg_sd_clk_register(const char *name, - void __iomem *base, unsigned int offset, const char *parent_name, - struct raw_notifier_head *notifiers, bool skip_first) + void __iomem *sdnckcr, const char *parent_name) { - struct clk_init_data init = {}; - struct sd_clock *clock; - struct clk *clk; - u32 val; - - clock = kzalloc(sizeof(*clock), GFP_KERNEL); - if (!clock) - return ERR_PTR(-ENOMEM); - - init.name = name; - init.ops = &cpg_sd_clock_ops; - init.flags = CLK_SET_RATE_PARENT; - init.parent_names = &parent_name; - init.num_parents = 1; - - clock->csn.reg = base + offset; - clock->hw.init = &init; - clock->div_table = cpg_sd_div_table; - clock->div_num = ARRAY_SIZE(cpg_sd_div_table); - - if (skip_first) { - clock->div_table++; - clock->div_num--; - } - - val = readl(clock->csn.reg) & ~CPG_SD_FC_MASK; - val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK); - writel(val, clock->csn.reg); - - clk = clk_register(NULL, &clock->hw); - if (IS_ERR(clk)) - goto free_clock; - - cpg_simple_notifier_register(notifiers, &clock->csn); - return clk; - -free_clock: - kfree(clock); - return clk; + return clk_register_divider_table(NULL, name, parent_name, 0, sdnckcr, + 0, 2, 0, cpg_sd_div_table, &cpg_lock); } diff --git a/drivers/clk/renesas/rcar-cpg-lib.h b/drivers/clk/renesas/rcar-cpg-lib.h index 548cb9562f35..0941c95a3006 100644 --- a/drivers/clk/renesas/rcar-cpg-lib.h +++ b/drivers/clk/renesas/rcar-cpg-lib.h @@ -31,7 +31,6 @@ struct clk * __init cpg_sdh_clk_register(const char *name, struct raw_notifier_head *notifiers); struct clk * __init cpg_sd_clk_register(const char *name, - void __iomem *base, unsigned int offset, const char *parent_name, - struct raw_notifier_head *notifiers, bool skip_first); + void __iomem *sdnckcr, const char *parent_name); #endif diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 182b189bc8f4..aa0797b98e89 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -491,9 +491,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, __clk_get_name(parent), notifiers); case CLK_TYPE_GEN3_SD: - return cpg_sd_clk_register(core->name, base, core->offset, - __clk_get_name(parent), notifiers, - cpg_quirks & SD_SKIP_FIRST); + return cpg_sd_clk_register(core->name, base + core->offset, + __clk_get_name(parent)); case CLK_TYPE_GEN3_R: if (cpg_quirks & RCKCR_CKSEL) { diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdhi.h index cd82420677cc..66d308e73e17 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -60,6 +60,7 @@ struct tmio_mmc_dma { struct renesas_sdhi { struct clk *clk; + struct clk *clkh; struct clk *clk_cd; struct tmio_mmc_data mmc_data; struct tmio_mmc_dma dma_priv; diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index 6fc4cf3c9dce..4572242f9816 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -127,10 +127,12 @@ static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) } static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, - unsigned int new_clock) + unsigned int wanted_clock) { struct renesas_sdhi *priv = host_to_priv(host); + struct clk *ref_clk = priv->clk; unsigned int freq, diff, best_freq = 0, diff_min = ~0; + unsigned int new_clock, clkh_shift = 0; int i; /* @@ -141,6 +143,16 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc)) return clk_get_rate(priv->clk); + if (priv->clkh) { + bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; + bool need_slow_clkh = (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) || + (host->mmc->ios.timing == MMC_TIMING_MMC_HS400); + clkh_shift = use_4tap && need_slow_clkh ? 1 : 2; + ref_clk = priv->clkh; + } + + new_clock = wanted_clock << clkh_shift; + /* * We want the bus clock to be as close as possible to, but no * greater than, new_clock. As we can divide by 1 << i for @@ -148,11 +160,10 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, * possible, but no greater than, new_clock << i. */ for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { - freq = clk_round_rate(priv->clk, new_clock << i); + freq = clk_round_rate(ref_clk, new_clock << i); if (freq > (new_clock << i)) { /* Too fast; look for a slightly slower option */ - freq = clk_round_rate(priv->clk, - (new_clock << i) / 4 * 3); + freq = clk_round_rate(ref_clk, (new_clock << i) / 4 * 3); if (freq > (new_clock << i)) continue; } @@ -164,7 +175,10 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, } } - clk_set_rate(priv->clk, best_freq); + clk_set_rate(ref_clk, best_freq); + + if (priv->clkh) + clk_set_rate(priv->clk, best_freq >> clkh_shift); return clk_get_rate(priv->clk); } @@ -945,6 +959,10 @@ int renesas_sdhi_probe(struct platform_device *pdev, mmc_data->max_segs = of_data->max_segs; dma_priv->dma_buswidth = of_data->dma_buswidth; host->bus_shift = of_data->bus_shift; + /* Fallback for old DTs */ + if (of_data->sdhi_flags & SDHI_FLAG_NEED_CLKH_FALLBACK) + priv->clkh = clk_get_parent(clk_get_parent(priv->clk)); + } host->write16_hook = renesas_sdhi_write16_hook; From patchwork Wed Nov 10 19:15:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612703 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7100C43217 for ; Wed, 10 Nov 2021 19:16:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D07FA611AD for ; Wed, 10 Nov 2021 19:16:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232960AbhKJTTR (ORCPT ); Wed, 10 Nov 2021 14:19:17 -0500 Received: from www.zeus03.de ([194.117.254.33]:55032 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232814AbhKJTTK (ORCPT ); Wed, 10 Nov 2021 14:19:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=AXGVIpUc08yi8/ jW6OixQziE9rF2msDo/V93xBc1ykA=; b=zHy4dBjc09rx1zKr2Kvl4PWrB3tbIz JYdfw+s8I3bA/HDlphPd3h3F9AShRjcvEM7Mrj71kqlMefJVFnqDbZMaoai5BWqI jCahIrwekvRjB/JLp628A+ikTMg3yQ/nfjfzLyACucX6sFwcQkyUeo+a58zj/9A0 nAc5LKTMH6OOw= Received: (qmail 722492 invoked from network); 10 Nov 2021 20:16:21 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:21 +0100 X-UD-Smtp-Session: l3s3148p1@FZmoD3TQ2pogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 06/21] clk: renesas: rcar-gen3: remove outdated SD_SKIP_FIRST Date: Wed, 10 Nov 2021 20:15:55 +0100 Message-Id: <20211110191610.5664-7-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org We handle it differently meanwhile. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- Changes since RFC v1: * fixed subject prefix * added tag from Geert drivers/clk/renesas/rcar-gen3-cpg.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index aa0797b98e89..c4b36c90e159 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -397,29 +397,20 @@ static u32 cpg_quirks __initdata; #define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */ #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */ -#define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */ static const struct soc_device_attribute cpg_quirks_match[] __initconst = { { .soc_id = "r8a7795", .revision = "ES1.0", - .data = (void *)(PLL_ERRATA | RCKCR_CKSEL | SD_SKIP_FIRST), + .data = (void *)(PLL_ERRATA | RCKCR_CKSEL), }, { .soc_id = "r8a7795", .revision = "ES1.*", - .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST), - }, - { - .soc_id = "r8a7795", .revision = "ES2.0", - .data = (void *)SD_SKIP_FIRST, + .data = (void *)(RCKCR_CKSEL), }, { .soc_id = "r8a7796", .revision = "ES1.0", - .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST), - }, - { - .soc_id = "r8a7796", .revision = "ES1.1", - .data = (void *)SD_SKIP_FIRST, + .data = (void *)(RCKCR_CKSEL), }, { /* sentinel */ } }; From patchwork Wed Nov 10 19:15:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C191C4332F for ; Wed, 10 Nov 2021 19:16:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 64AC56117A for ; Wed, 10 Nov 2021 19:16:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232797AbhKJTTP (ORCPT ); Wed, 10 Nov 2021 14:19:15 -0500 Received: from www.zeus03.de ([194.117.254.33]:55048 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232818AbhKJTTK (ORCPT ); Wed, 10 Nov 2021 14:19:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=vfBKx2aAd0E1y2 US/LygY9r+sBEYKlzcy7sO5zf5Flo=; b=0/25ZpLOALa/XqqhaCIZpB8tsa3bPa YkMdwTifbXLECvMtO7qTAYKL5NDbgflqnfxn4IUHNzjcF53q+82kwOc9ClkIlpU0 k3wt5tfuaD6RSn9yi8Whd9tSiqIoz9MYoMu7QCwEREPYWwa9OmUd4H3YW0DKI4op BwRfVlNRs4RWo= Received: (qmail 722514 invoked from network); 10 Nov 2021 20:16:21 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:21 +0100 X-UD-Smtp-Session: l3s3148p1@D8+uD3TQ3JogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 07/21] dt-bindings: mmc: renesas,sdhi: add optional SDnH clock Date: Wed, 10 Nov 2021 20:15:56 +0100 Message-Id: <20211110191610.5664-8-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Signed-off-by: Wolfram Sang Acked-by: Ulf Hansson --- Changes since RFC v1: * use 'oneOf' for the clock-names .../devicetree/bindings/mmc/renesas,sdhi.yaml | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index 9f1e7092cf44..190a58ae77b5 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -132,12 +132,20 @@ allOf: properties: clocks: minItems: 1 - maxItems: 2 + maxItems: 3 clock-names: - minItems: 1 - items: + oneOf: - const: core - - const: cd + - items: + - const: core + - const: cd + - items: + - const: core + - const: clkh + - items: + - const: core + - const: clkh + - const: cd - if: properties: From patchwork Wed Nov 10 19:15:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 630F8C4321E for ; Wed, 10 Nov 2021 19:16:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4CBE361186 for ; Wed, 10 Nov 2021 19:16:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232831AbhKJTTS (ORCPT ); Wed, 10 Nov 2021 14:19:18 -0500 Received: from www.zeus03.de ([194.117.254.33]:55072 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232839AbhKJTTL (ORCPT ); Wed, 10 Nov 2021 14:19:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=zOGR2xM5M/Xlh/ lXccN5MKOX/a7qSPGEJmhvoP9IIxQ=; b=NmoWv2Y0sP4QYdrHYnjYVCHWw9CU54 DTRzjXzejHxEk/lYiPGR9YSOnPpjMA0mKaXeP8ZeEGzKzfRmDzMT4EAuT0dwaySF UNzYAHe1uDQtyX6NNZqUqo+RsiX8WTDjHtkY42dTKg466crn/X5FpEpJ83OkteoA kK3LFd5Zp5q7w= Received: (qmail 722551 invoked from network); 10 Nov 2021 20:16:22 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:22 +0100 X-UD-Smtp-Session: l3s3148p1@Dbq0D3TQ3pogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 08/21] arm64: dts: reneas: r8a774a1: add SDnH clocks Date: Wed, 10 Nov 2021 20:15:57 +0100 Message-Id: <20211110191610.5664-9-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- Changes since RFC v1: * new patch arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 6f4fffacfca2..f9c4ae6f26a9 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -2276,7 +2276,8 @@ sdhi0: mmc@ee100000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2288,7 +2289,8 @@ sdhi1: mmc@ee120000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2300,7 +2302,8 @@ sdhi2: mmc@ee140000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2312,7 +2315,8 @@ sdhi3: mmc@ee160000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 311>; From patchwork Wed Nov 10 19:15:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612707 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4B5BC4167E for ; Wed, 10 Nov 2021 19:16:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A3564611AD for ; Wed, 10 Nov 2021 19:16:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232839AbhKJTTS (ORCPT ); Wed, 10 Nov 2021 14:19:18 -0500 Received: from www.zeus03.de ([194.117.254.33]:55090 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232433AbhKJTTM (ORCPT ); Wed, 10 Nov 2021 14:19:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=AFtByZooLSawox QwvSB8Im4yBuaNRUlxYDM0SfSP+fI=; b=S3efCruHhdRv00Uy4GTxDHNuPqbkvU mvMOAszJguh6AdBwj3rlwWQoH0vYN+ObYrgYbuwfnpX+tPasiatQPiA3Y4H9aJ43 GPc74ZMoqLWhjIts9kn7Yey/smwCU1M/PsSzlMy+yrHya7F4PxGEPT3AaqXIdM/B RCtYEnrd0svT0= Received: (qmail 722582 invoked from network); 10 Nov 2021 20:16:22 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:22 +0100 X-UD-Smtp-Session: l3s3148p1@bZq6D3TQ4JogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 09/21] arm64: dts: reneas: r8a774b1: add SDnH clocks Date: Wed, 10 Nov 2021 20:15:58 +0100 Message-Id: <20211110191610.5664-10-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- Changes since RFC v1: * new patch arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 0f7bdfc90a0d..0c175b8c2088 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -2133,7 +2133,8 @@ sdhi0: mmc@ee100000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774B1_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2145,7 +2146,8 @@ sdhi1: mmc@ee120000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774B1_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2157,7 +2159,8 @@ sdhi2: mmc@ee140000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774B1_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2169,7 +2172,8 @@ sdhi3: mmc@ee160000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774B1_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 311>; From patchwork Wed Nov 10 19:15:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09ACBC31D68 for ; Wed, 10 Nov 2021 19:16:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E0633611C9 for ; Wed, 10 Nov 2021 19:16:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232930AbhKJTTS (ORCPT ); Wed, 10 Nov 2021 14:19:18 -0500 Received: from www.zeus03.de ([194.117.254.33]:55098 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232816AbhKJTTM (ORCPT ); Wed, 10 Nov 2021 14:19:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=86vzeTOhO8TvXP queZTaibtj1+9DyANjAGdg4lC/5ZI=; b=UK+A4QSkZAoOam2dfaSsjeKlgPw3rc Mw964lLobqjYDn2xMqLS0RYYFktauj0bvYM7vLPTQU0ShYzj2KzBNhP9pLz8enZs sWCdEmMuPCcQQaxi14+fiE/INaLd7/ukZNIm6nRcycbUmJAUEcwDUjC1GoYN8cyL 8egVen9H3jJt0= Received: (qmail 722610 invoked from network); 10 Nov 2021 20:16:22 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:22 +0100 X-UD-Smtp-Session: l3s3148p1@jMXAD3TQ4pogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 10/21] arm64: dts: reneas: r8a774c0: add SDnH clocks Date: Wed, 10 Nov 2021 20:15:59 +0100 Message-Id: <20211110191610.5664-11-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- Changes since RFC v1: * new patch arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index d597772c4c37..5e16f6b1771e 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1626,7 +1626,8 @@ sdhi0: mmc@ee100000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774C0_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -1638,7 +1639,8 @@ sdhi1: mmc@ee120000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774C0_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -1650,7 +1652,8 @@ sdhi3: mmc@ee160000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774C0_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 311>; From patchwork Wed Nov 10 19:16:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612715 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E877BC433EF for ; Wed, 10 Nov 2021 19:16:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CAC46611C9 for ; Wed, 10 Nov 2021 19:16:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232894AbhKJTTT (ORCPT ); Wed, 10 Nov 2021 14:19:19 -0500 Received: from www.zeus03.de ([194.117.254.33]:55114 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232884AbhKJTTN (ORCPT ); Wed, 10 Nov 2021 14:19:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=l0auAhOCLDTIf6 2eOuLhuxCMAY7LdL4pZlM/WZKrmx4=; b=e2EgtYFcRuzscJHBkbxLrlKArNEmaQ 1HNmvsmsO97fAb5YSKgTq2JiqbucaK5y0ioDfHWLnH7LwVLEH20R9zoEiwGsPqqo Wm4BiGFhm1gW5yDYIosz9T6/epEjok5BIB9//9VgqcVJkNkx2U4mDA5gBNgEsywy 5pPfh0uXwg1sE= Received: (qmail 722636 invoked from network); 10 Nov 2021 20:16:23 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:23 +0100 X-UD-Smtp-Session: l3s3148p1@PrjGD3TQ5JogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 11/21] arm64: dts: reneas: r8a774e1: add SDnH clocks Date: Wed, 10 Nov 2021 20:16:00 +0100 Message-Id: <20211110191610.5664-12-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- Changes since RFC v1: * new patch arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 379a1300272b..673fcc631972 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2362,7 +2362,8 @@ sdhi0: mmc@ee100000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774E1_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2375,7 +2376,8 @@ sdhi1: mmc@ee120000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774E1_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2388,7 +2390,8 @@ sdhi2: mmc@ee140000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774E1_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2401,7 +2404,8 @@ sdhi3: mmc@ee160000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774E1_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 311>; From patchwork Wed Nov 10 19:16:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61148C31D97 for ; Wed, 10 Nov 2021 19:16:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 470BE611AD for ; Wed, 10 Nov 2021 19:16:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232816AbhKJTTT (ORCPT ); Wed, 10 Nov 2021 14:19:19 -0500 Received: from www.zeus03.de ([194.117.254.33]:55124 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232895AbhKJTTN (ORCPT ); Wed, 10 Nov 2021 14:19:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=Jt6bVIzu1maQuO YMTVao4BLGiLg8fziSQRhfzzFu/wM=; b=irTv7tz/vQo0TiEFdO/hh4ortlCe4p b+BUg4O9WaUpn5i1J3SisdjGuaClMLyfrN7XYAzAjZWng+R7+LC0wvwOtKSP8Y5F 73qiAGhhqDl/jalQxICiwouynjfLVc1k8rD4XGsn93Tvk5Yt9tmY0puYGIIuNTtw uXDkpTkw0e+iQ= Received: (qmail 722661 invoked from network); 10 Nov 2021 20:16:23 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:23 +0100 X-UD-Smtp-Session: l3s3148p1@uc/MD3TQ5pogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 12/21] arm64: dts: reneas: r8a77951: add SDnH clocks Date: Wed, 10 Nov 2021 20:16:01 +0100 Message-Id: <20211110191610.5664-13-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- Changes since RFC v1: * added tag from Geert * fixed subject prefix arch/arm64/boot/dts/renesas/r8a77951.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 1768a3e6bb8d..391ffe6ca03e 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -2668,7 +2668,8 @@ sdhi0: mmc@ee100000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7795_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2681,7 +2682,8 @@ sdhi1: mmc@ee120000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7795_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2694,7 +2696,8 @@ sdhi2: mmc@ee140000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7795_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2707,7 +2710,8 @@ sdhi3: mmc@ee160000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7795_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 311>; From patchwork Wed Nov 10 19:16:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68C8FC3525C for ; Wed, 10 Nov 2021 19:16:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 51C4E6117A for ; Wed, 10 Nov 2021 19:16:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232761AbhKJTTT (ORCPT ); Wed, 10 Nov 2021 14:19:19 -0500 Received: from www.zeus03.de ([194.117.254.33]:55160 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232920AbhKJTTP (ORCPT ); Wed, 10 Nov 2021 14:19:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=hyskDLEwKNDj7b rDGQKl4Ec8Lg4TQU0ghQYALjuUlb4=; b=cf4nqE7H/3F6mTXkYi0nfREA4F3/RL dNr1ieszTgCUbv29IO1Byz6xHSizT4NQeahVT6fS4+5Perzf5apUhqD4ucLT7PUM nrO/za+G7jU0suSsy5lu0ap3qDWm2QsaFgoY2oP+/Mt0FFHy6VXHCy/FR4rsZtWh rhij0rORCWvYE= Received: (qmail 722684 invoked from network); 10 Nov 2021 20:16:24 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:24 +0100 X-UD-Smtp-Session: l3s3148p1@FBLTD3TQ6JogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 13/21] arm64: dts: reneas: r8a77960: add SDnH clocks Date: Wed, 10 Nov 2021 20:16:02 +0100 Message-Id: <20211110191610.5664-14-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- Changes since RFC v1: * new patch arch/arm64/boot/dts/renesas/r8a77960.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 2bd8169735d3..b1a6cf76633d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -2468,7 +2468,8 @@ sdhi0: mmc@ee100000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7796_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2481,7 +2482,8 @@ sdhi1: mmc@ee120000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7796_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2494,7 +2496,8 @@ sdhi2: mmc@ee140000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7796_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2507,7 +2510,8 @@ sdhi3: mmc@ee160000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7796_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 311>; From patchwork Wed Nov 10 19:16:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E99DC35268 for ; Wed, 10 Nov 2021 19:16:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 087696117A for ; Wed, 10 Nov 2021 19:16:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232674AbhKJTTU (ORCPT ); Wed, 10 Nov 2021 14:19:20 -0500 Received: from www.zeus03.de ([194.117.254.33]:55178 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232949AbhKJTTP (ORCPT ); Wed, 10 Nov 2021 14:19:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=HQ2iypZIxhUd15 ApWsyV70eUctYifZ/5xcxHxQ/F190=; b=rr7booJNMsFZ/AXUdl1kZ16YbPTBXc 6Stq7uVSg/K2Zdt54/hetdcvfpxOSxcTf0ehlPZKVEmWGPddMYvF/s0Rl0KskknH p9ugnbhEm59h4cpOaz6mei904D0jUeHGI4w5xmfMHqVTK79yQNI9ONrEtCzOTe7l P81ZQMHhuAT+E= Received: (qmail 722717 invoked from network); 10 Nov 2021 20:16:24 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:24 +0100 X-UD-Smtp-Session: l3s3148p1@k+7YD3TQ6pogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 14/21] arm64: dts: reneas: r8a77961: add SDnH clocks Date: Wed, 10 Nov 2021 20:16:03 +0100 Message-Id: <20211110191610.5664-15-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- Changes since RFC v1: * new patch arch/arm64/boot/dts/renesas/r8a77961.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 86d59e7e1a87..1c1da6d7be49 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2312,7 +2312,8 @@ sdhi0: mmc@ee100000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77961_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2325,7 +2326,8 @@ sdhi1: mmc@ee120000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77961_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2338,7 +2340,8 @@ sdhi2: mmc@ee140000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77961_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2351,7 +2354,8 @@ sdhi3: mmc@ee160000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77961_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 311>; From patchwork Wed Nov 10 19:16:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612719 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7DCFC35263 for ; Wed, 10 Nov 2021 19:16:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B11DC611AD for ; Wed, 10 Nov 2021 19:16:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232900AbhKJTTU (ORCPT ); Wed, 10 Nov 2021 14:19:20 -0500 Received: from www.zeus03.de ([194.117.254.33]:55140 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232912AbhKJTTP (ORCPT ); Wed, 10 Nov 2021 14:19:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=nU63S1F0xzf6Yg 32Z+Yu1Rf2ZSUXlvGMT1zS+CqlmLs=; b=T3Y3V/eQBk1thSXSSqYCj51H2wutl8 QURXH14IxH15xk8smm5ZQtevnbq0Ih0hpNZlbyDiQtI4ErlNHLO3XvMNdtzwBhYp eAy6c9Rz/+/xo0o70FVLh8m8jzS2XAcerJTsxyrJ/q3tEk05sgUuoIS+bsgOn1pq GV8uUMMjOcmiY= Received: (qmail 722752 invoked from network); 10 Nov 2021 20:16:24 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:24 +0100 X-UD-Smtp-Session: l3s3148p1@A8/eD3TQ7JogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 15/21] arm64: dts: reneas: r8a77965: add SDnH clocks Date: Wed, 10 Nov 2021 20:16:04 +0100 Message-Id: <20211110191610.5664-16-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- Changes since RFC v1: * fixed subject prefix * added tag from Geert arch/arm64/boot/dts/renesas/r8a77965.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 08df75606430..3a357d958d4a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -2315,7 +2315,8 @@ sdhi0: mmc@ee100000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77965_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2328,7 +2329,8 @@ sdhi1: mmc@ee120000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77965_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2341,7 +2343,8 @@ sdhi2: mmc@ee140000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77965_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2354,7 +2357,8 @@ sdhi3: mmc@ee160000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77965_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 311>; From patchwork Wed Nov 10 19:16:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63A7DC43217 for ; Wed, 10 Nov 2021 19:16:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4B7EC611C9 for ; Wed, 10 Nov 2021 19:16:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232920AbhKJTTV (ORCPT ); Wed, 10 Nov 2021 14:19:21 -0500 Received: from www.zeus03.de ([194.117.254.33]:55192 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232952AbhKJTTR (ORCPT ); Wed, 10 Nov 2021 14:19:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=wQPrEci9TolAec PaBVnzk1aXgbeLcSVrYScyAClrDYA=; b=Ntb/0QP28JUBoWPIhvyFyY5cOnip6r AWtE/8h0/IXNk0PxAijzsIDT/b1sHaIGzbwAbtCo+fHAumlDJ6TvpNU2L5ouWJa0 ECI27qxLRNUaXpacM9y1JzRxMrbkG9pX8TavoUT4IbjHKuDkgW14ju27bEt6ORD+ SGfL6Wydy/SDA= Received: (qmail 722784 invoked from network); 10 Nov 2021 20:16:25 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:25 +0100 X-UD-Smtp-Session: l3s3148p1@SbblD3TQ7pogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 16/21] arm64: dts: reneas: r8a77980: add SDnH clocks Date: Wed, 10 Nov 2021 20:16:05 +0100 Message-Id: <20211110191610.5664-17-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- Changes since RFC v1: * new patch arch/arm64/boot/dts/renesas/r8a77980.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 6347d15e66b6..2a4513e7e2b5 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -1339,7 +1339,8 @@ mmc0: mmc@ee140000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77980_CLK_SD0H>; + clock-names = "core", "clkh"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 314>; max-frequency = <200000000>; From patchwork Wed Nov 10 19:16:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612721 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF128C35269 for ; Wed, 10 Nov 2021 19:16:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9F963611AD for ; Wed, 10 Nov 2021 19:16:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229781AbhKJTTV (ORCPT ); Wed, 10 Nov 2021 14:19:21 -0500 Received: from www.zeus03.de ([194.117.254.33]:55200 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232815AbhKJTTS (ORCPT ); Wed, 10 Nov 2021 14:19:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=9WG8k8z5vOkJTt qxrIL6zWecCZjdQWD3KhIzGyZUqyg=; b=iq/4TtI4xIYWyXJR1U8xH9xVT79ZQr P0OXhbyHDHC28Md0/sTDGCLNK2GlPhVdh/HFDsdVj0m0UFVmRoHM01N2KTnpClnB EeD903hz4zNkenBe6kJtfOQEYM+m/18l3AUoQm6xddnMV8Q68/fCOwD2cpsdue+O oob34+6mJJDvk= Received: (qmail 722817 invoked from network); 10 Nov 2021 20:16:25 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:25 +0100 X-UD-Smtp-Session: l3s3148p1@m53rD3TQ8JogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 17/21] arm64: dts: reneas: r8a77990: add SDnH clocks Date: Wed, 10 Nov 2021 20:16:06 +0100 Message-Id: <20211110191610.5664-18-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- Changes since RFC v1: * new patch arch/arm64/boot/dts/renesas/r8a77990.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 0ea300a8147d..8698058f25f3 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1788,7 +1788,8 @@ sdhi0: mmc@ee100000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77990_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -1801,7 +1802,8 @@ sdhi1: mmc@ee120000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77990_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -1814,7 +1816,8 @@ sdhi3: mmc@ee160000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77990_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 311>; From patchwork Wed Nov 10 19:16:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612725 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA8C3C4167D for ; Wed, 10 Nov 2021 19:16:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B318161186 for ; Wed, 10 Nov 2021 19:16:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232869AbhKJTTW (ORCPT ); Wed, 10 Nov 2021 14:19:22 -0500 Received: from www.zeus03.de ([194.117.254.33]:55218 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232846AbhKJTTT (ORCPT ); Wed, 10 Nov 2021 14:19:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=OrgGMZmww97SHe 5OQgC5aNrf+x4fONkJIfB4jt+34QI=; b=VK2/rZFJ2J47FqQM0MSwRc60CTRTAI aPNUPc6gdvFeNkXIP/5i4rX4hL0cSpdqFvGsd4NjJDkWdqwI8sD67ziUgYnl82Su hiRnq6PvE54MZKuaxU3pKwb5cXdbEj4TuV/WfWoknd405EiGHRrJvQ49M4P6BU9h sSIEhQnSXsEAc= Received: (qmail 722849 invoked from network); 10 Nov 2021 20:16:26 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:26 +0100 X-UD-Smtp-Session: l3s3148p1@0n/xD3TQ8pogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 18/21] arm64: dts: reneas: r8a77995: add SDnH clocks Date: Wed, 10 Nov 2021 20:16:07 +0100 Message-Id: <20211110191610.5664-19-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- Changes since RFC v1: * new patch arch/arm64/boot/dts/renesas/r8a77995.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 16ad5fc23a67..f29f3982a492 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -1216,7 +1216,8 @@ sdhi2: mmc@ee140000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77995_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 312>; From patchwork Wed Nov 10 19:16:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612729 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 670B2C4321E for ; Wed, 10 Nov 2021 19:16:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4E00661186 for ; Wed, 10 Nov 2021 19:16:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231714AbhKJTTW (ORCPT ); Wed, 10 Nov 2021 14:19:22 -0500 Received: from www.zeus03.de ([194.117.254.33]:55214 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232764AbhKJTTT (ORCPT ); Wed, 10 Nov 2021 14:19:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=s6HwuFqBbmVl70 ElFmxaCLk4/ZymU6t4KNsHZMq82/I=; b=UaHHZq+GpzfTQ+MTpgHYpqKODtCEbU Y9WdVHWGM0KrUKgtlT4SESVxwElc3P1OfABR7H81TulDPm2867RKuFpqHBuB+rwz pG1MPSVYqXmGUYHNi2Ysz3iSFYhjXmenagMWeWfNZ12STj4J39oNbo5sKc5p8F6n 8QIlO/ipAwB3g= Received: (qmail 722875 invoked from network); 10 Nov 2021 20:16:26 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:26 +0100 X-UD-Smtp-Session: l3s3148p1@bQj5D3TQ9JogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 19/21] mmc: sdhi: use dev_err_probe when getting clock fails Date: Wed, 10 Nov 2021 20:16:08 +0100 Message-Id: <20211110191610.5664-20-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org This is to improve deferred probe in this driver and to keep consistent with an up-to-date handling of a soon to be added second clock. Signed-off-by: Wolfram Sang Acked-by: Ulf Hansson Reviewed-by: Geert Uytterhoeven --- Changes since RFC v1: * new patch drivers/mmc/host/renesas_sdhi_core.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index 4572242f9816..230182de5e88 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -916,11 +916,8 @@ int renesas_sdhi_probe(struct platform_device *pdev, dma_priv = &priv->dma_priv; priv->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(priv->clk)) { - ret = PTR_ERR(priv->clk); - dev_err(&pdev->dev, "cannot get clock: %d\n", ret); - return ret; - } + if (IS_ERR(priv->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), "cannot get clock"); /* * Some controllers provide a 2nd clock just to run the internal card From patchwork Wed Nov 10 19:16:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612731 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78B5DC2BBC7 for ; Wed, 10 Nov 2021 19:16:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5C1C46117A for ; Wed, 10 Nov 2021 19:16:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232776AbhKJTTX (ORCPT ); Wed, 10 Nov 2021 14:19:23 -0500 Received: from www.zeus03.de ([194.117.254.33]:55238 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232935AbhKJTTU (ORCPT ); Wed, 10 Nov 2021 14:19:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=9REXrPm+GOEDu2 GmfHPmi/iMq4ONyRzWcUQGgWJ9mE8=; b=ErB9ixLzNi2bOUVJb1l6dhE8/3NOMd jgho4pzwjkgz4W3WeVhHjfBUFkr790eqd8rknil4TFap7FTjKzd40Og3DJFqJDGH O9gyPL94E1uDR+3ttIyhQsXmid00LfyvtqcjGgu20l1IPEOCCxldw6TYwX5t/LlN sPrNeUfpORR8c= Received: (qmail 722893 invoked from network); 10 Nov 2021 20:16:27 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:27 +0100 X-UD-Smtp-Session: l3s3148p1@1f3/D3TQ9pogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 20/21] mmc: sdhi: parse DT for SDnH Date: Wed, 10 Nov 2021 20:16:09 +0100 Message-Id: <20211110191610.5664-21-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org If there is a SDnH clock provided in DT, let's use it instead of relying on the fallback. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Acked-by: Ulf Hansson Reviewed-by: Geert Uytterhoeven --- Changes since RFC v1: * added tag from Geert * use dev_err_probe() drivers/mmc/host/renesas_sdhi_core.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index 230182de5e88..db053fba5330 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -919,6 +919,10 @@ int renesas_sdhi_probe(struct platform_device *pdev, if (IS_ERR(priv->clk)) return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), "cannot get clock"); + priv->clkh = devm_clk_get_optional(&pdev->dev, "clkh"); + if (IS_ERR(priv->clkh)) + return dev_err_probe(&pdev->dev, PTR_ERR(priv->clkh), "cannot get clkh"); + /* * Some controllers provide a 2nd clock just to run the internal card * detection logic. Unfortunately, the existing driver architecture does @@ -957,7 +961,7 @@ int renesas_sdhi_probe(struct platform_device *pdev, dma_priv->dma_buswidth = of_data->dma_buswidth; host->bus_shift = of_data->bus_shift; /* Fallback for old DTs */ - if (of_data->sdhi_flags & SDHI_FLAG_NEED_CLKH_FALLBACK) + if (!priv->clkh && of_data->sdhi_flags & SDHI_FLAG_NEED_CLKH_FALLBACK) priv->clkh = clk_get_parent(clk_get_parent(priv->clk)); } From patchwork Wed Nov 10 19:16:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 12612727 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 437DEC31D68 for ; Wed, 10 Nov 2021 19:16:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 19BA561186 for ; Wed, 10 Nov 2021 19:16:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232433AbhKJTTW (ORCPT ); Wed, 10 Nov 2021 14:19:22 -0500 Received: from www.zeus03.de ([194.117.254.33]:55244 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232884AbhKJTTU (ORCPT ); Wed, 10 Nov 2021 14:19:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=k1; bh=H6TupbfjYT9gR1 IYdLUV/bLW1MNe013qrV9bRIq2v0o=; b=x382USPGvLoUH330biZJHc8hwy1/bm 3ExgUNi7fPFq6yKkOfZi+vBYiolbArg7WuCUFyPCZpRisXjD5y+pGnyjq5PTpcGR V+LUiuAOqHvZsiGct2iuql5vscrkJ1buyfCc50cwOHfy7phmmsjfAxGR8lXf7i5W B+8hIlBV0uNno= Received: (qmail 722913 invoked from network); 10 Nov 2021 20:16:27 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 10 Nov 2021 20:16:27 +0100 X-UD-Smtp-Session: l3s3148p1@o0cGEHTQ+JogAwDPXwnKAAv7bcN/CGzA From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: linux-mmc@vger.kernel.org, Yoshihiro Shimoda , Geert Uytterhoeven , Wolfram Sang Subject: [RFC PATCH v2 21/21] arm64: dts: reneas: r8a779a0: add SDnH clocks Date: Wed, 10 Nov 2021 20:16:10 +0100 Message-Id: <20211110191610.5664-22-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> References: <20211110191610.5664-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- There is no dependency on patches 19 or 20. This patch is only last because I noticed only a few seconds before sending out that I overlooked this SoC. Changes since RFC v1: * new patch arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index f9a882b34f82..e3d7ef02a371 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -1097,7 +1097,8 @@ mmc0: mmc@ee140000 { "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 706>; + clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779A0_CLK_SD0H>; + clock-names = "core", "clkh"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 706>; max-frequency = <200000000>;