From patchwork Thu Nov 11 03:16:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12613977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F28D2C433F5 for ; Thu, 11 Nov 2021 03:17:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DDAEB61884 for ; Thu, 11 Nov 2021 03:17:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232002AbhKKDUS (ORCPT ); Wed, 10 Nov 2021 22:20:18 -0500 Received: from mx1.riseup.net ([198.252.153.129]:49936 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232001AbhKKDUQ (ORCPT ); Wed, 10 Nov 2021 22:20:16 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HqRjL5yPRzF4mW; Wed, 10 Nov 2021 19:17:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636600647; bh=Tb9BXhWjM8ETEr9rbF//OKUG6q3GkHqxrZkAdfraSgU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lOspmUKOKb4TgfVoHJfotckRvFbtbX8bPWkUN33uWcUxlDZ+2NPEwnjtGLFRAwBSR 1jMOB+bMJp9z+iEl7ze86bedf4gdtPaHhTJ6ErmCAW+kSxcTZOWv4YaeWfwVPJpUQ5 A1qx8Hfm/bXYL3qR1KfDXQcx2z/GwpJ7IKcwSF6c= X-Riseup-User-ID: 7AED29257AFD94FB1930A1A0AEC5A228E2C0E4FD3AABC1EF80977A3FD538E06E Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HqRjH4qKYz5vVT; Wed, 10 Nov 2021 19:17:23 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexey Min , Caleb Connolly , Martin Botka , Konrad Dybcio Subject: [PATCH v3 1/8] arm64: dts: qcom: sdm630: Assign numbers to eMMC and SD Date: Thu, 11 Nov 2021 10:16:28 +0700 Message-Id: <20211111031635.3839947-2-danct12@riseup.net> In-Reply-To: <20211111031635.3839947-1-danct12@riseup.net> References: <20211111031635.3839947-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This makes eMMC/SD device number consistent. Reviewed-by: Martin Botka Signed-off-by: Dang Huynh --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 3e0165bb61c5..b75bb87ed290 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -19,6 +19,11 @@ / { #address-cells = <2>; #size-cells = <2>; + aliases { + mmc1 = &sdhc_1; + mmc2 = &sdhc_2; + }; + chosen { }; clocks { From patchwork Thu Nov 11 03:16:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12613979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6578FC433FE for ; Thu, 11 Nov 2021 03:17:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4A95A61211 for ; Thu, 11 Nov 2021 03:17:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232317AbhKKDUU (ORCPT ); Wed, 10 Nov 2021 22:20:20 -0500 Received: from mx1.riseup.net ([198.252.153.129]:53750 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232091AbhKKDUU (ORCPT ); Wed, 10 Nov 2021 22:20:20 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HqRjQ1mTzzDyKY; Wed, 10 Nov 2021 19:17:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636600650; bh=9l5JzPtkU4CYHA3+qSbWPt8pduUa9OH5l7W3C86+7/0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nnYahDfYtX2DQOEYP1ymmwbWzbx+GLmue0is66W5mn7sAMyJoT3lvYVxu+RoCxu+u iGQLH9UaMBuHJYTBkPGTa4Op+4T9CfZ910FOUVmB10FBNQMyFWfWC3hXqoXn+99xf+ V3g+MsDE72k9KQ0I0B7RhwEOVS283di2HGQSt54U= X-Riseup-User-ID: 4DC6FD171D7D0A37399E494752934C102B8A6B70F60064293814D38E0B89A4FE Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HqRjM15V4z5vcG; Wed, 10 Nov 2021 19:17:26 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexey Min , Caleb Connolly , Martin Botka , Konrad Dybcio Subject: [PATCH v3 2/8] arm64: dts: qcom: sdm630-pm660: Move RESIN to pm660 dtsi Date: Thu, 11 Nov 2021 10:16:29 +0700 Message-Id: <20211111031635.3839947-3-danct12@riseup.net> In-Reply-To: <20211111031635.3839947-1-danct12@riseup.net> References: <20211111031635.3839947-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org It's not worth duplicating the same node over and over again, so let's keep the common bits in the pm660 DTSI, making only changing the status and keycode necessary. Also, disable RESIN/PWR by default just in case if there are devices that doesn't use them. Signed-off-by: Dang Huynh Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pm660.dtsi | 12 +++++++++++- .../boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 16 ++++++++-------- 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index d0ef8a1675e2..c482663aad56 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -54,14 +54,24 @@ pon: pon@800 { mode-bootloader = <0x2>; mode-recovery = <0x1>; - pwrkey { + pon_pwrkey: pwrkey { compatible = "qcom,pm8941-pwrkey"; interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; debounce = <15625>; bias-pull-up; linux,code = ; + + status = "disabled"; }; + pon_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + + status = "disabled"; + }; }; pm660_temp: temp-alarm@2400 { diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 11d0a8c1cf35..e90c9ec84675 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -215,14 +215,14 @@ &blsp2_uart1 { /* HCI Bluetooth */ }; -&pon { - volup { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + + linux,code = ; }; &qusb2phy { From patchwork Thu Nov 11 03:16:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12613981 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33EEBC433FE for ; Thu, 11 Nov 2021 03:17:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 169C361168 for ; Thu, 11 Nov 2021 03:17:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232091AbhKKDUX (ORCPT ); Wed, 10 Nov 2021 22:20:23 -0500 Received: from mx1.riseup.net ([198.252.153.129]:56372 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232644AbhKKDUW (ORCPT ); Wed, 10 Nov 2021 22:20:22 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HqRjT4WGJzF4mX; Wed, 10 Nov 2021 19:17:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636600653; bh=+E6VEAxjqlIym6A5Rttl+DMEOX5o+2rRv/k27jFeC3w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Z996MHV8evvvQcSE5W+/t8VnosLGVXPGIpSAZVWTl88/vukHKwOLHSlptD9/WfMpf oFeAU/THCN8rLH5apBbAarnzC0KWNmXSaIjXskpWGa07f93EY39fW78GWGHTL1ReTl pre8PKRO0IAzzmis4PlNSAWiwL+6VrMV/giG0X4o= X-Riseup-User-ID: 8FB5D1EF797A7D96A423D068CBECCB0D1A13D6D20AB4C596B6763F0AEED9EC11 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HqRjQ43tVz5vVT; Wed, 10 Nov 2021 19:17:30 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexey Min , Caleb Connolly , Martin Botka , Konrad Dybcio Subject: [PATCH v3 3/8] arm64: dts: qcom: sdm660-xiaomi-lavender: Add RPM and fixed regulators Date: Thu, 11 Nov 2021 10:16:30 +0700 Message-Id: <20211111031635.3839947-4-danct12@riseup.net> In-Reply-To: <20211111031635.3839947-1-danct12@riseup.net> References: <20211111031635.3839947-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add most of the RPM PM660/PM660L regulators and the fixed ones, defining the common electrical part of this platform. Reviewed-by: Caleb Connolly Reviewed-by: Konrad Dybcio Signed-off-by: Dang Huynh --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 296 ++++++++++++++++++ 1 file changed, 296 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 1edc53fd6941..a6e3062dd520 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -1,11 +1,14 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020, Alexey Minnekhanov + * Copyright (c) 2021, Dang Huynh */ /dts-v1/; #include "sdm660.dtsi" +#include "pm660.dtsi" +#include "pm660l.dtsi" / { model = "Xiaomi Redmi Note 7"; @@ -20,6 +23,16 @@ chosen { stdout-path = "serial0:115200n8"; }; + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -40,6 +53,289 @@ &blsp1_uart2 { status = "okay"; }; +&rpm_requests { + pm660l-regulators { + compatible = "qcom,rpm-pm660l-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>; + vdd_l2-supply = <&vreg_bob>; + vdd_l3_l5_l7_l8-supply = <&vreg_bob>; + vdd_l4_l6-supply = <&vreg_bob>; + vdd_bob-supply = <&vph_pwr>; + + vreg_s1b_1p125: s1 { + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_s2b_1p05: s2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + /* LDOs */ + vreg_l1b_0p925: l1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <925000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + /* SDHCI 3.3V signal doesn't seem to be supported. */ + vreg_l2b_2p95: l2 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2696000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l3b_3p3: l3 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l4b_2p95: l4 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + + regulator-min-microamp = <200>; + regulator-max-microamp = <600000>; + regulator-system-load = <570000>; + regulator-allow-set-load; + }; + + /* + * Downstream specifies a range of 1721-3600mV, + * but the only assigned consumers are SDHCI2 VMMC + * and Coresight QPDI that both request pinned 2.95V. + * Tighten the range to 1.8-3.328 (closest to 3.3) to + * make the mmc driver happy. + */ + vreg_l5b_2p95: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3328000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + regulator-system-load = <800000>; + }; + + vreg_l7b_3p125: l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3125000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l8b_3p3: l8 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + regulator-enable-ramp-delay = <500>; + regulator-ramp-delay = <0>; + }; + }; + + pm660-regulators { + compatible = "qcom,rpm-pm660-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>; + vdd_l2_l3-supply = <&vreg_s2b_1p05>; + vdd_l5-supply = <&vreg_s2b_1p05>; + vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>; + vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>; + + /* + * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed + * by the Core Power Reduction hardened (CPRh) and the + * Operating State Manager (OSM) HW automatically. + */ + + vreg_s4a_2p04: s4 { + regulator-min-microvolt = <1805000>; + regulator-max-microvolt = <2040000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + vreg_s5a_1p35: s5 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1350000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_s6a_0p87: s6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <992000>; + regulator-enable-ramp-delay = <150>; + regulator-ramp-delay = <0>; + }; + + /* LDOs */ + vreg_l1a_1p225: l1 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l2a_1p0: l2 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l3a_1p0: l3 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l5a_0p848: l5 { + regulator-min-microvolt = <525000>; + regulator-max-microvolt = <950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l6a_1p3: l6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1370000>; + regulator-allow-set-load; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l7a_1p2: l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l8a_1p8: l8 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-system-load = <325000>; + regulator-allow-set-load; + }; + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l10a_1p8: l10 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l11a_1p8: l11 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l12a_1p8: l12 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + /* This gives power to the LPDDR4: never turn it off! */ + vreg_l13a_1p8: l13 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_l14a_1p8: l14 { + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l15a_1p8: l15 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l16a_2p7: l16 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + vreg_l17a_1p8: l17 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l19a_3p3: l19 { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + }; +}; + &tlmm { gpio-reserved-ranges = <8 4>; }; From patchwork Thu Nov 11 03:16:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12613983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AC23C433EF for ; Thu, 11 Nov 2021 03:17:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 30FD26128E for ; Thu, 11 Nov 2021 03:17:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232854AbhKKDU3 (ORCPT ); Wed, 10 Nov 2021 22:20:29 -0500 Received: from mx1.riseup.net ([198.252.153.129]:56402 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232783AbhKKDU0 (ORCPT ); Wed, 10 Nov 2021 22:20:26 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HqRjY0NHzzF4mY; Wed, 10 Nov 2021 19:17:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636600657; bh=8TauUxZkiNg5ppZozh5OULeODk29ED0rFMX86FlIqf0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KpJeXd0LIC8oZPhQqnc50hc9GCpWhJrX+JJ3zfLLEgFeOvW/vh5olmO60aO4XGsZ8 6o1HCZzMGAmIjHd9N0IubtxBYF1CFqpAEGUBTdjiWM+NqEi0KydRFcWj8suI8FYgwg avCtVNwgHshUa6So1uO245yb2jfchvU+rVEsOy3Q= X-Riseup-User-ID: CCCA4FE7A3D4480E008B516950091965B64F715DC42B61FD00C1F9D47186F5C5 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HqRjT72jrz5vVT; Wed, 10 Nov 2021 19:17:33 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexey Min , Caleb Connolly , Martin Botka , Konrad Dybcio Subject: [PATCH v3 4/8] arm64: dts: qcom: sdm660-xiaomi-lavender: Add PWRKEY and RESIN Date: Thu, 11 Nov 2021 10:16:31 +0700 Message-Id: <20211111031635.3839947-5-danct12@riseup.net> In-Reply-To: <20211111031635.3839947-1-danct12@riseup.net> References: <20211111031635.3839947-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This enables the volume down key as well as the power button. Reviewed-by: Caleb Connolly Reviewed-by: Martin Botka Reviewed-by: Konrad Dybcio Signed-off-by: Dang Huynh Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index a6e3062dd520..729b71407c36 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -53,6 +53,16 @@ &blsp1_uart2 { status = "okay"; }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + + linux,code = ; +}; + &rpm_requests { pm660l-regulators { compatible = "qcom,rpm-pm660l-regulators"; From patchwork Thu Nov 11 03:16:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12613985 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9A40C43219 for ; Thu, 11 Nov 2021 03:17:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CEDE661168 for ; Thu, 11 Nov 2021 03:17:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233064AbhKKDUb (ORCPT ); Wed, 10 Nov 2021 22:20:31 -0500 Received: from mx1.riseup.net ([198.252.153.129]:59000 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232799AbhKKDU3 (ORCPT ); Wed, 10 Nov 2021 22:20:29 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HqRjc3kWrzF4mW; Wed, 10 Nov 2021 19:17:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636600660; bh=MpgI30sbqsmhgOb2wAZVGaCamJzY5tWBYSozOdcFyHU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=q1dnxi+IF+h8zmwikRMnXLbOjEBm332iU1P5UMuiquVf4cEgWtsw0hwiZ9vCjXrWN XnVcsGXVZVoQbmT05N3BGCZc0qr/49wfr3kQprgw+uUfeYU/A16oz3YJrWsucGk5fe +/Zfv0f/GNb+7DrnetEbi3r8G7hSsx9OLlP9LvUk= X-Riseup-User-ID: 6DC39C03D19EEADB7351C8E3E54ED413D0D0D00C907110C227F46FB53441DC24 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HqRjY2x7Zz5vVT; Wed, 10 Nov 2021 19:17:37 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexey Min , Caleb Connolly , Martin Botka , Konrad Dybcio Subject: [PATCH v3 5/8] arm64: dts: qcom: sdm660-xiaomi-lavender: Add volume up button Date: Thu, 11 Nov 2021 10:16:32 +0700 Message-Id: <20211111031635.3839947-6-danct12@riseup.net> In-Reply-To: <20211111031635.3839947-1-danct12@riseup.net> References: <20211111031635.3839947-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This enables the volume up key. Reviewed-by: Caleb Connolly Reviewed-by: Martin Botka Reviewed-by: Konrad Dybcio Signed-off-by: Dang Huynh --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 729b71407c36..456562cb6028 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -9,6 +9,9 @@ #include "sdm660.dtsi" #include "pm660.dtsi" #include "pm660l.dtsi" +#include +#include +#include / { model = "Xiaomi Redmi Note 7"; @@ -33,6 +36,18 @@ vph_pwr: vph-pwr-regulator { regulator-boot-on; }; + gpio-keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + volup { + label = "Volume Up"; + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; From patchwork Thu Nov 11 03:16:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12613987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A81D1C433FE for ; Thu, 11 Nov 2021 03:17:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 915C461168 for ; Thu, 11 Nov 2021 03:17:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233592AbhKKDUk (ORCPT ); Wed, 10 Nov 2021 22:20:40 -0500 Received: from mx1.riseup.net ([198.252.153.129]:34124 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233306AbhKKDUd (ORCPT ); Wed, 10 Nov 2021 22:20:33 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HqRjg6ZrQzDyKY; Wed, 10 Nov 2021 19:17:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636600664; bh=TTY9e8+tLz6bAHkA4/m+3pQrSMljSr4gAxpZh5sUHtY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FceAHeKMZyy5c29Tn1d49miIHqoEWifvJvyxnUmOn4salsYyzzJ6evZqC2reSZMO/ Z0ZX35V6aEk5608Nyykn0fLUrzxKtIC1cdm1QMwCOnaxwwsbEpGuwQ5JTUxlTClEQl 65Z/dIQAvOVSj5EWXFmxeQBRfQNviiKcGA1Fjhw0= X-Riseup-User-ID: F51ED192DB77A9AA1626900D723A59EF81DFEDF932FD0004E1F940A4E518E09A Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HqRjc60hYz5vVT; Wed, 10 Nov 2021 19:17:40 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexey Min , Caleb Connolly , Martin Botka , Konrad Dybcio Subject: [PATCH v3 6/8] arm64: dts: qcom: sdm660-xiaomi-lavender: Add eMMC and SD Date: Thu, 11 Nov 2021 10:16:33 +0700 Message-Id: <20211111031635.3839947-7-danct12@riseup.net> In-Reply-To: <20211111031635.3839947-1-danct12@riseup.net> References: <20211111031635.3839947-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This commit enable the SD card slot and internal MMC. Reviewed-by: Caleb Connolly Signed-off-by: Dang Huynh --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 456562cb6028..8de3e111f427 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -361,6 +361,25 @@ vreg_l19a_3p3: l19 { }; }; +&sdhc_1 { + status = "okay"; + supports-cqe; + + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + vmmc-supply = <&vreg_l4b_2p95>; + vqmmc-supply = <&vreg_l8a_1p8>; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&vreg_l5b_2p95>; + vqmmc-supply = <&vreg_l2b_2p95>; +}; + &tlmm { gpio-reserved-ranges = <8 4>; }; From patchwork Thu Nov 11 03:16:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12613989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4056AC433F5 for ; Thu, 11 Nov 2021 03:17:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2871B619E4 for ; Thu, 11 Nov 2021 03:17:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232890AbhKKDUm (ORCPT ); Wed, 10 Nov 2021 22:20:42 -0500 Received: from mx1.riseup.net ([198.252.153.129]:37566 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232911AbhKKDUh (ORCPT ); Wed, 10 Nov 2021 22:20:37 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HqRjl2syLzF4mW; Wed, 10 Nov 2021 19:17:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636600667; bh=I/aKdEnoiBFbiFzC2dEs2OH2kvICILIFbb+XDL8pUHQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nZZ7VLgnykRgh4S50VhSKAt9CVwuhObHR/dDmw8+hfO7tgHKAS+/oCykBQExuJoP3 CoSXT6EawePVthZZZbEGvC3oqbcYMt3bYUKZ7KhPo67u/mNauUXX+oxpBsQMC9jB5A L78CvgQ0jwg1VyS3QQZGizLmPemWYbyI2z0PD7xI= X-Riseup-User-ID: 0F508C3F93D0092647A4B9EA47CE91A5387A82371067F7314AEF16A127F36FBA Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HqRjh24Cjz5vVT; Wed, 10 Nov 2021 19:17:44 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexey Min , Caleb Connolly , Martin Botka , Konrad Dybcio Subject: [PATCH v3 7/8] arm64: dts: qcom: sdm660-xiaomi-lavender: Enable Simple Framebuffer Date: Thu, 11 Nov 2021 10:16:34 +0700 Message-Id: <20211111031635.3839947-8-danct12@riseup.net> In-Reply-To: <20211111031635.3839947-1-danct12@riseup.net> References: <20211111031635.3839947-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This lets the user sees the framebuffer console. Reviewed-by: Caleb Connolly Reviewed-by: Martin Botka Reviewed-by: Konrad Dybcio Signed-off-by: Dang Huynh Reviewed-by: Konrad Dybcio --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 8de3e111f427..712392545c2e 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -23,7 +23,20 @@ aliases { }; chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + stdout-path = "serial0:115200n8"; + + framebuffer0: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0 0x9d400000 0 (1080 * 2340 * 4)>; + width = <1080>; + height = <2340>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; }; vph_pwr: vph-pwr-regulator { @@ -61,6 +74,11 @@ ramoops@a0000000 { ftrace-size = <0x0>; pmsg-size = <0x20000>; }; + + framebuffer_mem: memory@9d400000 { + reg = <0x0 0x9d400000 0x0 0x23ff000>; + no-map; + }; }; }; From patchwork Thu Nov 11 03:16:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 12613991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEAFEC4332F for ; Thu, 11 Nov 2021 03:17:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C5C8E619BB for ; Thu, 11 Nov 2021 03:17:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233451AbhKKDUo (ORCPT ); Wed, 10 Nov 2021 22:20:44 -0500 Received: from mx1.riseup.net ([198.252.153.129]:38564 "EHLO mx1.riseup.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233488AbhKKDUk (ORCPT ); Wed, 10 Nov 2021 22:20:40 -0500 Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4HqRjp6K0nzF4mX; Wed, 10 Nov 2021 19:17:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1636600670; bh=rJOs4g7bozgwSUa7JZjdMB+XtSwhjDCNlVWpVg72aWc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=paaB4IG4j/C7kHdtFEBYm+xHxe+BBUGWloQk876gC/0fWd9OYJolI1tQ2x2BqZC8c fbRFCB4d4N2yqx2Smv3Vbfnt/e5b62ZRlOoZKKWcpVGajRxO4i40KMCBLz8qF50Q3M H6mbnSShAX8e0r5/FiZVJQlj3gqtzbewM+JRgcTA= X-Riseup-User-ID: 0B43D6D9C3711605E8FEDC38747C0B88BEA6669E54E02F47FA8820D4F5B9F74C Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4HqRjl5TtBz5vVT; Wed, 10 Nov 2021 19:17:47 -0800 (PST) From: Dang Huynh To: Dang Huynh Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexey Min , Caleb Connolly , Martin Botka , Konrad Dybcio Subject: [PATCH v3 8/8] arm64: dts: qcom: sdm660-xiaomi-lavender: Add USB Date: Thu, 11 Nov 2021 10:16:35 +0700 Message-Id: <20211111031635.3839947-9-danct12@riseup.net> In-Reply-To: <20211111031635.3839947-1-danct12@riseup.net> References: <20211111031635.3839947-1-danct12@riseup.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Alexey Min Enable and configure DWC3 and QUSB2 PHY to enable USB functionality on the Redmi Note 7. Signed-off-by: Alexey Min Co-developed-by: Dang Huynh Signed-off-by: Dang Huynh Reviewed-by: Konrad Dybcio --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 712392545c2e..bf7f334b0b5c 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -80,6 +80,15 @@ framebuffer_mem: memory@9d400000 { no-map; }; }; + + /* + * Until we hook up type-c detection, we + * have to stick with this. But it works. + */ + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + }; }; &blsp1_uart2 { @@ -96,6 +105,13 @@ &pon_resin { linux,code = ; }; +&qusb2phy { + status = "okay"; + + vdd-supply = <&vreg_l1b_0p925>; + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; +}; + &rpm_requests { pm660l-regulators { compatible = "qcom,rpm-pm660l-regulators"; @@ -401,3 +417,12 @@ &sdhc_2 { &tlmm { gpio-reserved-ranges = <8 4>; }; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; + extcon = <&extcon_usb>; +};