From patchwork Thu Nov 11 06:51:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srikandan, Nandhini" X-Patchwork-Id: 12614287 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C8B2C433EF for ; Thu, 11 Nov 2021 06:54:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7DD306112F for ; Thu, 11 Nov 2021 06:54:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231444AbhKKG5R (ORCPT ); Thu, 11 Nov 2021 01:57:17 -0500 Received: from mga11.intel.com ([192.55.52.93]:34073 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230400AbhKKG5Q (ORCPT ); Thu, 11 Nov 2021 01:57:16 -0500 X-IronPort-AV: E=McAfee;i="6200,9189,10164"; a="230324727" X-IronPort-AV: E=Sophos;i="5.87,225,1631602800"; d="scan'208";a="230324727" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2021 22:54:26 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,225,1631602800"; d="scan'208";a="642864895" Received: from ubuntu18.png.intel.com ([10.88.229.69]) by fmsmga001.fm.intel.com with ESMTP; 10 Nov 2021 22:54:23 -0800 From: nandhini.srikandan@intel.com To: fancer.lancer@gmail.com, broonie@kernel.org, robh+dt@kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org, mgross@linux.intel.com, kris.pan@intel.com, kenchappa.demakkanavar@intel.com, furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com, mahesh.r.vaidya@intel.com, nandhini.srikandan@intel.com, rashmi.a@intel.com Subject: [PATCH v3 1/5] dt-bindings: spi: Add SSTE support for DWC SSI controller Date: Thu, 11 Nov 2021 14:51:57 +0800 Message-Id: <20211111065201.10249-2-nandhini.srikandan@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211111065201.10249-1-nandhini.srikandan@intel.com> References: <20211111065201.10249-1-nandhini.srikandan@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Nandhini Srikandan Add Slave Select Toggle Enable(SSTE) support for DWC SSI controller. Signed-off-by: Nandhini Srikandan --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index ca91201a9926..866416d01e94 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -149,6 +149,12 @@ patternProperties: is an optional feature of the designware controller, and the upper limit is also subject to controller configuration. + snps,sste: + description: Slave select line will toggle between consecutive + data frames, with the serial clock being held to its default + value while slave select line is high. + type: boolean + unevaluatedProperties: false required: From patchwork Thu Nov 11 06:51:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srikandan, Nandhini" X-Patchwork-Id: 12614289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4743C433F5 for ; Thu, 11 Nov 2021 06:54:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B7D6F61284 for ; Thu, 11 Nov 2021 06:54:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231511AbhKKG5T (ORCPT ); Thu, 11 Nov 2021 01:57:19 -0500 Received: from mga11.intel.com ([192.55.52.93]:34073 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231514AbhKKG5S (ORCPT ); Thu, 11 Nov 2021 01:57:18 -0500 X-IronPort-AV: E=McAfee;i="6200,9189,10164"; a="230324733" X-IronPort-AV: E=Sophos;i="5.87,225,1631602800"; d="scan'208";a="230324733" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2021 22:54:30 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,225,1631602800"; d="scan'208";a="642864908" Received: from ubuntu18.png.intel.com ([10.88.229.69]) by fmsmga001.fm.intel.com with ESMTP; 10 Nov 2021 22:54:26 -0800 From: nandhini.srikandan@intel.com To: fancer.lancer@gmail.com, broonie@kernel.org, robh+dt@kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org, mgross@linux.intel.com, kris.pan@intel.com, kenchappa.demakkanavar@intel.com, furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com, mahesh.r.vaidya@intel.com, nandhini.srikandan@intel.com, rashmi.a@intel.com Subject: [PATCH v3 2/5] spi: dw: Add SSTE support for DWC SSI controller Date: Thu, 11 Nov 2021 14:51:58 +0800 Message-Id: <20211111065201.10249-3-nandhini.srikandan@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211111065201.10249-1-nandhini.srikandan@intel.com> References: <20211111065201.10249-1-nandhini.srikandan@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Nandhini Srikandan Add support for Slave Select Toggle Enable (SSTE) in DWC SSI controller via DTS. The slave select line will toggle between consecutive data frames, with the serial clock being held to its default value while slave select line is high. Signed-off-by: Nandhini Srikandan --- drivers/spi/spi-dw-core.c | 11 +++++++++++ drivers/spi/spi-dw.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index a305074c482e..bfa075a4f779 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -27,6 +27,7 @@ struct chip_data { u32 cr0; u32 rx_sample_dly; /* RX sample delay */ + bool sste; /* Slave select Toggle flag */ }; #ifdef CONFIG_DEBUG_FS @@ -269,6 +270,7 @@ static irqreturn_t dw_spi_irq(int irq, void *dev_id) static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi) { + struct chip_data *chip = spi_get_ctldata(spi); u32 cr0 = 0; if (!(dws->caps & DW_SPI_CAP_DWC_SSI)) { @@ -285,6 +287,9 @@ static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi) /* CTRLR0[11] Shift Register Loop */ cr0 |= ((spi->mode & SPI_LOOP) ? 1 : 0) << SPI_SRL_OFFSET; + + /* CTRLR0[24] Slave Select Toggle Enable */ + cr0 |= chip->sste << SPI_SSTE_OFFSET; } else { /* CTRLR0[ 7: 6] Frame Format */ cr0 |= SSI_MOTO_SPI << DWC_SSI_CTRLR0_FRF_OFFSET; @@ -300,6 +305,9 @@ static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi) /* CTRLR0[13] Shift Register Loop */ cr0 |= ((spi->mode & SPI_LOOP) ? 1 : 0) << DWC_SSI_CTRLR0_SRL_OFFSET; + /* CTRLR0[14] Slave Select Toggle Enable */ + cr0 |= chip->sste << DWC_SSI_CTRLR0_SSTE_OFFSET; + if (dws->caps & DW_SPI_CAP_KEEMBAY_MST) cr0 |= DWC_SSI_CTRLR0_KEEMBAY_MST; } @@ -789,6 +797,9 @@ static int dw_spi_setup(struct spi_device *spi) chip->rx_sample_dly = DIV_ROUND_CLOSEST(rx_sample_dly_ns, NSEC_PER_SEC / dws->max_freq); + + /* Get slave select toggling feature requirement */ + chip->sste = device_property_read_bool(&spi->dev, "snps,sste"); } /* diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index b665e040862c..2ee3f839de39 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -65,8 +65,10 @@ #define SPI_SLVOE_OFFSET 10 #define SPI_SRL_OFFSET 11 #define SPI_CFS_OFFSET 12 +#define SPI_SSTE_OFFSET 24 /* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */ +#define DWC_SSI_CTRLR0_SSTE_OFFSET 14 #define DWC_SSI_CTRLR0_SRL_OFFSET 13 #define DWC_SSI_CTRLR0_TMOD_OFFSET 10 #define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10) From patchwork Thu Nov 11 06:51:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srikandan, Nandhini" X-Patchwork-Id: 12614291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBA0FC433F5 for ; Thu, 11 Nov 2021 06:54:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B364C6128E for ; Thu, 11 Nov 2021 06:54:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231880AbhKKG52 (ORCPT ); Thu, 11 Nov 2021 01:57:28 -0500 Received: from mga11.intel.com ([192.55.52.93]:34073 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231723AbhKKG5X (ORCPT ); Thu, 11 Nov 2021 01:57:23 -0500 X-IronPort-AV: E=McAfee;i="6200,9189,10164"; a="230324755" X-IronPort-AV: E=Sophos;i="5.87,225,1631602800"; d="scan'208";a="230324755" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2021 22:54:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,225,1631602800"; d="scan'208";a="642864923" Received: from ubuntu18.png.intel.com ([10.88.229.69]) by fmsmga001.fm.intel.com with ESMTP; 10 Nov 2021 22:54:30 -0800 From: nandhini.srikandan@intel.com To: fancer.lancer@gmail.com, broonie@kernel.org, robh+dt@kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org, mgross@linux.intel.com, kris.pan@intel.com, kenchappa.demakkanavar@intel.com, furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com, mahesh.r.vaidya@intel.com, nandhini.srikandan@intel.com, rashmi.a@intel.com Subject: [PATCH v3 3/5] spi: dw: Add support for master mode selection for DWC SSI controller Date: Thu, 11 Nov 2021 14:51:59 +0800 Message-Id: <20211111065201.10249-4-nandhini.srikandan@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211111065201.10249-1-nandhini.srikandan@intel.com> References: <20211111065201.10249-1-nandhini.srikandan@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Nandhini Srikandan Add support to select the controller mode as master mode by setting Bit 31 of CTRLR0 register. This feature is supported for controller versions above v1.02. Signed-off-by: Nandhini Srikandan --- drivers/spi/spi-dw-core.c | 4 ++-- drivers/spi/spi-dw.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index bfa075a4f779..26d0ef87661d 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -308,8 +308,8 @@ static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi) /* CTRLR0[14] Slave Select Toggle Enable */ cr0 |= chip->sste << DWC_SSI_CTRLR0_SSTE_OFFSET; - if (dws->caps & DW_SPI_CAP_KEEMBAY_MST) - cr0 |= DWC_SSI_CTRLR0_KEEMBAY_MST; + /* CTRLR0[31] MST */ + cr0 |= DWC_SSI_CTRLR0_MST; } return cr0; diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 2ee3f839de39..d67f62ff79c9 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -78,11 +78,11 @@ #define DWC_SSI_CTRLR0_DFS_OFFSET 0 /* - * For Keem Bay, CTRLR0[31] is used to select controller mode. + * CTRLR0[31] is used to select controller mode. * 0: SSI is slave * 1: SSI is master */ -#define DWC_SSI_CTRLR0_KEEMBAY_MST BIT(31) +#define DWC_SSI_CTRLR0_MST BIT(31) /* Bit fields in CTRLR1 */ #define SPI_NDF_MASK GENMASK(15, 0) From patchwork Thu Nov 11 06:52:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srikandan, Nandhini" X-Patchwork-Id: 12614293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 763CEC433EF for ; Thu, 11 Nov 2021 06:54:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5C6BE6128E for ; Thu, 11 Nov 2021 06:54:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231740AbhKKG5a (ORCPT ); Thu, 11 Nov 2021 01:57:30 -0500 Received: from mga11.intel.com ([192.55.52.93]:34083 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231847AbhKKG50 (ORCPT ); Thu, 11 Nov 2021 01:57:26 -0500 X-IronPort-AV: E=McAfee;i="6200,9189,10164"; a="230324761" X-IronPort-AV: E=Sophos;i="5.87,225,1631602800"; d="scan'208";a="230324761" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2021 22:54:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,225,1631602800"; d="scan'208";a="642864947" Received: from ubuntu18.png.intel.com ([10.88.229.69]) by fmsmga001.fm.intel.com with ESMTP; 10 Nov 2021 22:54:34 -0800 From: nandhini.srikandan@intel.com To: fancer.lancer@gmail.com, broonie@kernel.org, robh+dt@kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org, mgross@linux.intel.com, kris.pan@intel.com, kenchappa.demakkanavar@intel.com, furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com, mahesh.r.vaidya@intel.com, nandhini.srikandan@intel.com, rashmi.a@intel.com Subject: [PATCH v3 4/5] dt-bindings: spi: Add bindings for Intel Thunder Bay SoC Date: Thu, 11 Nov 2021 14:52:00 +0800 Message-Id: <20211111065201.10249-5-nandhini.srikandan@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211111065201.10249-1-nandhini.srikandan@intel.com> References: <20211111065201.10249-1-nandhini.srikandan@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Nandhini Srikandan Add documentation for SPI controller in Intel Thunder Bay SoC. Signed-off-by: Nandhini Srikandan Acked-by: Rob Herring --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index 866416d01e94..5b126a034981 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -61,6 +61,8 @@ properties: - const: snps,dw-apb-ssi - description: Intel Keem Bay SPI Controller const: intel,keembay-ssi + - description: Intel Thunder Bay SPI Controller + const: intel,thunderbay-ssi - description: Baikal-T1 SPI Controller const: baikal,bt1-ssi - description: Baikal-T1 System Boot SPI Controller From patchwork Thu Nov 11 06:52:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srikandan, Nandhini" X-Patchwork-Id: 12614295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24F62C433F5 for ; Thu, 11 Nov 2021 06:54:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 110356112F for ; Thu, 11 Nov 2021 06:54:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232034AbhKKG5d (ORCPT ); Thu, 11 Nov 2021 01:57:33 -0500 Received: from mga11.intel.com ([192.55.52.93]:34073 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231730AbhKKG53 (ORCPT ); Thu, 11 Nov 2021 01:57:29 -0500 X-IronPort-AV: E=McAfee;i="6200,9189,10164"; a="230324766" X-IronPort-AV: E=Sophos;i="5.87,225,1631602800"; d="scan'208";a="230324766" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2021 22:54:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,225,1631602800"; d="scan'208";a="642864959" Received: from ubuntu18.png.intel.com ([10.88.229.69]) by fmsmga001.fm.intel.com with ESMTP; 10 Nov 2021 22:54:38 -0800 From: nandhini.srikandan@intel.com To: fancer.lancer@gmail.com, broonie@kernel.org, robh+dt@kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org, mgross@linux.intel.com, kris.pan@intel.com, kenchappa.demakkanavar@intel.com, furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com, mahesh.r.vaidya@intel.com, nandhini.srikandan@intel.com, rashmi.a@intel.com Subject: [PATCH v3 5/5] spi: dw: Add support for Intel Thunder Bay SPI controller Date: Thu, 11 Nov 2021 14:52:01 +0800 Message-Id: <20211111065201.10249-6-nandhini.srikandan@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211111065201.10249-1-nandhini.srikandan@intel.com> References: <20211111065201.10249-1-nandhini.srikandan@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Nandhini Srikandan Add support for Intel Thunder Bay SPI controller, which uses DesignWare DWC_ssi core and also add common init function for both Keem Bay and Thunder Bay. Signed-off-by: Nandhini Srikandan --- drivers/spi/spi-dw-mmio.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 3379720cfcb8..c357680f4aa3 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -214,10 +214,10 @@ static int dw_spi_dwc_ssi_init(struct platform_device *pdev, return 0; } -static int dw_spi_keembay_init(struct platform_device *pdev, - struct dw_spi_mmio *dwsmmio) +static int dw_spi_intel_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) { - dwsmmio->dws.caps = DW_SPI_CAP_KEEMBAY_MST | DW_SPI_CAP_DWC_SSI; + dwsmmio->dws.caps = DW_SPI_CAP_DWC_SSI; return 0; } @@ -348,7 +348,8 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init}, { .compatible = "renesas,rzn1-spi", .data = dw_spi_dw_apb_init}, { .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_dwc_ssi_init}, - { .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init}, + { .compatible = "intel,keembay-ssi", .data = dw_spi_intel_init}, + { .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init}, { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init}, { /* end of table */}