From patchwork Sun Nov 14 01:27:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 12617777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C00B6C433F5 for ; Sun, 14 Nov 2021 01:28:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9F2C96112F for ; Sun, 14 Nov 2021 01:28:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236070AbhKNBa7 (ORCPT ); Sat, 13 Nov 2021 20:30:59 -0500 Received: from relay06.th.seeweb.it ([5.144.164.167]:58337 "EHLO relay06.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229988AbhKNBa6 (ORCPT ); Sat, 13 Nov 2021 20:30:58 -0500 Received: from localhost.localdomain (83.6.165.118.neoplus.adsl.tpnet.pl [83.6.165.118]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 34B6A3EE3F; Sun, 14 Nov 2021 02:28:02 +0100 (CET) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , Kees Cook , Anton Vorontsov , Colin Cross , Tony Luck , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/16] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Date: Sun, 14 Nov 2021 02:27:40 +0100 Message-Id: <20211114012755.112226-1-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Almost any board that boots and has a way to interact with it (say for the rare cases of just-pstore or let's-rely-on-bootloader-setup) needs to set some GPIOs, so it makes no sense to include gpio.h separately each time. Hence move it to SoC DTSI. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 1 - arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 1 - arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 + 3 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index be062377c936..1e5e9405d8b1 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -5,7 +5,6 @@ /dts-v1/; -#include #include #include "sm8350.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts index 06eedbe52c42..122c282a62df 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts @@ -5,7 +5,6 @@ /dts-v1/; -#include #include #include "sm8350.dtsi" #include "pm8350.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index d134280e2939..ee183f00dbaf 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include From patchwork Sun Nov 14 01:27:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 12617781 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B555BC433EF for ; Sun, 14 Nov 2021 01:28:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 93F7860524 for ; Sun, 14 Nov 2021 01:28:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236127AbhKNBbD (ORCPT ); Sat, 13 Nov 2021 20:31:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236109AbhKNBbB (ORCPT ); Sat, 13 Nov 2021 20:31:01 -0500 Received: from relay07.th.seeweb.it (relay07.th.seeweb.it [IPv6:2001:4b7a:2000:18::168]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CDEFC061714; Sat, 13 Nov 2021 17:28:07 -0800 (PST) Received: from localhost.localdomain (83.6.165.118.neoplus.adsl.tpnet.pl [83.6.165.118]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 81E323EE52; Sun, 14 Nov 2021 02:28:03 +0100 (CET) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/16] arm64: dts: qcom: sm8350: Add missing QUPv3 ID2 Date: Sun, 14 Nov 2021 02:27:41 +0100 Message-Id: <20211114012755.112226-2-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211114012755.112226-1-konrad.dybcio@somainline.org> References: <20211114012755.112226-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the missing third QUPv3 master node. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index ee183f00dbaf..6cfe1f38dae9 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -597,6 +597,18 @@ ipcc: mailbox@408000 { #mbox-cells = <2>; }; + qupv3_id_2: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x009c0000 0x0 0x6000>; From patchwork Sun Nov 14 01:27:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 12617779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9F16C433F5 for ; Sun, 14 Nov 2021 01:28:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CD05360F22 for ; Sun, 14 Nov 2021 01:28:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236106AbhKNBbB (ORCPT ); Sat, 13 Nov 2021 20:31:01 -0500 Received: from relay05.th.seeweb.it ([5.144.164.166]:38765 "EHLO relay05.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236057AbhKNBbA (ORCPT ); Sat, 13 Nov 2021 20:31:00 -0500 Received: from localhost.localdomain (83.6.165.118.neoplus.adsl.tpnet.pl [83.6.165.118]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 9ECAC3EE53; Sun, 14 Nov 2021 02:28:04 +0100 (CET) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/16] arm64: dts: qcom: sm8350: Add redistributor stride to GICv3 Date: Sun, 14 Nov 2021 02:27:42 +0100 Message-Id: <20211114012755.112226-3-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211114012755.112226-1-konrad.dybcio@somainline.org> References: <20211114012755.112226-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The redistributor properties were missing. Add them. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 6cfe1f38dae9..a30ba3193d84 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1020,6 +1020,8 @@ intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0 0x20000>; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ interrupts = ; From patchwork Sun Nov 14 01:27:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 12617783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F349C4332F for ; Sun, 14 Nov 2021 01:28:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4036B60F70 for ; Sun, 14 Nov 2021 01:28:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236113AbhKNBbB (ORCPT ); Sat, 13 Nov 2021 20:31:01 -0500 Received: from m-r2.th.seeweb.it ([5.144.164.171]:56159 "EHLO m-r2.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236084AbhKNBbA (ORCPT ); Sat, 13 Nov 2021 20:31:00 -0500 Received: from localhost.localdomain (83.6.165.118.neoplus.adsl.tpnet.pl [83.6.165.118]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id BBDD43EE61; Sun, 14 Nov 2021 02:28:05 +0100 (CET) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/16] arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer Date: Sun, 14 Nov 2021 02:27:43 +0100 Message-Id: <20211114012755.112226-4-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211114012755.112226-1-konrad.dybcio@somainline.org> References: <20211114012755.112226-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Arch timer runs at 19.2 MHz. Specify the rate in the timer node. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index a30ba3193d84..60866a20a55c 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2484,5 +2484,6 @@ timer { , , ; + clock-frequency = <19200000>; }; }; From patchwork Sun Nov 14 01:27:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 12617785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C72F6C433FE for ; Sun, 14 Nov 2021 01:28:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A3A5D60F22 for ; Sun, 14 Nov 2021 01:28:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236142AbhKNBbF (ORCPT ); Sat, 13 Nov 2021 20:31:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236116AbhKNBbC (ORCPT ); Sat, 13 Nov 2021 20:31:02 -0500 Received: from relay05.th.seeweb.it (relay05.th.seeweb.it [IPv6:2001:4b7a:2000:18::166]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F2C0C061767 for ; Sat, 13 Nov 2021 17:28:09 -0800 (PST) Received: from localhost.localdomain (83.6.165.118.neoplus.adsl.tpnet.pl [83.6.165.118]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id E61583EE65; Sun, 14 Nov 2021 02:28:06 +0100 (CET) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/16] arm64: dts: qcom: sm[68]350: Use interrupts-extended with pdc interrupts Date: Sun, 14 Nov 2021 02:27:44 +0100 Message-Id: <20211114012755.112226-5-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211114012755.112226-1-konrad.dybcio@somainline.org> References: <20211114012755.112226-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Using interrupts = <&pdc X Y> makes the interrupt framework interpret this as the &pdc-nth range of the main interrupt controller (GIC). Fix it. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 43c8ecb85d17..8fcf04edbf30 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -842,7 +842,7 @@ tsens0: thermal-sensor@c263000 { reg = <0 0x0c263000 0 0x1ff>, /* TM */ <0 0x0c222000 0 0x8>; /* SROT */ #qcom,sensors = <16>; - interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; @@ -853,7 +853,7 @@ tsens1: thermal-sensor@c265000 { reg = <0 0x0c265000 0 0x1ff>, /* TM */ <0 0x0c223000 0 0x8>; /* SROT */ #qcom,sensors = <16>; - interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 60866a20a55c..f3e8549c6572 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -923,7 +923,7 @@ tsens0: thermal-sensor@c263000 { reg = <0 0x0c263000 0 0x1ff>, /* TM */ <0 0x0c222000 0 0x8>; /* SROT */ #qcom,sensors = <15>; - interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; @@ -934,7 +934,7 @@ tsens1: thermal-sensor@c265000 { reg = <0 0x0c265000 0 0x1ff>, /* TM */ <0 0x0c223000 0 0x8>; /* SROT */ #qcom,sensors = <14>; - interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; From patchwork Sun Nov 14 01:27:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 12617787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67377C4332F for ; Sun, 14 Nov 2021 01:28:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4AB9460F36 for ; Sun, 14 Nov 2021 01:28:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236147AbhKNBbG (ORCPT ); Sat, 13 Nov 2021 20:31:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236125AbhKNBbD (ORCPT ); Sat, 13 Nov 2021 20:31:03 -0500 Received: from m-r2.th.seeweb.it (m-r2.th.seeweb.it [IPv6:2001:4b7a:2000:18::171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 492CCC061714; Sat, 13 Nov 2021 17:28:10 -0800 (PST) Received: from localhost.localdomain (83.6.165.118.neoplus.adsl.tpnet.pl [83.6.165.118]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 10B3D3EE53; Sun, 14 Nov 2021 02:28:08 +0100 (CET) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/16] arm64: dts: qcom: sm8350: Shorten camera-thermal-bottom name Date: Sun, 14 Nov 2021 02:27:45 +0100 Message-Id: <20211114012755.112226-6-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211114012755.112226-1-konrad.dybcio@somainline.org> References: <20211114012755.112226-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Thermal zone names should not be longer than 20 names, which is indicated by a message at boot. Change "camera-thermal-bottom" to "cam-thermal-bottom" to fix it. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index f3e8549c6572..7e0aa4c25094 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2462,7 +2462,7 @@ camera1_alert0: trip-point0 { }; }; - camera-thermal-bottom { + cam-thermal-bottom { polling-delay-passive = <250>; polling-delay = <1000>; From patchwork Sun Nov 14 01:27:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 12617789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02238C43219 for ; Sun, 14 Nov 2021 01:28:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E01F461262 for ; Sun, 14 Nov 2021 01:28:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236162AbhKNBbH (ORCPT ); Sat, 13 Nov 2021 20:31:07 -0500 Received: from relay07.th.seeweb.it ([5.144.164.168]:49741 "EHLO relay07.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236130AbhKNBbE (ORCPT ); Sat, 13 Nov 2021 20:31:04 -0500 Received: from localhost.localdomain (83.6.165.118.neoplus.adsl.tpnet.pl [83.6.165.118]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 3ED6D3EE3F; Sun, 14 Nov 2021 02:28:09 +0100 (CET) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/16] arm64: dts: qcom: *8350* Consolidate PON/RESIN usage Date: Sun, 14 Nov 2021 02:27:46 +0100 Message-Id: <20211114012755.112226-7-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211114012755.112226-1-konrad.dybcio@somainline.org> References: <20211114012755.112226-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Disable PON/RESIN keys by default and keep the RESIN keycode set-per-board, as these settings are not common between devices (one cannot even assume all devices have buttons nowadays..). Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pmk8350.dtsi | 7 ++++--- arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 9 +++++++++ 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi index 769f9726806f..0f94c46a1444 100644 --- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi @@ -19,16 +19,17 @@ pmk8350_pon: pon@1300 { compatible = "qcom,pm8998-pon"; reg = <0x1300>; - pwrkey { + pon_pwrkey: pwrkey { compatible = "qcom,pmk8350-pwrkey"; interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; linux,code = ; + status = "disabled"; }; - resin { + pon_resin: resin { compatible = "qcom,pmk8350-resin"; interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; - linux,code = ; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts index 122c282a62df..52cf3045602f 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts @@ -289,6 +289,15 @@ &pmk8350_rtc { status = "okay"; }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + linux,code = ; +}; + &qupv3_id_0 { status = "okay"; }; From patchwork Sun Nov 14 01:27:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 12617791 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 993B5C433FE for ; Sun, 14 Nov 2021 01:28:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8074260F22 for ; Sun, 14 Nov 2021 01:28:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236196AbhKNBbJ (ORCPT ); Sat, 13 Nov 2021 20:31:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236131AbhKNBbG (ORCPT ); Sat, 13 Nov 2021 20:31:06 -0500 Received: from relay06.th.seeweb.it (relay06.th.seeweb.it [IPv6:2001:4b7a:2000:18::167]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBE21C061746; Sat, 13 Nov 2021 17:28:12 -0800 (PST) Received: from localhost.localdomain (83.6.165.118.neoplus.adsl.tpnet.pl [83.6.165.118]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 547E53EE52; Sun, 14 Nov 2021 02:28:10 +0100 (CET) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/16] arm64: dts: qcom: sm8350: Describe GCC dependency clocks Date: Sun, 14 Nov 2021 02:27:47 +0100 Message-Id: <20211114012755.112226-8-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211114012755.112226-1-konrad.dybcio@somainline.org> References: <20211114012755.112226-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add all the clock names that the GCC driver expects to get via DT, so that the clock handles can be filled as the development progresses. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 7e0aa4c25094..3d0d80e61405 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -584,8 +584,30 @@ gcc: clock-controller@100000 { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - clock-names = "bi_tcxo", "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", + "sleep_clk", + "pcie_0_pipe_clk", + "pcie_1_pipe_clk", + "ufs_card_rx_symbol_0_clk", + "ufs_card_rx_symbol_1_clk", + "ufs_card_tx_symbol_0_clk", + "ufs_phy_rx_symbol_0_clk", + "ufs_phy_rx_symbol_1_clk", + "ufs_phy_tx_symbol_0_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk", + "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; }; ipcc: mailbox@408000 { From patchwork Sun Nov 14 01:27:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 12617793 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E801CC4332F for ; Sun, 14 Nov 2021 01:28:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D0AE36124A for ; Sun, 14 Nov 2021 01:28:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236161AbhKNBbL (ORCPT ); Sat, 13 Nov 2021 20:31:11 -0500 Received: from relay07.th.seeweb.it ([5.144.164.168]:43441 "EHLO relay07.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235100AbhKNBbH (ORCPT ); Sat, 13 Nov 2021 20:31:07 -0500 Received: from localhost.localdomain (83.6.165.118.neoplus.adsl.tpnet.pl [83.6.165.118]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 7E13C3EE65; Sun, 14 Nov 2021 02:28:11 +0100 (CET) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/16] arm64: dts: qcom: sm8350: Set up WRAP0 QUPs Date: Sun, 14 Nov 2021 02:27:48 +0100 Message-Id: <20211114012755.112226-9-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211114012755.112226-1-konrad.dybcio@somainline.org> References: <20211114012755.112226-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Set up I2C&SPI hosts and UARTs connected to WRAP0 and their respective pins. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 287 +++++++++++++++++++++++++++ 1 file changed, 287 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 3d0d80e61405..4b864fcb04e0 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -619,6 +619,25 @@ ipcc: mailbox@408000 { #mbox-cells = <2>; }; + qup_opp_table_100mhz: qup-100mhz-opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + qupv3_id_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; @@ -642,6 +661,84 @@ qupv3_id_0: geniqup@9c0000 { ranges; status = "disabled"; + i2c0: i2c@980000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00980000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@980000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00980000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00984000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@984000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00984000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00988000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00988000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart2: serial@98c000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x0098c000 0 0x4000>; @@ -650,6 +747,140 @@ uart2: serial@98c000 { pinctrl-names = "default"; pinctrl-0 = <&qup_uart3_default_state>; interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* QUP no. 3 seems to be strictly SPI-only */ + + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0098c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00990000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@990000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00990000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00994000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c5_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@994000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00994000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@998000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00998000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c6_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@998000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00998000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart6: serial@998000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00998000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart6_default>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + status = "disabled"; + }; + + i2c7: i2c@99c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0099c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c7_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi7: spi@99c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0099c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1017,6 +1248,62 @@ tx { }; }; + qup_uart6_default: qup-uart6-default { + pins = "gpio30", "gpio31"; + function = "qup6"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c0_default: qup-i2c0-default { + pins = "gpio4", "gpio5"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default { + pins = "gpio8", "gpio9"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default { + pins = "gpio12", "gpio13"; + function = "qup2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_default: qup-i2c4-default { + pins = "gpio20", "gpio21"; + function = "qup4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_default: qup-i2c5-default { + pins = "gpio24", "gpio25"; + function = "qup5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c6_default: qup-i2c6-default { + pins = "gpio28", "gpio29"; + function = "qup6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c7_default: qup-i2c7-default { + pins = "gpio32", "gpio33"; + function = "qup7"; + drive-strength = <2>; + bias-disable; + }; + qup_i2c13_default_state: qup-i2c13-default-state { mux { pins = "gpio0", "gpio1"; From patchwork Sun Nov 14 01:27:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 12617799 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DA8AC433FE for ; Sun, 14 Nov 2021 01:28:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 06C53610FE for ; Sun, 14 Nov 2021 01:28:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236193AbhKNBbS (ORCPT ); Sat, 13 Nov 2021 20:31:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236189AbhKNBbJ (ORCPT ); Sat, 13 Nov 2021 20:31:09 -0500 Received: from relay08.th.seeweb.it (relay08.th.seeweb.it [IPv6:2001:4b7a:2000:18::169]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF362C061206; Sat, 13 Nov 2021 17:28:14 -0800 (PST) Received: from localhost.localdomain (83.6.165.118.neoplus.adsl.tpnet.pl [83.6.165.118]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id A14EF3EE6C; Sun, 14 Nov 2021 02:28:12 +0100 (CET) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/16] arm64: dts: qcom: sm8350: Set up WRAP1 QUPs Date: Sun, 14 Nov 2021 02:27:49 +0100 Message-Id: <20211114012755.112226-10-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211114012755.112226-1-konrad.dybcio@somainline.org> References: <20211114012755.112226-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Set up I2C&SPI hosts and UARTs connected to WRAP1 and their respective pins. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 213 +++++++++++++++++++++++++-- 1 file changed, 202 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 4b864fcb04e0..033d3984d572 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -638,6 +638,25 @@ opp-100000000 { }; }; + qup_opp_table_120mhz: qup-120mhz-opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + qupv3_id_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; @@ -898,18 +917,161 @@ qupv3_id_1: geniqup@ac0000 { ranges; status = "disabled"; + i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a80000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi8: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a80000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a84000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c9_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a84000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a8c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c11_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a8c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a90000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c12_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a90000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c13: i2c@a94000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_default_state>; + pinctrl-0 = <&qup_i2c13_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; + + spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a94000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; apps_smmu: iommu@15000000 { @@ -1304,17 +1466,46 @@ qup_i2c7_default: qup-i2c7-default { bias-disable; }; - qup_i2c13_default_state: qup-i2c13-default-state { - mux { - pins = "gpio0", "gpio1"; - function = "qup13"; - }; + qup_i2c8_default: qup-i2c8-default { + pins = "gpio36", "gpio37"; + function = "qup8"; + drive-strength = <2>; + bias-pull-up; + }; - config { - pins = "gpio0", "gpio1"; - drive-strength = <2>; - bias-pull-up; - }; + qup_i2c9_default: qup-i2c9-default { + pins = "gpio40", "gpio41"; + function = "qup9"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c10_default: qup-i2c10-default { + pins = "gpio44", "gpio45"; + function = "qup10"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c11_default: qup-i2c11-default { + pins = "gpio48", "gpio49"; + function = "qup11"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c12_default: qup-i2c12-default { + pins = "gpio52", "gpio53"; + function = "qup12"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c13_default: qup-i2c13-default { + pins = "gpio0", "gpio1"; + function = "qup13"; + drive-strength = <2>; + bias-pull-up; }; }; From patchwork Sun Nov 14 01:27:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 12617797 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFE85C4332F for ; Sun, 14 Nov 2021 01:28:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AC0D261163 for ; Sun, 14 Nov 2021 01:28:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236277AbhKNBbQ (ORCPT ); Sat, 13 Nov 2021 20:31:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236193AbhKNBbJ (ORCPT ); Sat, 13 Nov 2021 20:31:09 -0500 Received: from relay08.th.seeweb.it (relay08.th.seeweb.it [IPv6:2001:4b7a:2000:18::169]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D343FC06120A for ; Sat, 13 Nov 2021 17:28:15 -0800 (PST) Received: from localhost.localdomain (83.6.165.118.neoplus.adsl.tpnet.pl [83.6.165.118]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id C1FAA3EE3F; Sun, 14 Nov 2021 02:28:13 +0100 (CET) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/16] arm64: dts: qcom: sm8350: Set up WRAP2 QUPs Date: Sun, 14 Nov 2021 02:27:50 +0100 Message-Id: <20211114012755.112226-11-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211114012755.112226-1-konrad.dybcio@somainline.org> References: <20211114012755.112226-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Set up I2C&SPI hosts and UARTs connected to WRAP2 and their respective pins. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 200 +++++++++++++++++++++++++++ 1 file changed, 200 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 033d3984d572..944ad864f73e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -667,6 +667,164 @@ qupv3_id_2: geniqup@8c0000 { #size-cells = <2>; ranges; status = "disabled"; + + i2c14: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00880000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c14_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi14: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00880000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c15: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00884000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c15_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi15: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00884000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c16: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c16_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi16: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c17: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c17_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi17: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* QUP no. 18 seems to be strictly SPI/UART-only */ + + spi18: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart18: serial@890000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart18_default>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + status = "disabled"; + }; + + i2c19: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c19_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi19: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; qupv3_id_0: geniqup@9c0000 { @@ -1417,6 +1575,13 @@ qup_uart6_default: qup-uart6-default { bias-disable; }; + qup_uart18_default: qup-uart18-default { + pins = "gpio58", "gpio59"; + function = "qup18"; + drive-strength = <2>; + bias-disable; + }; + qup_i2c0_default: qup-i2c0-default { pins = "gpio4", "gpio5"; function = "qup0"; @@ -1507,6 +1672,41 @@ qup_i2c13_default: qup-i2c13-default { drive-strength = <2>; bias-pull-up; }; + + qup_i2c14_default: qup-i2c14-default { + pins = "gpio56", "gpio57"; + function = "qup14"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c15_default: qup-i2c15-default { + pins = "gpio60", "gpio61"; + function = "qup15"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c16_default: qup-i2c16-default { + pins = "gpio64", "gpio65"; + function = "qup16"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c17_default: qup-i2c17-default { + pins = "gpio72", "gpio73"; + function = "qup17"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c19_default: qup-i2c19-default { + pins = "gpio76", "gpio77"; + function = "qup19"; + drive-strength = <2>; + bias-disable; + }; }; rng: rng@10d3000 { From patchwork Sun Nov 14 01:27:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 12617795 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63CA7C433EF for ; Sun, 14 Nov 2021 01:28:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4CF4E60524 for ; Sun, 14 Nov 2021 01:28:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236146AbhKNBbQ (ORCPT ); Sat, 13 Nov 2021 20:31:16 -0500 Received: from relay08.th.seeweb.it ([5.144.164.169]:42775 "EHLO relay08.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235402AbhKNBbJ (ORCPT ); Sat, 13 Nov 2021 20:31:09 -0500 Received: from localhost.localdomain (83.6.165.118.neoplus.adsl.tpnet.pl [83.6.165.118]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id D26B93EE52; Sun, 14 Nov 2021 02:28:14 +0100 (CET) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/16] arm64: dts: qcom: sm8350: Assign iommus property to QUP WRAPs Date: Sun, 14 Nov 2021 02:27:51 +0100 Message-Id: <20211114012755.112226-12-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211114012755.112226-1-konrad.dybcio@somainline.org> References: <20211114012755.112226-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Assign the iommus property to allow access to QUP hosts that were not set up by the bootloader. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 944ad864f73e..0ea735d0df49 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -663,6 +663,7 @@ qupv3_id_2: geniqup@8c0000 { clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x5e3 0x0>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -833,6 +834,7 @@ qupv3_id_0: geniqup@9c0000 { clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x5a3 0>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -1070,6 +1072,7 @@ qupv3_id_1: geniqup@ac0000 { clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x43 0>; #address-cells = <2>; #size-cells = <2>; ranges; From patchwork Sun Nov 14 01:27:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 12617801 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33960C433EF for ; Sun, 14 Nov 2021 01:28:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1BA5560524 for ; Sun, 14 Nov 2021 01:28:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236219AbhKNBbT (ORCPT ); Sat, 13 Nov 2021 20:31:19 -0500 Received: from relay05.th.seeweb.it ([5.144.164.166]:50979 "EHLO relay05.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236216AbhKNBbN (ORCPT ); Sat, 13 Nov 2021 20:31:13 -0500 Received: from localhost.localdomain (83.6.165.118.neoplus.adsl.tpnet.pl [83.6.165.118]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id EEBC63EE61; Sun, 14 Nov 2021 02:28:17 +0100 (CET) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , Kees Cook , Anton Vorontsov , Colin Cross , Tony Luck , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 13/16] arm64: dts: qcom: Add support for Xperia 1 III / 5 III Date: Sun, 14 Nov 2021 02:27:52 +0100 Message-Id: <20211114012755.112226-13-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211114012755.112226-1-konrad.dybcio@somainline.org> References: <20211114012755.112226-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for SONY Xperia 1 III (PDX215) and 5 III (PDX214) smartphones. Both are based on the SM8350 Sagami platform and feature some really high-end specs, such as: - 4K (1 III / PRO-I) / 1080p (5 III), 120Hz HDR OLED 10-bit panels - USB-C 3.1 with HDMI in (yes, phone as display!) and DP out - 5G - 8 or 12 gigs of ram, 128/256/512 gigs of storage - A 3.5mm headphone jack, a RGB notification LED and a uSD card slot :) - IP65/68 dust/water resistance - Dual front-firing speakers and a lot of microphones - Crazy complex camera hardware (especially on the PRO-I), which includes 4 cameras, an RGBIR sensor and a 3D iToF The aforementioned PRO-I (PDX217) is not supported in this patch, because even though it shares most of the code with 1 III, nobody really has it (yet?) This only adds basic support for booting to a USB shell with a bootloader-enabled display, support for all the awesome hardware listed above will (hopefully) come (hopefully) soon. In order to get a working boot image, you need to run (e.g. for 1 III): cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/sm8350-sony-xperia-\ sagami-pdx215.dtb > .Image.gz-dtb mkbootimg \ --kernel .Image.gz-dtb \ --ramdisk some_initrd.img \ --pagesize 4096 \ --base 0x0 \ --kernel_offset 0x8000 \ --ramdisk_offset 0x1000000 \ --tags_offset 0x100 \ --cmdline "SOME_CMDLINE" \ --dtb_offset 0x1f00000 \ --header_version 1 \ --os_version 11 \ --os_patch_level 2021-10 \ # or newer -o boot.img-sony-xperia-pdx215 Then, you need to flash it on the device and get rid of all the vendor_boot/dtbo mess: fastboot flash boot boot.img-sony-xperia-pdx215 fastboot erase vendor_boot fastboot flash dtbo emptydtbo.img fastboot reboot Where emptydtbo.img is a tiny file that consists of 2 bytes (all zeroes), doing a "fastboot erase" won't cut it, the bootloader will go crazy and things will fall apart when it tries to overlay random bytes from an empty partition onto a perfectly good appended DTB. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../qcom/sm8350-sony-xperia-sagami-pdx214.dts | 19 +++ .../qcom/sm8350-sony-xperia-sagami-pdx215.dts | 13 ++ .../dts/qcom/sm8350-sony-xperia-sagami.dtsi | 132 ++++++++++++++++++ 4 files changed, 166 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts create mode 100644 arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts create mode 100644 arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index bc38b79f4b5b..3a825bdc9052 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -110,3 +110,5 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts new file mode 100644 index 000000000000..cc650508dc2d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include "sm8350-sony-xperia-sagami.dtsi" + +/ { + model = "Sony Xperia 5 III"; + compatible = "sony,pdx214-generic", "qcom,sm8350"; +}; + +&framebuffer { + width = <1080>; + height = <2520>; + stride = <(1080 * 4)>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts new file mode 100644 index 000000000000..d21bbeb603a6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include "sm8350-sony-xperia-sagami.dtsi" + +/ { + model = "Sony Xperia 1 III"; + compatible = "sony,pdx215-generic", "qcom,sm8350"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi new file mode 100644 index 000000000000..b50f04ffee95 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +#include "sm8350.dtsi" +#include "pm8350.dtsi" +#include "pm8350b.dtsi" +#include "pm8350c.dtsi" +#include "pmk8350.dtsi" +#include "pmr735a.dtsi" +#include "pmr735b.dtsi" + +/ { + /* + * Yes, you are correct, there is NO MORE {msm,board,pmic}-id on SM8350! + * Adding it will cause the bootloader to go crazy and randomly crash + * shortly after closing UEFI boot services.. Perhaps that has something + * to do with the OS running inside a VM now..? + */ + + chassis-type = "handset"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@e1000000 { + compatible = "simple-framebuffer"; + reg = <0 0xe1000000 0 0x2300000>; + + /* The display, even though it's 4K, initializes at 1080-ish p */ + width = <1096>; + height = <2560>; + stride = <(1096 * 4)>; + format = "a8r8g8b8"; + /* + * That's (going to be) a lot of clocks, but it's necessary due + * to unused clk cleanup & no panel driver yet + */ + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + /* For reasons still unknown, GAssist key and Camera Focus/Shutter don't work.. */ + + vol-down { + label = "Volume Down"; + linux,code = ; + gpios = <&pmk8350_gpios 3 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + }; + + reserved-memory { + cont_splash_mem: memory@e1000000 { + reg = <0 0xe1000000 0 0x2300000>; + no-map; + }; + + ramoops@ffc00000 { + compatible = "ramoops"; + reg = <0 0xffc00000 0 0x100000>; + console-size = <0x40000>; + record-size = <0x1000>; + no-map; + }; + }; +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + linux,code = ; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <44 4>; +}; + +/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */ +&ufs_mem_hc { status = "disabled"; }; +&ufs_mem_phy { status = "disabled"; }; + +/* TODO: Make USB3 work (perhaps needs regulators for higher-current operation?) */ +&usb_1 { + status = "okay"; + + qcom,select-utmi-as-pipe-clk; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; + + maximum-speed = "high-speed"; + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; +}; + +&usb_1_hsphy { + status = "okay"; +}; + +&usb_1_qmpphy { + status = "okay"; +}; From patchwork Sun Nov 14 01:27:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 12617803 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBC3DC433EF for ; Sun, 14 Nov 2021 01:28:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CF1BA60F36 for ; Sun, 14 Nov 2021 01:28:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236332AbhKNBbZ (ORCPT ); Sat, 13 Nov 2021 20:31:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236252AbhKNBbO (ORCPT ); Sat, 13 Nov 2021 20:31:14 -0500 Received: from relay07.th.seeweb.it (relay07.th.seeweb.it [IPv6:2001:4b7a:2000:18::168]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57BFEC061204; Sat, 13 Nov 2021 17:28:21 -0800 (PST) Received: from localhost.localdomain (83.6.165.118.neoplus.adsl.tpnet.pl [83.6.165.118]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 4931D3EE3F; Sun, 14 Nov 2021 02:28:19 +0100 (CET) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 14/16] arm64: dts: qcom: sm8350-sagami: Enable and populate I2C/SPI nodes Date: Sun, 14 Nov 2021 02:27:53 +0100 Message-Id: <20211114012755.112226-14-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211114012755.112226-1-konrad.dybcio@somainline.org> References: <20211114012755.112226-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Based on current driver availability, add either nodes or comments regarding peripherals connected via I2C/SPI. Signed-off-by: Konrad Dybcio --- .../dts/qcom/sm8350-sony-xperia-sagami.dtsi | 101 ++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index b50f04ffee95..c44376aa0742 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -75,6 +75,93 @@ ramoops@ffc00000 { }; }; +&i2c1 { + status = "okay"; + clock-frequency = <1000000>; + + /* Some subset of SONY IMX663 camera sensor @ 38 */ +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + /* Richwave RTC6226 FM Radio Receiver @ 64 */ +}; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + /* Samsung Touchscreen (needs I2C GPI DMA) @ 48 */ +}; + +&i2c11 { + status = "okay"; + clock-frequency = <1000000>; + + cs35l41_l: cs35l41@40 { + compatible = "cirrus,cs35l41"; + reg = <0x40>; + interrupt-parent = <&tlmm>; + interrupts = <36 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + cirrus,boost-peak-milliamp = <4000>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,asp-sdout-hiz = <3>; + cirrus,gpio2-src-select = <2>; + cirrus,gpio2-output-enable; + #sound-dai-cells = <1>; + }; + + cs35l41_r: cs35l41@41 { + compatible = "cirrus,cs35l41"; + reg = <0x41>; + interrupt-parent = <&tlmm>; + interrupts = <36 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + cirrus,boost-peak-milliamp = <4000>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,asp-sdout-hiz = <3>; + cirrus,gpio2-src-select = <2>; + cirrus,gpio2-output-enable; + #sound-dai-cells = <1>; + }; +}; + +&i2c12 { + status = "okay"; + /* Clock frequency was not specified downstream, let's park it to 100 KHz */ + clock-frequency = <100000>; + + /* AMS TCS3490 RGB+IR color sensor @ 72 */ +}; + +&i2c13 { + status = "okay"; + /* Clock frequency was not specified downstream, let's park it to 100 KHz */ + clock-frequency = <100000>; + + /* Qualcomm PM8008i/PM8008j (?) @ 8, 9, c, d */ + /* Dialog SLG51000 CMIC @ 75 */ +}; + +&i2c15 { + status = "okay"; + clock-frequency = <400000>; + + /* NXP SN1X0 NFC @ 28 */ +}; + +&i2c17 { + status = "okay"; + clock-frequency = <1000000>; + + /* Cirrus Logic CS40L25A boosted haptics driver @ 40 */ +}; + &pmk8350_rtc { status = "okay"; }; @@ -100,8 +187,22 @@ &qupv3_id_2 { status = "okay"; }; +&spi14 { + status = "okay"; + + /* NXP SN1X0 NFC Secure Element @ 0 */ +}; + &tlmm { gpio-reserved-ranges = <44 4>; + + ts_int_default: ts-int-default { + pin = "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; }; /* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */ From patchwork Sun Nov 14 01:27:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 12617805 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F4DAC4332F for ; Sun, 14 Nov 2021 01:28:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7A44360F36 for ; Sun, 14 Nov 2021 01:28:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236350AbhKNBb0 (ORCPT ); Sat, 13 Nov 2021 20:31:26 -0500 Received: from m-r2.th.seeweb.it ([5.144.164.171]:55225 "EHLO m-r2.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236250AbhKNBbP (ORCPT ); Sat, 13 Nov 2021 20:31:15 -0500 Received: from localhost.localdomain (83.6.165.118.neoplus.adsl.tpnet.pl [83.6.165.118]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 5F0983EE65; Sun, 14 Nov 2021 02:28:20 +0100 (CET) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 15/16] arm64: dts: qcom: sm8350-sagami: Configure remote processors Date: Sun, 14 Nov 2021 02:27:54 +0100 Message-Id: <20211114012755.112226-15-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211114012755.112226-1-konrad.dybcio@somainline.org> References: <20211114012755.112226-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Configure ADSP, CDSP, MPSS, SLPI and IPA on SoMC Sagami. Signed-off-by: Konrad Dybcio --- .../dts/qcom/sm8350-sony-xperia-sagami.dtsi | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index c44376aa0742..90b13cbe2fa6 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -75,6 +75,16 @@ ramoops@ffc00000 { }; }; +&adsp { + status = "okay"; + firmware-name = "qcom/adsp.mbn"; +}; + +&cdsp { + status = "okay"; + firmware-name = "qcom/cdsp.mbn"; +}; + &i2c1 { status = "okay"; clock-frequency = <1000000>; @@ -162,6 +172,17 @@ &i2c17 { /* Cirrus Logic CS40L25A boosted haptics driver @ 40 */ }; +&ipa { + status = "okay"; + memory-region = <&pil_ipa_fw_mem>; + firmware-name = "qcom/ipa_fws.mbn"; +}; + +&mpss { + status = "okay"; + firmware-name = "qcom/modem.mbn"; +}; + &pmk8350_rtc { status = "okay"; }; @@ -187,6 +208,11 @@ &qupv3_id_2 { status = "okay"; }; +&slpi { + status = "okay"; + firmware-name = "qcom/slpi.mbn"; +}; + &spi14 { status = "okay"; From patchwork Sun Nov 14 01:27:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 12617807 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA347C433FE for ; Sun, 14 Nov 2021 01:28:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D68CE61154 for ; Sun, 14 Nov 2021 01:28:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236248AbhKNBbb (ORCPT ); Sat, 13 Nov 2021 20:31:31 -0500 Received: from relay07.th.seeweb.it ([5.144.164.168]:49711 "EHLO relay07.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236268AbhKNBbQ (ORCPT ); Sat, 13 Nov 2021 20:31:16 -0500 Received: from localhost.localdomain (83.6.165.118.neoplus.adsl.tpnet.pl [83.6.165.118]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 867973EE53; Sun, 14 Nov 2021 02:28:21 +0100 (CET) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 16/16] arm64: dts: qcom: sm8350: Add LLCC node Date: Sun, 14 Nov 2021 02:27:55 +0100 Message-Id: <20211114012755.112226-16-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211114012755.112226-1-konrad.dybcio@somainline.org> References: <20211114012755.112226-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Configure the Last-Level Cache Controller for SM8350. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 0ea735d0df49..7323ed74f41a 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2232,6 +2232,12 @@ gem_noc: interconnect@9100000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + system-cache-controller@9200000 { + compatible = "qcom,sm8350-llcc"; + reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + }; + usb_1: usb@a6f8800 { compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>;