From patchwork Mon Nov 15 09:18:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 12619133 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38723C433F5 for ; Mon, 15 Nov 2021 09:21:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1E8E961BD4 for ; Mon, 15 Nov 2021 09:21:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237536AbhKOJYO (ORCPT ); Mon, 15 Nov 2021 04:24:14 -0500 Received: from mx1.tq-group.com ([93.104.207.81]:12298 "EHLO mx1.tq-group.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237590AbhKOJXf (ORCPT ); Mon, 15 Nov 2021 04:23:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1636968041; x=1668504041; h=from:to:cc:subject:date:message-id; bh=9cFyr0y761pT/zVc4s7vOYwjjT571s07IyHIJLr/+MU=; b=pczY0aIE0g8DKelIfHjTH/kPaNn0xLrhFV+0BxcbtEtqSjy9CmpaUUj8 2+GhkWRV9gi7nBXzVXXjWsiLMpWpcw6McZ8ZG9Xv2+wKf55a/9VhQye06 QcUSLtpDn2xiRuawltVvqIVGYWP/aZnHfKoxVFZyo/zIFkppdY5r5Vfgt HA9xrbLckz1+qAtYqe1VzZQNckr74i07SqDu6Bg+c4fBNPaKt1FkT5m7M Pf9B4Cc/et2B2Zv5y60W8IiDdp9gIaDTFfRMhXQIVc3i9/sagSdOZpjju 3aP9mGsmpVi9+QWHNpwb+0g7KyTM+aIPd2PLImD7xZU6C9Bl+T9lLOwMf w==; X-IronPort-AV: E=Sophos;i="5.87,236,1631570400"; d="scan'208";a="20459392" Received: from unknown (HELO tq-pgp-pr1.tq-net.de) ([192.168.6.15]) by mx1-pgp.tq-group.com with ESMTP; 15 Nov 2021 10:20:19 +0100 Received: from mx1.tq-group.com ([192.168.6.7]) by tq-pgp-pr1.tq-net.de (PGP Universal service); Mon, 15 Nov 2021 10:20:19 +0100 X-PGP-Universal: processed; by tq-pgp-pr1.tq-net.de on Mon, 15 Nov 2021 10:20:19 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1636968019; x=1668504019; h=from:to:cc:subject:date:message-id; bh=9cFyr0y761pT/zVc4s7vOYwjjT571s07IyHIJLr/+MU=; b=VCWRnF0mHtbUxKzKlOLw/E05vf6qDAQp+V7XFiroaIrrJj/aR6puVzDI +cL62+Hu60axwM9DNH82AZdGHJBf0ilqo8tDrIAFXnTimgIg2d98CqGot SDAEFS4jmFdRL/jCrxea+D148ESf5LpzOMJt9nBhntFoRNlqzgAZLVfA5 fwahpJmpnN9L+s+LZTneAkKaUhHXHawwfSJ3SLUkNUKYClnsbPhMSMk+9 xl5NGn9NXA8tBluMb/R6P3/lTxnnGyqlBxqwSvderqWEHxFDRqYZ3qh6t Apcg+anj63UH6x2D8AyhzScdOyOBKf9KtyNiPILkrWw42XihUSQn73uyw w==; X-IronPort-AV: E=Sophos;i="5.87,236,1631570400"; d="scan'208";a="20459391" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 15 Nov 2021 10:20:19 +0100 Received: from schifferm-ubuntu4.tq-net.de (schifferm-ubuntu4.tq-net.de [10.121.48.12]) by vtuxmail01.tq-net.de (Postfix) with ESMTPA id E8FA4280075; Mon, 15 Nov 2021 10:20:18 +0100 (CET) From: Matthias Schiffer To: Chandrasekar Ramakrishnan , Wolfgang Grandegger , Marc Kleine-Budde Cc: "David S. Miller" , Jakub Kicinski , "Felipe Balbi (Intel)" , Jarkko Nikula , linux-can@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Schiffer Subject: [PATCH net 1/4] can: m_can: pci: fix incorrect reference clock rate Date: Mon, 15 Nov 2021 10:18:49 +0100 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org When testing the CAN controller on our Ekhart Lake hardware, we determined that all communication was running with twice the configured bitrate. Changing the reference clock rate from 100MHz to 200MHz fixed this. Intel's support has confirmed to us that 200MHz is indeed the correct clock rate. Fixes: cab7ffc0324f ("can: m_can: add PCI glue driver for Intel Elkhart Lake") Signed-off-by: Matthias Schiffer Acked-by: Jarkko Nikula Reviewed-by: Jarkko Nikula --- drivers/net/can/m_can/m_can_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/can/m_can/m_can_pci.c b/drivers/net/can/m_can/m_can_pci.c index 89cc3d41e952..d3c030a13cbe 100644 --- a/drivers/net/can/m_can/m_can_pci.c +++ b/drivers/net/can/m_can/m_can_pci.c @@ -18,7 +18,7 @@ #define M_CAN_PCI_MMIO_BAR 0 -#define M_CAN_CLOCK_FREQ_EHL 100000000 +#define M_CAN_CLOCK_FREQ_EHL 200000000 #define CTL_CSR_INT_CTL_OFFSET 0x508 struct m_can_pci_priv { From patchwork Mon Nov 15 09:18:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 12619131 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C024EC4332F for ; Mon, 15 Nov 2021 09:21:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A31DE63215 for ; Mon, 15 Nov 2021 09:21:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237360AbhKOJYL (ORCPT ); Mon, 15 Nov 2021 04:24:11 -0500 Received: from mx1.tq-group.com ([93.104.207.81]:45337 "EHLO mx1.tq-group.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237595AbhKOJXg (ORCPT ); Mon, 15 Nov 2021 04:23:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1636968041; x=1668504041; h=from:to:cc:subject:date:message-id; bh=aVBt81scfc0Gj2SHHVWURSNtrhvz6bU+CHiaiOknVOc=; b=a8NZ/e5qD6S4hRL42mN2hAshZ0iplraWsqfCd9k9TJ+L2JsnbdiNMPEY kkXwerra5neqSBa+E82qMCUz6uUapDf0Kc0gn0E6DbB1u9VIRP4LmRtYu t/L3SGFhXUEcIpqbvpsmW4UgqaW8eEy8K4cm0lMokLGV9voWuGw5x5Yip TX+sQ2rzZ5KsJA7f17j/CqNBYs5qeU1CyvkMEpWBD3vkBED2hR3xdu8ha 0vVO8PEuHDc0SR5r2aZxkEEyVwDftfsBX3yQVzhl5DDqdIsmoyCWHpgqz XSh1hzth+MGMaSGSwhXhENgmgjLw4P2gI0koRLBj3Ve262afYVVlHWYgM g==; X-IronPort-AV: E=Sophos;i="5.87,236,1631570400"; d="scan'208";a="20459394" Received: from unknown (HELO tq-pgp-pr1.tq-net.de) ([192.168.6.15]) by mx1-pgp.tq-group.com with ESMTP; 15 Nov 2021 10:20:19 +0100 Received: from mx1.tq-group.com ([192.168.6.7]) by tq-pgp-pr1.tq-net.de (PGP Universal service); Mon, 15 Nov 2021 10:20:19 +0100 X-PGP-Universal: processed; by tq-pgp-pr1.tq-net.de on Mon, 15 Nov 2021 10:20:19 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1636968019; x=1668504019; h=from:to:cc:subject:date:message-id; bh=aVBt81scfc0Gj2SHHVWURSNtrhvz6bU+CHiaiOknVOc=; b=lam6DKpdbl6nDRvIA6S3QCvsg1QoYGTNPAIC0lII0XEgtw20hWFxAvwS tGo3Q7bFHd0Qm+YnMjwaWwJfxiMP8x0vV/r+F6BwIC4mFCIxwzG4nd1iG nk4BzOp+HV5ElOyGu0PYG6z3RmUNy389E5UkumdI7gMOvEqzKGl8BZTCt 8PSgrMHmAKlLnLDYOxEoKJN9QTbDjI+/HgOH33yv+ZH6kWFGo2WRSYoT/ 2aRQZ2emQMV/kEl7l5s/E6jKcAQxEeQZLw6OBEcl+9bWIzuTtMm5ZVLsx /iut11R/aNL5aCKC7HnqTzrFPMGY311pTVilMtt26+wqypVBQvAw+stmE Q==; X-IronPort-AV: E=Sophos;i="5.87,236,1631570400"; d="scan'208";a="20459393" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 15 Nov 2021 10:20:19 +0100 Received: from schifferm-ubuntu4.tq-net.de (schifferm-ubuntu4.tq-net.de [10.121.48.12]) by vtuxmail01.tq-net.de (Postfix) with ESMTPA id 29D1E280078; Mon, 15 Nov 2021 10:20:19 +0100 (CET) From: Matthias Schiffer To: Chandrasekar Ramakrishnan , Wolfgang Grandegger , Marc Kleine-Budde Cc: "David S. Miller" , Jakub Kicinski , "Felipe Balbi (Intel)" , Jarkko Nikula , linux-can@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Schiffer Subject: [PATCH net 2/4] Revert "can: m_can: remove support for custom bit timing" Date: Mon, 15 Nov 2021 10:18:50 +0100 Message-Id: <00c9e2596b1a548906921a574d4ef7a03c0dace0.1636967198.git.matthias.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The timing limits specified by the Elkhart Lake CPU datasheets do not match the defaults. Let's reintroduce the support for custom bit timings. This reverts commit 0ddd83fbebbc5537f9d180d31f659db3564be708. Signed-off-by: Matthias Schiffer --- drivers/net/can/m_can/m_can.c | 24 ++++++++++++++++++------ drivers/net/can/m_can/m_can.h | 3 +++ 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index 2470c47b2e31..529f754faae6 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -1494,20 +1494,32 @@ static int m_can_dev_setup(struct m_can_classdev *cdev) case 30: /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */ can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); - cdev->can.bittiming_const = &m_can_bittiming_const_30X; - cdev->can.data_bittiming_const = &m_can_data_bittiming_const_30X; + cdev->can.bittiming_const = cdev->bit_timing ? + cdev->bit_timing : &m_can_bittiming_const_30X; + + cdev->can.data_bittiming_const = cdev->data_timing ? + cdev->data_timing : + &m_can_data_bittiming_const_30X; break; case 31: /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */ can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); - cdev->can.bittiming_const = &m_can_bittiming_const_31X; - cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X; + cdev->can.bittiming_const = cdev->bit_timing ? + cdev->bit_timing : &m_can_bittiming_const_31X; + + cdev->can.data_bittiming_const = cdev->data_timing ? + cdev->data_timing : + &m_can_data_bittiming_const_31X; break; case 32: case 33: /* Support both MCAN version v3.2.x and v3.3.0 */ - cdev->can.bittiming_const = &m_can_bittiming_const_31X; - cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X; + cdev->can.bittiming_const = cdev->bit_timing ? + cdev->bit_timing : &m_can_bittiming_const_31X; + + cdev->can.data_bittiming_const = cdev->data_timing ? + cdev->data_timing : + &m_can_data_bittiming_const_31X; cdev->can.ctrlmode_supported |= (m_can_niso_supported(cdev) ? diff --git a/drivers/net/can/m_can/m_can.h b/drivers/net/can/m_can/m_can.h index d18b515e6ccc..ad063b101411 100644 --- a/drivers/net/can/m_can/m_can.h +++ b/drivers/net/can/m_can/m_can.h @@ -85,6 +85,9 @@ struct m_can_classdev { struct sk_buff *tx_skb; struct phy *transceiver; + struct can_bittiming_const *bit_timing; + struct can_bittiming_const *data_timing; + struct m_can_ops *ops; int version; From patchwork Mon Nov 15 09:18:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 12619129 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77AC3C4167B for ; Mon, 15 Nov 2021 09:21:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4BE7E61BD4 for ; Mon, 15 Nov 2021 09:21:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237129AbhKOJYG (ORCPT ); Mon, 15 Nov 2021 04:24:06 -0500 Received: from mx1.tq-group.com ([93.104.207.81]:12298 "EHLO mx1.tq-group.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230302AbhKOJX6 (ORCPT ); Mon, 15 Nov 2021 04:23:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1636968063; x=1668504063; h=from:to:cc:subject:date:message-id; bh=R7JejJ5VAsSxtFi0cVkHZzS9RvuBmx6TwR8T9DEr7IQ=; b=eTq/A/vSJYkYNTOVOSco2tCrGpK3Xlb9l8+p5Jg6k6eugSFou9L+Ytpt 9wtlPDFdQiIE4Nuz6dUn5JZJF75CiasoEp23OfgN6gesY86YsaNtHXg1j f9hY+jT2D7unmcTEDcMf9UK3taacKjF5PE5h+9trWshB1DoTicPRTG6TU za8UCfwYvbi5JnAUkpuUAdzpQ/dH/q/iIhmz5Kdb23JOkRpXwGg7RKdbg 9zKuskN4LZ6YYSlT26aSmPWO+L3L1OdqszwMovDMU/MgUMxeoP2iZQY2T JeByLjVhrQ9hgmSQhxsCJCs52f4cRv6pTyy99cS68GMHRnVz68Mb3IkRO g==; X-IronPort-AV: E=Sophos;i="5.87,236,1631570400"; d="scan'208";a="20459396" Received: from unknown (HELO tq-pgp-pr1.tq-net.de) ([192.168.6.15]) by mx1-pgp.tq-group.com with ESMTP; 15 Nov 2021 10:20:19 +0100 Received: from mx1.tq-group.com ([192.168.6.7]) by tq-pgp-pr1.tq-net.de (PGP Universal service); Mon, 15 Nov 2021 10:20:19 +0100 X-PGP-Universal: processed; by tq-pgp-pr1.tq-net.de on Mon, 15 Nov 2021 10:20:19 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1636968019; x=1668504019; h=from:to:cc:subject:date:message-id; bh=R7JejJ5VAsSxtFi0cVkHZzS9RvuBmx6TwR8T9DEr7IQ=; b=Mk7ZMzkATH+7DeIgEUGGMeNddfenbH4W9D+Ya1MrynX4oujAUkMP041T ivmBSvwoz7KKbANPX4gKaXwT3YVDEF31WZNfyAVNyRCsMX+GjFxHuXHGd uNx/6r6o7V3fkjBnlCcgx7fYBAy3v/k6GsV8a+4Z+NfeJkyKpSF24u6wW kgoeQSPPyyiFWzA/5QHhlQUcS7BqYwOL1HRQQvVbAYqg7weTxiTyMwUda gy/JriNEdjoZjG9FU62BjK/ZbkG1V5EgDE2kC6hYiuL5qiXY0p09LA6ec JfDi8UBmhYkmnN8N2n6sPJ01x1ghS8nlETHv+KFbiwkL7DnRMISQ+LDVl Q==; X-IronPort-AV: E=Sophos;i="5.87,236,1631570400"; d="scan'208";a="20459395" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 15 Nov 2021 10:20:19 +0100 Received: from schifferm-ubuntu4.tq-net.de (schifferm-ubuntu4.tq-net.de [10.121.48.12]) by vtuxmail01.tq-net.de (Postfix) with ESMTPA id 5615228007C; Mon, 15 Nov 2021 10:20:19 +0100 (CET) From: Matthias Schiffer To: Chandrasekar Ramakrishnan , Wolfgang Grandegger , Marc Kleine-Budde Cc: "David S. Miller" , Jakub Kicinski , "Felipe Balbi (Intel)" , Jarkko Nikula , linux-can@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Schiffer Subject: [PATCH net 3/4] can: m_can: make custom bittiming fields const Date: Mon, 15 Nov 2021 10:18:51 +0100 Message-Id: <4508fa4e639164b2584c49a065d90c78a91fa568.1636967198.git.matthias.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The assigned timing structs will be defined a const anyway, so we can avoid a few casts by declaring the struct fields as const as well. Signed-off-by: Matthias Schiffer --- drivers/net/can/m_can/m_can.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/can/m_can/m_can.h b/drivers/net/can/m_can/m_can.h index ad063b101411..2c5d40997168 100644 --- a/drivers/net/can/m_can/m_can.h +++ b/drivers/net/can/m_can/m_can.h @@ -85,8 +85,8 @@ struct m_can_classdev { struct sk_buff *tx_skb; struct phy *transceiver; - struct can_bittiming_const *bit_timing; - struct can_bittiming_const *data_timing; + const struct can_bittiming_const *bit_timing; + const struct can_bittiming_const *data_timing; struct m_can_ops *ops; From patchwork Mon Nov 15 09:18:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 12619127 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9ECDC4321E for ; Mon, 15 Nov 2021 09:21:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 825BA61BD4 for ; Mon, 15 Nov 2021 09:21:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236975AbhKOJYF (ORCPT ); Mon, 15 Nov 2021 04:24:05 -0500 Received: from mx1.tq-group.com ([93.104.207.81]:45337 "EHLO mx1.tq-group.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236638AbhKOJX6 (ORCPT ); Mon, 15 Nov 2021 04:23:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1636968063; x=1668504063; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=7+q5wOUq3ntaAvVRKhGKpGVjQieDwZAsdV21wJvDGe8=; b=jV/RPWlW+DobyRIOZ+U6VaqCnybBOAHBC31ZY1peJ5ZCg5b0ldTQaxVk YkEOc8f9z+K8EW6G3Qp5aeatoz4yK0mbSNaMqPzcdcT0EpeaCGCqwcrZQ UuqT0kvJQ/tuK4CKPiPAWk9qtfQYcWtSCK3cV4VS1i7L+4DDXTLGljMdC sOUcM1by/Uej/eZavcJFr+sqr+7mpXlk/miSxRbV8BJCugwjVhl/8Oi0M lT9kDYgSNJg4iHbBrlz+bM0c0ubziH4ahC+lYrOxrrOHvJz5InR/JGpaN CUqXDQ7RlqVuxHH3842eFfuSENI/M+z0Br6D7vxPjj+xLmFL+gKP0Wgin w==; X-IronPort-AV: E=Sophos;i="5.87,236,1631570400"; d="scan'208";a="20459398" Received: from unknown (HELO tq-pgp-pr1.tq-net.de) ([192.168.6.15]) by mx1-pgp.tq-group.com with ESMTP; 15 Nov 2021 10:20:19 +0100 Received: from mx1.tq-group.com ([192.168.6.7]) by tq-pgp-pr1.tq-net.de (PGP Universal service); Mon, 15 Nov 2021 10:20:19 +0100 X-PGP-Universal: processed; by tq-pgp-pr1.tq-net.de on Mon, 15 Nov 2021 10:20:19 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1636968019; x=1668504019; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=7+q5wOUq3ntaAvVRKhGKpGVjQieDwZAsdV21wJvDGe8=; b=me7vdP7UgpW0m6fTZt9K17MMH0JXBBo5v34HGQ9nhmTbe5Il8YLpoaj8 OAOV2xuoe1DeQ/Y6jdhambzQG8WEOJWDvHSxJua2YihV40gAgr9tPjwui LAxM/LhMluBIjyR2TTmAoRjO/e9Fju5PTREXmmryrPSan72sTUX0zKicM 9T7lYEMZOekB2/IkvzakDMTbRWHCXViLYQ+KbAKU9kON1DGXZeCDXRmaY kv4jN9gIp6UyK1DNajXFYiIBjNBfTwu6HO8Qx62vIi1UZVBkRXjCjGppW ypGRnr4ZyQRRSOOGu8ViiEQBivL2J9c9XL0tugyWprQSX4coyHRaVKNjY A==; X-IronPort-AV: E=Sophos;i="5.87,236,1631570400"; d="scan'208";a="20459397" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 15 Nov 2021 10:20:19 +0100 Received: from schifferm-ubuntu4.tq-net.de (schifferm-ubuntu4.tq-net.de [10.121.48.12]) by vtuxmail01.tq-net.de (Postfix) with ESMTPA id 8B74428007F; Mon, 15 Nov 2021 10:20:19 +0100 (CET) From: Matthias Schiffer To: Chandrasekar Ramakrishnan , Wolfgang Grandegger , Marc Kleine-Budde Cc: "David S. Miller" , Jakub Kicinski , "Felipe Balbi (Intel)" , Jarkko Nikula , linux-can@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Schiffer Subject: [PATCH net 4/4] can: m_can: pci: use custom bit timings for Elkhart Lake Date: Mon, 15 Nov 2021 10:18:52 +0100 Message-Id: <9eba5d7c05a48ead4024ffa6e5926f191d8c6b38.1636967198.git.matthias.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The relevant datasheet [1] specifies nonstandard limits for the bit timing parameters. While it is unclear what the exact effect of violating these limits is, it seems like a good idea to adhere to the documentation. [1] Intel Atom® x6000E Series, and Intel® Pentium® and Celeron® N and J Series Processors for IoT Applications Datasheet, Volume 2 (Book 3 of 3), July 2021, Revision 001 Fixes: cab7ffc0324f ("can: m_can: add PCI glue driver for Intel Elkhart Lake") Signed-off-by: Matthias Schiffer --- drivers/net/can/m_can/m_can_pci.c | 48 ++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 4 deletions(-) diff --git a/drivers/net/can/m_can/m_can_pci.c b/drivers/net/can/m_can/m_can_pci.c index d3c030a13cbe..8bbbaa264f0d 100644 --- a/drivers/net/can/m_can/m_can_pci.c +++ b/drivers/net/can/m_can/m_can_pci.c @@ -18,9 +18,14 @@ #define M_CAN_PCI_MMIO_BAR 0 -#define M_CAN_CLOCK_FREQ_EHL 200000000 #define CTL_CSR_INT_CTL_OFFSET 0x508 +struct m_can_pci_config { + const struct can_bittiming_const *bit_timing; + const struct can_bittiming_const *data_timing; + unsigned int clock_freq; +}; + struct m_can_pci_priv { struct m_can_classdev cdev; @@ -74,9 +79,40 @@ static struct m_can_ops m_can_pci_ops = { .read_fifo = iomap_read_fifo, }; +static const struct can_bittiming_const m_can_bittiming_const_ehl = { + .name = KBUILD_MODNAME, + .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ + .tseg1_max = 64, + .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ + .tseg2_max = 128, + .sjw_max = 128, + .brp_min = 1, + .brp_max = 512, + .brp_inc = 1, +}; + +static const struct can_bittiming_const m_can_data_bittiming_const_ehl = { + .name = KBUILD_MODNAME, + .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ + .tseg1_max = 16, + .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ + .tseg2_max = 8, + .sjw_max = 4, + .brp_min = 1, + .brp_max = 32, + .brp_inc = 1, +}; + +static const struct m_can_pci_config m_can_pci_ehl = { + .bit_timing = &m_can_bittiming_const_ehl, + .data_timing = &m_can_data_bittiming_const_ehl, + .clock_freq = 200000000, +}; + static int m_can_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) { struct device *dev = &pci->dev; + const struct m_can_pci_config *cfg; struct m_can_classdev *mcan_class; struct m_can_pci_priv *priv; void __iomem *base; @@ -104,6 +140,8 @@ static int m_can_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) if (!mcan_class) return -ENOMEM; + cfg = (const struct m_can_pci_config *)id->driver_data; + priv = cdev_to_priv(mcan_class); priv->base = base; @@ -115,7 +153,9 @@ static int m_can_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) mcan_class->dev = &pci->dev; mcan_class->net->irq = pci_irq_vector(pci, 0); mcan_class->pm_clock_support = 1; - mcan_class->can.clock.freq = id->driver_data; + mcan_class->bit_timing = cfg->bit_timing; + mcan_class->data_timing = cfg->data_timing; + mcan_class->can.clock.freq = cfg->clock_freq; mcan_class->ops = &m_can_pci_ops; pci_set_drvdata(pci, mcan_class); @@ -168,8 +208,8 @@ static SIMPLE_DEV_PM_OPS(m_can_pci_pm_ops, m_can_pci_suspend, m_can_pci_resume); static const struct pci_device_id m_can_pci_id_table[] = { - { PCI_VDEVICE(INTEL, 0x4bc1), M_CAN_CLOCK_FREQ_EHL, }, - { PCI_VDEVICE(INTEL, 0x4bc2), M_CAN_CLOCK_FREQ_EHL, }, + { PCI_VDEVICE(INTEL, 0x4bc1), (kernel_ulong_t)&m_can_pci_ehl, }, + { PCI_VDEVICE(INTEL, 0x4bc2), (kernel_ulong_t)&m_can_pci_ehl, }, { } /* Terminating Entry */ }; MODULE_DEVICE_TABLE(pci, m_can_pci_id_table);