From patchwork Tue Dec 18 04:07:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrey Smirnov X-Patchwork-Id: 10734705 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0A41413B5 for ; Tue, 18 Dec 2018 04:07:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EE8DF2A431 for ; Tue, 18 Dec 2018 04:07:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E311E2A76D; Tue, 18 Dec 2018 04:07:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 256372A431 for ; Tue, 18 Dec 2018 04:07:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726574AbeLREHX (ORCPT ); Mon, 17 Dec 2018 23:07:23 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:43511 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726296AbeLREHW (ORCPT ); Mon, 17 Dec 2018 23:07:22 -0500 Received: by mail-pf1-f195.google.com with SMTP id w73so7447450pfk.10; Mon, 17 Dec 2018 20:07:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=o9euarsav/I7Ly8L1DuHInXCM/cMkfcijwQSR5z4WR0=; b=BY7OvDO0YnvIy3hULxANFR+Bzce9L6Ut8av2NnQXxImslaVZPFgL2GzuAIKb/LVYyC 34t+nJXN/wSnpVP2YaLxvA+3P1s4lFhE+B+7fZWEX/sRv50q/79j6SmRym5oaveFP41Z oorZ1KNd8tJfIpIqVCQ8z4wyzY1TrKvEMSelnId6ym+HIHpuq4RIKzuqQjtnJWss1ikU /mrffje+4uMhnI8oKrJJ3ivPJf5qV9rYr28brKyK+lpfPmyBnrBviL5lBsk47rsUuL0H nNwNttCG2ibhHIp73dwnK5VkD1nZQNE4StH8dw5e5cWAtk2giRfXPoIIUrEJHs5yMiW3 80Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o9euarsav/I7Ly8L1DuHInXCM/cMkfcijwQSR5z4WR0=; b=hPecRDQlCwyVwj46abrnaDAG5ZHgUB69LlygV7VDy7hHXWL9hmq9jr8xvbRjCAOoYQ 3hId2+gbb6Tm4X78uaf1+ep0Hv+nB7vOM/+Y4ggeEsgqmv1t7OtrJBKg3lkMXnHHvWko dr4bgxxdGgNNXL2FWlV44vbpnWdO8+MychrZs7jwRv3UhgVgwo8hBHFVA2Dr2h3+n+ts BkYeVnMQ4SPNwtdWH30LZT+2MBqwge9oo7BH3HCLHy+ud7Wl/cNIQwEItdowfDBaS8d0 BrhF4rpvLS3+fW5M5SivVOBamOlbtlQCwu8mthQdjSw83CABIOIsHxnKTiLqGqjb0aax OwGA== X-Gm-Message-State: AA+aEWY+17v05+kgE0dUO+W8sRcjRMz6QWZkmWCwuvYaiZkq8O8jzkTQ qO8WZYn37mCGAZ3iyt4OC9Q= X-Google-Smtp-Source: AFSGD/UJPXqBPh57W/mpOqwRodEIpJUrnFqZbtvqtWtO2XEwvM5iDrNaa5m3DULCPJWxRZtGqosK3Q== X-Received: by 2002:a65:6684:: with SMTP id b4mr14520076pgw.55.1545106041828; Mon, 17 Dec 2018 20:07:21 -0800 (PST) Received: from squirtle.lan (c-24-22-235-96.hsd1.wa.comcast.net. [24.22.235.96]) by smtp.gmail.com with ESMTPSA id m67sm18538837pfm.73.2018.12.17.20.07.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 20:07:20 -0800 (PST) From: Andrey Smirnov To: Lorenzo Pieralisi Cc: Andrey Smirnov , Bjorn Helgaas , Fabio Estevam , Chris Healy , Lucas Stach , Leonard Crestez , "A.s. Dong" , Richard Zhu , linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Stefan Agner Subject: [PATCH v3 1/3] PCI: imx6: introduce drvdata Date: Mon, 17 Dec 2018 20:07:00 -0800 Message-Id: <20181218040702.29231-2-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181218040702.29231-1-andrew.smirnov@gmail.com> References: <20181218040702.29231-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Introduce driver data struct. This will simplify handling of device specific differences. Cc: Bjorn Helgaas Cc: Fabio Estevam Cc: Chris Healy Cc: Lucas Stach Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Signed-off-by: Stefan Agner Reviewed-by: Lucas Stach [andrew.smirnov@gmail.com reformatted drvdata, to simplify future diffs] Signed-off-by: Andrey Smirnov --- drivers/pci/controller/dwc/pci-imx6.c | 56 ++++++++++++++++++--------- 1 file changed, 37 insertions(+), 19 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 26087b3da590..d50ed69e7a57 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -41,6 +41,10 @@ enum imx6_pcie_variants { IMX7D, }; +struct imx6_pcie_drvdata { + enum imx6_pcie_variants variant; +}; + struct imx6_pcie { struct dw_pcie *pci; int reset_gpio; @@ -53,7 +57,6 @@ struct imx6_pcie { struct reset_control *pciephy_reset; struct reset_control *apps_reset; struct reset_control *turnoff_reset; - enum imx6_pcie_variants variant; u32 tx_deemph_gen1; u32 tx_deemph_gen2_3p5db; u32 tx_deemph_gen2_6db; @@ -66,6 +69,7 @@ struct imx6_pcie { struct device *pd_pcie; /* power domain for pcie phy */ struct device *pd_pcie_phy; + const struct imx6_pcie_drvdata *drvdata; }; /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ @@ -340,7 +344,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) { struct device *dev = imx6_pcie->pci->dev; - switch (imx6_pcie->variant) { + switch (imx6_pcie->drvdata->variant) { case IMX7D: reset_control_assert(imx6_pcie->pciephy_reset); reset_control_assert(imx6_pcie->apps_reset); @@ -382,7 +386,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) struct device *dev = pci->dev; int ret = 0; - switch (imx6_pcie->variant) { + switch (imx6_pcie->drvdata->variant) { case IMX6SX: ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi); if (ret) { @@ -485,7 +489,7 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) !imx6_pcie->gpio_active_high); } - switch (imx6_pcie->variant) { + switch (imx6_pcie->drvdata->variant) { case IMX7D: reset_control_deassert(imx6_pcie->pciephy_reset); imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie); @@ -523,7 +527,7 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) { - switch (imx6_pcie->variant) { + switch (imx6_pcie->drvdata->variant) { case IMX7D: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); @@ -645,7 +649,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev) { struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); - switch (imx6_pcie->variant) { + switch (imx6_pcie->drvdata->variant) { case IMX6Q: case IMX6SX: case IMX6QP: @@ -698,7 +702,7 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) tmp |= PORT_LOGIC_SPEED_CHANGE; dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); - if (imx6_pcie->variant != IMX7D) { + if (imx6_pcie->drvdata->variant != IMX7D) { /* * On i.MX7, DIRECT_SPEED_CHANGE behaves differently * from i.MX6 family when no link speed transition @@ -801,7 +805,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev) { struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); - switch (imx6_pcie->variant) { + switch (imx6_pcie->drvdata->variant) { case IMX6SX: case IMX6QP: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, @@ -827,7 +831,7 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) } /* Others poke directly at IOMUXC registers */ - switch (imx6_pcie->variant) { + switch (imx6_pcie->drvdata->variant) { case IMX6SX: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF, @@ -857,7 +861,7 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) clk_disable_unprepare(imx6_pcie->pcie_phy); clk_disable_unprepare(imx6_pcie->pcie_bus); - switch (imx6_pcie->variant) { + switch (imx6_pcie->drvdata->variant) { case IMX6SX: clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); break; @@ -873,8 +877,8 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) static inline bool imx6_pcie_supports_suspend(struct imx6_pcie *imx6_pcie) { - return (imx6_pcie->variant == IMX7D || - imx6_pcie->variant == IMX6SX); + return (imx6_pcie->drvdata->variant == IMX7D || + imx6_pcie->drvdata->variant == IMX6SX); } static int imx6_pcie_suspend_noirq(struct device *dev) @@ -939,8 +943,7 @@ static int imx6_pcie_probe(struct platform_device *pdev) pci->ops = &dw_pcie_ops; imx6_pcie->pci = pci; - imx6_pcie->variant = - (enum imx6_pcie_variants)of_device_get_match_data(dev); + imx6_pcie->drvdata = of_device_get_match_data(dev); dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); pci->dbi_base = devm_ioremap_resource(dev, dbi_base); @@ -984,7 +987,7 @@ static int imx6_pcie_probe(struct platform_device *pdev) return PTR_ERR(imx6_pcie->pcie); } - switch (imx6_pcie->variant) { + switch (imx6_pcie->drvdata->variant) { case IMX6SX: imx6_pcie->pcie_inbound_axi = devm_clk_get(dev, "pcie_inbound_axi"); @@ -1082,11 +1085,26 @@ static void imx6_pcie_shutdown(struct platform_device *pdev) imx6_pcie_assert_core_reset(imx6_pcie); } +static const struct imx6_pcie_drvdata drvdata[] = { + [IMX6Q] = { + .variant = IMX6Q, + }, + [IMX6SX] = { + .variant = IMX6SX, + }, + [IMX6QP] = { + .variant = IMX6QP, + }, + [IMX7D] = { + .variant = IMX7D, + }, +}; + static const struct of_device_id imx6_pcie_of_match[] = { - { .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, }, - { .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, }, - { .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, }, - { .compatible = "fsl,imx7d-pcie", .data = (void *)IMX7D, }, + { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], }, + { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], }, + { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], }, + { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], }, {}, }; From patchwork Tue Dec 18 04:07:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrey Smirnov X-Patchwork-Id: 10734699 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4FE6A13B5 for ; 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[24.22.235.96]) by smtp.gmail.com with ESMTPSA id m67sm18538837pfm.73.2018.12.17.20.07.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 20:07:22 -0800 (PST) From: Andrey Smirnov To: Lorenzo Pieralisi Cc: Andrey Smirnov , Bjorn Helgaas , Fabio Estevam , Chris Healy , Lucas Stach , Leonard Crestez , "A.s. Dong" , Richard Zhu , linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v3 2/3] PCI: imx6: Mark PHY functions as i.MX6 specific Date: Mon, 17 Dec 2018 20:07:01 -0800 Message-Id: <20181218040702.29231-3-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181218040702.29231-1-andrew.smirnov@gmail.com> References: <20181218040702.29231-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP PCIE PHY IP block on i.MX7D differs from the one used on i.MX6 family, so none of the code in current implementation of imx6_setup_phy_mpll() and imx6_pcie_reset_phy() is applicable. Tested-by: Trent Piepho Signed-off-by: Andrey Smirnov Reviewed-by: Lucas Stach Cc: Bjorn Helgaas Cc: Fabio Estevam Cc: Chris Healy Cc: Lucas Stach Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org --- drivers/pci/controller/dwc/pci-imx6.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index d50ed69e7a57..caa05104b90b 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -41,8 +41,11 @@ enum imx6_pcie_variants { IMX7D, }; +#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) + struct imx6_pcie_drvdata { enum imx6_pcie_variants variant; + u32 flags; }; struct imx6_pcie { @@ -256,6 +259,9 @@ static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie) { u32 tmp; + if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) + return; + pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN); @@ -573,6 +579,9 @@ static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) int mult, div; u32 val; + if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) + return 0; + switch (phy_rate) { case 125000000: /* @@ -1088,12 +1097,15 @@ static void imx6_pcie_shutdown(struct platform_device *pdev) static const struct imx6_pcie_drvdata drvdata[] = { [IMX6Q] = { .variant = IMX6Q, + .flags = IMX6_PCIE_FLAG_IMX6_PHY, }, [IMX6SX] = { .variant = IMX6SX, + .flags = IMX6_PCIE_FLAG_IMX6_PHY, }, [IMX6QP] = { .variant = IMX6QP, + .flags = IMX6_PCIE_FLAG_IMX6_PHY, }, [IMX7D] = { .variant = IMX7D, From patchwork Tue Dec 18 04:07:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrey Smirnov X-Patchwork-Id: 10734701 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DA3FD14DE for ; Tue, 18 Dec 2018 04:07:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CA8192A431 for ; Tue, 18 Dec 2018 04:07:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BEB322A76D; Tue, 18 Dec 2018 04:07:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E52D02A76B for ; Tue, 18 Dec 2018 04:07:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726663AbeLREH1 (ORCPT ); Mon, 17 Dec 2018 23:07:27 -0500 Received: from mail-pl1-f195.google.com ([209.85.214.195]:39763 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726296AbeLREH0 (ORCPT ); Mon, 17 Dec 2018 23:07:26 -0500 Received: by mail-pl1-f195.google.com with SMTP id 101so7183112pld.6; Mon, 17 Dec 2018 20:07:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8hbxQ7pbzmoG8DptIpBL4q1hVZ/kFq3RVjs8c2/Dq+I=; b=owK56QDnVvLYdmX85ssZXsGpRFle2dWza5i0kYzcJvR4tzkBVNAwYlIqrjb32/FWml XEAskOVkbi2A6BfLUdwFo1y6X6A2pUCJsFP456aZjZCRnRrVpuyej9AG2dLfvZIf3CMz kN0iexsYzNvfnWY2PWEvVOoEB1gnh5tTkqcLhZTiodEs47wOhdLU8AIZbRo9HY1Tuqgj 5BPNN7Xx/5OAHQMmkwVlYFSP5awpLfo/Dyo7VOf51XF7P5zZaaENuRgHeSYnxXp+hYf7 BubhURcuto1PyPpBTc/sMaaCg6uCMDxJT91/6Hx4Gwjt9o4pCwP/Uiwt7ISfrepz27Ch aJ5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8hbxQ7pbzmoG8DptIpBL4q1hVZ/kFq3RVjs8c2/Dq+I=; b=CnCvUiVvshZbo03sMq/pRQo4iFOLbuojVD7UpPuUZ6jriWV1XRP1GWWXBsPLYE9P0v KTcVoQzi9VVB2wuUxwBXXLya6DMEQkf44M5x+Jfau4dpyY9whUqB8bR3URLFYd0zYu6X s/Pm6RHFOfo5dhgqxu/FC/Uj5YJcUK02wHkb+FHDNbZ3DEZoRmh+mbl4NUAZ5YWtOBMp Jea7K6pgFjgI7nTCAUOJTrbWlRno43euYl350i6ONP2L+HaA04+ga/3ffRnwRqQQ31Cb MqXz0ra4yJIWXnwfqam4Rs22Qsd+m/s924Mjb6qT/2WqvHfMDDxBdGdzoL5gslV37q5S brsg== X-Gm-Message-State: AA+aEWZXpRj6Sut9HJ8+VfjY2WTg2fG4FX9gn17llmt2v33hy4EptvRJ mwwDK7z3sJe9NalSsE09LLh09Bmm X-Google-Smtp-Source: AFSGD/WPSOXyx1B5AeQQewvG8T9W2mrcIzIcC1fmWFxPRm8UiojgY1S9EGer7E1aoOjl1EFIkk0/9g== X-Received: by 2002:a17:902:4464:: with SMTP id k91mr15311642pld.13.1545106045745; Mon, 17 Dec 2018 20:07:25 -0800 (PST) Received: from squirtle.lan (c-24-22-235-96.hsd1.wa.comcast.net. [24.22.235.96]) by smtp.gmail.com with ESMTPSA id m67sm18538837pfm.73.2018.12.17.20.07.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 20:07:24 -0800 (PST) From: Andrey Smirnov To: Lorenzo Pieralisi Cc: Andrey Smirnov , Bjorn Helgaas , Fabio Estevam , Chris Healy , Lucas Stach , Leonard Crestez , "A.s. Dong" , Richard Zhu , Rob Herring , devicetree@vger.kernel.org, linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v3 3/3] PCI: imx6: Add support for i.MX8MQ Date: Mon, 17 Dec 2018 20:07:02 -0800 Message-Id: <20181218040702.29231-4-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181218040702.29231-1-andrew.smirnov@gmail.com> References: <20181218040702.29231-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add code needed to support i.MX8MQ variant. Signed-off-by: Andrey Smirnov Reviewed-by: Lucas Stach Cc: Bjorn Helgaas Cc: Fabio Estevam Cc: Chris Healy Cc: Lucas Stach Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu Cc: Rob Herring Cc: devicetree@vger.kernel.org Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org --- .../bindings/pci/fsl,imx6q-pcie.txt | 6 +- drivers/pci/controller/dwc/Kconfig | 4 +- drivers/pci/controller/dwc/pci-imx6.c | 82 ++++++++++++++++++- 3 files changed, 87 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index d514c1f2365f..1a10c313e8d7 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -9,6 +9,7 @@ Required properties: - "fsl,imx6sx-pcie", - "fsl,imx6qp-pcie" - "fsl,imx7d-pcie" + - "fsl,imx8mq-pcie" - reg: base address and length of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. @@ -45,7 +46,7 @@ Additional required properties for imx6sx-pcie: PCIE_PHY power domains - power-domain-names: Must be "pcie", "pcie_phy" -Additional required properties for imx7d-pcie: +Additional required properties for imx7d-pcie and imx8mq-pcie: - power-domains: Must be set to a phandle pointing to PCIE_PHY power domain - resets: Must contain phandles to PCIe-related reset lines exposed by SRC IP block @@ -54,6 +55,9 @@ Additional required properties for imx7d-pcie: - "apps" - "turnoff" +Additional required properties for imx8mq-pcie: +- fsl,controller-id: Logical ID of a given PCIE controller. PCIE1 is 0, PCIE2 is 1; + Example: pcie@01000000 { diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 6aafec3fad00..83ea318ad989 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -89,8 +89,8 @@ config PCI_EXYNOS select PCIE_DW_HOST config PCI_IMX6 - bool "Freescale i.MX6/7 PCIe controller" - depends on SOC_IMX6Q || SOC_IMX7D || (ARM && COMPILE_TEST) + bool "Freescale i.MX6/7/8 PCIe controller" + depends on SOC_IMX6Q || SOC_IMX7D || (ARM64 && ARCH_MXC) || ((ARM || ARM64) && COMPILE_TEST) depends on PCI_MSI_IRQ_DOMAIN select PCIE_DW_HOST diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index caa05104b90b..d71680920155 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -8,6 +8,7 @@ * Author: Sean Cross */ +#include #include #include #include @@ -32,6 +33,11 @@ #include "pcie-designware.h" +#define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) +#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10) +#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11) +#define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) + #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) enum imx6_pcie_variants { @@ -39,6 +45,7 @@ enum imx6_pcie_variants { IMX6SX, IMX6QP, IMX7D, + IMX8MQ, }; #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) @@ -57,6 +64,7 @@ struct imx6_pcie { struct clk *pcie_inbound_axi; struct clk *pcie; struct regmap *iomuxc_gpr; + u32 controller_id; struct reset_control *pciephy_reset; struct reset_control *apps_reset; struct reset_control *turnoff_reset; @@ -275,6 +283,7 @@ static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie) pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); } +#ifdef CONFIG_ARM /* Added for PCI abort handling */ static int imx6q_pcie_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) @@ -308,6 +317,7 @@ static int imx6q_pcie_abort_handler(unsigned long addr, return 1; } +#endif static int imx6_pcie_attach_pd(struct device *dev) { @@ -352,6 +362,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) switch (imx6_pcie->drvdata->variant) { case IMX7D: + case IMX8MQ: reset_control_assert(imx6_pcie->pciephy_reset); reset_control_assert(imx6_pcie->apps_reset); break; @@ -390,6 +401,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) { struct dw_pcie *pci = imx6_pcie->pci; struct device *dev = pci->dev; + unsigned int offset; int ret = 0; switch (imx6_pcie->drvdata->variant) { @@ -420,6 +432,29 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) break; case IMX7D: break; + case IMX8MQ: + switch (imx6_pcie->controller_id) { + case 0: + offset = IOMUXC_GPR14; + break; + case 1: + offset = IOMUXC_GPR16; + break; + default: + return -EINVAL; + } + + /* + * Set the over ride low and enabled + * make sure that REF_CLK is turned on. + */ + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, + 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, + IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); + break; } return ret; @@ -496,6 +531,9 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) } switch (imx6_pcie->drvdata->variant) { + case IMX8MQ: + reset_control_deassert(imx6_pcie->pciephy_reset); + break; case IMX7D: reset_control_deassert(imx6_pcie->pciephy_reset); imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie); @@ -533,7 +571,36 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) { + + + unsigned int mask, val, offset; + + mask = IMX6Q_GPR12_DEVICE_TYPE; + val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT); + switch (imx6_pcie->drvdata->variant) { + case IMX8MQ: + switch (imx6_pcie->controller_id) { + case 0: + offset = IOMUXC_GPR14; + break; + case 1: + offset = IOMUXC_GPR16; + mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE; + val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, + PCI_EXP_TYPE_ROOT_PORT); + break; + default: + return; + } + /* + * TODO: Currently this code assumes external + * oscillator is being used + */ + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + IMX8MQ_GPR_PCIE_REF_USE_PAD, + IMX8MQ_GPR_PCIE_REF_USE_PAD); + break; case IMX7D: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); @@ -569,8 +636,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) break; } - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val); } static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) @@ -667,6 +733,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev) IMX6Q_GPR12_PCIE_CTL_2); break; case IMX7D: + case IMX8MQ: reset_control_deassert(imx6_pcie->apps_reset); break; } @@ -954,6 +1021,10 @@ static int imx6_pcie_probe(struct platform_device *pdev) imx6_pcie->pci = pci; imx6_pcie->drvdata = of_device_get_match_data(dev); + if (of_property_read_u32(node, "fsl,controller-id", + &imx6_pcie->controller_id)) + imx6_pcie->controller_id = 0; + dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); pci->dbi_base = devm_ioremap_resource(dev, dbi_base); if (IS_ERR(pci->dbi_base)) @@ -1006,6 +1077,7 @@ static int imx6_pcie_probe(struct platform_device *pdev) } break; case IMX7D: + case IMX8MQ: imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); if (IS_ERR(imx6_pcie->pciephy_reset)) { @@ -1110,6 +1182,9 @@ static const struct imx6_pcie_drvdata drvdata[] = { [IMX7D] = { .variant = IMX7D, }, + [IMX8MQ] = { + .variant = IMX8MQ, + }, }; static const struct of_device_id imx6_pcie_of_match[] = { @@ -1117,6 +1192,7 @@ static const struct of_device_id imx6_pcie_of_match[] = { { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], }, { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], }, { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], }, + { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], }, {}, }; @@ -1133,6 +1209,7 @@ static struct platform_driver imx6_pcie_driver = { static int __init imx6_pcie_init(void) { +#ifdef CONFIG_ARM /* * Since probe() can be deferred we need to make sure that * hook_fault_code is not called after __init memory is freed @@ -1142,6 +1219,7 @@ static int __init imx6_pcie_init(void) */ hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0, "external abort on non-linefetch"); +#endif return platform_driver_register(&imx6_pcie_driver); }