From patchwork Tue Nov 16 15:48:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Sm/Do28gTcOhcmlvIERvbWluZ29z?= X-Patchwork-Id: 12622763 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 341D1C433EF for ; Tue, 16 Nov 2021 15:48:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CE37F6128A for ; Tue, 16 Nov 2021 15:48:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org CE37F6128A Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=tecnico.ulisboa.pt Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=olr/0rH1Cvq4ocOpSX96nNk5gt3CUr7ATkmklQYKsKs=; b=hYz2bZu7p8NrUX 373pG4iwpkhOtzucvYCXxiU6zjckfnjBEY/IRsy8KUs/NeFXMQjU9lA+m9/wTpzgCCa8bOE/uRgPt P8aG2WCGlZri7MLg3IdvaPm7hoLGY5jtT2/K+woK2NUfnhrCMnuMDgYldGJ84by1/i6ukxO/EaL6v p7korZUn1vgrx9VMfF0Erc/I4w8GPHRopGUGBrXCV5RIRoT/T2kKRUBogczXlR/JUI+VU+YlPgOLI m+0Hgecvcll9dWsTA2Yk70xAnIIcMzipMHrak8iQRG3FjuV0/G/PSCHE1zbT9Nipbm3S/maM+aPlI ipSuWEb+CwVVBjHB9nBA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mn0hN-002BjF-Ae; Tue, 16 Nov 2021 15:48:41 +0000 Received: from smtp1.tecnico.ulisboa.pt ([193.136.128.21]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mn0hI-002Ben-2h for linux-riscv@lists.infradead.org; Tue, 16 Nov 2021 15:48:38 +0000 Received: from localhost (localhost.localdomain [127.0.0.1]) by smtp1.tecnico.ulisboa.pt (Postfix) with ESMTP id 05B776005C2B; Tue, 16 Nov 2021 15:48:18 +0000 (WET) X-Virus-Scanned: by amavisd-new-2.11.0 (20160426) (Debian) at tecnico.ulisboa.pt Received: from smtp1.tecnico.ulisboa.pt ([127.0.0.1]) by localhost (smtp1.tecnico.ulisboa.pt [127.0.0.1]) (amavisd-new, port 10025) with LMTP id 7suzIrNTA-lf; Tue, 16 Nov 2021 15:48:14 +0000 (WET) Received: from mail2.tecnico.ulisboa.pt (mail2.ist.utl.pt [IPv6:2001:690:2100:1::4750:b5b4]) by smtp1.tecnico.ulisboa.pt (Postfix) with ESMTPS id 873936005C2C; Tue, 16 Nov 2021 15:48:14 +0000 (WET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tecnico.ulisboa.pt; s=mail; t=1637077694; bh=EsbqsfDwR3GCr6eujE8yzM6eJnlvI/PG3VO6iR63Ji8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=EFSRGDrk0Lji+eHSFF6QjNgniPFr1qyHOC2TC4bSZ+Pv4PfSL9DFeoWRnc7fxXrtV ZoLgfHbyNx2/Iymj19NLbgs31gu4UgJ2I4JczCeASMbtW9e3N+OmhkY6a/cv6jwSyE 8+tasQSJ8uiky5a5SThGqu+0uKZeTDloQ4U8AKq8= Received: from joaomariovmubuntu.Home (unknown [IPv6:2001:8a0:fa2d:4500:215:5dff:fe40:101]) (Authenticated sender: ist181713) by mail2.tecnico.ulisboa.pt (Postfix) with ESMTPSA id 59F7B56007D; Tue, 16 Nov 2021 15:48:14 +0000 (WET) From: =?utf-8?b?Sm/Do28gTcOhcmlvIERvbWluZ29z?= To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu Cc: atish.patra@wdc.com, anup.patel@wdc.com, linux-riscv@lists.infradead.org, nikita.shubin@maquefel.me, joao.mario@tecnico.ulisboa.pt Subject: [PATCH v2 1/4] RISC-V: Create unique identification for SoC PMU Date: Tue, 16 Nov 2021 15:48:09 +0000 Message-Id: <20211116154812.17008-2-joao.mario@tecnico.ulisboa.pt> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211116154812.17008-1-joao.mario@tecnico.ulisboa.pt> References: <20211109102555.16381-1-joao.mario@tecnico.ulisboa.pt> <20211116154812.17008-1-joao.mario@tecnico.ulisboa.pt> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211116_074836_461724_1F00B84F X-CRM114-Status: GOOD ( 14.33 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The SBI PMU platform driver did not provide any identification for perf events matching. This patch introduces a new sysfs file inside the platform device (soc:pmu/id) for pmu identification. The identification is a 64-bit value generated as: [63-32]: mvendorid; [31]: marchid[MSB]; [30-16]: marchid[15-0]; [15-0]: mimpid[15MSBs]; The CSRs are detailed in the RISC-V privileged spec [1]. The marchid is split in MSB + 15LSBs, due to the MSB being used for open-source architecture identification. [1] https://github.com/riscv/riscv-isa-manual Signed-off-by: João Mário Domingos --- arch/riscv/kernel/sbi.c | 3 +++ drivers/perf/riscv_pmu_sbi.c | 47 ++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 7402a417f38e..4e4f5671b864 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -551,16 +551,19 @@ long sbi_get_mvendorid(void) { return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID); } +EXPORT_SYMBOL(sbi_get_mvendorid); long sbi_get_marchid(void) { return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID); } +EXPORT_SYMBOL(sbi_get_marchid); long sbi_get_mimpid(void) { return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID); } +EXPORT_SYMBOL(sbi_get_mimpid); static void sbi_send_cpumask_ipi(const struct cpumask *target) { diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 7a68dfa89f6f..a69251ec7a3e 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -642,6 +642,46 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde return 0; } +static uint64_t pmu_sbi_get_pmu_id(void) +{ + union sbi_pmu_id { + uint64_t value; + struct { + uint16_t imp:16; + uint16_t arch:16; + uint32_t vendor:32; + }; + } pmuid; + + pmuid.value = 0; + pmuid.vendor = (uint32_t) sbi_get_mvendorid(); + pmuid.arch = (sbi_get_marchid() >> (63 - 15) & (1 << 15)) | (sbi_get_marchid() & 0x7FFF); + pmuid.imp = (sbi_get_mimpid() >> 16); + + return pmuid.value; +} + +static ssize_t pmu_sbi_id_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int len; + + len = sprintf(buf, "0x%llx\n", pmu_sbi_get_pmu_id()); + if (len <= 0) + dev_err(dev, "mydrv: Invalid sprintf len: %dn", len); + + return len; +} + +static DEVICE_ATTR(id, S_IRUGO | S_IWUSR, pmu_sbi_id_show, 0); + +static struct attribute *pmu_sbi_attrs[] = { + &dev_attr_id.attr, + NULL +}; + +ATTRIBUTE_GROUPS(pmu_sbi); + static int pmu_sbi_device_probe(struct platform_device *pdev) { struct riscv_pmu *pmu = NULL; @@ -680,6 +720,13 @@ static int pmu_sbi_device_probe(struct platform_device *pdev) pmu->ctr_clear_idx = pmu_sbi_ctr_clear_idx; pmu->ctr_read = pmu_sbi_ctr_read; + ret = sysfs_create_group(&pdev->dev.kobj, &pmu_sbi_group); + if (ret) { + dev_err(&pdev->dev, "sysfs creation failed\n"); + return ret; + } + pdev->dev.groups = pmu_sbi_groups; + ret = cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node); if (ret) return ret; From patchwork Tue Nov 16 15:48:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Sm/Do28gTcOhcmlvIERvbWluZ29z?= X-Patchwork-Id: 12622765 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B20CC433F5 for ; Tue, 16 Nov 2021 15:48:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C549F6120F for ; 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a=rsa-sha256; c=relaxed/simple; d=tecnico.ulisboa.pt; s=mail; t=1637077694; bh=L0uH4y+eLrotmKlSZwpxLB8DIS1Pj8tO75awDvkaK4s=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=S9moGslAUYiv7OvNr3jAy/3nvOSy9OrZh8Ij1eRibolhvUpGhztrxDhZzlB1W0SyE 7LIsWzK+GzTAWQNQS/cpvxqHiMDPkg1Fjjf6l+IhYliBSJ4/nJ1WpZksYbk8CacygG xL41YSmfQ313KzLpXn4kzk2CXZelOvqXqH3zBaMs= Received: from joaomariovmubuntu.Home (unknown [IPv6:2001:8a0:fa2d:4500:215:5dff:fe40:101]) (Authenticated sender: ist181713) by mail2.tecnico.ulisboa.pt (Postfix) with ESMTPSA id 7F89056007E; Tue, 16 Nov 2021 15:48:14 +0000 (WET) From: =?utf-8?b?Sm/Do28gTcOhcmlvIERvbWluZ29z?= To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu Cc: atish.patra@wdc.com, anup.patel@wdc.com, linux-riscv@lists.infradead.org, nikita.shubin@maquefel.me, joao.mario@tecnico.ulisboa.pt Subject: [PATCH v2 2/4] RISC-V: Support CPUID for risc-v in perf Date: Tue, 16 Nov 2021 15:48:10 +0000 Message-Id: <20211116154812.17008-3-joao.mario@tecnico.ulisboa.pt> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211116154812.17008-1-joao.mario@tecnico.ulisboa.pt> References: <20211109102555.16381-1-joao.mario@tecnico.ulisboa.pt> <20211116154812.17008-1-joao.mario@tecnico.ulisboa.pt> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211116_074836_475942_575708A8 X-CRM114-Status: GOOD ( 17.23 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This patch creates the header.c file for the risc-v architecture and introduces support for PMU identification through sysfs. It is now possible to configure pmu-events in risc-v. Depends on patch [1], that introduces the id sysfs file. Signed-off-by: João Mário Domingos --- drivers/perf/riscv_pmu.c | 18 ++++++++ tools/perf/arch/riscv/util/Build | 1 + tools/perf/arch/riscv/util/header.c | 66 +++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) create mode 100644 tools/perf/arch/riscv/util/header.c diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c index 0c853e23f679..3752ffd4edaf 100644 --- a/drivers/perf/riscv_pmu.c +++ b/drivers/perf/riscv_pmu.c @@ -17,6 +17,23 @@ #include +PMU_FORMAT_ATTR(event, "config:0-63"); + +static struct attribute *riscv_arch_formats_attr[] = { + &format_attr_event.attr, + NULL, +}; + +static struct attribute_group riscv_pmu_format_group = { + .name = "format", + .attrs = riscv_arch_formats_attr, +}; + +static const struct attribute_group *riscv_pmu_attr_groups[] = { + &riscv_pmu_format_group, + NULL, +}; + static unsigned long csr_read_num(int csr_num) { #define switchcase_csr_read(__csr_num, __val) {\ @@ -314,6 +331,7 @@ struct riscv_pmu *riscv_pmu_alloc(void) cpuc->events[i] = NULL; } pmu->pmu = (struct pmu) { + .attr_groups = riscv_pmu_attr_groups, .event_init = riscv_pmu_event_init, .add = riscv_pmu_add, .del = riscv_pmu_del, diff --git a/tools/perf/arch/riscv/util/Build b/tools/perf/arch/riscv/util/Build index 7d3050134ae0..603dbb5ae4dc 100644 --- a/tools/perf/arch/riscv/util/Build +++ b/tools/perf/arch/riscv/util/Build @@ -1,4 +1,5 @@ perf-y += perf_regs.o +perf-y += header.o perf-$(CONFIG_DWARF) += dwarf-regs.o perf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o diff --git a/tools/perf/arch/riscv/util/header.c b/tools/perf/arch/riscv/util/header.c new file mode 100644 index 000000000000..b4ca8a768f11 --- /dev/null +++ b/tools/perf/arch/riscv/util/header.c @@ -0,0 +1,66 @@ +#include +#include +#include +#include +#include "../../util/debug.h" +#include "../../util/header.h" + +#define STR_LEN 1024 +#define ID_SIZE 64 + +static int _get_cpuid(char *buf, size_t sz) +{ + const char *sysfs = sysfs__mountpoint(); + u64 id = 0; + char path[PATH_MAX]; + FILE *file; + + if (!sysfs || sz < ID_SIZE) + return -EINVAL; + + scnprintf(path, PATH_MAX, "%s/devices/platform/soc/soc:pmu/id", + sysfs); + + file = fopen(path, "r"); + if (!file) { + pr_debug("fopen failed for file %s\n", path); + return -EINVAL; + } + if (!fgets(buf, ID_SIZE, file)) { + fclose(file); + return -EINVAL; + } + + fclose(file); + + /*Check if value is numeric and remove special characters*/ + id = strtoul(buf, NULL, 16); + if (!id) + return -EINVAL; + scnprintf(buf, ID_SIZE, "0x%lx", id); + + return 0; +} + +char *get_cpuid_str(struct perf_pmu *pmu __maybe_unused) +{ + char *buf = NULL; + int res; + + if (!pmu) + return NULL; + + buf = malloc(ID_SIZE); + if (!buf) + return NULL; + + /* read id */ + res = _get_cpuid(buf, ID_SIZE); + if (res) { + pr_err("failed to get cpuid string for PMU %s\n", pmu->name); + free(buf); + buf = NULL; + } + + return buf; +} From patchwork Tue Nov 16 15:48:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Sm/Do28gTcOhcmlvIERvbWluZ29z?= X-Patchwork-Id: 12622767 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DF6AC433EF for ; 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Tue, 16 Nov 2021 15:48:14 +0000 (WET) Received: from mail2.tecnico.ulisboa.pt (mail2.ist.utl.pt [IPv6:2001:690:2100:1::4750:b5b4]) by smtp1.tecnico.ulisboa.pt (Postfix) with ESMTPS id D36C46005C3B; Tue, 16 Nov 2021 15:48:14 +0000 (WET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tecnico.ulisboa.pt; s=mail; t=1637077694; bh=BUt3n9BzCCHEiumrAk8fSOpSQV2oFo7rA8gPyndev38=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Bje/1opA/pF4ldNH2tj9MF03Z7GeE5qonlXy2bc7yXhiWPzAbC5mq03GpXswRRyQy Gck65ulrPRRzxU4h1om+Xbihir7l7yTIPtWLuEV8YnclStRLj5nWHVwzM727forFkw WBy7Js08Ga0vSuUPoD1pDkAqMFq2Lf+dH5s2oCts= Received: from joaomariovmubuntu.Home (unknown [IPv6:2001:8a0:fa2d:4500:215:5dff:fe40:101]) (Authenticated sender: ist181713) by mail2.tecnico.ulisboa.pt (Postfix) with ESMTPSA id A60F856007F; Tue, 16 Nov 2021 15:48:14 +0000 (WET) From: =?utf-8?b?Sm/Do28gTcOhcmlvIERvbWluZ29z?= To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu Cc: atish.patra@wdc.com, anup.patel@wdc.com, linux-riscv@lists.infradead.org, nikita.shubin@maquefel.me, joao.mario@tecnico.ulisboa.pt Subject: [PATCH v2 3/4] RISC-V: Added generic pmu-events mapfile Date: Tue, 16 Nov 2021 15:48:11 +0000 Message-Id: <20211116154812.17008-4-joao.mario@tecnico.ulisboa.pt> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211116154812.17008-1-joao.mario@tecnico.ulisboa.pt> References: <20211109102555.16381-1-joao.mario@tecnico.ulisboa.pt> <20211116154812.17008-1-joao.mario@tecnico.ulisboa.pt> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211116_074836_457203_C0C0D322 X-CRM114-Status: GOOD ( 11.11 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The pmu-events now supports custom events for RISC-V, plus the cycle, time and instret events were defined. Signed-off-by: João Mário Domingos --- tools/perf/pmu-events/arch/riscv/mapfile.csv | 14 +++++++++++++ .../pmu-events/arch/riscv/riscv-generic.json | 20 +++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-generic.json diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv new file mode 100644 index 000000000000..4f2aa199d9cb --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv @@ -0,0 +1,14 @@ +# Format: +# MIDR,Version,JSON/file/pathname,Type +# +# where +# MIDR Processor version +# Variant[23:20] and Revision [3:0] should be zero. +# Version could be used to track version of JSON file +# but currently unused. +# JSON/file/pathname is the path to JSON file, relative +# to tools/perf/pmu-events/arch/riscv/. +# Type is core, uncore etc +# +# +#Family-model,Version,Filename,EventType diff --git a/tools/perf/pmu-events/arch/riscv/riscv-generic.json b/tools/perf/pmu-events/arch/riscv/riscv-generic.json new file mode 100644 index 000000000000..013e50efad99 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json @@ -0,0 +1,20 @@ +[ + { + "PublicDescription": "CPU Cycles", + "EventCode": "0x00", + "EventName": "riscv_cycles", + "BriefDescription": "CPU cycles RISC-V generic counter" + }, + { + "PublicDescription": "CPU Time", + "EventCode": "0x01", + "EventName": "riscv_time", + "BriefDescription": "CPU time RISC-V generic counter" + }, + { + "PublicDescription": "CPU Instructions", + "EventCode": "0x02", + "EventName": "riscv_instret", + "BriefDescription": "CPU retired instructions RISC-V generic counter" + } +] \ No newline at end of file From patchwork Tue Nov 16 15:48:12 2021 Content-Type: text/plain; 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Tue, 16 Nov 2021 15:48:14 +0000 (WET) From: =?utf-8?b?Sm/Do28gTcOhcmlvIERvbWluZ29z?= To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu Cc: atish.patra@wdc.com, anup.patel@wdc.com, linux-riscv@lists.infradead.org, nikita.shubin@maquefel.me, joao.mario@tecnico.ulisboa.pt Subject: [PATCH v2 4/4] RISC-V: Added HiFive Unmatched PMU events Date: Tue, 16 Nov 2021 15:48:12 +0000 Message-Id: <20211116154812.17008-5-joao.mario@tecnico.ulisboa.pt> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211116154812.17008-1-joao.mario@tecnico.ulisboa.pt> References: <20211109102555.16381-1-joao.mario@tecnico.ulisboa.pt> <20211116154812.17008-1-joao.mario@tecnico.ulisboa.pt> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211116_074836_493447_96551265 X-CRM114-Status: GOOD ( 12.16 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This patch contains all the available events for the HiFive Unmatched performance monitoring unit. Depends on patch [3], for the base mapfile.csv file. Signed-off-by: João Mário Domingos --- tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + .../arch/riscv/sifive/u74/instructions.json | 92 +++++++++++++++++++ .../arch/riscv/sifive/u74/memory.json | 32 +++++++ .../arch/riscv/sifive/u74/microarch.json | 57 ++++++++++++ 4 files changed, 182 insertions(+) create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv index 4f2aa199d9cb..bda3fb9382f1 100644 --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv @@ -12,3 +12,4 @@ # # #Family-model,Version,Filename,EventType +0x48980072018,v1,sifive/u74,core diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json new file mode 100644 index 000000000000..5eab718c9256 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json @@ -0,0 +1,92 @@ +[ + { + "EventName": "EXCEPTION_TAKEN", + "EventCode": "0x0000100", + "BriefDescription": "Exception taken" + }, + { + "EventName": "INTEGER_LOAD_RETIRED", + "EventCode": "0x0000200", + "BriefDescription": "Integer load instruction retired" + }, + { + "EventName": "INTEGER_STORE_RETIRED", + "EventCode": "0x0000400", + "BriefDescription": "Integer store instruction retired" + }, + { + "EventName": "ATOMIC_MEMORY_RETIRED", + "EventCode": "0x0000800", + "BriefDescription": "Atomic memory operation retired" + }, + { + "EventName": "SYSTEM_INSTRUCTION_RETIRED", + "EventCode": "0x0001000", + "BriefDescription": "System instruction retired" + }, + { + "EventName": "INTEGER_ARITHMETIC_RETIRED", + "EventCode": "0x0002000", + "BriefDescription": "Integer arithmetic instruction retired" + }, + { + "EventName": "CONDITIONAL_BRANCH_RETIRED", + "EventCode": "0x0004000", + "BriefDescription": "Conditional branch retired" + }, + { + "EventName": "JAL_INSTRUCTION_RETIRED", + "EventCode": "0x0008000", + "BriefDescription": "JAL instruction retired" + }, + { + "EventName": "JALR_INSTRUCTION_RETIRED", + "EventCode": "0x0010000", + "BriefDescription": "JALR instruction retired" + }, + { + "EventName": "INTEGER_MULTIPLICATION_RETIRED", + "EventCode": "0x0020000", + "BriefDescription": "Integer multiplication instruction retired" + }, + { + "EventName": "INTEGER_DIVISION_RETIRED", + "EventCode": "0x0040000", + "BriefDescription": "Integer division instruction retired" + }, + { + "EventName": "FP_LOAD_RETIRED", + "EventCode": "0x0080000", + "BriefDescription": "Floating-point load instruction retired" + }, + { + "EventName": "FP_STORE_RETIRED", + "EventCode": "0x0100000", + "BriefDescription": "Floating-point store instruction retired" + }, + { + "EventName": "FP_ADDITION_RETIRED", + "EventCode": "0x0200000", + "BriefDescription": "Floating-point addition retired" + }, + { + "EventName": "FP_MULTIPLICATION_RETIRED", + "EventCode": "0x0400000", + "BriefDescription": "Floating-point multiplication retired" + }, + { + "EventName": "FP_FUSEDMADD_RETIRED", + "EventCode": "0x0800000", + "BriefDescription": "Floating-point fused multiply-add retired" + }, + { + "EventName": "FP_DIV_SQRT_RETIRED", + "EventCode": "0x1000000", + "BriefDescription": "Floating-point division or square-root retired" + }, + { + "EventName": "OTHER_FP_RETIRED", + "EventCode": "0x2000000", + "BriefDescription": "Other floating-point instruction retired" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json new file mode 100644 index 000000000000..be1a46312ac3 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json @@ -0,0 +1,32 @@ +[ + { + "EventName": "ICACHE_RETIRED", + "EventCode": "0x0000102", + "BriefDescription": "Instruction cache miss" + }, + { + "EventName": "DCACHE_MISS_MMIO_ACCESSES", + "EventCode": "0x0000202", + "BriefDescription": "Data cache miss or memory-mapped I/O access" + }, + { + "EventName": "DCACHE_WRITEBACK", + "EventCode": "0x0000402", + "BriefDescription": "Data cache write-back" + }, + { + "EventName": "INST_TLB_MISS", + "EventCode": "0x0000802", + "BriefDescription": "Instruction TLB miss" + }, + { + "EventName": "DATA_TLB_MISS", + "EventCode": "0x0001002", + "BriefDescription": "Data TLB miss" + }, + { + "EventName": "UTLB_MISS", + "EventCode": "0x0002002", + "BriefDescription": "UTLB miss" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json new file mode 100644 index 000000000000..50ffa55418cb --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json @@ -0,0 +1,57 @@ +[ + { + "EventName": "ADDRESSGEN_INTERLOCK", + "EventCode": "0x0000101", + "BriefDescription": "Address-generation interlock" + }, + { + "EventName": "LONGLAT_INTERLOCK", + "EventCode": "0x0000201", + "BriefDescription": "Long-latency interlock" + }, + { + "EventName": "CSR_READ_INTERLOCK", + "EventCode": "0x0000401", + "BriefDescription": "CSR read interlock" + }, + { + "EventName": "ICACHE_ITIM_BUSY", + "EventCode": "0x0000801", + "BriefDescription": "Instruction cache/ITIM busy" + }, + { + "EventName": "DCACHE_DTIM_BUSY", + "EventCode": "0x0001001", + "BriefDescription": "Data cache/DTIM busy" + }, + { + "EventName": "BRANCH_DIRECTION_MISPREDICTION", + "EventCode": "0x0002001", + "BriefDescription": "Branch direction misprediction" + }, + { + "EventName": "BRANCH_TARGET_MISPREDICTION", + "EventCode": "0x0004001", + "BriefDescription": "Branch/jump target misprediction" + }, + { + "EventName": "PIPE_FLUSH_CSR_WRITE", + "EventCode": "0x0008001", + "BriefDescription": "Pipeline flush from CSR write" + }, + { + "EventName": "PIPE_FLUSH_OTHER_EVENT", + "EventCode": "0x0010001", + "BriefDescription": "Pipeline flush from other event" + }, + { + "EventName": "INTEGER_MULTIPLICATION_INTERLOCK", + "EventCode": "0x0020001", + "BriefDescription": "Integer multiplication interlock" + }, + { + "EventName": "FP_INTERLOCK", + "EventCode": "0x0040001", + "BriefDescription": "Floating-point interlock" + } +] \ No newline at end of file