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Miller" , Jakub Kicinski , Heiner Kallweit , Russell King Subject: [PATCH v1 net-next 1/3] net: mdio: mscc-miim: convert to a regmap implementation Date: Fri, 19 Nov 2021 13:39:16 -0800 Message-Id: <20211119213918.2707530-2-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211119213918.2707530-1-colin.foster@in-advantage.com> References: <20211119213918.2707530-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MW4PR04CA0376.namprd04.prod.outlook.com (2603:10b6:303:81::21) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 Received: from localhost.localdomain (67.185.175.147) by MW4PR04CA0376.namprd04.prod.outlook.com (2603:10b6:303:81::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.19 via Frontend Transport; Fri, 19 Nov 2021 21:39:28 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bbce439f-6e9d-4c06-2d59-08d9aba51085 X-MS-TrafficTypeDiagnostic: MWHPR1001MB2304: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:655; 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This will allow for custom regmaps to be used by way of the mscc_miim_setup function. Signed-off-by: Colin Foster --- drivers/net/mdio/mdio-mscc-miim.c | 150 +++++++++++++++++++++--------- 1 file changed, 105 insertions(+), 45 deletions(-) diff --git a/drivers/net/mdio/mdio-mscc-miim.c b/drivers/net/mdio/mdio-mscc-miim.c index 17f98f609ec8..f55ad20c28d5 100644 --- a/drivers/net/mdio/mdio-mscc-miim.c +++ b/drivers/net/mdio/mdio-mscc-miim.c @@ -14,6 +14,7 @@ #include #include #include +#include #define MSCC_MIIM_REG_STATUS 0x0 #define MSCC_MIIM_STATUS_STAT_PENDING BIT(2) @@ -35,37 +36,47 @@ #define MSCC_PHY_REG_PHY_STATUS 0x4 struct mscc_miim_dev { - void __iomem *regs; - void __iomem *phy_regs; + struct regmap *regs; + struct regmap *phy_regs; }; /* When high resolution timers aren't built-in: we can't use usleep_range() as * we would sleep way too long. Use udelay() instead. */ -#define mscc_readl_poll_timeout(addr, val, cond, delay_us, timeout_us) \ -({ \ - if (!IS_ENABLED(CONFIG_HIGH_RES_TIMERS)) \ - readl_poll_timeout_atomic(addr, val, cond, delay_us, \ - timeout_us); \ - readl_poll_timeout(addr, val, cond, delay_us, timeout_us); \ +#define mscc_readx_poll_timeout(op, addr, val, cond, delay_us, timeout_us)\ +({ \ + if (!IS_ENABLED(CONFIG_HIGH_RES_TIMERS)) \ + readx_poll_timeout_atomic(op, addr, val, cond, delay_us, \ + timeout_us); \ + readx_poll_timeout(op, addr, val, cond, delay_us, timeout_us); \ }) -static int mscc_miim_wait_ready(struct mii_bus *bus) +static int mscc_miim_status(struct mii_bus *bus) { struct mscc_miim_dev *miim = bus->priv; + int val, err; + + err = regmap_read(miim->regs, MSCC_MIIM_REG_STATUS, &val); + if (err < 0) + WARN_ONCE(1, "mscc miim status read error %d\n", err); + + return val; +} + +static int mscc_miim_wait_ready(struct mii_bus *bus) +{ u32 val; - return mscc_readl_poll_timeout(miim->regs + MSCC_MIIM_REG_STATUS, val, + return mscc_readx_poll_timeout(mscc_miim_status, bus, val, !(val & MSCC_MIIM_STATUS_STAT_BUSY), 50, 10000); } static int mscc_miim_wait_pending(struct mii_bus *bus) { - struct mscc_miim_dev *miim = bus->priv; u32 val; - return mscc_readl_poll_timeout(miim->regs + MSCC_MIIM_REG_STATUS, val, + return mscc_readx_poll_timeout(mscc_miim_status, bus, val, !(val & MSCC_MIIM_STATUS_STAT_PENDING), 50, 10000); } @@ -73,22 +84,30 @@ static int mscc_miim_wait_pending(struct mii_bus *bus) static int mscc_miim_read(struct mii_bus *bus, int mii_id, int regnum) { struct mscc_miim_dev *miim = bus->priv; + int ret, err; u32 val; - int ret; ret = mscc_miim_wait_pending(bus); if (ret) goto out; - writel(MSCC_MIIM_CMD_VLD | (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) | - (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) | MSCC_MIIM_CMD_OPR_READ, - miim->regs + MSCC_MIIM_REG_CMD); + err = regmap_write(miim->regs, MSCC_MIIM_REG_CMD, MSCC_MIIM_CMD_VLD | + (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) | + (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) | + MSCC_MIIM_CMD_OPR_READ); + + if (err < 0) + WARN_ONCE(1, "mscc miim write cmd reg error %d\n", err); ret = mscc_miim_wait_ready(bus); if (ret) goto out; - val = readl(miim->regs + MSCC_MIIM_REG_DATA); + err = regmap_read(miim->regs, MSCC_MIIM_REG_DATA, &val); + + if (err < 0) + WARN_ONCE(1, "mscc miim read data reg error %d\n", err); + if (val & MSCC_MIIM_DATA_ERROR) { ret = -EIO; goto out; @@ -103,18 +122,20 @@ static int mscc_miim_write(struct mii_bus *bus, int mii_id, int regnum, u16 value) { struct mscc_miim_dev *miim = bus->priv; - int ret; + int err, ret; ret = mscc_miim_wait_pending(bus); if (ret < 0) goto out; - writel(MSCC_MIIM_CMD_VLD | (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) | - (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) | - (value << MSCC_MIIM_CMD_WRDATA_SHIFT) | - MSCC_MIIM_CMD_OPR_WRITE, - miim->regs + MSCC_MIIM_REG_CMD); + err = regmap_write(miim->regs, MSCC_MIIM_REG_CMD, MSCC_MIIM_CMD_VLD | + (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) | + (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) | + (value << MSCC_MIIM_CMD_WRDATA_SHIFT) | + MSCC_MIIM_CMD_OPR_WRITE); + if (err < 0) + WARN_ONCE(1, "mscc miim write error %d\n", err); out: return ret; } @@ -122,24 +143,35 @@ static int mscc_miim_write(struct mii_bus *bus, int mii_id, static int mscc_miim_reset(struct mii_bus *bus) { struct mscc_miim_dev *miim = bus->priv; + int err; if (miim->phy_regs) { - writel(0, miim->phy_regs + MSCC_PHY_REG_PHY_CFG); - writel(0x1ff, miim->phy_regs + MSCC_PHY_REG_PHY_CFG); + err = regmap_write(miim->phy_regs, MSCC_PHY_REG_PHY_CFG, 0); + if (err < 0) + WARN_ONCE(1, "mscc reset set error %d\n", err); + + err = regmap_write(miim->phy_regs, MSCC_PHY_REG_PHY_CFG, 0x1ff); + if (err < 0) + WARN_ONCE(1, "mscc reset clear error %d\n", err); + mdelay(500); } return 0; } -static int mscc_miim_probe(struct platform_device *pdev) +static const struct regmap_config mscc_miim_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + +static int mscc_miim_setup(struct device *dev, struct mii_bus *bus, + struct regmap *mii_regmap, struct regmap *phy_regmap) { - struct mscc_miim_dev *dev; - struct resource *res; - struct mii_bus *bus; - int ret; + struct mscc_miim_dev *miim; - bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*dev)); + bus = devm_mdiobus_alloc_size(dev, sizeof(*miim)); if (!bus) return -ENOMEM; @@ -147,26 +179,54 @@ static int mscc_miim_probe(struct platform_device *pdev) bus->read = mscc_miim_read; bus->write = mscc_miim_write; bus->reset = mscc_miim_reset; - snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev)); - bus->parent = &pdev->dev; + snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(dev)); + bus->parent = dev; + + miim = bus->priv; + + miim->regs = mii_regmap; + miim->phy_regs = phy_regmap; + + return 0; +} - dev = bus->priv; - dev->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); - if (IS_ERR(dev->regs)) { +static int mscc_miim_probe(struct platform_device *pdev) +{ + struct regmap *mii_regmap, *phy_regmap; + void __iomem *regs, *phy_regs; + struct mscc_miim_dev *dev; + struct mii_bus *bus; + int ret; + + regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + if (IS_ERR(regs)) { dev_err(&pdev->dev, "Unable to map MIIM registers\n"); - return PTR_ERR(dev->regs); + return PTR_ERR(regs); } - /* This resource is optional */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (res) { - dev->phy_regs = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(dev->phy_regs)) { - dev_err(&pdev->dev, "Unable to map internal phy registers\n"); - return PTR_ERR(dev->phy_regs); - } + mii_regmap = devm_regmap_init_mmio(&pdev->dev, regs, + &mscc_miim_regmap_config); + + if (IS_ERR(mii_regmap)) { + dev_err(&pdev->dev, "Unable to create MIIM regmap\n"); + return PTR_ERR(mii_regmap); } + phy_regs = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(dev->phy_regs)) { + dev_err(&pdev->dev, "Unable to map internal phy registers\n"); + return PTR_ERR(dev->phy_regs); + } + + phy_regmap = devm_regmap_init_mmio(&pdev->dev, phy_regs, + &mscc_miim_regmap_config); + if (IS_ERR(phy_regmap)) { + dev_err(&pdev->dev, "Unable to create phy register regmap\n"); + return PTR_ERR(dev->phy_regs); + } + + mscc_miim_setup(&pdev->dev, bus, mii_regmap, phy_regmap); + ret = of_mdiobus_register(bus, pdev->dev.of_node); if (ret < 0) { dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret); From patchwork Fri Nov 19 21:39:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 12629571 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DABBBC433EF for ; Fri, 19 Nov 2021 21:39:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235668AbhKSVmh (ORCPT ); Fri, 19 Nov 2021 16:42:37 -0500 Received: from mail-sn1anam02on2114.outbound.protection.outlook.com ([40.107.96.114]:1767 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S235650AbhKSVme (ORCPT ); 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Fri, 19 Nov 2021 21:39:29 +0000 From: Colin Foster To: linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Vladimir Oltean , Claudiu Manoil , Alexandre Belloni , UNGLinuxDriver@microchip.com, Andrew Lunn , Vivien Didelot , Florian Fainelli , "David S. Miller" , Jakub Kicinski , Heiner Kallweit , Russell King Subject: [PATCH v1 net-next 2/3] net: dsa: ocelot: seville: utilize of_mdiobus_register Date: Fri, 19 Nov 2021 13:39:17 -0800 Message-Id: <20211119213918.2707530-3-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211119213918.2707530-1-colin.foster@in-advantage.com> References: <20211119213918.2707530-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MW4PR04CA0376.namprd04.prod.outlook.com (2603:10b6:303:81::21) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 Received: from localhost.localdomain (67.185.175.147) by MW4PR04CA0376.namprd04.prod.outlook.com (2603:10b6:303:81::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.19 via Frontend Transport; Fri, 19 Nov 2021 21:39:28 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4287fc28-1c16-4125-b7c1-08d9aba51107 X-MS-TrafficTypeDiagnostic: MWHPR1001MB2304: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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This code is about to be pulled into a separate module that can optionally define ports by the device_node. Signed-off-by: Colin Foster Reviewed-by: Florian Fainelli Reviewed-by: Vladimir Oltean --- drivers/net/dsa/ocelot/seville_vsc9953.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/ocelot/seville_vsc9953.c b/drivers/net/dsa/ocelot/seville_vsc9953.c index 899b98193b4a..db124922c374 100644 --- a/drivers/net/dsa/ocelot/seville_vsc9953.c +++ b/drivers/net/dsa/ocelot/seville_vsc9953.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "felix.h" #define MSCC_MIIM_CMD_OPR_WRITE BIT(1) @@ -1112,7 +1113,7 @@ static int vsc9953_mdio_bus_alloc(struct ocelot *ocelot) snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); /* Needed in order to initialize the bus mutex lock */ - rc = mdiobus_register(bus); + rc = of_mdiobus_register(bus, NULL); if (rc < 0) { dev_err(dev, "failed to register MDIO bus\n"); return rc; From patchwork Fri Nov 19 21:39:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 12629573 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F439C433F5 for ; Fri, 19 Nov 2021 21:39:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235698AbhKSVmi (ORCPT ); Fri, 19 Nov 2021 16:42:38 -0500 Received: from mail-sn1anam02on2114.outbound.protection.outlook.com ([40.107.96.114]:1767 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S235655AbhKSVmg (ORCPT ); Fri, 19 Nov 2021 16:42:36 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=fL/mHmbmMMb9OcMKJA12lPqrzU6VGds2nkEQwF0aweBkC8sQQRoRWhug4Os/l7pTspO+qS9TZNfDgtFqvsHRX6a0cZ0hEoFajarutV9s4tym8bFOEId9pMj4qlKp1y2t8wq+RodSNBGmg8aLx1v83vbRtVFqO9GMJs0krd4lPzkWYyQrSRo5g8ovfK26juFghXPy5c6DGk11M4q6wxRjaMYRVDy/wXe3MVvDetL/bRhhlX9zIw+EoO9EuYKrBBwlN5wKoB31LSF1+OYfl4ttumHZHuZqPxz2xaHguGpS1Rwt+lq2GBmr5hIwwv+/3NPseHBpmwu/GriLJ4uo59Pqaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=7QxgCzLldC0Q5MQhnNS/IkIVLuCS+MwrDtaCIjnFtuo=; b=loeKiX4JXIXPSG18gtxPN3/UTPSj/zHguAJQR/Q3Z9sOsQRTUq8UX91whMWlP51VDbLzOJd4hiPwvDF519nP7+C4BKGJUfIYmduNyI1n9VmojRZR/dvSyyS+jXKzcV6Vfe6se2GIndJv7aguM59OumRFeqPC8qh0ueaowje5jjt23w0ogFnQHweSX7LsGKHc37ZR0OdPHe+7Hb07iJTVWbyaLm1D6Yxbl8b7N7622/E3u+SJv7oAPUUCXqjVvghuZxDlUgAixrpKRofN4nXQiDj+Jvfbfiq/DUtitTOCceCIlMT6M89BG6gin/Ye05uu2HmXGD7hBpcRXw5UfUSPnA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=in-advantage.com; dmarc=pass action=none header.from=in-advantage.com; dkim=pass header.d=in-advantage.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=inadvantage.onmicrosoft.com; s=selector2-inadvantage-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7QxgCzLldC0Q5MQhnNS/IkIVLuCS+MwrDtaCIjnFtuo=; b=VGrs9spvegS84UAoeL4AbWzLV6opW9ouCp/lQ7uwbkqthZfeG8kj1Mrm2u4GHLg60j0TBjJaGa50582z01Ftu9FG9hrkFIkDjtLFHIfba6JWpfJjBmpqsos6LZ0XE9Q4SNhbyvSsxMoBr20KvHhZsrgUmUSFZqZBK7itb+e2wLg= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=in-advantage.com; Received: from MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) by MWHPR1001MB2304.namprd10.prod.outlook.com (2603:10b6:301:2e::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.21; Fri, 19 Nov 2021 21:39:30 +0000 Received: from MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::6430:b20:8805:cd9f]) by MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::6430:b20:8805:cd9f%5]) with mapi id 15.20.4713.019; Fri, 19 Nov 2021 21:39:30 +0000 From: Colin Foster To: linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Vladimir Oltean , Claudiu Manoil , Alexandre Belloni , UNGLinuxDriver@microchip.com, Andrew Lunn , Vivien Didelot , Florian Fainelli , "David S. Miller" , Jakub Kicinski , Heiner Kallweit , Russell King Subject: [PATCH v1 net-next 3/3] net: dsa: ocelot: felix: switch to mdio-mscc-miim driver for indirect mdio access Date: Fri, 19 Nov 2021 13:39:18 -0800 Message-Id: <20211119213918.2707530-4-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211119213918.2707530-1-colin.foster@in-advantage.com> References: <20211119213918.2707530-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MW4PR04CA0376.namprd04.prod.outlook.com (2603:10b6:303:81::21) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 Received: from localhost.localdomain (67.185.175.147) by MW4PR04CA0376.namprd04.prod.outlook.com (2603:10b6:303:81::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.19 via Frontend Transport; Fri, 19 Nov 2021 21:39:29 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 30b24986-4eec-48a4-7cfa-08d9aba51167 X-MS-TrafficTypeDiagnostic: MWHPR1001MB2304: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4125; 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+ struct device *dev = ocelot->dev; + int rc; + + /* Needed in order to initialize the bus mutex lock */ + rc = of_mdiobus_register(felix->imdio, np); + if (rc < 0) { + dev_err(dev, "failed to register MDIO bus\n"); + felix->imdio = NULL; + } + + return rc; +} + +int felix_mdio_bus_alloc(struct ocelot *ocelot) +{ + struct felix *felix = ocelot_to_felix(ocelot); + struct device *dev = ocelot->dev; + struct mii_bus *bus; + int err; + + err = mscc_miim_setup(dev, &bus, ocelot->targets[GCB], + ocelot->map[GCB][GCB_MIIM_MII_STATUS & REG_MASK], + ocelot->targets[GCB], + ocelot->map[GCB][GCB_PHY_PHY_CFG & REG_MASK]); + + if (!err) + felix->imdio = bus; + + return err; +} + +void felix_mdio_bus_free(struct ocelot *ocelot) +{ + struct felix *felix = ocelot_to_felix(ocelot); + + if (felix->imdio) + mdiobus_unregister(felix->imdio); +} diff --git a/drivers/net/dsa/ocelot/felix_mdio.h b/drivers/net/dsa/ocelot/felix_mdio.h new file mode 100644 index 000000000000..93286f598c3b --- /dev/null +++ b/drivers/net/dsa/ocelot/felix_mdio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* Shared code for indirect MDIO access for Felix drivers + * + * Author: Colin Foster + * Copyright (C) 2021 Innovative Advantage + */ +#include +#include +#include + +int felix_mdio_bus_alloc(struct ocelot *ocelot); +int felix_of_mdio_register(struct ocelot *ocelot, struct device_node *np); +void felix_mdio_bus_free(struct ocelot *ocelot); diff --git a/drivers/net/dsa/ocelot/seville_vsc9953.c b/drivers/net/dsa/ocelot/seville_vsc9953.c index db124922c374..dd7ae6a1d843 100644 --- a/drivers/net/dsa/ocelot/seville_vsc9953.c +++ b/drivers/net/dsa/ocelot/seville_vsc9953.c @@ -10,15 +10,9 @@ #include #include #include -#include #include "felix.h" +#include "felix_mdio.h" -#define MSCC_MIIM_CMD_OPR_WRITE BIT(1) -#define MSCC_MIIM_CMD_OPR_READ BIT(2) -#define MSCC_MIIM_CMD_WRDATA_SHIFT 4 -#define MSCC_MIIM_CMD_REGAD_SHIFT 20 -#define MSCC_MIIM_CMD_PHYAD_SHIFT 25 -#define MSCC_MIIM_CMD_VLD BIT(31) #define VSC9953_VCAP_POLICER_BASE 11 #define VSC9953_VCAP_POLICER_MAX 31 #define VSC9953_VCAP_POLICER_BASE2 120 @@ -862,7 +856,6 @@ static struct vcap_props vsc9953_vcap_props[] = { #define VSC9953_INIT_TIMEOUT 50000 #define VSC9953_GCB_RST_SLEEP 100 #define VSC9953_SYS_RAMINIT_SLEEP 80 -#define VCS9953_MII_TIMEOUT 10000 static int vsc9953_gcb_soft_rst_status(struct ocelot *ocelot) { @@ -882,82 +875,6 @@ static int vsc9953_sys_ram_init_status(struct ocelot *ocelot) return val; } -static int vsc9953_gcb_miim_pending_status(struct ocelot *ocelot) -{ - int val; - - ocelot_field_read(ocelot, GCB_MIIM_MII_STATUS_PENDING, &val); - - return val; -} - -static int vsc9953_gcb_miim_busy_status(struct ocelot *ocelot) -{ - int val; - - ocelot_field_read(ocelot, GCB_MIIM_MII_STATUS_BUSY, &val); - - return val; -} - -static int vsc9953_mdio_write(struct mii_bus *bus, int phy_id, int regnum, - u16 value) -{ - struct ocelot *ocelot = bus->priv; - int err, cmd, val; - - /* Wait while MIIM controller becomes idle */ - err = readx_poll_timeout(vsc9953_gcb_miim_pending_status, ocelot, - val, !val, 10, VCS9953_MII_TIMEOUT); - if (err) { - dev_err(ocelot->dev, "MDIO write: pending timeout\n"); - goto out; - } - - cmd = MSCC_MIIM_CMD_VLD | (phy_id << MSCC_MIIM_CMD_PHYAD_SHIFT) | - (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) | - (value << MSCC_MIIM_CMD_WRDATA_SHIFT) | - MSCC_MIIM_CMD_OPR_WRITE; - - ocelot_write(ocelot, cmd, GCB_MIIM_MII_CMD); - -out: - return err; -} - -static int vsc9953_mdio_read(struct mii_bus *bus, int phy_id, int regnum) -{ - struct ocelot *ocelot = bus->priv; - int err, cmd, val; - - /* Wait until MIIM controller becomes idle */ - err = readx_poll_timeout(vsc9953_gcb_miim_pending_status, ocelot, - val, !val, 10, VCS9953_MII_TIMEOUT); - if (err) { - dev_err(ocelot->dev, "MDIO read: pending timeout\n"); - goto out; - } - - /* Write the MIIM COMMAND register */ - cmd = MSCC_MIIM_CMD_VLD | (phy_id << MSCC_MIIM_CMD_PHYAD_SHIFT) | - (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) | MSCC_MIIM_CMD_OPR_READ; - - ocelot_write(ocelot, cmd, GCB_MIIM_MII_CMD); - - /* Wait while read operation via the MIIM controller is in progress */ - err = readx_poll_timeout(vsc9953_gcb_miim_busy_status, ocelot, - val, !val, 10, VCS9953_MII_TIMEOUT); - if (err) { - dev_err(ocelot->dev, "MDIO read: busy timeout\n"); - goto out; - } - - val = ocelot_read(ocelot, GCB_MIIM_MII_DATA); - - err = val & 0xFFFF; -out: - return err; -} /* CORE_ENA is in SYS:SYSTEM:RESET_CFG * MEM_INIT is in SYS:SYSTEM:RESET_CFG @@ -1089,7 +1006,6 @@ static int vsc9953_mdio_bus_alloc(struct ocelot *ocelot) { struct felix *felix = ocelot_to_felix(ocelot); struct device *dev = ocelot->dev; - struct mii_bus *bus; int port; int rc; @@ -1101,26 +1017,18 @@ static int vsc9953_mdio_bus_alloc(struct ocelot *ocelot) return -ENOMEM; } - bus = devm_mdiobus_alloc(dev); - if (!bus) - return -ENOMEM; - - bus->name = "VSC9953 internal MDIO bus"; - bus->read = vsc9953_mdio_read; - bus->write = vsc9953_mdio_write; - bus->parent = dev; - bus->priv = ocelot; - snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); + rc = felix_mdio_bus_alloc(ocelot); + if (rc < 0) { + dev_err(dev, "failed to allocate MDIO bus\n"); + return rc; + } - /* Needed in order to initialize the bus mutex lock */ - rc = of_mdiobus_register(bus, NULL); + rc = felix_of_mdio_register(ocelot, NULL); if (rc < 0) { dev_err(dev, "failed to register MDIO bus\n"); return rc; } - felix->imdio = bus; - for (port = 0; port < felix->info->num_ports; port++) { struct ocelot_port *ocelot_port = ocelot->ports[port]; int addr = port + 4; @@ -1165,7 +1073,7 @@ static void vsc9953_mdio_bus_free(struct ocelot *ocelot) mdio_device_free(pcs->mdio); lynx_pcs_destroy(pcs); } - mdiobus_unregister(felix->imdio); + felix_mdio_bus_free(ocelot); } static const struct felix_info seville_info_vsc9953 = { diff --git a/drivers/net/mdio/mdio-mscc-miim.c b/drivers/net/mdio/mdio-mscc-miim.c index f55ad20c28d5..cf3fa7a4459c 100644 --- a/drivers/net/mdio/mdio-mscc-miim.c +++ b/drivers/net/mdio/mdio-mscc-miim.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -37,7 +38,9 @@ struct mscc_miim_dev { struct regmap *regs; + int mii_status_offset; struct regmap *phy_regs; + int phy_reset_offset; }; /* When high resolution timers aren't built-in: we can't use usleep_range() as @@ -56,7 +59,8 @@ static int mscc_miim_status(struct mii_bus *bus) struct mscc_miim_dev *miim = bus->priv; int val, err; - err = regmap_read(miim->regs, MSCC_MIIM_REG_STATUS, &val); + err = regmap_read(miim->regs, + MSCC_MIIM_REG_STATUS + miim->mii_status_offset, &val); if (err < 0) WARN_ONCE(1, "mscc miim status read error %d\n", err); @@ -91,7 +95,9 @@ static int mscc_miim_read(struct mii_bus *bus, int mii_id, int regnum) if (ret) goto out; - err = regmap_write(miim->regs, MSCC_MIIM_REG_CMD, MSCC_MIIM_CMD_VLD | + err = regmap_write(miim->regs, + MSCC_MIIM_REG_CMD + miim->mii_status_offset, + MSCC_MIIM_CMD_VLD | (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) | (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) | MSCC_MIIM_CMD_OPR_READ); @@ -103,7 +109,8 @@ static int mscc_miim_read(struct mii_bus *bus, int mii_id, int regnum) if (ret) goto out; - err = regmap_read(miim->regs, MSCC_MIIM_REG_DATA, &val); + err = regmap_read(miim->regs, + MSCC_MIIM_REG_DATA + miim->mii_status_offset, &val); if (err < 0) WARN_ONCE(1, "mscc miim read data reg error %d\n", err); @@ -128,7 +135,9 @@ static int mscc_miim_write(struct mii_bus *bus, int mii_id, if (ret < 0) goto out; - err = regmap_write(miim->regs, MSCC_MIIM_REG_CMD, MSCC_MIIM_CMD_VLD | + err = regmap_write(miim->regs, + MSCC_MIIM_REG_CMD + miim->mii_status_offset, + MSCC_MIIM_CMD_VLD | (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) | (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) | (value << MSCC_MIIM_CMD_WRDATA_SHIFT) | @@ -143,14 +152,17 @@ static int mscc_miim_write(struct mii_bus *bus, int mii_id, static int mscc_miim_reset(struct mii_bus *bus) { struct mscc_miim_dev *miim = bus->priv; + int offset = miim->phy_reset_offset; int err; if (miim->phy_regs) { - err = regmap_write(miim->phy_regs, MSCC_PHY_REG_PHY_CFG, 0); + err = regmap_write(miim->phy_regs, + MSCC_PHY_REG_PHY_CFG + offset, 0); if (err < 0) WARN_ONCE(1, "mscc reset set error %d\n", err); - err = regmap_write(miim->phy_regs, MSCC_PHY_REG_PHY_CFG, 0x1ff); + err = regmap_write(miim->phy_regs, + MSCC_PHY_REG_PHY_CFG + offset, 0x1ff); if (err < 0) WARN_ONCE(1, "mscc reset clear error %d\n", err); @@ -166,10 +178,12 @@ static const struct regmap_config mscc_miim_regmap_config = { .reg_stride = 4, }; -static int mscc_miim_setup(struct device *dev, struct mii_bus *bus, - struct regmap *mii_regmap, struct regmap *phy_regmap) +int mscc_miim_setup(struct device *dev, struct mii_bus **pbus, + struct regmap *mii_regmap, int status_offset, + struct regmap *phy_regmap, int reset_offset) { struct mscc_miim_dev *miim; + struct mii_bus *bus; bus = devm_mdiobus_alloc_size(dev, sizeof(*miim)); if (!bus) @@ -185,10 +199,15 @@ static int mscc_miim_setup(struct device *dev, struct mii_bus *bus, miim = bus->priv; miim->regs = mii_regmap; + miim->mii_status_offset = status_offset; miim->phy_regs = phy_regmap; + miim->phy_reset_offset = reset_offset; + + *pbus = bus; return 0; } +EXPORT_SYMBOL(mscc_miim_setup); static int mscc_miim_probe(struct platform_device *pdev) { @@ -225,7 +244,7 @@ static int mscc_miim_probe(struct platform_device *pdev) return PTR_ERR(dev->phy_regs); } - mscc_miim_setup(&pdev->dev, bus, mii_regmap, phy_regmap); + mscc_miim_setup(&pdev->dev, &bus, mii_regmap, 0, phy_regmap, 0); ret = of_mdiobus_register(bus, pdev->dev.of_node); if (ret < 0) { diff --git a/include/linux/mdio/mdio-mscc-miim.h b/include/linux/mdio/mdio-mscc-miim.h new file mode 100644 index 000000000000..3ceab7b6ffc1 --- /dev/null +++ b/include/linux/mdio/mdio-mscc-miim.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Driver for the MDIO interface of Microsemi network switches. + * + * Author: Colin Foster + * Copyright (C) 2021 Innovative Advantage + */ +#ifndef MDIO_MSCC_MIIM_H +#define MDIO_MSCC_MIIM_H + +#include +#include +#include + +int mscc_miim_setup(struct device *device, struct mii_bus **bus, + struct regmap *mii_regmap, int status_offset, + struct regmap *phy_regmap, int reset_offset); + +#endif diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h index 89d17629efe5..9d6fe8ce9dd1 100644 --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h @@ -398,6 +398,7 @@ enum ocelot_reg { GCB_MIIM_MII_STATUS, GCB_MIIM_MII_CMD, GCB_MIIM_MII_DATA, + GCB_PHY_PHY_CFG, DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET, DEV_PORT_MISC, DEV_EVENTS,