From patchwork Sat Nov 20 00:16:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Li X-Patchwork-Id: 12629897 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 324BCC433EF for ; Sat, 20 Nov 2021 00:16:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236449AbhKTATb (ORCPT ); Fri, 19 Nov 2021 19:19:31 -0500 Received: from inva020.nxp.com ([92.121.34.13]:45086 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236323AbhKTATa (ORCPT ); Fri, 19 Nov 2021 19:19:30 -0500 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 3F4001A17FD; Sat, 20 Nov 2021 01:16:26 +0100 (CET) Received: from smtp.na-rdc02.nxp.com (usphx01srsp001v.us-phx01.nxp.com [134.27.49.11]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 01CD01A054C; Sat, 20 Nov 2021 01:16:26 +0100 (CET) Received: from right.am.freescale.net (right.am.freescale.net [10.81.116.142]) by usphx01srsp001v.us-phx01.nxp.com (Postfix) with ESMTP id 1E43240BF1; Fri, 19 Nov 2021 17:16:25 -0700 (MST) From: Li Yang To: Bjorn Helgaas , Rob Herring , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hou Zhiqiang Cc: Rob Herring Subject: [PATCH 1/4] dt-bindings: pci: layerscape-pci: Add a optional property big-endian Date: Fri, 19 Nov 2021 18:16:18 -0600 Message-Id: <20211120001621.21246-2-leoyang.li@nxp.com> X-Mailer: git-send-email 2.25.1.377.g2d2118b In-Reply-To: <20211120001621.21246-1-leoyang.li@nxp.com> References: <20211120001621.21246-1-leoyang.li@nxp.com> MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang This property is to indicate the endianness when accessing the PEX_LUT and PF register block, so if these registers are implemented in big-endian, specify this property. Signed-off-by: Hou Zhiqiang Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index f36efa73a470..215d2ee65c83 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -40,6 +40,10 @@ Required properties: of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. +Optional properties: +- big-endian: If the PEX_LUT and PF register block is in big-endian, specify + this property. + Example: pcie@3400000 { From patchwork Sat Nov 20 00:16:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Li X-Patchwork-Id: 12629899 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2597BC433FE for ; Sat, 20 Nov 2021 00:16:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236489AbhKTATc (ORCPT ); Fri, 19 Nov 2021 19:19:32 -0500 Received: from inva020.nxp.com ([92.121.34.13]:45126 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236430AbhKTATa (ORCPT ); Fri, 19 Nov 2021 19:19:30 -0500 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 935F51A17F7; Sat, 20 Nov 2021 01:16:26 +0100 (CET) Received: from smtp.na-rdc02.nxp.com (usphx01srsp001v.us-phx01.nxp.com [134.27.49.11]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 53F7D1A054C; Sat, 20 Nov 2021 01:16:26 +0100 (CET) Received: from right.am.freescale.net (right.am.freescale.net [10.81.116.142]) by usphx01srsp001v.us-phx01.nxp.com (Postfix) with ESMTP id 740AF40BF6; Fri, 19 Nov 2021 17:16:25 -0700 (MST) From: Li Yang To: Bjorn Helgaas , Rob Herring , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hou Zhiqiang Cc: Rob Herring Subject: [PATCH 2/4] dt-bindings: pci: layerscape-pci: Update the description of SCFG property Date: Fri, 19 Nov 2021 18:16:19 -0600 Message-Id: <20211120001621.21246-3-leoyang.li@nxp.com> X-Mailer: git-send-email 2.25.1.377.g2d2118b In-Reply-To: <20211120001621.21246-1-leoyang.li@nxp.com> References: <20211120001621.21246-1-leoyang.li@nxp.com> MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang Update the description of the second entry of 'fsl,pcie-scfg' property, as the LS1043A PCIe controller also has some control registers in SCFG block, while it has 3 controllers. Signed-off-by: Hou Zhiqiang Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 215d2ee65c83..f1115fcd8088 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -34,7 +34,7 @@ Required properties: "intr": The interrupt that is asserted for controller interrupts - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node - The second entry must be '0' or '1' based on physical PCIe controller index. + The second entry is the physical PCIe controller index starting from '0'. This is used to get SCFG PEXN registers - dma-coherent: Indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software From patchwork Sat Nov 20 00:16:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Li X-Patchwork-Id: 12629903 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D9E7C4332F for ; Sat, 20 Nov 2021 00:16:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236504AbhKTATg (ORCPT ); Fri, 19 Nov 2021 19:19:36 -0500 Received: from inva021.nxp.com ([92.121.34.21]:59988 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236442AbhKTATa (ORCPT ); Fri, 19 Nov 2021 19:19:30 -0500 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id E588A201809; Sat, 20 Nov 2021 01:16:26 +0100 (CET) Received: from smtp.na-rdc02.nxp.com (usphx01srsp001v.us-phx01.nxp.com [134.27.49.11]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id A8838200A97; Sat, 20 Nov 2021 01:16:26 +0100 (CET) Received: from right.am.freescale.net (right.am.freescale.net [10.81.116.142]) by usphx01srsp001v.us-phx01.nxp.com (Postfix) with ESMTP id C7B4B40BF7; Fri, 19 Nov 2021 17:16:25 -0700 (MST) From: Li Yang To: Bjorn Helgaas , Rob Herring , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hou Zhiqiang Cc: Xiaowei Bao , Li Yang Subject: [PATCH 3/4] dt-bindings: pci: layerscape-pci: Add EP mode compatible strings for ls1028a Date: Fri, 19 Nov 2021 18:16:20 -0600 Message-Id: <20211120001621.21246-4-leoyang.li@nxp.com> X-Mailer: git-send-email 2.25.1.377.g2d2118b In-Reply-To: <20211120001621.21246-1-leoyang.li@nxp.com> References: <20211120001621.21246-1-leoyang.li@nxp.com> MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Xiaowei Bao Add EP mode compatible string for ls1028a. Signed-off-by: Xiaowei Bao Signed-off-by: Hou Zhiqiang Signed-off-by: Li Yang Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index f1115fcd8088..8fd6039a826b 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -23,6 +23,7 @@ Required properties: "fsl,ls1012a-pcie" "fsl,ls1028a-pcie" EP mode: + "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep" "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep" "fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep" From patchwork Sat Nov 20 00:16:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Li X-Patchwork-Id: 12629901 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FDBCC433F5 for ; Sat, 20 Nov 2021 00:16:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236323AbhKTATg (ORCPT ); Fri, 19 Nov 2021 19:19:36 -0500 Received: from inva021.nxp.com ([92.121.34.21]:60032 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236447AbhKTATa (ORCPT ); Fri, 19 Nov 2021 19:19:30 -0500 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 4081E201807; Sat, 20 Nov 2021 01:16:27 +0100 (CET) Received: from smtp.na-rdc02.nxp.com (usphx01srsp001v.us-phx01.nxp.com [134.27.49.11]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 04CD1200A97; Sat, 20 Nov 2021 01:16:27 +0100 (CET) Received: from right.am.freescale.net (right.am.freescale.net [10.81.116.142]) by usphx01srsp001v.us-phx01.nxp.com (Postfix) with ESMTP id 2C73840A85; Fri, 19 Nov 2021 17:16:26 -0700 (MST) From: Li Yang To: Bjorn Helgaas , Rob Herring , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hou Zhiqiang Cc: Li Yang Subject: [PATCH 4/4] dt-bindings: pci: layerscape-pci: define aer/pme interrupts Date: Fri, 19 Nov 2021 18:16:21 -0600 Message-Id: <20211120001621.21246-5-leoyang.li@nxp.com> X-Mailer: git-send-email 2.25.1.377.g2d2118b In-Reply-To: <20211120001621.21246-1-leoyang.li@nxp.com> References: <20211120001621.21246-1-leoyang.li@nxp.com> MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Some platforms using this controller have separated interrupt lines for aer or pme events instead of having a single interrupt line for miscellaneous events. Define interrupts in the binding for these interrupt lines. Signed-off-by: Li Yang --- .../devicetree/bindings/pci/layerscape-pci.txt | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 8fd6039a826b..bcf11bfc4bab 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -31,8 +31,13 @@ Required properties: - reg: base addresses and lengths of the PCIe controller register blocks. - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. -- interrupt-names: Must include the following entries: - "intr": The interrupt that is asserted for controller interrupts +- interrupt-names: It could include the following entries: + "aer": For interrupt line reporting aer events when non MSI/MSI-X/INTx mode + is used + "pme": For interrupt line reporting pme events when non MSI/MSI-X/INTx mode + is used + "intr": For interrupt line reporting miscellaneous controller events + ...... - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node The second entry is the physical PCIe controller index starting from '0'. @@ -52,8 +57,9 @@ Example: reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; /* controller interrupt */ - interrupt-names = "intr"; + interrupts = , /* aer interrupt */ + ; /* pme interrupt */ + interrupt-names = "aer", "pme"; fsl,pcie-scfg = <&scfg 0>; #address-cells = <3>; #size-cells = <2>;