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[194.187.74.233]) by smtp.gmail.com with ESMTPSA id a18-v6sm3022061ljk.86.2018.12.18.07.58.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Dec 2018 07:58:16 -0800 (PST) From: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= To: Linus Walleij , linux-gpio@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org Subject: [PATCH] pinctrl: bcm: ns: support updated DT binding as syscon subnode Date: Tue, 18 Dec 2018 16:58:08 +0100 Message-Id: <20181218155808.19517-1-zajec5@gmail.com> X-Mailer: git-send-email 2.13.7 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181218_075829_676434_D049A27B X-CRM114-Status: GOOD ( 18.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Florian Fainelli , Scott Branden , Ray Jui , bcm-kernel-feedback-list@broadcom.com, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rafał Miłecki Documentation has been recently updated specifying that pinctrl should be subnode of the CRU "syscon". Support that by using parent node for regmap and reading "offset" property from the DT. Signed-off-by: Rafał Miłecki --- drivers/pinctrl/bcm/pinctrl-ns.c | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-ns.c b/drivers/pinctrl/bcm/pinctrl-ns.c index d7f8175d2c1c..e79690bd8b85 100644 --- a/drivers/pinctrl/bcm/pinctrl-ns.c +++ b/drivers/pinctrl/bcm/pinctrl-ns.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -12,6 +13,7 @@ #include #include #include +#include #include #define FLAG_BCM4708 BIT(1) @@ -22,7 +24,8 @@ struct ns_pinctrl { struct device *dev; unsigned int chipset_flag; struct pinctrl_dev *pctldev; - void __iomem *base; + struct regmap *regmap; + u32 offset; struct pinctrl_desc pctldesc; struct ns_pinctrl_group *groups; @@ -229,9 +232,9 @@ static int ns_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev, unset |= BIT(pin_number); } - tmp = readl(ns_pinctrl->base); + regmap_read(ns_pinctrl->regmap, ns_pinctrl->offset, &tmp); tmp &= ~unset; - writel(tmp, ns_pinctrl->base); + regmap_write(ns_pinctrl->regmap, ns_pinctrl->offset, tmp); return 0; } @@ -263,13 +266,13 @@ static const struct of_device_id ns_pinctrl_of_match_table[] = { static int ns_pinctrl_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; const struct of_device_id *of_id; struct ns_pinctrl *ns_pinctrl; struct pinctrl_desc *pctldesc; struct pinctrl_pin_desc *pin; struct ns_pinctrl_group *group; struct ns_pinctrl_function *function; - struct resource *res; int i; ns_pinctrl = devm_kzalloc(dev, sizeof(*ns_pinctrl), GFP_KERNEL); @@ -287,12 +290,18 @@ static int ns_pinctrl_probe(struct platform_device *pdev) return -EINVAL; ns_pinctrl->chipset_flag = (uintptr_t)of_id->data; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, - "cru_gpio_control"); - ns_pinctrl->base = devm_ioremap_resource(dev, res); - if (IS_ERR(ns_pinctrl->base)) { - dev_err(dev, "Failed to map pinctrl regs\n"); - return PTR_ERR(ns_pinctrl->base); + ns_pinctrl->regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(ns_pinctrl->regmap)) { + int err = PTR_ERR(ns_pinctrl->regmap); + + dev_err(dev, "Failed to map pinctrl regs: %d\n", err); + + return err; + } + + if (of_property_read_u32(np, "offset", &ns_pinctrl->offset)) { + dev_err(dev, "Failed to get register offset\n"); + return -ENOENT; } memcpy(pctldesc, &ns_pinctrl_desc, sizeof(*pctldesc));