From patchwork Tue Nov 23 17:40:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Schimmel X-Patchwork-Id: 12634865 X-Patchwork-Delegate: mkubecek+ethtool@suse.cz Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64029C433FE for ; Tue, 23 Nov 2021 17:41:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239155AbhKWRoe (ORCPT ); Tue, 23 Nov 2021 12:44:34 -0500 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:32999 "EHLO out3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233491AbhKWRoe (ORCPT ); Tue, 23 Nov 2021 12:44:34 -0500 Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id CFF5C5C0116; Tue, 23 Nov 2021 12:41:25 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); Tue, 23 Nov 2021 12:41:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=FxvEW7W2NLx6CMPThusI1PYYRxtEoTK5LJ4VL6o5Sf8=; b=QqRE0uvO EFNcD42vyUimVR7zvoM0gX67jDK5S3N7CLasIqZyTaB5biyckDzkTlH5yAB90lJr lM8eNp6wyF75t+f5q4FW52e3ROWA/XRPF5AGBefe7dQxoQnZxIDkntCbTIGz08/e jhST/HLRod63K6DQryUQ7GeKaB1wG+5OY/rVz+asXqY+vK4EkMTYv2FR4d7fERkD nRdXqueYr8GRvi6uW2/5aIx3AuDGp81oI94UkUGv0oA+87JlMvJK6NnVHHsePtGr yccJmiO3UwC1X8FufZiflTqKtbAAsgrUJiyx1ruEnsqNluvcN4kDKgCjRRqGHr0x hYI+GqauT29Bgg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvuddrgeeigddutdegucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomhepkfguohcuufgthhhimhhmvghluceoihguohhstghhsehiugho shgthhdrohhrgheqnecuggftrfgrthhtvghrnhepudetieevffffveelkeeljeffkefhke ehgfdtffethfelvdejgffghefgveejkefhnecuvehluhhsthgvrhfuihiivgeptdenucfr rghrrghmpehmrghilhhfrhhomhepihguohhstghhsehiughoshgthhdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 23 Nov 2021 12:41:23 -0500 (EST) From: Ido Schimmel To: netdev@vger.kernel.org Cc: mkubecek@suse.cz, popadrian1996@gmail.com, andrew@lunn.ch, mlxsw@nvidia.com, moshe@nvidia.com, Ido Schimmel Subject: [PATCH ethtool-next 1/8] sff-8636: Use an SFF-8636 specific define for maximum number of channels Date: Tue, 23 Nov 2021 19:40:55 +0200 Message-Id: <20211123174102.3242294-2-idosch@idosch.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211123174102.3242294-1-idosch@idosch.org> References: <20211123174102.3242294-1-idosch@idosch.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: mkubecek+ethtool@suse.cz From: Ido Schimmel 'MAX_CHANNEL_NUM' is defined in the common SFF code as 4 and used to set the size of the per-channel diagnostics array in the common 'sff_diags' structure. The CMIS parsing code is also going to use the structure, but it can have up to 32 channels, unlike SFF-8636 that only has 4. Therefore, set 'MAX_CHANNEL_NUM' to 32 and change the SFF-8636 code to use an SFF-8636 specific define instead of the common 'MAX_CHANNEL_NUM'. Signed-off-by: Ido Schimmel --- qsfp.c | 9 +++++---- sff-common.h | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/qsfp.c b/qsfp.c index e7c2f51cd9c6..58c4c4775e9b 100644 --- a/qsfp.c +++ b/qsfp.c @@ -71,6 +71,7 @@ struct sff8636_memory_map { #define SFF8636_PAGE_SIZE 0x80 #define SFF8636_I2C_ADDRESS 0x50 +#define SFF8636_MAX_CHANNEL_NUM 4 #define MAX_DESC_SIZE 42 @@ -761,7 +762,7 @@ static void sff8636_dom_parse(const struct sff8636_memory_map *map, out: /* Channel Specific Data */ - for (i = 0; i < MAX_CHANNEL_NUM; i++) { + for (i = 0; i < SFF8636_MAX_CHANNEL_NUM; i++) { u8 rx_power_offset, tx_bias_offset; u8 tx_power_offset; @@ -832,13 +833,13 @@ static void sff8636_show_dom(const struct sff8636_memory_map *map) printf("\t%-41s : %s\n", "Alarm/warning flags implemented", (sd.supports_alarms ? "Yes" : "No")); - for (i = 0; i < MAX_CHANNEL_NUM; i++) { + for (i = 0; i < SFF8636_MAX_CHANNEL_NUM; i++) { snprintf(power_string, MAX_DESC_SIZE, "%s (Channel %d)", "Laser tx bias current", i+1); PRINT_BIAS(power_string, sd.scd[i].bias_cur); } - for (i = 0; i < MAX_CHANNEL_NUM; i++) { + for (i = 0; i < SFF8636_MAX_CHANNEL_NUM; i++) { snprintf(power_string, MAX_DESC_SIZE, "%s (Channel %d)", "Transmit avg optical power", i+1); PRINT_xX_PWR(power_string, sd.scd[i].tx_power); @@ -849,7 +850,7 @@ static void sff8636_show_dom(const struct sff8636_memory_map *map) else rx_power_string = "Rcvr signal avg optical power"; - for (i = 0; i < MAX_CHANNEL_NUM; i++) { + for (i = 0; i < SFF8636_MAX_CHANNEL_NUM; i++) { snprintf(power_string, MAX_DESC_SIZE, "%s(Channel %d)", rx_power_string, i+1); PRINT_xX_PWR(power_string, sd.scd[i].rx_power); diff --git a/sff-common.h b/sff-common.h index 2183f41ff9c9..aab306e0b74f 100644 --- a/sff-common.h +++ b/sff-common.h @@ -160,7 +160,7 @@ struct sff_channel_diags { /* Module Monitoring Fields */ struct sff_diags { -#define MAX_CHANNEL_NUM 4 +#define MAX_CHANNEL_NUM 32 #define LWARN 0 #define HWARN 1 #define LALRM 2 From patchwork Tue Nov 23 17:40:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Schimmel X-Patchwork-Id: 12634867 X-Patchwork-Delegate: mkubecek+ethtool@suse.cz Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34304C433EF for ; Tue, 23 Nov 2021 17:41:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239225AbhKWRoh (ORCPT ); Tue, 23 Nov 2021 12:44:37 -0500 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:41013 "EHLO out3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233491AbhKWRog (ORCPT ); Tue, 23 Nov 2021 12:44:36 -0500 Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id AE4405C00F7; Tue, 23 Nov 2021 12:41:27 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); Tue, 23 Nov 2021 12:41:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=FgZ96pTkfJRsWMQ5w7DpJFNDbGcJGgNmkxL2+zaAdN8=; b=gdwAm1qJ AVoPwFLH/dCNUlw7DQf+k7qVuPNTPiJlqElBisLY0BC++uDV7h9+GALK8dROFO7M i1EgmCAtk7yc0WB8HnfRZxFkoVMBFEgtCBIS1xjBlSx3awX1EpJSEzVTxpYpJVrz 7p67iOxWlApG4eZXmTw8Z4lJWzMdi6qX+XiZxdV2wCgJ/W239ingy0UdC4he6gpB uZLObjHQNpyeDLtRr6I/FrhXyG8DrRtFNSw6hRpBWph4iW4UapJdvQtSs0Q68fIL J+7Z2p/lrHB2tfFHf7pF6TW9U2BfV6ajokcoIdrrjhpIHZi1q1YtifJkEG0llKwZ U3DH6+OB6aEbXA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvuddrgeeigddutdegucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomhepkfguohcuufgthhhimhhmvghluceoihguohhstghhsehiugho shgthhdrohhrgheqnecuggftrfgrthhtvghrnhepudetieevffffveelkeeljeffkefhke ehgfdtffethfelvdejgffghefgveejkefhnecuvehluhhsthgvrhfuihiivgepudenucfr rghrrghmpehmrghilhhfrhhomhepihguohhstghhsehiughoshgthhdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 23 Nov 2021 12:41:26 -0500 (EST) From: Ido Schimmel To: netdev@vger.kernel.org Cc: mkubecek@suse.cz, popadrian1996@gmail.com, andrew@lunn.ch, mlxsw@nvidia.com, moshe@nvidia.com, Ido Schimmel Subject: [PATCH ethtool-next 2/8] sff-common: Move OFFSET_TO_U16_PTR() to common header file Date: Tue, 23 Nov 2021 19:40:56 +0200 Message-Id: <20211123174102.3242294-3-idosch@idosch.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211123174102.3242294-1-idosch@idosch.org> References: <20211123174102.3242294-1-idosch@idosch.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: mkubecek+ethtool@suse.cz From: Ido Schimmel The define is also useful for CMIS, so move it from SFF-8636 to the common header file. Signed-off-by: Ido Schimmel --- qsfp.c | 1 - sff-common.h | 4 ++-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/qsfp.c b/qsfp.c index 58c4c4775e9b..b3c9e1516af9 100644 --- a/qsfp.c +++ b/qsfp.c @@ -700,7 +700,6 @@ sff8636_show_wavelength_or_copper_compliance(const struct sff8636_memory_map *ma * Second byte are 1/256th of degree, which are added to the dec part. */ #define SFF8636_OFFSET_TO_TEMP(offset) ((__s16)OFFSET_TO_U16(offset)) -#define OFFSET_TO_U16_PTR(ptr, offset) (ptr[offset] << 8 | ptr[(offset) + 1]) static void sff8636_dom_parse(const struct sff8636_memory_map *map, struct sff_diags *sd) diff --git a/sff-common.h b/sff-common.h index aab306e0b74f..9e323008ba19 100644 --- a/sff-common.h +++ b/sff-common.h @@ -126,8 +126,8 @@ #define SFF8024_ENCODING_PAM4 0x08 /* Most common case: 16-bit unsigned integer in a certain unit */ -#define OFFSET_TO_U16(offset) \ - (id[offset] << 8 | id[(offset) + 1]) +#define OFFSET_TO_U16_PTR(ptr, offset) (ptr[offset] << 8 | ptr[(offset) + 1]) +#define OFFSET_TO_U16(offset) OFFSET_TO_U16_PTR(id, offset) # define PRINT_xX_PWR(string, var) \ printf("\t%-41s : %.4f mW / %.2f dBm\n", (string), \ From patchwork Tue Nov 23 17:40:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Schimmel X-Patchwork-Id: 12634869 X-Patchwork-Delegate: mkubecek+ethtool@suse.cz Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15F86C433FE for ; Tue, 23 Nov 2021 17:41:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239301AbhKWRoi (ORCPT ); Tue, 23 Nov 2021 12:44:38 -0500 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:50905 "EHLO out3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233491AbhKWRoi (ORCPT ); Tue, 23 Nov 2021 12:44:38 -0500 Received: from compute6.internal (compute6.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id 7CE4B5C00F4; Tue, 23 Nov 2021 12:41:29 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute6.internal (MEProxy); Tue, 23 Nov 2021 12:41:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=zHGroaHsxmqyA4dOOzMmE/qfyjyRVRpxFoUila5riVk=; b=JeV4grM0 gnIL6UJg+8rsszIukHWfQDISAyVj5CFLX3uNfsGGCAterHUdpKIrgKGb7OIKHQ7R wV8Niw1pkdiJo6eSUGiK+gfITpIAM2svh8C41MiOJs1qr0GA0BPzldPWEIX7jW+T wUUHXjfqR8E7WiWDXekDwy3DPcaJDY54WEfeRHVdsDFCa2bvazzs5DqXotPHIZLI a3ilIZtB9I+N8nfKO/1wOzlyzq/wbrwcyoB55vLbJ0/w6uxb8e3TEY3Omrmw9D6r LbXKmmjjOSk0zoQfSyn3MA3TYapBz+LVX4CLTsEzOMnQDh/5exIKUFSBNTnWzeWv ydmu/gJPRDKbdg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvuddrgeeigddutdegucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomhepkfguohcuufgthhhimhhmvghluceoihguohhstghhsehiugho shgthhdrohhrgheqnecuggftrfgrthhtvghrnhepudetieevffffveelkeeljeffkefhke ehgfdtffethfelvdejgffghefgveejkefhnecuvehluhhsthgvrhfuihiivgeptdenucfr rghrrghmpehmrghilhhfrhhomhepihguohhstghhsehiughoshgthhdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 23 Nov 2021 12:41:27 -0500 (EST) From: Ido Schimmel To: netdev@vger.kernel.org Cc: mkubecek@suse.cz, popadrian1996@gmail.com, andrew@lunn.ch, mlxsw@nvidia.com, moshe@nvidia.com, Ido Schimmel Subject: [PATCH ethtool-next 3/8] cmis: Initialize Page 02h in memory map Date: Tue, 23 Nov 2021 19:40:57 +0200 Message-Id: <20211123174102.3242294-4-idosch@idosch.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211123174102.3242294-1-idosch@idosch.org> References: <20211123174102.3242294-1-idosch@idosch.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: mkubecek+ethtool@suse.cz From: Ido Schimmel Page 02h stores module and lane thresholds that are going to be parsed and displayed in subsequent patches. Request it via the 'MODULE_EEPROM_GET' netlink message and initialize it in the memory map. Signed-off-by: Ido Schimmel --- cmis.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/cmis.c b/cmis.c index 4798fd4c7d68..55b9d1b959cd 100644 --- a/cmis.c +++ b/cmis.c @@ -17,9 +17,10 @@ struct cmis_memory_map { const __u8 *lower_memory; - const __u8 *upper_memory[1][2]; /* Bank, Page */ + const __u8 *upper_memory[1][3]; /* Bank, Page */ #define page_00h upper_memory[0x0][0x0] #define page_01h upper_memory[0x0][0x1] +#define page_02h upper_memory[0x0][0x2] }; #define CMIS_PAGE_SIZE 0x80 @@ -423,8 +424,8 @@ cmis_memory_map_init_pages(struct cmd_context *ctx, return ret; map->page_00h = request.data - CMIS_PAGE_SIZE; - /* Page 01h is only present when the module memory model is paged and - * not flat. + /* Pages 01h and 02h are only present when the module memory model is + * paged and not flat. */ if (map->lower_memory[CMIS_MEMORY_MODEL_OFFSET] & CMIS_MEMORY_MODEL_MASK) @@ -436,6 +437,12 @@ cmis_memory_map_init_pages(struct cmd_context *ctx, return ret; map->page_01h = request.data - CMIS_PAGE_SIZE; + cmis_request_init(&request, 0, 0x2, CMIS_PAGE_SIZE); + ret = nl_get_eeprom_page(ctx, &request); + if (ret < 0) + return ret; + map->page_02h = request.data - CMIS_PAGE_SIZE; + return 0; } From patchwork Tue Nov 23 17:40:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Schimmel X-Patchwork-Id: 12634871 X-Patchwork-Delegate: mkubecek+ethtool@suse.cz Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 227EFC433F5 for ; Tue, 23 Nov 2021 17:41:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239317AbhKWRok (ORCPT ); Tue, 23 Nov 2021 12:44:40 -0500 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:44955 "EHLO out3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239305AbhKWRoj (ORCPT ); Tue, 23 Nov 2021 12:44:39 -0500 Received: from compute6.internal (compute6.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id 408B45C00CB; Tue, 23 Nov 2021 12:41:31 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute6.internal (MEProxy); Tue, 23 Nov 2021 12:41:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=UisYoqP0W0o2AFCQ0Ss1mNbGs7BbEm3yHju4sKD7Htc=; b=ky7qvPbX qlaFxGtRxevX5MDf+CzyUnv8BYp69nXA2Gok6wHDGafrgvcysY+YGWiFudNLODAb IIPsN8CqWF6tyjDehL2EFiNg5/hVAKOKX2WsLXQIQn2Zi9OIeDzcKMYbLotTpHw9 KM+4WjFGZtht5GDGg4Q4lPtc+6OpZZx0VC5wndlKmv6hgodphYrjZ0RJXBNu8HEq EI54Kd+m1YMbTsLrgNy3o+O2kogFa8JbrOijDy/pJXDjz6Dn+wCp+KeDRSvbM79A mFuOln8fmKAodWFMkcad+thE5I/T3zwvbfwSXTjxrpUsbmlTE0VwRUScE5yuyjWV t/NgALIPcis7nA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvuddrgeeigddutdegucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomhepkfguohcuufgthhhimhhmvghluceoihguohhstghhsehiugho shgthhdrohhrgheqnecuggftrfgrthhtvghrnhepudetieevffffveelkeeljeffkefhke ehgfdtffethfelvdejgffghefgveejkefhnecuvehluhhsthgvrhfuihiivgepudenucfr rghrrghmpehmrghilhhfrhhomhepihguohhstghhsehiughoshgthhdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 23 Nov 2021 12:41:29 -0500 (EST) From: Ido Schimmel To: netdev@vger.kernel.org Cc: mkubecek@suse.cz, popadrian1996@gmail.com, andrew@lunn.ch, mlxsw@nvidia.com, moshe@nvidia.com, Ido Schimmel Subject: [PATCH ethtool-next 4/8] cmis: Initialize Banked Page 11h in memory map Date: Tue, 23 Nov 2021 19:40:58 +0200 Message-Id: <20211123174102.3242294-5-idosch@idosch.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211123174102.3242294-1-idosch@idosch.org> References: <20211123174102.3242294-1-idosch@idosch.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: mkubecek+ethtool@suse.cz From: Ido Schimmel Banked Page 11h stores, among other things, lane-specific flags and monitors that are going to be parsed and displayed in subsequent patches. Request it via the 'MODULE_EEPROM_GET' netlink message and initialize it in the memory map. Only initialize it in supported Banks. Signed-off-by: Ido Schimmel --- cmis.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++-- cmis.h | 7 +++++++ 2 files changed, 54 insertions(+), 2 deletions(-) diff --git a/cmis.c b/cmis.c index 55b9d1b959cd..83ced4d253ae 100644 --- a/cmis.c +++ b/cmis.c @@ -15,9 +15,17 @@ #include "cmis.h" #include "netlink/extapi.h" +/* The maximum number of supported Banks. Relevant documents: + * [1] CMIS Rev. 5, page. 128, section 8.4.4, Table 8-40 + */ +#define CMIS_MAX_BANKS 4 + +/* We are not parsing further than Page 11h. */ +#define CMIS_MAX_PAGES 18 + struct cmis_memory_map { const __u8 *lower_memory; - const __u8 *upper_memory[1][3]; /* Bank, Page */ + const __u8 *upper_memory[CMIS_MAX_BANKS][CMIS_MAX_PAGES]; #define page_00h upper_memory[0x0][0x0] #define page_01h upper_memory[0x0][0x1] #define page_02h upper_memory[0x0][0x2] @@ -399,12 +407,33 @@ static void cmis_request_init(struct ethtool_module_eeprom *request, u8 bank, request->data = NULL; } +static int cmis_num_banks_get(const struct cmis_memory_map *map, + int *p_num_banks) +{ + switch (map->page_01h[CMIS_PAGES_ADVER_OFFSET] & + CMIS_BANKS_SUPPORTED_MASK) { + case CMIS_BANK_0_SUPPORTED: + *p_num_banks = 1; + break; + case CMIS_BANK_0_1_SUPPORTED: + *p_num_banks = 2; + break; + case CMIS_BANK_0_3_SUPPORTED: + *p_num_banks = 4; + break; + default: + return -EINVAL; + } + + return 0; +} + static int cmis_memory_map_init_pages(struct cmd_context *ctx, struct cmis_memory_map *map) { struct ethtool_module_eeprom request; - int ret; + int num_banks, i, ret; /* Lower Memory and Page 00h are always present. * @@ -443,6 +472,22 @@ cmis_memory_map_init_pages(struct cmd_context *ctx, return ret; map->page_02h = request.data - CMIS_PAGE_SIZE; + /* Bank 0 of Page 11h provides lane-specific registers for the first 8 + * lanes, and each additional Banks provides support for an additional + * 8 lanes. Only initialize supported Banks. + */ + ret = cmis_num_banks_get(map, &num_banks); + if (ret < 0) + return ret; + + for (i = 0; i < num_banks; i++) { + cmis_request_init(&request, i, 0x11, CMIS_PAGE_SIZE); + ret = nl_get_eeprom_page(ctx, &request); + if (ret < 0) + return ret; + map->upper_memory[i][0x11] = request.data - CMIS_PAGE_SIZE; + } + return 0; } diff --git a/cmis.h b/cmis.h index 911491dc5c8f..8d90a04756ad 100644 --- a/cmis.h +++ b/cmis.h @@ -114,6 +114,13 @@ #define CMIS_WAVELENGTH_TOL_MSB 0x8C #define CMIS_WAVELENGTH_TOL_LSB 0x8D +/* Supported Pages Advertising (Page 1) */ +#define CMIS_PAGES_ADVER_OFFSET 0x8E +#define CMIS_BANKS_SUPPORTED_MASK 0x03 +#define CMIS_BANK_0_SUPPORTED 0x00 +#define CMIS_BANK_0_1_SUPPORTED 0x01 +#define CMIS_BANK_0_3_SUPPORTED 0x02 + /* Signal integrity controls */ #define CMIS_SIG_INTEG_TX_OFFSET 0xA1 #define CMIS_SIG_INTEG_RX_OFFSET 0xA2 From patchwork Tue Nov 23 17:40:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Schimmel X-Patchwork-Id: 12634875 X-Patchwork-Delegate: mkubecek+ethtool@suse.cz Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6879CC433EF for ; Tue, 23 Nov 2021 17:41:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239334AbhKWRoo (ORCPT ); Tue, 23 Nov 2021 12:44:44 -0500 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:43841 "EHLO out3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239324AbhKWRom (ORCPT ); Tue, 23 Nov 2021 12:44:42 -0500 Received: from compute6.internal (compute6.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id F24545C00FB; Tue, 23 Nov 2021 12:41:33 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute6.internal (MEProxy); Tue, 23 Nov 2021 12:41:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=k4htUu9E4RZwfnnpC1ceuyNpNagBCmqp0zjxl4hz/tI=; b=IOxkvrVz zvy+XHY86T4cCyxMreY8hvceQpMj6taoH/2uSKKAyVrtTyJTD9CaLZ3K86tGZuJH kKPR2swJiNrCmZzzXFnkLz09RiWkDdAC7me6QzM5RdO996hqicy2BErGrDTHZhEK OGL83hzTJ7HtNYbiFOzGc6yIdvY+Dpd007mCQFp/aXUfLdu3aY8Pd5Q91QTpQUyk kFX+72TfVHkgGXmSHAAVLVGuBDwWiOt8vMJgBfjWlyi49GI+asyOtrdYzY10Fa5T HuWMy3rnRAzXbiNQc9TcpIY/e2Vz7daY34Kb5Yx8bGHRKTYZczEf33kTxkNin1uM CvbwdAByUBdyuQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvuddrgeeigddutdegucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomhepkfguohcuufgthhhimhhmvghluceoihguohhstghhsehiugho shgthhdrohhrgheqnecuggftrfgrthhtvghrnhepudetieevffffveelkeeljeffkefhke ehgfdtffethfelvdejgffghefgveejkefhnecuvehluhhsthgvrhfuihiivgepudenucfr rghrrghmpehmrghilhhfrhhomhepihguohhstghhsehiughoshgthhdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 23 Nov 2021 12:41:31 -0500 (EST) From: Ido Schimmel To: netdev@vger.kernel.org Cc: mkubecek@suse.cz, popadrian1996@gmail.com, andrew@lunn.ch, mlxsw@nvidia.com, moshe@nvidia.com, Ido Schimmel Subject: [PATCH ethtool-next 5/8] cmis: Parse and print diagnostic information Date: Tue, 23 Nov 2021 19:40:59 +0200 Message-Id: <20211123174102.3242294-6-idosch@idosch.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211123174102.3242294-1-idosch@idosch.org> References: <20211123174102.3242294-1-idosch@idosch.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: mkubecek+ethtool@suse.cz From: Ido Schimmel Like SFF-8636, CMIS has module-level monitors such as temperature and voltage and channel-level monitors such as Tx optical power. These monitors have thresholds and flags that are set when the monitors cross the thresholds. Print and parse these values in a similar fashion to SFF-8636. Signed-off-by: Ido Schimmel --- cmis.c | 466 +++++++++++++++++++++++++++++++++++++++++++++++++++++---- cmis.h | 79 ++++++++++ 2 files changed, 518 insertions(+), 27 deletions(-) diff --git a/cmis.c b/cmis.c index 83ced4d253ae..d7b7097139b3 100644 --- a/cmis.c +++ b/cmis.c @@ -19,6 +19,8 @@ * [1] CMIS Rev. 5, page. 128, section 8.4.4, Table 8-40 */ #define CMIS_MAX_BANKS 4 +#define CMIS_CHANNELS_PER_BANK 8 +#define CMIS_MAX_CHANNEL_NUM (CMIS_MAX_BANKS * CMIS_CHANNELS_PER_BANK) /* We are not parsing further than Page 11h. */ #define CMIS_MAX_PAGES 18 @@ -34,6 +36,80 @@ struct cmis_memory_map { #define CMIS_PAGE_SIZE 0x80 #define CMIS_I2C_ADDRESS 0x50 +static struct { + const char *str; + int offset; + __u8 value; /* Alarm is on if (offset & value) != 0. */ +} cmis_aw_mod_flags[] = { + { "Module temperature high alarm", + CMIS_TEMP_AW_OFFSET, CMIS_TEMP_HALARM_STATUS }, + { "Module temperature low alarm", + CMIS_TEMP_AW_OFFSET, CMIS_TEMP_LALARM_STATUS }, + { "Module temperature high warning", + CMIS_TEMP_AW_OFFSET, CMIS_TEMP_HWARN_STATUS }, + { "Module temperature low warning", + CMIS_TEMP_AW_OFFSET, CMIS_TEMP_LWARN_STATUS }, + + { "Module voltage high alarm", + CMIS_VCC_AW_OFFSET, CMIS_VCC_HALARM_STATUS }, + { "Module voltage low alarm", + CMIS_VCC_AW_OFFSET, CMIS_VCC_LALARM_STATUS }, + { "Module voltage high warning", + CMIS_VCC_AW_OFFSET, CMIS_VCC_HWARN_STATUS }, + { "Module voltage low warning", + CMIS_VCC_AW_OFFSET, CMIS_VCC_LWARN_STATUS }, + + { NULL, 0, 0 }, +}; + +static struct { + const char *fmt_str; + int offset; + int adver_offset; /* In Page 01h. */ + __u8 adver_value; /* Supported if (offset & value) != 0. */ +} cmis_aw_chan_flags[] = { + { "Laser bias current high alarm (Chan %d)", + CMIS_TX_BIAS_AW_HALARM_OFFSET, + CMIS_DIAG_CHAN_ADVER_OFFSET, CMIS_TX_BIAS_MON_MASK }, + { "Laser bias current low alarm (Chan %d)", + CMIS_TX_BIAS_AW_LALARM_OFFSET, + CMIS_DIAG_CHAN_ADVER_OFFSET, CMIS_TX_BIAS_MON_MASK }, + { "Laser bias current high warning (Chan %d)", + CMIS_TX_BIAS_AW_HWARN_OFFSET, + CMIS_DIAG_CHAN_ADVER_OFFSET, CMIS_TX_BIAS_MON_MASK }, + { "Laser bias current low warning (Chan %d)", + CMIS_TX_BIAS_AW_LWARN_OFFSET, + CMIS_DIAG_CHAN_ADVER_OFFSET, CMIS_TX_BIAS_MON_MASK }, + + { "Laser tx power high alarm (Channel %d)", + CMIS_TX_PWR_AW_HALARM_OFFSET, + CMIS_DIAG_CHAN_ADVER_OFFSET, CMIS_TX_PWR_MON_MASK }, + { "Laser tx power low alarm (Channel %d)", + CMIS_TX_PWR_AW_LALARM_OFFSET, + CMIS_DIAG_CHAN_ADVER_OFFSET, CMIS_TX_PWR_MON_MASK }, + { "Laser tx power high warning (Channel %d)", + CMIS_TX_PWR_AW_HWARN_OFFSET, + CMIS_DIAG_CHAN_ADVER_OFFSET, CMIS_TX_PWR_MON_MASK }, + { "Laser tx power low warning (Channel %d)", + CMIS_TX_PWR_AW_LWARN_OFFSET, + CMIS_DIAG_CHAN_ADVER_OFFSET, CMIS_TX_PWR_MON_MASK }, + + { "Laser rx power high alarm (Channel %d)", + CMIS_RX_PWR_AW_HALARM_OFFSET, + CMIS_DIAG_CHAN_ADVER_OFFSET, CMIS_RX_PWR_MON_MASK }, + { "Laser rx power low alarm (Channel %d)", + CMIS_RX_PWR_AW_LALARM_OFFSET, + CMIS_DIAG_CHAN_ADVER_OFFSET, CMIS_RX_PWR_MON_MASK }, + { "Laser rx power high warning (Channel %d)", + CMIS_RX_PWR_AW_HWARN_OFFSET, + CMIS_DIAG_CHAN_ADVER_OFFSET, CMIS_RX_PWR_MON_MASK }, + { "Laser rx power low warning (Channel %d)", + CMIS_RX_PWR_AW_LWARN_OFFSET, + CMIS_DIAG_CHAN_ADVER_OFFSET, CMIS_RX_PWR_MON_MASK }, + + { NULL, 0, 0, 0 }, +}; + static void cmis_show_identifier(const struct cmis_memory_map *map) { sff8024_show_identifier(map->lower_memory, CMIS_ID_OFFSET); @@ -277,32 +353,6 @@ static void cmis_show_mit_compliance(const struct cmis_memory_map *map) } } -/* - * 2-byte internal temperature conversions: - * First byte is a signed 8-bit integer, which is the temp decimal part - * Second byte is a multiple of 1/256th of a degree, which is added to - * the dec part. - */ -#define OFFSET_TO_TEMP(offset) ((__s16)OFFSET_TO_U16(offset)) - -/** - * Print relevant module level monitoring values. Relevant documents: - * [1] CMIS Rev. 3: - * --> pag. 50, section 1.7.2.4, Table 22 - * - * [2] CMIS Rev. 4: - * --> pag. 84, section 8.2.4, Table 8-6 - */ -static void cmis_show_mod_lvl_monitors(const struct cmis_memory_map *map) -{ - const __u8 *id = map->lower_memory; - - PRINT_TEMP("Module temperature", - OFFSET_TO_TEMP(CMIS_CURR_TEMP_OFFSET)); - PRINT_VCC("Module voltage", - OFFSET_TO_U16(CMIS_CURR_VCC_OFFSET)); -} - /** * Print relevant info about the maximum supported fiber media length * for each type of fiber media at the maximum module-supported bit rate. @@ -352,6 +402,368 @@ static void cmis_show_vendor_info(const struct cmis_memory_map *map) CMIS_CLEI_END_OFFSET, "CLEI code"); } +static void cmis_parse_dom_power_type(const struct cmis_memory_map *map, + struct sff_diags *sd) +{ + sd->rx_power_type = map->page_01h[CMIS_DIAG_TYPE_OFFSET] & + CMIS_RX_PWR_TYPE_MASK; + sd->tx_power_type = map->page_01h[CMIS_DIAG_CHAN_ADVER_OFFSET] & + CMIS_TX_PWR_MON_MASK; +} + +static void cmis_parse_dom_mod_lvl_monitors(const struct cmis_memory_map *map, + struct sff_diags *sd) +{ + sd->sfp_voltage[MCURR] = OFFSET_TO_U16_PTR(map->lower_memory, + CMIS_CURR_VCC_OFFSET); + sd->sfp_temp[MCURR] = (__s16)OFFSET_TO_U16_PTR(map->lower_memory, + CMIS_CURR_TEMP_OFFSET); +} + +static void cmis_parse_dom_mod_lvl_thresh(const struct cmis_memory_map *map, + struct sff_diags *sd) +{ + /* Page is not present in IOCTL path. */ + if (!map->page_02h) + return; + sd->supports_alarms = 1; + + sd->sfp_voltage[HALRM] = OFFSET_TO_U16_PTR(map->page_02h, + CMIS_VCC_HALRM_OFFSET); + sd->sfp_voltage[LALRM] = OFFSET_TO_U16_PTR(map->page_02h, + CMIS_VCC_LALRM_OFFSET); + sd->sfp_voltage[HWARN] = OFFSET_TO_U16_PTR(map->page_02h, + CMIS_VCC_HWARN_OFFSET); + sd->sfp_voltage[LWARN] = OFFSET_TO_U16_PTR(map->page_02h, + CMIS_VCC_LWARN_OFFSET); + + sd->sfp_temp[HALRM] = (__s16)OFFSET_TO_U16_PTR(map->page_02h, + CMIS_TEMP_HALRM_OFFSET); + sd->sfp_temp[LALRM] = (__s16)OFFSET_TO_U16_PTR(map->page_02h, + CMIS_TEMP_LALRM_OFFSET); + sd->sfp_temp[HWARN] = (__s16)OFFSET_TO_U16_PTR(map->page_02h, + CMIS_TEMP_HWARN_OFFSET); + sd->sfp_temp[LWARN] = (__s16)OFFSET_TO_U16_PTR(map->page_02h, + CMIS_TEMP_LWARN_OFFSET); +} + +static __u8 cmis_tx_bias_mul(const struct cmis_memory_map *map) +{ + switch (map->page_01h[CMIS_DIAG_CHAN_ADVER_OFFSET] & + CMIS_TX_BIAS_MUL_MASK) { + case CMIS_TX_BIAS_MUL_1: + return 0; + case CMIS_TX_BIAS_MUL_2: + return 1; + case CMIS_TX_BIAS_MUL_4: + return 2; + } + + return 0; +} + +static void +cmis_parse_dom_chan_lvl_monitors_bank(const struct cmis_memory_map *map, + struct sff_diags *sd, int bank) +{ + const __u8 *page_11h = map->upper_memory[bank][0x11]; + int i; + + if (!page_11h) + return; + + for (i = 0; i < CMIS_CHANNELS_PER_BANK; i++) { + __u8 tx_bias_offset, rx_power_offset, tx_power_offset; + int chan = bank * CMIS_CHANNELS_PER_BANK + i; + __u8 bias_mul = cmis_tx_bias_mul(map); + + tx_bias_offset = CMIS_TX_BIAS_OFFSET + i * sizeof(__u16); + rx_power_offset = CMIS_RX_PWR_OFFSET + i * sizeof(__u16); + tx_power_offset = CMIS_TX_PWR_OFFSET + i * sizeof(__u16); + + sd->scd[chan].bias_cur = OFFSET_TO_U16_PTR(page_11h, + tx_bias_offset); + sd->scd[chan].bias_cur >>= bias_mul; + sd->scd[chan].rx_power = OFFSET_TO_U16_PTR(page_11h, + rx_power_offset); + sd->scd[chan].tx_power = OFFSET_TO_U16_PTR(page_11h, + tx_power_offset); + } +} + +static void cmis_parse_dom_chan_lvl_monitors(const struct cmis_memory_map *map, + struct sff_diags *sd) +{ + int i; + + for (i = 0; i < CMIS_MAX_BANKS; i++) + cmis_parse_dom_chan_lvl_monitors_bank(map, sd, i); +} + +static void cmis_parse_dom_chan_lvl_thresh(const struct cmis_memory_map *map, + struct sff_diags *sd) +{ + __u8 bias_mul = cmis_tx_bias_mul(map); + + if (!map->page_02h) + return; + + sd->bias_cur[HALRM] = OFFSET_TO_U16_PTR(map->page_02h, + CMIS_TX_BIAS_HALRM_OFFSET); + sd->bias_cur[HALRM] >>= bias_mul; + sd->bias_cur[LALRM] = OFFSET_TO_U16_PTR(map->page_02h, + CMIS_TX_BIAS_LALRM_OFFSET); + sd->bias_cur[LALRM] >>= bias_mul; + sd->bias_cur[HWARN] = OFFSET_TO_U16_PTR(map->page_02h, + CMIS_TX_BIAS_HWARN_OFFSET); + sd->bias_cur[HWARN] >>= bias_mul; + sd->bias_cur[LWARN] = OFFSET_TO_U16_PTR(map->page_02h, + CMIS_TX_BIAS_LWARN_OFFSET); + sd->bias_cur[LWARN] >>= bias_mul; + + sd->tx_power[HALRM] = OFFSET_TO_U16_PTR(map->page_02h, + CMIS_TX_PWR_HALRM_OFFSET); + sd->tx_power[LALRM] = OFFSET_TO_U16_PTR(map->page_02h, + CMIS_TX_PWR_LALRM_OFFSET); + sd->tx_power[HWARN] = OFFSET_TO_U16_PTR(map->page_02h, + CMIS_TX_PWR_HWARN_OFFSET); + sd->tx_power[LWARN] = OFFSET_TO_U16_PTR(map->page_02h, + CMIS_TX_PWR_LWARN_OFFSET); + + sd->rx_power[HALRM] = OFFSET_TO_U16_PTR(map->page_02h, + CMIS_RX_PWR_HALRM_OFFSET); + sd->rx_power[LALRM] = OFFSET_TO_U16_PTR(map->page_02h, + CMIS_RX_PWR_LALRM_OFFSET); + sd->rx_power[HWARN] = OFFSET_TO_U16_PTR(map->page_02h, + CMIS_RX_PWR_HWARN_OFFSET); + sd->rx_power[LWARN] = OFFSET_TO_U16_PTR(map->page_02h, + CMIS_RX_PWR_LWARN_OFFSET); +} + +static void cmis_parse_dom(const struct cmis_memory_map *map, + struct sff_diags *sd) +{ + cmis_parse_dom_power_type(map, sd); + cmis_parse_dom_mod_lvl_monitors(map, sd); + cmis_parse_dom_mod_lvl_thresh(map, sd); + cmis_parse_dom_chan_lvl_monitors(map, sd); + cmis_parse_dom_chan_lvl_thresh(map, sd); +} + +/* Print module-level monitoring values. Relevant documents: + * [1] CMIS Rev. 5, page 110, section 8.2.5, Table 8-9 + */ +static void cmis_show_dom_mod_lvl_monitors(const struct sff_diags *sd) +{ + PRINT_TEMP("Module temperature", sd->sfp_temp[MCURR]); + PRINT_VCC("Module voltage", sd->sfp_voltage[MCURR]); +} + +/* Print channel Tx laser bias current. Relevant documents: + * [1] CMIS Rev. 5, page 165, section 8.9.4, Table 8-79 + */ +static void +cmis_show_dom_chan_lvl_tx_bias_bank(const struct cmis_memory_map *map, + const struct sff_diags *sd, int bank) +{ + const __u8 *page_11h = map->upper_memory[bank][0x11]; + int i; + + if (!page_11h) + return; + + for (i = 0; i < CMIS_CHANNELS_PER_BANK; i++) { + int chan = bank * CMIS_CHANNELS_PER_BANK + i; + char fmt_str[80]; + + snprintf(fmt_str, 80, "%s (Channel %d)", + "Laser tx bias current", chan + 1); + PRINT_BIAS(fmt_str, sd->scd[chan].bias_cur); + } +} + +static void cmis_show_dom_chan_lvl_tx_bias(const struct cmis_memory_map *map, + const struct sff_diags *sd) +{ + int i; + + if(!(map->page_01h[CMIS_DIAG_CHAN_ADVER_OFFSET] & + CMIS_TX_BIAS_MON_MASK)) + return; + + for (i = 0; i < CMIS_MAX_BANKS; i++) + cmis_show_dom_chan_lvl_tx_bias_bank(map, sd, i); +} + +/* Print channel Tx average optical power. Relevant documents: + * [1] CMIS Rev. 5, page 165, section 8.9.4, Table 8-79 + */ +static void +cmis_show_dom_chan_lvl_tx_power_bank(const struct cmis_memory_map *map, + const struct sff_diags *sd, int bank) +{ + const __u8 *page_11h = map->upper_memory[bank][0x11]; + int i; + + if (!page_11h) + return; + + for (i = 0; i < CMIS_CHANNELS_PER_BANK; i++) { + int chan = bank * CMIS_CHANNELS_PER_BANK + i; + char fmt_str[80]; + + snprintf(fmt_str, 80, "%s (Channel %d)", + "Transmit avg optical power", chan + 1); + PRINT_xX_PWR(fmt_str, sd->scd[chan].tx_power); + } +} + +static void cmis_show_dom_chan_lvl_tx_power(const struct cmis_memory_map *map, + const struct sff_diags *sd) +{ + int i; + + if (!sd->tx_power_type) + return; + + for (i = 0; i < CMIS_MAX_BANKS; i++) + cmis_show_dom_chan_lvl_tx_power_bank(map, sd, i); +} + +/* Print channel Rx input optical power. Relevant documents: + * [1] CMIS Rev. 5, page 165, section 8.9.4, Table 8-79 + */ +static void +cmis_show_dom_chan_lvl_rx_power_bank(const struct cmis_memory_map *map, + const struct sff_diags *sd, int bank) +{ + const __u8 *page_11h = map->upper_memory[bank][0x11]; + int i; + + if (!page_11h) + return; + + for (i = 0; i < CMIS_CHANNELS_PER_BANK; i++) { + int chan = bank * CMIS_CHANNELS_PER_BANK + i; + char *rx_power_str; + char fmt_str[80]; + + if (!sd->rx_power_type) + rx_power_str = "Receiver signal OMA"; + else + rx_power_str = "Rcvr signal avg optical power"; + + snprintf(fmt_str, 80, "%s (Channel %d)", rx_power_str, + chan + 1); + PRINT_xX_PWR(fmt_str, sd->scd[chan].rx_power); + } +} + +static void cmis_show_dom_chan_lvl_rx_power(const struct cmis_memory_map *map, + const struct sff_diags *sd) +{ + int i; + + if(!(map->page_01h[CMIS_DIAG_CHAN_ADVER_OFFSET] & CMIS_RX_PWR_MON_MASK)) + return; + + for (i = 0; i < CMIS_MAX_BANKS; i++) + cmis_show_dom_chan_lvl_rx_power_bank(map, sd, i); +} + +static void cmis_show_dom_chan_lvl_monitors(const struct cmis_memory_map *map, + const struct sff_diags *sd) +{ + cmis_show_dom_chan_lvl_tx_bias(map, sd); + cmis_show_dom_chan_lvl_tx_power(map, sd); + cmis_show_dom_chan_lvl_rx_power(map, sd); +} + +/* Print module-level flags. Relevant documents: + * [1] CMIS Rev. 5, page 109, section 8.2.4, Table 8-8 + */ +static void cmis_show_dom_mod_lvl_flags(const struct cmis_memory_map *map) +{ + int i; + + for (i = 0; cmis_aw_mod_flags[i].str; i++) { + printf("\t%-41s : %s\n", cmis_aw_mod_flags[i].str, + map->lower_memory[cmis_aw_mod_flags[i].offset] & + cmis_aw_mod_flags[i].value ? "On" : "Off"); + } +} + +/* Print channel-level flags. Relevant documents: + * [1] CMIS Rev. 5, page 162, section 8.9.3, Table 8-77 + * [1] CMIS Rev. 5, page 164, section 8.9.3, Table 8-78 + */ +static void cmis_show_dom_chan_lvl_flags_chan(const struct cmis_memory_map *map, + int bank, int chan) +{ + const __u8 *page_11h = map->upper_memory[bank][0x11]; + int i; + + for (i = 0; cmis_aw_chan_flags[i].fmt_str; i++) { + char str[80]; + + if (!(map->page_01h[cmis_aw_chan_flags[i].adver_offset] & + cmis_aw_chan_flags[i].adver_value)) + continue; + + snprintf(str, 80, cmis_aw_chan_flags[i].fmt_str, chan + 1); + printf("\t%-41s : %s\n", str, + page_11h[cmis_aw_chan_flags[i].offset] & chan ? + "On" : "Off"); + } +} + +static void +cmis_show_dom_chan_lvl_flags_bank(const struct cmis_memory_map *map, + int bank) +{ + const __u8 *page_11h = map->upper_memory[bank][0x11]; + int i; + + if (!page_11h) + return; + + for (i = 0; i < CMIS_CHANNELS_PER_BANK; i++) { + int chan = bank * CMIS_CHANNELS_PER_BANK + i; + + cmis_show_dom_chan_lvl_flags_chan(map, bank, chan); + } +} + +static void cmis_show_dom_chan_lvl_flags(const struct cmis_memory_map *map) +{ + int i; + + for (i = 0; i < CMIS_MAX_BANKS; i++) + cmis_show_dom_chan_lvl_flags_bank(map, i); +} + + +static void cmis_show_dom(const struct cmis_memory_map *map) +{ + struct sff_diags sd = {}; + + /* Diagnostic information is only relevant when the module memory + * model is paged and not flat. + */ + if (map->lower_memory[CMIS_MEMORY_MODEL_OFFSET] & + CMIS_MEMORY_MODEL_MASK) + return; + + cmis_parse_dom(map, &sd); + + cmis_show_dom_mod_lvl_monitors(&sd); + cmis_show_dom_chan_lvl_monitors(map, &sd); + cmis_show_dom_mod_lvl_flags(map); + cmis_show_dom_chan_lvl_flags(map); + if (sd.supports_alarms) + sff_show_thresholds(sd); +} + static void cmis_show_all_common(const struct cmis_memory_map *map) { cmis_show_identifier(map); @@ -360,10 +772,10 @@ static void cmis_show_all_common(const struct cmis_memory_map *map) cmis_show_cbl_asm_len(map); cmis_show_sig_integrity(map); cmis_show_mit_compliance(map); - cmis_show_mod_lvl_monitors(map); cmis_show_link_len(map); cmis_show_vendor_info(map); cmis_show_rev_compliance(map); + cmis_show_dom(map); } static void cmis_memory_map_init_buf(struct cmis_memory_map *map, diff --git a/cmis.h b/cmis.h index 8d90a04756ad..310697b0ef32 100644 --- a/cmis.h +++ b/cmis.h @@ -7,6 +7,18 @@ #define CMIS_MEMORY_MODEL_OFFSET 0x02 #define CMIS_MEMORY_MODEL_MASK 0x80 +/* Module Flags (Page 0) */ +#define CMIS_VCC_AW_OFFSET 0x09 +#define CMIS_VCC_LWARN_STATUS 0x80 +#define CMIS_VCC_HWARN_STATUS 0x40 +#define CMIS_VCC_LALARM_STATUS 0x20 +#define CMIS_VCC_HALARM_STATUS 0x10 +#define CMIS_TEMP_AW_OFFSET 0x09 +#define CMIS_TEMP_LWARN_STATUS 0x08 +#define CMIS_TEMP_HWARN_STATUS 0x04 +#define CMIS_TEMP_LALARM_STATUS 0x02 +#define CMIS_TEMP_HALARM_STATUS 0x01 + #define CMIS_MODULE_TYPE_OFFSET 0x55 #define CMIS_MT_MMF 0x01 #define CMIS_MT_SMF 0x02 @@ -121,10 +133,77 @@ #define CMIS_BANK_0_1_SUPPORTED 0x01 #define CMIS_BANK_0_3_SUPPORTED 0x02 +/* Module Characteristics Advertising (Page 1) */ +#define CMIS_DIAG_TYPE_OFFSET 0x97 +#define CMIS_RX_PWR_TYPE_MASK 0x10 + +/* Supported Monitors Advertisement (Page 1) */ +#define CMIS_DIAG_CHAN_ADVER_OFFSET 0xA0 +#define CMIS_TX_BIAS_MON_MASK 0x01 +#define CMIS_TX_PWR_MON_MASK 0x02 +#define CMIS_RX_PWR_MON_MASK 0x04 +#define CMIS_TX_BIAS_MUL_MASK 0x18 +#define CMIS_TX_BIAS_MUL_1 0x00 +#define CMIS_TX_BIAS_MUL_2 0x08 +#define CMIS_TX_BIAS_MUL_4 0x10 + /* Signal integrity controls */ #define CMIS_SIG_INTEG_TX_OFFSET 0xA1 #define CMIS_SIG_INTEG_RX_OFFSET 0xA2 +/*----------------------------------------------------------------------- + * Upper Memory Page 0x02: Optional Page that informs about module-defined + * thresholds for module-level and lane-specific threshold crossing monitors. + */ + +/* Module-Level Monitor Thresholds (Page 2) */ +#define CMIS_TEMP_HALRM_OFFSET 0x80 +#define CMIS_TEMP_LALRM_OFFSET 0x82 +#define CMIS_TEMP_HWARN_OFFSET 0x84 +#define CMIS_TEMP_LWARN_OFFSET 0x86 +#define CMIS_VCC_HALRM_OFFSET 0x88 +#define CMIS_VCC_LALRM_OFFSET 0x8A +#define CMIS_VCC_HWARN_OFFSET 0x8C +#define CMIS_VCC_LWARN_OFFSET 0x8E + +/* Lane-Related Monitor Thresholds (Page 2) */ +#define CMIS_TX_PWR_HALRM_OFFSET 0xB0 +#define CMIS_TX_PWR_LALRM_OFFSET 0xB2 +#define CMIS_TX_PWR_HWARN_OFFSET 0xB4 +#define CMIS_TX_PWR_LWARN_OFFSET 0xB6 +#define CMIS_TX_BIAS_HALRM_OFFSET 0xB8 +#define CMIS_TX_BIAS_LALRM_OFFSET 0xBA +#define CMIS_TX_BIAS_HWARN_OFFSET 0xBC +#define CMIS_TX_BIAS_LWARN_OFFSET 0xBE +#define CMIS_RX_PWR_HALRM_OFFSET 0xC0 +#define CMIS_RX_PWR_LALRM_OFFSET 0xC2 +#define CMIS_RX_PWR_HWARN_OFFSET 0xC4 +#define CMIS_RX_PWR_LWARN_OFFSET 0xC6 + +/*----------------------------------------------------------------------- + * Upper Memory Page 0x11: Optional Page that contains lane dynamic status + * bytes. + */ + +/* Media Lane-Specific Flags (Page 0x11) */ +#define CMIS_TX_PWR_AW_HALARM_OFFSET 0x8B +#define CMIS_TX_PWR_AW_LALARM_OFFSET 0x8C +#define CMIS_TX_PWR_AW_HWARN_OFFSET 0x8D +#define CMIS_TX_PWR_AW_LWARN_OFFSET 0x8E +#define CMIS_TX_BIAS_AW_HALARM_OFFSET 0x8F +#define CMIS_TX_BIAS_AW_LALARM_OFFSET 0x90 +#define CMIS_TX_BIAS_AW_HWARN_OFFSET 0x91 +#define CMIS_TX_BIAS_AW_LWARN_OFFSET 0x92 +#define CMIS_RX_PWR_AW_HALARM_OFFSET 0x95 +#define CMIS_RX_PWR_AW_LALARM_OFFSET 0x96 +#define CMIS_RX_PWR_AW_HWARN_OFFSET 0x97 +#define CMIS_RX_PWR_AW_LWARN_OFFSET 0x98 + +/* Media Lane-Specific Monitors (Page 0x11) */ +#define CMIS_TX_PWR_OFFSET 0x9A +#define CMIS_TX_BIAS_OFFSET 0xAA +#define CMIS_RX_PWR_OFFSET 0xBA + #define YESNO(x) (((x) != 0) ? "Yes" : "No") #define ONOFF(x) (((x) != 0) ? "On" : "Off") From patchwork Tue Nov 23 17:41:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Schimmel X-Patchwork-Id: 12634873 X-Patchwork-Delegate: mkubecek+ethtool@suse.cz Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29794C433FE for ; Tue, 23 Nov 2021 17:41:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239324AbhKWRop (ORCPT ); Tue, 23 Nov 2021 12:44:45 -0500 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:40899 "EHLO out3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239289AbhKWRoo (ORCPT ); Tue, 23 Nov 2021 12:44:44 -0500 Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.nyi.internal (Postfix) with ESMTP id EF7FD5C00E2; Tue, 23 Nov 2021 12:41:35 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Tue, 23 Nov 2021 12:41:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=1n9MJ/pk4PtOUTC5FiG1cp9Naodq8qe0kwVsL/qt8pY=; b=j/fFh6Dt 4F01UW03oAawQUjfOODaPjst+n9cAl7CR2Pnq6U/jBtaJ70EYpaXD3rwmzXgXV6V /dikPWepxzrvrLyJ5A7xpRS+uiPi7OaEJ+87FqlplyBttfVaKeSTnbDlouaK9Ixi TXAc2W3FlHQ7+MkW5EXBOyxImVtcYXoXIF3VMuqnDlvldct9ri4bvFE+VkhByiY6 P3t7IAKSCi1G0TMSqw8u4vxpv/dGwYSRDLaPwaDXujCTfDNxNJ3h5GKbkcfm5f7Y USlGLGGDwmHhltDTqOsmjVuCHjJfjpkTrWzrQSrqSJissPRouFZvmrZGu5sRyAZ4 OJQ6+wOa6yVo0Q== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvuddrgeeigddutdegucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomhepkfguohcuufgthhhimhhmvghluceoihguohhstghhsehiugho shgthhdrohhrgheqnecuggftrfgrthhtvghrnhepudetieevffffveelkeeljeffkefhke ehgfdtffethfelvdejgffghefgveejkefhnecuvehluhhsthgvrhfuihiivgeptdenucfr rghrrghmpehmrghilhhfrhhomhepihguohhstghhsehiughoshgthhdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 23 Nov 2021 12:41:34 -0500 (EST) From: Ido Schimmel To: netdev@vger.kernel.org Cc: mkubecek@suse.cz, popadrian1996@gmail.com, andrew@lunn.ch, mlxsw@nvidia.com, moshe@nvidia.com, Ido Schimmel Subject: [PATCH ethtool-next 6/8] cmis: Print Module State and Fault Cause Date: Tue, 23 Nov 2021 19:41:00 +0200 Message-Id: <20211123174102.3242294-7-idosch@idosch.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211123174102.3242294-1-idosch@idosch.org> References: <20211123174102.3242294-1-idosch@idosch.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: mkubecek+ethtool@suse.cz From: Ido Schimmel Print the CMIS Module State when dumping EEPROM contents via the '-m' option. It can be used, for example, to test module power mode settings. Example output: # ethtool -m swp11 Identifier : 0x18 (QSFP-DD Double Density 8X Pluggable Transceiver (INF-8628)) ... Module State : 0x03 (ModuleReady) # ethtool --set-module swp11 power-mode-policy auto # ethtool -m swp11 Identifier : 0x18 (QSFP-DD Double Density 8X Pluggable Transceiver (INF-8628)) ... Module State : 0x01 (ModuleLowPwr) In case the module is in fault state, print the CMIS Module Fault Cause. Signed-off-by: Ido Schimmel --- cmis.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ cmis.h | 16 ++++++++++++++ 2 files changed, 86 insertions(+) diff --git a/cmis.c b/cmis.c index d7b7097139b3..a32cc9f8b1f6 100644 --- a/cmis.c +++ b/cmis.c @@ -402,6 +402,74 @@ static void cmis_show_vendor_info(const struct cmis_memory_map *map) CMIS_CLEI_END_OFFSET, "CLEI code"); } +/* Print the current Module State. Relevant documents: + * [1] CMIS Rev. 5, pag. 57, section 6.3.2.2, Figure 6-3 + * [2] CMIS Rev. 5, pag. 60, section 6.3.2.3, Figure 6-4 + * [3] CMIS Rev. 5, pag. 107, section 8.2.2, Table 8-6 + */ +static void cmis_show_mod_state(const struct cmis_memory_map *map) +{ + __u8 mod_state; + + mod_state = (map->lower_memory[CMIS_MODULE_STATE_OFFSET] & + CMIS_MODULE_STATE_MASK) >> 1; + printf("\t%-41s : 0x%02x", "Module State", mod_state); + switch (mod_state) { + case CMIS_MODULE_STATE_MODULE_LOW_PWR: + printf(" (ModuleLowPwr)\n"); + break; + case CMIS_MODULE_STATE_MODULE_PWR_UP: + printf(" (ModulePwrUp)\n"); + break; + case CMIS_MODULE_STATE_MODULE_READY: + printf(" (ModuleReady)\n"); + break; + case CMIS_MODULE_STATE_MODULE_PWR_DN: + printf(" (ModulePwrDn)\n"); + break; + case CMIS_MODULE_STATE_MODULE_FAULT: + printf(" (ModuleFault)\n"); + break; + default: + printf(" (reserved or unknown)\n"); + break; + } +} + +/* Print the Module Fault Information. Relevant documents: + * [1] CMIS Rev. 5, pag. 64, section 6.3.2.12 + * [2] CMIS Rev. 5, pag. 115, section 8.2.10, Table 8-15 + */ +static void cmis_show_mod_fault_cause(const struct cmis_memory_map *map) +{ + __u8 mod_state, fault_cause; + + mod_state = (map->lower_memory[CMIS_MODULE_STATE_OFFSET] & + CMIS_MODULE_STATE_MASK) >> 1; + if (mod_state != CMIS_MODULE_STATE_MODULE_FAULT) + return; + + fault_cause = map->lower_memory[CMIS_MODULE_FAULT_OFFSET]; + printf("\t%-41s : 0x%02x", "Module Fault Cause", fault_cause); + switch (fault_cause) { + case CMIS_MODULE_FAULT_NO_FAULT: + printf(" (No fault detected / not supported)\n"); + break; + case CMIS_MODULE_FAULT_TEC_RUNAWAY: + printf(" (TEC runaway)\n"); + break; + case CMIS_MODULE_FAULT_DATA_MEM_CORRUPTED: + printf(" (Data memory corrupted)\n"); + break; + case CMIS_MODULE_FAULT_PROG_MEM_CORRUPTED: + printf(" (Program memory corrupted)\n"); + break; + default: + printf(" (reserved or unknown)\n"); + break; + } +} + static void cmis_parse_dom_power_type(const struct cmis_memory_map *map, struct sff_diags *sd) { @@ -775,6 +843,8 @@ static void cmis_show_all_common(const struct cmis_memory_map *map) cmis_show_link_len(map); cmis_show_vendor_info(map); cmis_show_rev_compliance(map); + cmis_show_mod_state(map); + cmis_show_mod_fault_cause(map); cmis_show_dom(map); } diff --git a/cmis.h b/cmis.h index 310697b0ef32..2c67ad5640ab 100644 --- a/cmis.h +++ b/cmis.h @@ -7,6 +7,15 @@ #define CMIS_MEMORY_MODEL_OFFSET 0x02 #define CMIS_MEMORY_MODEL_MASK 0x80 +/* Global Status Information (Page 0) */ +#define CMIS_MODULE_STATE_OFFSET 0x03 +#define CMIS_MODULE_STATE_MASK 0x0E +#define CMIS_MODULE_STATE_MODULE_LOW_PWR 0x01 +#define CMIS_MODULE_STATE_MODULE_PWR_UP 0x02 +#define CMIS_MODULE_STATE_MODULE_READY 0x03 +#define CMIS_MODULE_STATE_MODULE_PWR_DN 0x04 +#define CMIS_MODULE_STATE_MODULE_FAULT 0x05 + /* Module Flags (Page 0) */ #define CMIS_VCC_AW_OFFSET 0x09 #define CMIS_VCC_LWARN_STATUS 0x80 @@ -27,6 +36,13 @@ #define CMIS_CURR_TEMP_OFFSET 0x0E #define CMIS_CURR_VCC_OFFSET 0x10 +/* Module Fault Information (Page 0) */ +#define CMIS_MODULE_FAULT_OFFSET 0x29 +#define CMIS_MODULE_FAULT_NO_FAULT 0x00 +#define CMIS_MODULE_FAULT_TEC_RUNAWAY 0x01 +#define CMIS_MODULE_FAULT_DATA_MEM_CORRUPTED 0x02 +#define CMIS_MODULE_FAULT_PROG_MEM_CORRUPTED 0x03 + #define CMIS_CTOR_OFFSET 0xCB /* Vendor related information (Page 0) */ From patchwork Tue Nov 23 17:41:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Schimmel X-Patchwork-Id: 12634877 X-Patchwork-Delegate: mkubecek+ethtool@suse.cz Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D032C433FE for ; Tue, 23 Nov 2021 17:41:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239365AbhKWRor (ORCPT ); Tue, 23 Nov 2021 12:44:47 -0500 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:50589 "EHLO out3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239289AbhKWRoq (ORCPT ); Tue, 23 Nov 2021 12:44:46 -0500 Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.nyi.internal (Postfix) with ESMTP id 180BC5C00ED; Tue, 23 Nov 2021 12:41:38 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); 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Tue, 23 Nov 2021 12:41:36 -0500 (EST) From: Ido Schimmel To: netdev@vger.kernel.org Cc: mkubecek@suse.cz, popadrian1996@gmail.com, andrew@lunn.ch, mlxsw@nvidia.com, moshe@nvidia.com, Ido Schimmel Subject: [PATCH ethtool-next 7/8] cmis: Print Module-Level Controls Date: Tue, 23 Nov 2021 19:41:01 +0200 Message-Id: <20211123174102.3242294-8-idosch@idosch.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211123174102.3242294-1-idosch@idosch.org> References: <20211123174102.3242294-1-idosch@idosch.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: mkubecek+ethtool@suse.cz From: Ido Schimmel Print the CMIS Module-Level Controls when dumping EEPROM contents via the '-m' option. It can be used to understand low power mode enforcement by the host. Example output: # ethtool -m swp11 Identifier : 0x18 (QSFP-DD Double Density 8X Pluggable Transceiver (INF-8628)) ... Module State : 0x03 (ModuleReady) LowPwrAllowRequestHW : Off LowPwrRequestSW : Off ... Transmit avg optical power (Channel 1) : 1.3222 mW / 1.21 dBm Transmit avg optical power (Channel 2) : 1.2666 mW / 1.03 dBm Transmit avg optical power (Channel 3) : 1.2860 mW / 1.09 dBm Transmit avg optical power (Channel 4) : 1.2988 mW / 1.14 dBm Transmit avg optical power (Channel 5) : 1.2828 mW / 1.08 dBm Transmit avg optical power (Channel 6) : 1.2913 mW / 1.11 dBm Transmit avg optical power (Channel 7) : 1.2636 mW / 1.02 dBm Transmit avg optical power (Channel 8) : 1.3408 mW / 1.27 dBm Transmit avg optical power (Channel 9) : 1.3222 mW / 1.21 dBm Transmit avg optical power (Channel 10) : 1.2666 mW / 1.03 dBm Transmit avg optical power (Channel 11) : 1.2860 mW / 1.09 dBm Transmit avg optical power (Channel 12) : 1.2988 mW / 1.14 dBm Transmit avg optical power (Channel 13) : 1.2828 mW / 1.08 dBm Transmit avg optical power (Channel 14) : 1.2913 mW / 1.11 dBm Transmit avg optical power (Channel 15) : 1.2636 mW / 1.02 dBm Transmit avg optical power (Channel 16) : 1.3408 mW / 1.27 dBm Rcvr signal avg optical power (Channel 1) : 1.1351 mW / 0.55 dBm Rcvr signal avg optical power (Channel 2) : 1.1603 mW / 0.65 dBm Rcvr signal avg optical power (Channel 3) : 1.1529 mW / 0.62 dBm Rcvr signal avg optical power (Channel 4) : 1.1670 mW / 0.67 dBm Rcvr signal avg optical power (Channel 5) : 1.1759 mW / 0.70 dBm Rcvr signal avg optical power (Channel 6) : 1.1744 mW / 0.70 dBm Rcvr signal avg optical power (Channel 7) : 1.1188 mW / 0.49 dBm Rcvr signal avg optical power (Channel 8) : 1.1640 mW / 0.66 dBm Rcvr signal avg optical power (Channel 9) : 1.1351 mW / 0.55 dBm Rcvr signal avg optical power (Channel 10) : 1.1603 mW / 0.65 dBm Rcvr signal avg optical power (Channel 11) : 1.1529 mW / 0.62 dBm Rcvr signal avg optical power (Channel 12) : 1.1670 mW / 0.67 dBm Rcvr signal avg optical power (Channel 13) : 1.1759 mW / 0.70 dBm Rcvr signal avg optical power (Channel 14) : 1.1744 mW / 0.70 dBm Rcvr signal avg optical power (Channel 15) : 1.1188 mW / 0.49 dBm Rcvr signal avg optical power (Channel 16) : 1.1640 mW / 0.66 dBm # ethtool --set-module swp11 power-mode-policy auto # ethtool -m swp11 Identifier : 0x18 (QSFP-DD Double Density 8X Pluggable Transceiver (INF-8628)) ... Module State : 0x01 (ModuleLowPwr) LowPwrAllowRequestHW : Off LowPwrRequestSW : On ... Transmit avg optical power (Channel 1) : 0.0001 mW / -40.00 dBm Transmit avg optical power (Channel 2) : 0.0001 mW / -40.00 dBm Transmit avg optical power (Channel 3) : 0.0001 mW / -40.00 dBm Transmit avg optical power (Channel 4) : 0.0001 mW / -40.00 dBm Transmit avg optical power (Channel 5) : 0.0001 mW / -40.00 dBm Transmit avg optical power (Channel 6) : 0.0001 mW / -40.00 dBm Transmit avg optical power (Channel 7) : 0.0001 mW / -40.00 dBm Transmit avg optical power (Channel 8) : 0.0001 mW / -40.00 dBm Transmit avg optical power (Channel 9) : 0.0001 mW / -40.00 dBm Transmit avg optical power (Channel 10) : 0.0001 mW / -40.00 dBm Transmit avg optical power (Channel 11) : 0.0001 mW / -40.00 dBm Transmit avg optical power (Channel 12) : 0.0001 mW / -40.00 dBm Transmit avg optical power (Channel 13) : 0.0001 mW / -40.00 dBm Transmit avg optical power (Channel 14) : 0.0001 mW / -40.00 dBm Transmit avg optical power (Channel 15) : 0.0001 mW / -40.00 dBm Transmit avg optical power (Channel 16) : 0.0001 mW / -40.00 dBm Rcvr signal avg optical power (Channel 1) : 0.0001 mW / -40.00 dBm Rcvr signal avg optical power (Channel 2) : 0.0001 mW / -40.00 dBm Rcvr signal avg optical power (Channel 3) : 0.0001 mW / -40.00 dBm Rcvr signal avg optical power (Channel 4) : 0.0001 mW / -40.00 dBm Rcvr signal avg optical power (Channel 5) : 0.0001 mW / -40.00 dBm Rcvr signal avg optical power (Channel 6) : 0.0001 mW / -40.00 dBm Rcvr signal avg optical power (Channel 7) : 0.0001 mW / -40.00 dBm Rcvr signal avg optical power (Channel 8) : 0.0001 mW / -40.00 dBm Rcvr signal avg optical power (Channel 9) : 0.0001 mW / -40.00 dBm Rcvr signal avg optical power (Channel 10) : 0.0001 mW / -40.00 dBm Rcvr signal avg optical power (Channel 11) : 0.0001 mW / -40.00 dBm Rcvr signal avg optical power (Channel 12) : 0.0001 mW / -40.00 dBm Rcvr signal avg optical power (Channel 13) : 0.0001 mW / -40.00 dBm Rcvr signal avg optical power (Channel 14) : 0.0001 mW / -40.00 dBm Rcvr signal avg optical power (Channel 15) : 0.0001 mW / -40.00 dBm Rcvr signal avg optical power (Channel 16) : 0.0001 mW / -40.00 dBm # ethtool --set-module swp11 power-mode-policy high # ethtool -m swp11 Identifier : 0x18 (QSFP-DD Double Density 8X Pluggable Transceiver (INF-8628)) ... Module State : 0x03 (ModuleReady) LowPwrAllowRequestHW : Off LowPwrRequestSW : Off ... Transmit avg optical power (Channel 1) : 1.3690 mW / 1.36 dBm Transmit avg optical power (Channel 2) : 1.3036 mW / 1.15 dBm Transmit avg optical power (Channel 3) : 1.3358 mW / 1.26 dBm Transmit avg optical power (Channel 4) : 1.3509 mW / 1.31 dBm Transmit avg optical power (Channel 5) : 1.3193 mW / 1.20 dBm Transmit avg optical power (Channel 6) : 1.3314 mW / 1.24 dBm Transmit avg optical power (Channel 7) : 1.3042 mW / 1.15 dBm Transmit avg optical power (Channel 8) : 1.3919 mW / 1.44 dBm Transmit avg optical power (Channel 9) : 1.3690 mW / 1.36 dBm Transmit avg optical power (Channel 10) : 1.3036 mW / 1.15 dBm Transmit avg optical power (Channel 11) : 1.3358 mW / 1.26 dBm Transmit avg optical power (Channel 12) : 1.3509 mW / 1.31 dBm Transmit avg optical power (Channel 13) : 1.3193 mW / 1.20 dBm Transmit avg optical power (Channel 14) : 1.3314 mW / 1.24 dBm Transmit avg optical power (Channel 15) : 1.3042 mW / 1.15 dBm Transmit avg optical power (Channel 16) : 1.3919 mW / 1.44 dBm Rcvr signal avg optical power (Channel 1) : 1.1299 mW / 0.53 dBm Rcvr signal avg optical power (Channel 2) : 1.1566 mW / 0.63 dBm Rcvr signal avg optical power (Channel 3) : 1.1484 mW / 0.60 dBm Rcvr signal avg optical power (Channel 4) : 1.1655 mW / 0.67 dBm Rcvr signal avg optical power (Channel 5) : 1.1751 mW / 0.70 dBm Rcvr signal avg optical power (Channel 6) : 1.1595 mW / 0.64 dBm Rcvr signal avg optical power (Channel 7) : 1.1158 mW / 0.48 dBm Rcvr signal avg optical power (Channel 8) : 1.1595 mW / 0.64 dBm Rcvr signal avg optical power (Channel 9) : 1.1299 mW / 0.53 dBm Rcvr signal avg optical power (Channel 10) : 1.1566 mW / 0.63 dBm Rcvr signal avg optical power (Channel 11) : 1.1484 mW / 0.60 dBm Rcvr signal avg optical power (Channel 12) : 1.1655 mW / 0.67 dBm Rcvr signal avg optical power (Channel 13) : 1.1751 mW / 0.70 dBm Rcvr signal avg optical power (Channel 14) : 1.1595 mW / 0.64 dBm Rcvr signal avg optical power (Channel 15) : 1.1158 mW / 0.48 dBm Rcvr signal avg optical power (Channel 16) : 1.1595 mW / 0.64 dBm In the above example, the LowPwrRequestHW signal is ignored and low power mode is controlled via software only. Signed-off-by: Ido Schimmel --- cmis.c | 15 +++++++++++++++ cmis.h | 5 +++++ 2 files changed, 20 insertions(+) diff --git a/cmis.c b/cmis.c index a32cc9f8b1f6..d0b62728e998 100644 --- a/cmis.c +++ b/cmis.c @@ -470,6 +470,20 @@ static void cmis_show_mod_fault_cause(const struct cmis_memory_map *map) } } +/* Print the current Module-Level Controls. Relevant documents: + * [1] CMIS Rev. 5, pag. 58, section 6.3.2.2, Table 6-12 + * [2] CMIS Rev. 5, pag. 111, section 8.2.6, Table 8-10 + */ +static void cmis_show_mod_lvl_controls(const struct cmis_memory_map *map) +{ + printf("\t%-41s : ", "LowPwrAllowRequestHW"); + printf("%s\n", ONOFF(map->lower_memory[CMIS_MODULE_CONTROL_OFFSET] & + CMIS_LOW_PWR_ALLOW_REQUEST_HW_MASK)); + printf("\t%-41s : ", "LowPwrRequestSW"); + printf("%s\n", ONOFF(map->lower_memory[CMIS_MODULE_CONTROL_OFFSET] & + CMIS_LOW_PWR_REQUEST_SW_MASK)); +} + static void cmis_parse_dom_power_type(const struct cmis_memory_map *map, struct sff_diags *sd) { @@ -845,6 +859,7 @@ static void cmis_show_all_common(const struct cmis_memory_map *map) cmis_show_rev_compliance(map); cmis_show_mod_state(map); cmis_show_mod_fault_cause(map); + cmis_show_mod_lvl_controls(map); cmis_show_dom(map); } diff --git a/cmis.h b/cmis.h index 2c67ad5640ab..46797081f13c 100644 --- a/cmis.h +++ b/cmis.h @@ -36,6 +36,11 @@ #define CMIS_CURR_TEMP_OFFSET 0x0E #define CMIS_CURR_VCC_OFFSET 0x10 +/* Module Global Controls (Page 0) */ +#define CMIS_MODULE_CONTROL_OFFSET 0x1A +#define CMIS_LOW_PWR_ALLOW_REQUEST_HW_MASK 0x40 +#define CMIS_LOW_PWR_REQUEST_SW_MASK 0x10 + /* Module Fault Information (Page 0) */ #define CMIS_MODULE_FAULT_OFFSET 0x29 #define CMIS_MODULE_FAULT_NO_FAULT 0x00 From patchwork Tue Nov 23 17:41:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Schimmel X-Patchwork-Id: 12634879 X-Patchwork-Delegate: mkubecek+ethtool@suse.cz Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2BB3C433F5 for ; Tue, 23 Nov 2021 17:41:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239376AbhKWRou (ORCPT ); Tue, 23 Nov 2021 12:44:50 -0500 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:34377 "EHLO out3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239375AbhKWRot (ORCPT ); Tue, 23 Nov 2021 12:44:49 -0500 Received: from compute6.internal (compute6.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id 602955C00F3; Tue, 23 Nov 2021 12:41:40 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute6.internal (MEProxy); Tue, 23 Nov 2021 12:41:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=CwFfsmJrlSpA/jGeMXK/nr7qnI2bWKt+/CIqGoP5O2Q=; b=MoF8qgy0 R7Jru+droGxoFg27DNLiiVX0MynOcJTIp5bHogWkIXmxG9KIUmtvKVbwL1giSDy1 wVTA0axnaS73wgCDi3+BCeFM4pdnCEFeHGPQoIjQAsExBox7AMBJf1IStHDiuPNo S7pEagmZHmQ8QDzP4+zphfULdq7nAQLMc/Vub1cwdbkVpXKX1BiYL9xs7mEWGZpm M5zJWYIRsf/vHRDj9+89nNXwGbWyNAOxg1IqXKp8MCbMqD86ruHpcYdLwTUiA3tt qZDRN4okCBDOqEYH3LE1gZEjn3wVAqFRpTHCx7T60iIgfsjfztzrjCAFD0tBd9eb kj15BafrxgmhCQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvuddrgeeigddutdegucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomhepkfguohcuufgthhhimhhmvghluceoihguohhstghhsehiugho shgthhdrohhrgheqnecuggftrfgrthhtvghrnhepudetieevffffveelkeeljeffkefhke ehgfdtffethfelvdejgffghefgveejkefhnecuvehluhhsthgvrhfuihiivgepfeenucfr rghrrghmpehmrghilhhfrhhomhepihguohhstghhsehiughoshgthhdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 23 Nov 2021 12:41:38 -0500 (EST) From: Ido Schimmel To: netdev@vger.kernel.org Cc: mkubecek@suse.cz, popadrian1996@gmail.com, andrew@lunn.ch, mlxsw@nvidia.com, moshe@nvidia.com, Ido Schimmel Subject: [PATCH ethtool-next 8/8] sff-8636: Print Power set and Power override bits Date: Tue, 23 Nov 2021 19:41:02 +0200 Message-Id: <20211123174102.3242294-9-idosch@idosch.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211123174102.3242294-1-idosch@idosch.org> References: <20211123174102.3242294-1-idosch@idosch.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: mkubecek+ethtool@suse.cz From: Ido Schimmel Print the SFF-8636 Power set and Power override bits when dumping EEPROM contents via the '-m' option. They can be used to understand low power mode enforcement by the host. The 'SFF8636_LOW_PWR_MODE' define is renamed to 'SFF8636_LOW_PWR_SET' to reflect its naming in the standard for QSFP+/QSFP28. Example output: # ethtool -m swp13 Identifier : 0x11 (QSFP28) ... Extended identifier description : 5.0W max. Power consumption, High Power Class (> 3.5 W) enabled Power set : Off Power override : On ... Transmit avg optical power (Channel 1) : 0.7633 mW / -1.17 dBm Transmit avg optical power (Channel 2) : 0.7649 mW / -1.16 dBm Transmit avg optical power (Channel 3) : 0.7696 mW / -1.14 dBm Transmit avg optical power (Channel 4) : 0.7739 mW / -1.11 dBm Rcvr signal avg optical power(Channel 1) : 0.9240 mW / -0.34 dBm Rcvr signal avg optical power(Channel 2) : 0.9129 mW / -0.40 dBm Rcvr signal avg optical power(Channel 3) : 0.9194 mW / -0.36 dBm Rcvr signal avg optical power(Channel 4) : 0.8708 mW / -0.60 dBm # ethtool --set-module swp13 power-mode-policy auto # ethtool -m swp13 Identifier : 0x11 (QSFP28) ... Extended identifier description : 5.0W max. Power consumption, High Power Class (> 3.5 W) not enabled Power set : On Power override : On ... Transmit avg optical power (Channel 1) : 0.0000 mW / -inf dBm Transmit avg optical power (Channel 2) : 0.0000 mW / -inf dBm Transmit avg optical power (Channel 3) : 0.0000 mW / -inf dBm Transmit avg optical power (Channel 4) : 0.0000 mW / -inf dBm Rcvr signal avg optical power(Channel 1) : 0.0000 mW / -inf dBm Rcvr signal avg optical power(Channel 2) : 0.0000 mW / -inf dBm Rcvr signal avg optical power(Channel 3) : 0.0000 mW / -inf dBm Rcvr signal avg optical power(Channel 4) : 0.0000 mW / -inf dBm # ethtool --set-module swp13 power-mode-policy high # ethtool -m swp13 Identifier : 0x11 (QSFP28) ... Extended identifier description : 5.0W max. Power consumption, High Power Class (> 3.5 W) enabled Power set : Off Power override : On ... Transmit avg optical power (Channel 1) : 0.7733 mW / -1.12 dBm Transmit avg optical power (Channel 2) : 0.7754 mW / -1.10 dBm Transmit avg optical power (Channel 3) : 0.7885 mW / -1.03 dBm Transmit avg optical power (Channel 4) : 0.7886 mW / -1.03 dBm Rcvr signal avg optical power(Channel 1) : 0.9248 mW / -0.34 dBm Rcvr signal avg optical power(Channel 2) : 0.9129 mW / -0.40 dBm Rcvr signal avg optical power(Channel 3) : 0.9187 mW / -0.37 dBm Rcvr signal avg optical power(Channel 4) : 0.8785 mW / -0.56 dBm In the above example, the LPMode signal is ignored (Power override is always on) and low power mode is controlled via software only. Signed-off-by: Ido Schimmel --- qsfp.c | 6 ++++++ qsfp.h | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/qsfp.c b/qsfp.c index b3c9e1516af9..57aac86bd5f6 100644 --- a/qsfp.c +++ b/qsfp.c @@ -268,6 +268,12 @@ static void sff8636_show_ext_identifier(const struct sff8636_memory_map *map) printf(" High Power Class (> 3.5 W) enabled\n"); else printf(" High Power Class (> 3.5 W) not enabled\n"); + printf("\t%-41s : ", "Power set"); + printf("%s\n", ONOFF(map->lower_memory[SFF8636_PWR_MODE_OFFSET] & + SFF8636_LOW_PWR_SET)); + printf("\t%-41s : ", "Power override"); + printf("%s\n", ONOFF(map->lower_memory[SFF8636_PWR_MODE_OFFSET] & + SFF8636_PWR_OVERRIDE)); } static void sff8636_show_connector(const struct sff8636_memory_map *map) diff --git a/qsfp.h b/qsfp.h index 1d8f24b5cbc2..aabf09fdc623 100644 --- a/qsfp.h +++ b/qsfp.h @@ -180,7 +180,7 @@ #define SFF8636_PWR_MODE_OFFSET 0x5D #define SFF8636_HIGH_PWR_ENABLE (1 << 2) -#define SFF8636_LOW_PWR_MODE (1 << 1) +#define SFF8636_LOW_PWR_SET (1 << 1) #define SFF8636_PWR_OVERRIDE (1 << 0) #define SFF8636_TX_APP_SELECT_4_OFFSET 0x5E