From patchwork Thu Nov 25 15:38:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Siqueira Jordao X-Patchwork-Id: 12639409 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 49E2EC433EF for ; Thu, 25 Nov 2021 15:39:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8A9BC6E9BA; Thu, 25 Nov 2021 15:39:42 +0000 (UTC) Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2065.outbound.protection.outlook.com [40.107.92.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id B3B206E992; Thu, 25 Nov 2021 15:39:38 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=dUpBRKZo54FChSFWw+VWlW/McE5ffcKaJdDehKnqqjCYYBzczXIRYGRQreDxsU73oUqgnNpeoyD6YkBr2xU2lIj83F5FIq5tjiuSqYefpnVfYW639tdE60ni9pMpdoXSZEuQj0Xd9jbRl844b3rAwfKT71/GFjnpckniCBC3b9LOVB40fjg7TA3xJrXRsXsrkT4Ekc2NJKhewwFPKVMsiMVYzFlsveFUMkwvSBD1C/AFVUBiYiQvyTLIhE+C0B2rEB4RRT+q/EM0X17fwoGUlKzwtNdZjwAMH9Mb9BlA+s7T+qPqn+9mK8gb7i4gDjOG7uZv84YTn29+9WmrYZ8nHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=yxXOWAvojSdU/R7I4G/UDTDnFRo5g7eBPwOIjvjdH3E=; b=eKBnKEqbh5mQiLlutiTGEG60rdb+MO2bBuWP+MHdff1lXP5B35yok418REMXJ6LGaZBaiwyFh8NaMCn2EnWeN10EcdaSkrEqW1EqcP1kM96dWasfxm3E1pzm2JeXq3iSs4+7rDW8QNspX5LWIuZMXm6rnswsq7VxyG/pUs1xSMxypg7Wl0+0xSoBWbSwGRddfHRWh4oJPb0pHPN04FqWADwQhz6lYdozrB6CtrGMFQuyvP4gzgnOMcfghm5bDJ7ga3kFzinAaqpF1F46/ak6NoIh4a8Eq98MpOoGfwHz4zUjp8Ssq8gUp0AlH+NRj5b5nTsTVel9uo66qPxkN+lUPw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=emersion.fr smtp.mailfrom=amd.com; dmarc=bestguesspass action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yxXOWAvojSdU/R7I4G/UDTDnFRo5g7eBPwOIjvjdH3E=; b=yMdn+hT1vZHyId17SDgOGFT0bPEXxolZJ9u2wdpsBiywFYe/+H0I0MryDAuufmqkLCqvPOJbuUKb2MNJZdXWfWi2yCe0IbmTaSQaeOtn2gcn4Wn7B0r5Bydu0zSRP3xWqEL2GfejXanRSo+KuTYvClS76qKPXhRieSobQvg46n0= Received: from BN6PR2001CA0041.namprd20.prod.outlook.com (2603:10b6:405:16::27) by BY5PR12MB4129.namprd12.prod.outlook.com (2603:10b6:a03:213::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.19; Thu, 25 Nov 2021 15:39:35 +0000 Received: from BN8NAM11FT066.eop-nam11.prod.protection.outlook.com (2603:10b6:405:16:cafe::40) by BN6PR2001CA0041.outlook.office365.com (2603:10b6:405:16::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4734.22 via Frontend Transport; Thu, 25 Nov 2021 15:39:35 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT066.mail.protection.outlook.com (10.13.177.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Thu, 25 Nov 2021 15:39:34 +0000 Received: from atma2.hitronhub.home (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 25 Nov 2021 09:39:32 -0600 From: Rodrigo Siqueira To: Simon Ser , =?utf-8?q?Michel_D=C3=A4nzer?= , Bas Nieuwenhuizen , =?utf-8?b?TWFyZWsgT2zFocOhaw==?= , Roman Gilg , Nicholas Kazlauskas , "Harry Wentland" , Mark Yacoub , Sean Paul , Pekka Paalanen Subject: [PATCH 1/6] Documentation/gpu: Reorganize DC documentation Date: Thu, 25 Nov 2021 10:38:25 -0500 Message-ID: <20211125153830.1352994-2-Rodrigo.Siqueira@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125153830.1352994-1-Rodrigo.Siqueira@amd.com> References: <20211125153830.1352994-1-Rodrigo.Siqueira@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c2525242-b58e-4a92-e4a3-08d9b029c808 X-MS-TrafficTypeDiagnostic: BY5PR12MB4129: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1332; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: avAEM1DLeRt+jrsKqaP4vN/nWE1w/pGRK42uwxettnqjIoqkwBAWu207SlesQFxQglR7Ue0VygT3qKoKGKFJmFguOFxMwCkIy8SNa9XCHY3gcCWe3r4JSD4fMEa5xhcrSIKyCOI09ADaf9eDBYdEDUwsIgeQZclXeG1fIWQBOIR8oQSEPfqBDw6zDfBYeuk6NfZFf24ge3uROLV5uZy5/aaV3g1oQcOA4iJ+4rInqdpy83SYyUBiSaZdTlaUZOSWvM0p1uRebWx4a4gGJUuAP6I1Z27jEl+a22pHbw/wbs4mKCz6nSsXDE5PK7VuvAEEV1thVjikFEeYxtK+e9NE+DvsV8mRirPJRRVjYELkb5OLCDg8iXA5+tYcjEY6P6iJe3L6tsZFvC4Dwhz3Pf8oA8c8KfmX8Pl8hz/8hnEjmqp2zOKXxbRfPPyJFuRrVP9ssTff+10AecXQKheeCg5ltcilZEkI08SuPj9PWLciCjpNwmkrijNi7B/5hfWlVHH0zoNB+NJJo4lrgRxbqaz6o+QmegqxyaTL8C/Hn0rNzFuJUsIOcfIcAUb2pkugup/6VcrtOiskwoXkAi2oMJO4v8ntDrAYvrXBbnQKU3AksMneEekpx/OGt7HLexQGi52nB0hC1vVY+Za/hWpaS2UML2W+ljSxXQQT9jiAkAmp9WhJkin46CHLxDb/FBCrp6c+UUzK3Yghk+Ot2TSxhoWdNsO/IVFfRsOuY8DUzVpkyZAO4/6UepH+jNPnF5N4mo1O X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(5660300002)(316002)(4326008)(6666004)(54906003)(921005)(186003)(426003)(86362001)(36860700001)(70586007)(336012)(7416002)(2616005)(83380400001)(81166007)(82310400004)(8676002)(2906002)(1076003)(110136005)(26005)(70206006)(47076005)(508600001)(36756003)(16526019)(8936002)(356005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2021 15:39:34.5359 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c2525242-b58e-4a92-e4a3-08d9b029c808 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT066.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4129 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-doc@vger.kernel.org, qingqing.zhuo@amd.com, roman.li@amd.com, amd-gfx@lists.freedesktop.org, aurabindo.pillai@amd.com, nicholas.choi@amd.com, dri-devel@lists.freedesktop.org, Alex Deucher , bhawanpreet.lakha@amd.com, =?utf-8?q?Christian_K=C3=B6nig?= Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Display core documentation is not well organized, and it is hard to find information due to the lack of sections. This commit reorganizes the documentation layout, and it is preparation work for future changes. Signed-off-by: Rodrigo Siqueira --- Documentation/gpu/amdgpu-dc.rst | 74 ------------------- .../gpu/amdgpu-dc/amdgpu-dc-debug.rst | 4 + Documentation/gpu/amdgpu-dc/amdgpu-dc.rst | 29 ++++++++ Documentation/gpu/amdgpu-dc/amdgpu-dm.rst | 42 +++++++++++ Documentation/gpu/drivers.rst | 2 +- 5 files changed, 76 insertions(+), 75 deletions(-) delete mode 100644 Documentation/gpu/amdgpu-dc.rst create mode 100644 Documentation/gpu/amdgpu-dc/amdgpu-dc-debug.rst create mode 100644 Documentation/gpu/amdgpu-dc/amdgpu-dc.rst create mode 100644 Documentation/gpu/amdgpu-dc/amdgpu-dm.rst diff --git a/Documentation/gpu/amdgpu-dc.rst b/Documentation/gpu/amdgpu-dc.rst deleted file mode 100644 index f7ff7e1309de..000000000000 --- a/Documentation/gpu/amdgpu-dc.rst +++ /dev/null @@ -1,74 +0,0 @@ -=================================== -drm/amd/display - Display Core (DC) -=================================== - -*placeholder - general description of supported platforms, what dc is, etc.* - -Because it is partially shared with other operating systems, the Display Core -Driver is divided in two pieces. - -1. **Display Core (DC)** contains the OS-agnostic components. Things like - hardware programming and resource management are handled here. -2. **Display Manager (DM)** contains the OS-dependent components. Hooks to the - amdgpu base driver and DRM are implemented here. - -It doesn't help that the entire package is frequently referred to as DC. But -with the context in mind, it should be clear. - -When CONFIG_DRM_AMD_DC is enabled, DC will be initialized by default for -supported ASICs. To force disable, set `amdgpu.dc=0` on kernel command line. -Likewise, to force enable on unsupported ASICs, set `amdgpu.dc=1`. - -To determine if DC is loaded, search dmesg for the following entry: - -``Display Core initialized with `` - -AMDgpu Display Manager -====================== - -.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c - :doc: overview - -.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h - :internal: - -Lifecycle ---------- - -.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c - :doc: DM Lifecycle - -.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c - :functions: dm_hw_init dm_hw_fini - -Interrupts ----------- - -.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c - :doc: overview - -.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c - :internal: - -.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c - :functions: register_hpd_handlers dm_crtc_high_irq dm_pflip_high_irq - -Atomic Implementation ---------------------- - -.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c - :doc: atomic - -.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c - :functions: amdgpu_dm_atomic_check amdgpu_dm_atomic_commit_tail - -Display Core -============ - -**WIP** - -FreeSync Video --------------- - -.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c - :doc: FreeSync Video diff --git a/Documentation/gpu/amdgpu-dc/amdgpu-dc-debug.rst b/Documentation/gpu/amdgpu-dc/amdgpu-dc-debug.rst new file mode 100644 index 000000000000..bbb8c3fc8eee --- /dev/null +++ b/Documentation/gpu/amdgpu-dc/amdgpu-dc-debug.rst @@ -0,0 +1,4 @@ +Display Core Debug tools +======================== + +TODO diff --git a/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst b/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst new file mode 100644 index 000000000000..3685b3b1ad64 --- /dev/null +++ b/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst @@ -0,0 +1,29 @@ +=================================== +drm/amd/display - Display Core (DC) +=================================== + +*placeholder - general description of supported platforms, what dc is, etc.* + +Because it is partially shared with other operating systems, the Display Core +Driver is divided in two pieces. + +1. **Display Core (DC)** contains the OS-agnostic components. Things like + hardware programming and resource management are handled here. +2. **Display Manager (DM)** contains the OS-dependent components. Hooks to the + amdgpu base driver and DRM are implemented here. + +It doesn't help that the entire package is frequently referred to as DC. But +with the context in mind, it should be clear. + +When CONFIG_DRM_AMD_DC is enabled, DC will be initialized by default for +supported ASICs. To force disable, set `amdgpu.dc=0` on kernel command line. +Likewise, to force enable on unsupported ASICs, set `amdgpu.dc=1`. + +To determine if DC is loaded, search dmesg for the following entry: + +.. toctree:: + + amdgpu-dm.rst + amdgpu-dc-debug.rst + +``Display Core initialized with `` diff --git a/Documentation/gpu/amdgpu-dc/amdgpu-dm.rst b/Documentation/gpu/amdgpu-dc/amdgpu-dm.rst new file mode 100644 index 000000000000..7ce31f89d9a0 --- /dev/null +++ b/Documentation/gpu/amdgpu-dc/amdgpu-dm.rst @@ -0,0 +1,42 @@ +====================== +AMDgpu Display Manager +====================== + +.. contents:: Table of Contents + :depth: 3 + +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c + :doc: overview + +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h + :internal: + +Lifecycle +========= + +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c + :doc: DM Lifecycle + +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c + :functions: dm_hw_init dm_hw_fini + +Interrupts +========== + +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c + :doc: overview + +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c + :internal: + +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c + :functions: register_hpd_handlers dm_crtc_high_irq dm_pflip_high_irq + +Atomic Implementation +===================== + +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c + :doc: atomic + +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c + :functions: amdgpu_dm_atomic_check amdgpu_dm_atomic_commit_tail diff --git a/Documentation/gpu/drivers.rst b/Documentation/gpu/drivers.rst index b4a0ed3ca961..dffe52d837cd 100644 --- a/Documentation/gpu/drivers.rst +++ b/Documentation/gpu/drivers.rst @@ -5,7 +5,7 @@ GPU Driver Documentation .. toctree:: amdgpu - amdgpu-dc + amdgpu-dc/amdgpu-dc i915 mcde meson From patchwork Thu Nov 25 15:38:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Siqueira Jordao X-Patchwork-Id: 12639411 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8CC7FC4332F for ; Thu, 25 Nov 2021 15:40:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D04BE6E9C6; Thu, 25 Nov 2021 15:39:51 +0000 (UTC) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2057.outbound.protection.outlook.com [40.107.94.57]) by gabe.freedesktop.org (Postfix) with ESMTPS id 78F156E9A9; Thu, 25 Nov 2021 15:39:39 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bGe0m0FZ7O3zNmI1XmVtlOhiOMS6PjWG2KVRjM/j2WD8LJw/yf1grUg6u88ShYCzkh22R9z+/5vUhCrttPssZ0IugqRyCeXHfbfFc1QCVNFvSV2h6jVeYvO3i/PQCUkKJ0S4icze+3NgvxLZzEjhEsEvLiCgBEtl9a4Jdo0QCCMh4R2Ty33zLr5TVo3UrDYLPcaXTBm+/8L2RcFGroiOfPR49pplgeBan/zKub+6A9e42O9h2+oTmB8z6tRSM7551pKa3u4Jsl82HIHHYg/mmxWXyOP32aqJ+oLD7w/1GmWN/Sj0GWjzv7dH6CdG6uOrUrvji3ejMH3yW0U2tB8vxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=8EegBR2Pqnsz+vVOkDV+uJ2XE85pA6KgmjrVhCSPzeo=; b=C66S1QwgSdq7C7N+Vl2wjfdhH/oSyCqYHUMqMpe2oeNrwiq/346DeBRXwpgUNC/siBuxhvhEH8SVkXxiACHI+zegbRFpmRpAIbK+XJ91DDRhNYsvoj84FJzUfLRANw2CbwX3EcEvkvtzIRSiQNNozC9CIXZsORmgsFn/a/gSpTxbVfEQsExO+CE+IuDLH61l6Hmi5dUAcEHgg9068KpYUKB63oaEj3SWDnOaMsLRngDTRZwrdsNaTDPnjFQCQYGieYKotXhsYbWoKpIq1E0GniuD2bx37lVPSe2bh1v5VJFyxYWNkTZqQhfkjI6YLtFRB+779wekJKVcXjB1sPLLag== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=emersion.fr smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=8EegBR2Pqnsz+vVOkDV+uJ2XE85pA6KgmjrVhCSPzeo=; b=k/QER9fBOwzNHBY3bC1g1gWEotUqsGldnS+vHiacWBg0WBGIAyctR3Et9+RN+1h9C8sFYETafCnChe1BvFY8psp+GFbAa8cxdORTiJ4MOUX1Va/AGKN4BSXtjN7oCH5wMSL0ch5klcyXaVS+6a2LTNWvr/eP1qlEzT9egJQCk7o= Received: from BN6PR2001CA0037.namprd20.prod.outlook.com (2603:10b6:405:16::23) by DM8PR12MB5429.namprd12.prod.outlook.com (2603:10b6:8:29::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4734.22; Thu, 25 Nov 2021 15:39:36 +0000 Received: from BN8NAM11FT066.eop-nam11.prod.protection.outlook.com (2603:10b6:405:16:cafe::76) by BN6PR2001CA0037.outlook.office365.com (2603:10b6:405:16::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4734.21 via Frontend Transport; Thu, 25 Nov 2021 15:39:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT066.mail.protection.outlook.com (10.13.177.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Thu, 25 Nov 2021 15:39:36 +0000 Received: from atma2.hitronhub.home (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 25 Nov 2021 09:39:34 -0600 From: Rodrigo Siqueira To: Simon Ser , =?utf-8?q?Michel_D=C3=A4nzer?= , Bas Nieuwenhuizen , =?utf-8?b?TWFyZWsgT2zFocOhaw==?= , Roman Gilg , Nicholas Kazlauskas , "Harry Wentland" , Mark Yacoub , Sean Paul , Pekka Paalanen Subject: [PATCH 2/6] Documentation/gpu: Document amdgpu_dm_visual_confirm debugfs entry Date: Thu, 25 Nov 2021 10:38:26 -0500 Message-ID: <20211125153830.1352994-3-Rodrigo.Siqueira@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125153830.1352994-1-Rodrigo.Siqueira@amd.com> References: <20211125153830.1352994-1-Rodrigo.Siqueira@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 62dcc467-2f5d-4bb5-73c4-08d9b029c90c X-MS-TrafficTypeDiagnostic: DM8PR12MB5429: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3276; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ch+ahmD2RIzRP+6gP/jd/5F1LE9CdUaVSw/h3Zt02xUvQH3sJWEEutH6rM2aABU3plRkCJ9lzCxq6AULOOyuAY9OZ+XI+ETdJjfXtekXenUMIwPur0I1RhuSfI1jbwG0cIrfOpW190ENQu/4TfNdSAvprhEM8K8FhxJ6ND0IRDGjgBjIR4B/j1pejYWmU2PrclJudz9g+jJjTV564T1ngxqoDH/UqfKRohNujLH9YTHpmXNQCuobFRBaOzrdtEVi1LN4M/LyJMZ5uGci9JbRe2xT19uZm82t7tcQ7IwVa2OTGyq4TIwYB/I6PqKYq+8mQFcPP5Mb8t7btnO1cSdR+OsKdvzb271QGTE79R2PDEEZQc0FKDzrsKNgsaMiZf/0B+5PFoHM9fS2at3I+att8MAFockGp6zxnbjyqEgEA9yBWILnytlO1sSR/gcu2jI9e0uo4lNHr6x9N2plmw2oOGD/QAd6oa3SagNeKqCUMFW5WKzHUy8Oxr5nSdUZqrmI/BewPix4OvTLAJxAkMmJOnJ+JRdVnQhuAlyJcsMUNhO0QOodzGAFwRGaDohcfK7/7ZQqdkfKwQI7LuaIATUpsHUHpJYFzcExgb5urFdq4Hm9jMxU9rDnhNpJVCz/IQVc1AJjz4+5ojIjjKv5y794JVAkzw9OXRrhkpDwzHbKnrPAWP5IWZ8050BdoTXnGjLU1T9tRhdS+/jtLQy2+Qn3GbEo54aV9ngBJtdLvPUMb8RkJ5nnXHboHvVTdeZlghuT X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(36860700001)(54906003)(110136005)(426003)(336012)(186003)(2616005)(8936002)(36756003)(6666004)(8676002)(1076003)(316002)(5660300002)(921005)(356005)(70586007)(7416002)(70206006)(86362001)(81166007)(82310400004)(47076005)(508600001)(4326008)(2906002)(16526019)(83380400001)(26005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2021 15:39:36.2380 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 62dcc467-2f5d-4bb5-73c4-08d9b029c90c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT066.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5429 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-doc@vger.kernel.org, qingqing.zhuo@amd.com, roman.li@amd.com, amd-gfx@lists.freedesktop.org, aurabindo.pillai@amd.com, nicholas.choi@amd.com, dri-devel@lists.freedesktop.org, Alex Deucher , bhawanpreet.lakha@amd.com, =?utf-8?q?Christian_K=C3=B6nig?= Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Display core provides a feature that makes it easy for users to debug Multiple planes by enabling a visual notification at the bottom of each plane. This commit introduces how to use such a feature. Signed-off-by: Rodrigo Siqueira --- .../gpu/amdgpu-dc/amdgpu-dc-debug.rst | 34 ++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/Documentation/gpu/amdgpu-dc/amdgpu-dc-debug.rst b/Documentation/gpu/amdgpu-dc/amdgpu-dc-debug.rst index bbb8c3fc8eee..532cbbd64863 100644 --- a/Documentation/gpu/amdgpu-dc/amdgpu-dc-debug.rst +++ b/Documentation/gpu/amdgpu-dc/amdgpu-dc-debug.rst @@ -1,4 +1,36 @@ +======================== Display Core Debug tools ======================== -TODO +DC Debugfs +========== + +Multiple Planes Debug +--------------------- + +If you want to enable or debug multiple planes in a specific user-space +application, you can leverage a debug feature named visual confirm. For +enabling it, you will need:: + + echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm + +You need to reload your GUI to see the visual confirmation. When the plane +configuration changes or a full update occurs there will be a colored bar at +the bottom of each hardware plane being drawn on the screen. + +* The color indicates the format - For example, red is AR24 and green is NV12 +* The height of the bar indicates the index of the plane +* Pipe split can be observed if there are two bars with a difference in height + covering the same plane + +Consider the video playback case in which a video is played in a specific +plane, and the desktop is drawn in another plane. The video plane should +feature one or two green bars at the bottom of the video depending on pipe +split configuration. + +* There should **not** be any visual corruption +* There should **not** be any underflow or screen flashes +* There should **not** be any black screens +* There should **not** be any cursor corruption +* Multiple plane **may** be briefly disabled during window transitions or + resizing but should come back after the action has finished From patchwork Thu Nov 25 15:38:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Siqueira Jordao X-Patchwork-Id: 12639407 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70707C433F5 for ; Thu, 25 Nov 2021 15:39:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E5D6F6E9B9; Thu, 25 Nov 2021 15:39:42 +0000 (UTC) Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2071.outbound.protection.outlook.com [40.107.93.71]) by gabe.freedesktop.org (Postfix) with ESMTPS id 13EC66E992; Thu, 25 Nov 2021 15:39:40 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=X2TtDOPtViimhqQ5Wvg0RcsMwZdFujNq3ORKsWgcbgxFu/tg3Dso7LLSCnnFcea650hXjl9rlLD577QAWG6+knb2M5KI8KsCSpkG3h8+ANlKZQjKkugUepPI4VGv63RRF8923U3bW7eg1pKfJZHxwG3Xy0+abycwMZaLo8GBHcHelV/ttk5naRXsF0UH9WgwB5nEB/9PAzIp7ix4wOobhfnWWa4GVGPfepJWqZNtELDEKmMcYcFtUnyh01ZNuMnXmn9wR/xPZqBFDOVsEOkYbKjlTT1nZ1H64sySFEf6NlBNVHRFxAOeIa5usFEBL31Ka6nDaffHmlKC5ffIpl1nJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0sfyX8rewW8zfLYEzw5yGHmfsHKGuwNnAb2ozuA4XpI=; b=iTh0l2XbrcIy4HSiyKzOa4A3OayF4J2Iyf2KDrFkCgleE3HUTNvV4bKNkjKiOGl6kfsDnRALNx/1e03vVoSIED7GZS9IpHz/f+OOCobC70NdCJK0PrEG5tm1boYlWbUZ2T5+sP0inKZK8XMUt/KIVXVkRUEOB1X9uwMyG+li5WhcP7b7OErQl47DvgN2cLIlmHNU2sPST8u2ig/ro/+1TrVXqwnmgTS3JD4jC0Gy/yUGUrCEu3S+J3+qMX8N15vp3fUjdlI89yKfT0Swpjcs4ahZdXWTj3IqB5BXqffta1JLc+tIrvgCtYtWsM89ReguM0ui6shQK5snVqbLVsai0w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=emersion.fr smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0sfyX8rewW8zfLYEzw5yGHmfsHKGuwNnAb2ozuA4XpI=; b=KGxF4fMSoDOcHk7W2q+yW9aZzNC6ObxMgUg4nHa3GVJu0FdeiINYOgbftF2+TzGVFZdzk1VEtqWi5Bhfg4u2NEsVFiVgdDqC6K96Gwug7mneI67tyvr1WCfFOo9dvbaQQKXUQME5WWSNjm+6VLmjqD+qJ663BUJh4bMp3XK2+ug= Received: from BN0PR02CA0012.namprd02.prod.outlook.com (2603:10b6:408:e4::17) by SJ0PR12MB5405.namprd12.prod.outlook.com (2603:10b6:a03:3af::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.26; Thu, 25 Nov 2021 15:39:37 +0000 Received: from BN8NAM11FT009.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e4:cafe::a) by BN0PR02CA0012.outlook.office365.com (2603:10b6:408:e4::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4734.20 via Frontend Transport; Thu, 25 Nov 2021 15:39:37 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT009.mail.protection.outlook.com (10.13.176.65) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Thu, 25 Nov 2021 15:39:37 +0000 Received: from atma2.hitronhub.home (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 25 Nov 2021 09:39:35 -0600 From: Rodrigo Siqueira To: Simon Ser , =?utf-8?q?Michel_D=C3=A4nzer?= , Bas Nieuwenhuizen , =?utf-8?b?TWFyZWsgT2zFocOhaw==?= , Roman Gilg , Nicholas Kazlauskas , "Harry Wentland" , Mark Yacoub , Sean Paul , Pekka Paalanen Subject: [PATCH 3/6] Documentation/gpu: Document pipe split visual confirmation Date: Thu, 25 Nov 2021 10:38:27 -0500 Message-ID: <20211125153830.1352994-4-Rodrigo.Siqueira@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125153830.1352994-1-Rodrigo.Siqueira@amd.com> References: <20211125153830.1352994-1-Rodrigo.Siqueira@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8327eae1-072c-4e93-a422-08d9b029c9aa X-MS-TrafficTypeDiagnostic: SJ0PR12MB5405: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4125; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Bow3XxMfs14Yv1rhu3k1N8yJG7fpExIGEFQMnx7gCMrIkUFpddbL8jEnkj1S/spvQubDlYV6hxKoPYzD0DnmntiDFqQRZjTMN9Qx5ZAIDneuKJs7y7bB96w7dKd3ExhV8bsbLAL9NN+w50p9KkWoasJhB6gO0UnukVwvaFdIPP/HVMeqO8rmiwZGG46z/I8sll5hAyuo96dsX7FXwlPkBFWjcDvRZNpUoxb5fWxlbA/7gKyda6DgqGIDO8V4ClnDnO6ppYUq0cp8RgxaR5B2kHPKoxUop7slO4OX6oMOmw6LzsVAs5XcUZos+bdYwzXflIyuGfMDlyG1PSavPAuF+G+EXyauCkHFhnxerfj7+08bflubpvX76ewmvzeIDly5sLFGyS6ApJPD4dtANHxtnuIVbZANmNN7QIR7X52xnzLbSHNbaeihIXu9QTQUsSUH5grZYTpIuOj9HL1HKaNpha16x6avV2qhyZD5KZJ93R1imvLUdepX/yinzIdF+Wge9Mtd6B4V+IihrzTgep9VsE9SPlMqyBS7l9razuIkgMWbPYQFcWGBZZE3I2ZwW/u1DkbG3WBz+pU7juMrCYBGUvw0QBOY368Sl1HpeLCUctUlej2e9+MlsDVC+cowxWIJM1acWULptW/QHU5XE6kyJr35VE6aARUjPrccrxW1kN03gclitOKP7jkcA0ValFztxKCMjxL6IW4TNGP10U9tq21UPXQrrZQ7rtIjxQAvGOcDRUrmhfhgkT08RGCYsxay X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(54906003)(110136005)(8936002)(316002)(8676002)(36756003)(2616005)(4326008)(426003)(2906002)(82310400004)(86362001)(1076003)(6666004)(186003)(26005)(16526019)(356005)(921005)(70206006)(5660300002)(508600001)(36860700001)(81166007)(83380400001)(47076005)(7416002)(336012)(70586007)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2021 15:39:37.2747 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8327eae1-072c-4e93-a422-08d9b029c9aa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5405 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-doc@vger.kernel.org, qingqing.zhuo@amd.com, roman.li@amd.com, amd-gfx@lists.freedesktop.org, aurabindo.pillai@amd.com, nicholas.choi@amd.com, dri-devel@lists.freedesktop.org, Alex Deucher , bhawanpreet.lakha@amd.com, =?utf-8?q?Christian_K=C3=B6nig?= Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Display core provides a feature that makes it easy for users to debug Pipe Split. This commit introduces how to use such a debug option. Signed-off-by: Rodrigo Siqueira --- .../gpu/amdgpu-dc/amdgpu-dc-debug.rst | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/Documentation/gpu/amdgpu-dc/amdgpu-dc-debug.rst b/Documentation/gpu/amdgpu-dc/amdgpu-dc-debug.rst index 532cbbd64863..6dbd21f7f59e 100644 --- a/Documentation/gpu/amdgpu-dc/amdgpu-dc-debug.rst +++ b/Documentation/gpu/amdgpu-dc/amdgpu-dc-debug.rst @@ -2,8 +2,18 @@ Display Core Debug tools ======================== -DC Debugfs -========== +DC Visual Confirmation +====================== + +Display core provides a feature named visual confirmation, which is a set of +bars added at the scanout time by the driver to convey some specific +information. In general, you can enable this debug option by using:: + + echo > /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm + +Where `N` is an integer number for some specific scenarios that the developer +wants to enable, you will see some of these debug cases in the following +subsection. Multiple Planes Debug --------------------- @@ -34,3 +44,17 @@ split configuration. * There should **not** be any cursor corruption * Multiple plane **may** be briefly disabled during window transitions or resizing but should come back after the action has finished + +Pipe Split Debug +---------------- + +Sometimes we need to debug if DCN is splitting pipes correctly, and visual +confirmation is also handy for this case. Similar to the MPO case, you can use +the below command to enable visual confirmation:: + + echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm + +In this case, if you have a pipe split, you will see one small red bar at the +bottom of the display covering the entire display width and another bar +covering the second pipe. In other words, you will see a bit high bar in the +second pipe. From patchwork Thu Nov 25 15:38:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Siqueira Jordao X-Patchwork-Id: 12639413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CF9B7C433F5 for ; Thu, 25 Nov 2021 15:40:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1224D6E9CC; Thu, 25 Nov 2021 15:39:53 +0000 (UTC) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2089.outbound.protection.outlook.com [40.107.223.89]) by gabe.freedesktop.org (Postfix) with ESMTPS id 18B736E9C1; Thu, 25 Nov 2021 15:39:45 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=l+Av/UcDEVPDsO360MRAWm0ua+mw46g7y2DN03CWXCOE2i+kdk96x1itElVB4PFEPginSFLR6h6/rVGlZfqEygBXv62fdSVk13CYGvnIMHGx+uKLyXSXsAchZ2mcRWGkcImZNkP6NudrUKhp2lP9/yTT5D6IgqoXVmjrKD9JBFYmVahkrlqbBBadh7jgiwkQzQzT80aBIIpYCsRLNL0lGiEmdN5RuoCbSemBLGIora1EEejfmuEOHigd0rafogeGEzk4CXYkvmi4wUT8t1nbuEk/Bbzj+77YOFlv6RxMdjUXovYJFJSbNjrRJ4kHp5k6tLgmFNQzFFy0RcMpDtBlgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hirdCUpasD1Ja3Y761A6BiDeNyQ2OYHYPTJT4Ggah3g=; b=gxDUpqImWmUQ/Wsm6SMY2+FsVg569V6KWS766hL95+6+OTH7qKJCt+/Bo2pZS2pPtpzyEyCxqTPNi+iuSb3AjLftO0nTVOfR3OFM4zXnJHGj28pUWs2bquT5pkSFK5GFysSVWDJUp42hPZzb/g+XnF5yF/ZGYQh3iobtaEfuSpyIZtwC2Bya2KHNje5G7nijIE6LoUcKvX5RGYnjz3SFvrV7vZDTLa1bZuj/KlLX3qzkFKX05DCw3JeRfoiuZ2ilDj7vofnjYBevVVD/sQaBfKipHOHrU6RFPrtOWp0d2NSLOBXZq5Fk5Xnp9e0EGgMe8b2hVn6PoM0boe5GnmThSA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=emersion.fr smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hirdCUpasD1Ja3Y761A6BiDeNyQ2OYHYPTJT4Ggah3g=; b=Ynq3NcldpF8DYd6mCHYj/AAQ0jrXldxf2FlENhvh4sCPpCmby4qp3weeux2B7z2YyI1Tz+gQDUO0r/7coM6/zqKiKASjk99fJzSIhDNo0k/YNzmJH6bMUMNtAbeDxX7FKKBeulh21Xb+iODGEtcldcUH9EXFwXwmPgSNrUOR88s= Received: from BN6PR12CA0042.namprd12.prod.outlook.com (2603:10b6:405:70::28) by MN2PR12MB4456.namprd12.prod.outlook.com (2603:10b6:208:266::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.19; Thu, 25 Nov 2021 15:39:38 +0000 Received: from BN8NAM11FT063.eop-nam11.prod.protection.outlook.com (2603:10b6:405:70:cafe::50) by BN6PR12CA0042.outlook.office365.com (2603:10b6:405:70::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.22 via Frontend Transport; Thu, 25 Nov 2021 15:39:38 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT063.mail.protection.outlook.com (10.13.177.110) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Thu, 25 Nov 2021 15:39:38 +0000 Received: from atma2.hitronhub.home (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 25 Nov 2021 09:39:36 -0600 From: Rodrigo Siqueira To: Simon Ser , =?utf-8?q?Michel_D=C3=A4nzer?= , Bas Nieuwenhuizen , =?utf-8?b?TWFyZWsgT2zFocOhaw==?= , Roman Gilg , Nicholas Kazlauskas , "Harry Wentland" , Mark Yacoub , Sean Paul , Pekka Paalanen Subject: [PATCH 4/6] Documentation/gpu: How to collect DTN log Date: Thu, 25 Nov 2021 10:38:28 -0500 Message-ID: <20211125153830.1352994-5-Rodrigo.Siqueira@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125153830.1352994-1-Rodrigo.Siqueira@amd.com> References: <20211125153830.1352994-1-Rodrigo.Siqueira@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ad29d254-8130-40dc-ebb2-08d9b029ca7d X-MS-TrafficTypeDiagnostic: MN2PR12MB4456: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4RB6himl+VgJvmO/SOtRtiruL2F8I0R5W9cFEckXAkEwcBntV/2CSOvqIxFaQYYfSezujDRS7lwzPvJ+jnNOJ3DElK9QAGRGnYXYvirl89p6MEdJcOvOUaKgniNpEsgRBKbsQSZS7OiLerGxLn9vhoP+Tzos7tqL+ubXQiKMVAZYodmANeVWLFHVn4VPWkXBG58iy3BtebkxegJwt3VW79mulxVZrYW+IS+0I2HHZhLBFg15Luz/ZKJmb1QOjjXe2rDOuDLvHi8MN4YLXxXm6ODWO2PhDmz6ZkpXYvwmNc+DdKQR72JUjrjFw6zsQvl92aIoMf+fu8oVwmxQoP/WngYqbzsM7M+6wh7RxdA3pPapVgpvRRpIoZEDrp8b8urOGrB8FGK8wGU/kZboYnpBEQ9xI39AsETRDKAV45KvrCWL6iuVhFhcMmWDTFhbQ2/IISFz7oQQ7rZ1Jbf1CQfpMCHWl1/vMxpqR/nDb981qdb28ec0q8l/1ob2WoT0tiwHFIgQwu11MZQ106cDEIDeujYrmamQjaCKwQ22/8v2oDEFSkAZ/lna/E8S1EtLQlBL9E9iPrikvvJiieCUqc5RlTOIe9iMtNZ5B9BnhvDqzBrINIj5YSq/b8drpdSkg3udXuUjYEoBcCYWUZKfRRQ1aZplkvvbW1qbWo1RMIEg1SATR4RDwWJSrpHXaHL2Ji7VyVHIodfb3onwRJZApIJpPFgUmm2Tlsc/entTh0u2Y3q7a8jfTNcHsG6nY7q/7p+i X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(82310400004)(47076005)(70206006)(316002)(2616005)(36860700001)(86362001)(4326008)(16526019)(6666004)(921005)(186003)(26005)(426003)(8936002)(5660300002)(1076003)(70586007)(2906002)(36756003)(81166007)(508600001)(54906003)(83380400001)(7416002)(356005)(8676002)(336012)(110136005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2021 15:39:38.6593 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ad29d254-8130-40dc-ebb2-08d9b029ca7d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4456 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-doc@vger.kernel.org, qingqing.zhuo@amd.com, roman.li@amd.com, amd-gfx@lists.freedesktop.org, aurabindo.pillai@amd.com, nicholas.choi@amd.com, dri-devel@lists.freedesktop.org, Alex Deucher , bhawanpreet.lakha@amd.com, =?utf-8?q?Christian_K=C3=B6nig?= Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Introduce how to collect DTN log from debugfs. Signed-off-by: Rodrigo Siqueira --- Documentation/gpu/amdgpu-dc/amdgpu-dc-debug.rst | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/gpu/amdgpu-dc/amdgpu-dc-debug.rst b/Documentation/gpu/amdgpu-dc/amdgpu-dc-debug.rst index 6dbd21f7f59e..40c55a618918 100644 --- a/Documentation/gpu/amdgpu-dc/amdgpu-dc-debug.rst +++ b/Documentation/gpu/amdgpu-dc/amdgpu-dc-debug.rst @@ -58,3 +58,20 @@ In this case, if you have a pipe split, you will see one small red bar at the bottom of the display covering the entire display width and another bar covering the second pipe. In other words, you will see a bit high bar in the second pipe. + +DTN Debug +========= + +DC (DCN) provides an extensive log that dumps multiple details from our +hardware configuration. Via debugfs, you can capture those status values by +using Display Test Next (DTN) log, which can be captured via debugfs by using:: + + cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log + +Since this log is updated accordingly with DCN status, you can also follow the +change in real-time by using something like:: + + sudo watch -d cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log + +When reporting a bug related to DC, consider attaching this log before and +after you reproduce the bug. From patchwork Thu Nov 25 15:38:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Siqueira Jordao X-Patchwork-Id: 12639417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4538AC433F5 for ; Thu, 25 Nov 2021 15:40:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 61EA46E9EE; Thu, 25 Nov 2021 15:39:53 +0000 (UTC) Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam08on2058.outbound.protection.outlook.com [40.107.102.58]) by gabe.freedesktop.org (Postfix) with ESMTPS id 224646EA09; Thu, 25 Nov 2021 15:39:46 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Dr67slwP75gorn+vhurzu7alq20x1qAkK1klWpD9YVkQucILjJtvGmao6XiaMJewfuz+1emjWsJs/iG5q0wHKhk06qFRhzm5AnRfUmvqnKDKMHS0epOwClahOcfSjmkAVXr162pcSP+G0wnQvOYek9LQV7CArvHG6QcnzXA3m5Q+IpS+8GNDs1HGjC1kJ9IkO93TKomJB01lkcbhLBz8ilLBjOf+YdsoQucP6aNPU+Qc8FS2evN/6cm/ByS1/IsBZ6HV6jsKwT8mOTWszrfLcwQAMciiv3shE0gy/m4qYkim51PQpImRl5yeimtdqXk/EhdhBnkZKPwi2J7xWoVX0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6IRU5XVBoB2ckYgrNalUU6mjHxIxY7qzdnVx6FS6Gbg=; b=JG5wQpv4TYcSWyIUJIzKLG2EnniSP+UBEcXSH8ppdjbL/LnWcQwE3UTjLxzED5n/RGHgRzqbTWCnu4IYMlLp5LC8N/MEECnN2F6RHoZK5m6pMA6pbeW/lRb0bNX+21/R80GL9qF7bQKRY199g3tkbS8YTwOjZDpWFkn2UJzxxZKTAwZgb2/ouRMdESLkBsgn+/PLuOaO+oYz3FtOOuKxeVE1U6Y7AWsKdcONlUMIRGwfoQe+F3Tf1LbgVVs53NFyvME76xLInpqxdCgzOoaJVS6kOohftxS4yNPcAqCU75o/hHBZ7M3MKq+AkKiL/ip5Fx48c3NvncrrJtEdN/pGhw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=emersion.fr smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6IRU5XVBoB2ckYgrNalUU6mjHxIxY7qzdnVx6FS6Gbg=; b=3vUeQjIrEQ8Y+nwwEGRWd11zZf6e22kA8yD4+y8NFqtr4YtUnbjggmsaWsSy6rvusA5TOEEuwBH0cQAoakBHylSzqnObTOn59htMgr8fsyFDuHR1EIhXN85gxfh3uC7gesvGSpufcnXgWgDIVE8VTcCEU4Db3Ux5Se/9ncj+tPw= Received: from BN0PR04CA0201.namprd04.prod.outlook.com (2603:10b6:408:e9::26) by DM5PR12MB1417.namprd12.prod.outlook.com (2603:10b6:3:73::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4734.22; Thu, 25 Nov 2021 15:39:40 +0000 Received: from BN8NAM11FT052.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e9:cafe::c8) by BN0PR04CA0201.outlook.office365.com (2603:10b6:408:e9::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.21 via Frontend Transport; Thu, 25 Nov 2021 15:39:40 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT052.mail.protection.outlook.com (10.13.177.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Thu, 25 Nov 2021 15:39:40 +0000 Received: from atma2.hitronhub.home (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 25 Nov 2021 09:39:38 -0600 From: Rodrigo Siqueira To: Simon Ser , =?utf-8?q?Michel_D=C3=A4nzer?= , Bas Nieuwenhuizen , =?utf-8?b?TWFyZWsgT2zFocOhaw==?= , Roman Gilg , Nicholas Kazlauskas , "Harry Wentland" , Mark Yacoub , Sean Paul , Pekka Paalanen Subject: [PATCH 5/6] Documentation/gpu: Add basic overview of DC pipeline Date: Thu, 25 Nov 2021 10:38:29 -0500 Message-ID: <20211125153830.1352994-6-Rodrigo.Siqueira@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125153830.1352994-1-Rodrigo.Siqueira@amd.com> References: <20211125153830.1352994-1-Rodrigo.Siqueira@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d6694c28-d113-4655-468c-08d9b029cbb8 X-MS-TrafficTypeDiagnostic: DM5PR12MB1417: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 1pJzDDh8XS5zoie6xO0DKOSroq3foywhk9qCuhQ3MjqVNyvLN1gpB5uZhCQYSiUBVRvyiARYOVNEebNjnVUx05bCHQqnuDe8L0ple0kPmHq/U7fIyMV1Tz6Et1tsvuSUO/fr4P3vrrw/Vfwz2H1eNxv7n14KI0aRPF5liqtyVif2CBkF7IlJofFbYFzedsQDE669CWcYDZFGJDvE8sdSFFkai0fKn1GC+xvPP2dNIeAnqMh/DH1XjeSWShwxDQnD0iV5835D1bnl1ytJESq+ViU9hJeIY/WZwQRLY1NerIrX29oxIVxphjVbws7Rtt1SJq0+LDL9+oCtBRjq6b+76wxL1p5OIB9aDrgDFcs/lWzUfA2P3tHhfYBDk6wPm5pGrll7f2wa4xe18VMqUa05OSgfHvjo4OtlHApbG5Mt6LSAYvVZb0oi5BNM1NlUfwGcTLtuWzwH5dQxOjPsXDBu+EBuinBXvyN52Mv628wJ4pNdrrwNhmXgs10jD0BTHdMWgJ8HHMWGHcUe9VGBBrqn32O4rwdDnasMSd7I9Hm3L47EdcYtRTgNlg6sHWxUnYD4pm5fXIqRMEXHl8gRnFxI01b7McM29pqmoDr9DzyopRC0YwMA0qM9gDSS1cTsLfp7F61vcLwyrXfZXq0bGe72P1jDLvetMPrMo8nVYNvZq9G9GAAso3QYiqUgLl+4ZOhfv33UNmz2bg2wS1yZLN7WWw/bbpGs0LOTuhndARKlpxMxgIM9kY4muEi3celJQ3Bb8/38F1ZlZM6N1a0AuJf/dsQEeL5IU4z0TsTc7jcZNyAKAzQlgn0sjw7GdnTCe2RrYw+M6ji2S4RSs4t9t6cCeQnZ2+jsRWBx3xQv/jx8UCCUCMDFqJd0U+sIEAjT+BhTn9CKHq2ECdZ88IUvFN7wZw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(82310400004)(426003)(36860700001)(86362001)(7416002)(83380400001)(5660300002)(16526019)(508600001)(47076005)(30864003)(186003)(36756003)(336012)(2616005)(4326008)(356005)(70586007)(26005)(2906002)(19273905006)(8676002)(70206006)(81166007)(6666004)(316002)(8936002)(1076003)(921005)(54906003)(110136005)(36900700001)(579004)(559001)(563064011); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2021 15:39:40.7185 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d6694c28-d113-4655-468c-08d9b029cbb8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT052.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1417 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-doc@vger.kernel.org, qingqing.zhuo@amd.com, roman.li@amd.com, amd-gfx@lists.freedesktop.org, aurabindo.pillai@amd.com, nicholas.choi@amd.com, dri-devel@lists.freedesktop.org, Alex Deucher , bhawanpreet.lakha@amd.com, =?utf-8?q?Christian_K=C3=B6nig?= Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This commit describes how DCN works by providing high-level diagrams with an explanation of each component. In particular, it details the Global Sync signals. Signed-off-by: Rodrigo Siqueira --- Documentation/gpu/amdgpu-dc/amdgpu-dc.rst | 22 +- .../gpu/amdgpu-dc/amdgpu-dcn-overview.rst | 168 +++ .../gpu/amdgpu-dc/config_example.svg | 414 ++++++ .../gpu/amdgpu-dc/dc_pipeline_overview.svg | 1125 +++++++++++++++++ .../gpu/amdgpu-dc/global_sync_vblank.svg | 485 +++++++ 5 files changed, 2203 insertions(+), 11 deletions(-) create mode 100644 Documentation/gpu/amdgpu-dc/amdgpu-dcn-overview.rst create mode 100644 Documentation/gpu/amdgpu-dc/config_example.svg create mode 100644 Documentation/gpu/amdgpu-dc/dc_pipeline_overview.svg create mode 100644 Documentation/gpu/amdgpu-dc/global_sync_vblank.svg diff --git a/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst b/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst index 3685b3b1ad64..2e45e83d9a2a 100644 --- a/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst +++ b/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst @@ -2,28 +2,28 @@ drm/amd/display - Display Core (DC) =================================== -*placeholder - general description of supported platforms, what dc is, etc.* - -Because it is partially shared with other operating systems, the Display Core -Driver is divided in two pieces. +AMD display engine is partially shared with other operating systems; for this +reason, our Display Core Driver is divided into two pieces: 1. **Display Core (DC)** contains the OS-agnostic components. Things like hardware programming and resource management are handled here. 2. **Display Manager (DM)** contains the OS-dependent components. Hooks to the amdgpu base driver and DRM are implemented here. -It doesn't help that the entire package is frequently referred to as DC. But -with the context in mind, it should be clear. +The display pipe is responsible for "scanning out" a rendered frame from the +GPU memory (also called VRAM, FrameBuffer, etc.) to a display. In other words, +it would: -When CONFIG_DRM_AMD_DC is enabled, DC will be initialized by default for -supported ASICs. To force disable, set `amdgpu.dc=0` on kernel command line. -Likewise, to force enable on unsupported ASICs, set `amdgpu.dc=1`. +1. Read frame information from memory; +2. Perform required transformation; +3. Send pixel data to sink devices. -To determine if DC is loaded, search dmesg for the following entry: +If you want to learn more about our driver details, take a look at the below +table of content: .. toctree:: + amdgpu-dcn-overview.rst amdgpu-dm.rst amdgpu-dc-debug.rst -``Display Core initialized with `` diff --git a/Documentation/gpu/amdgpu-dc/amdgpu-dcn-overview.rst b/Documentation/gpu/amdgpu-dc/amdgpu-dcn-overview.rst new file mode 100644 index 000000000000..47e9a70de8ae --- /dev/null +++ b/Documentation/gpu/amdgpu-dc/amdgpu-dcn-overview.rst @@ -0,0 +1,168 @@ +======================= +Display Core Next (DCN) +======================= + +To equip our readers with the basic knowledge of how AMD Display Core Next +(DCN) works, we need to start with an overview of the hardware pipeline. Below +you can see a picture that provides a DCN overview, keep in mind that this is a +generic diagram, and we have variations per ASIC. + +.. kernel-figure:: dc_pipeline_overview.svg + +Based on this diagram, we can pass through each block and briefly describe +them: + +* **Display Controller Hub (DCHUB)**: This is the gateway between the Scalable + Data Port (SDP) and DCN. This component has multiple features, such as memory + arbitration, rotation, and cursor manipulation. + +* **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel + processing such as color space conversion, linearization of pixel data, tone + mapping, and gamut mapping. + +* **Multiple Pipe/Plane Combined (MPC)**: This component performs blending of + multiple planes, using global or per-pixel alpha. + +* **Output Pixel Processing (OPP)**: Process and format pixels to be sent to + the display. + +* **Output Pipe Timing Combiner (OPTC)**: It generates time output to combine + streams or divide capabilities. CRC values are generated in this block. + +* **Display Output (DIO)**: Codify the output to the display connected to our + GPU. + +* **Display Writeback (DWB)**: It provides the ability to write the output of + the display pipe back to memory as video frames. + +* **DCN Management Unit (DMU)**: It provides registers with access control and + interrupts the controller to the SOC host interrupt unit. This block includes + the Display Micro-Controller Unit - version B (DMCUB), which is handled via + firmware. + +* **DCN Clock Generator Block (DCCG)**: It provides the clocks and resets + for all of the display controller clock domains. + +* **Azalia (AZ)**: Audio engine. + +The above diagram is an architecture generalization of DCN, which means that +every ASIC has variations around this base model. Notice that the display +pipeline is connected to the Scalable Data Port (SDP) via DCHUB; you can see +the SDP as the element from our Data Fabric that feeds the display pipe. + +Always approach the DCN architecture as something flexible that can be +configured and reconfigured in multiple ways; in other words, each block can be +setup or ignored accordingly with userspace demands. For example, if we +want to drive an 8k@60Hz with a DSC enabled, our DCN may require 4 DPP and 2 +OPP. It is DC's responsibility to drive the best configuration for each +specific scenario. Orchestrate all of these components together requires a +sophisticated communication interface which is highlighted in the diagram by +the edges that connect each block; from the chart, each connection between +these blocks represents: + +1. Pixel data interface (red): Represents the pixel data flow; +2. Global sync signals (green): It is a set of synchronization signals composed + by VStartup, VUpdate, and VReady; +3. Config interface: Responsible to configure blocks; +4. Sideband signals: All other signals that do not fit the previous one. + +These signals are essential and play an important role in DCN. Nevertheless, +the Global Sync deserves an extra level of detail described in the next +section. + +All of these components are represented by a data structure named dc_state. +From DCHUB to MPC, we have a representation called dc_plane; from MPC to OPTC, +we have dc_stream, and the output (DIO) is handled by dc_link. Keep in mind +that HUBP accesses a surface using a specific format read from memory, and our +dc_plane should work to convert all pixels in the plane to something that can +be sent to the display via dc_stream and dc_link. + +Front End and Back End +---------------------- + +Display pipeline can be broken down into two components that are usually +referred as **Front End (FE)** and **Back End (BE)**, where FE consists of: + +* DCHUB (Mainly referring to a subcomponent named HUBP) +* DPP +* MPC + +On the other hand, BE consist of + +* OPP +* OPTC +* DIO (DP/HDMI stream encoder and link encoder) + +OPP and OPTC are two joining blocks between FE and BE. On a side note, this is +a one-to-one mapping of the link encoder to PHY, but we can configure the DCN +to choose which link encoder to connect to which PHY. FE's main responsibility +is to change, blend and compose pixel data, while BE's job is to frame a +generic pixel stream to a specific display's pixel stream. + +Data Flow +--------- + +Initially, data is passed in from VRAM through Data Fabric (DF) in native pixel +formats. Such data format stays through till HUBP in DCHUB, where HUBP unpacks +different pixel formats and outputs them to DPP in uniform streams through 4 +channels (1 for alpha + 3 for colors). + +The Converter and Cursor (CNVC) in DPP would then normalize the data +representation and convert them to a DCN specific floating-point format (i.e., +different from the IEEE floating-point format). In the process, CNVC also +applies a degamma function to transform the data from non-linear to linear +space to relax the floating-point calculations following. Data would stay in +this floating-point format from DPP to OPP. + +Starting OPP, because color transformation and blending have been completed +(i.e alpha can be dropped), and the end sinks do not require the precision and +dynamic range that floating points provide (i.e. all displays are in integer +depth format), bit-depth reduction/dithering would kick in. In OPP, we would +also apply a regamma function to introduce the gamma removed earlier back. +Eventually, we output data in integer format at DIO. + +Global Sync +----------- + +Many DCN registers are double buffered, most importantly the surface address. +This allows us to updated DCN hardware atomically for page flips, as well as +for most other updates that don't require enabling or disabling of new pipes. + +(Note: There are many scenarios when DC will decide to reserve extra pipes +in order to support outputs that need a very high pixel clock, or for +power saving purposes.) + +These atomic register updates are driven by global sync signals in DCN. In +order to understand how atomic updates interact with DCN hardware, and how DCN +signals page flip and vblank events it is helpful to understand how global sync +is programmed. + +Global sync consists of three signals, VSTARTUP, VUPDATE, and VREADY. These are +calculated by the Display Mode Library - DML (drivers/gpu/drm/amd/display/dc/dml) +based on a large number of parameters and ensure our hardware is able to feed +the DCN pipeline without underflows or hangs in any given system configuration. +The global sync signals always happen during VBlank, are independent from the +VSync signal, and do not overlap each other. + +VUPDATE is the only signal that is of interest to the rest of the driver stack +or userspace clients as it signals the point at which hardware latches to +atomically programmed (i.e. double buffered) registers. Even though it is +independent of the VSync signal we use VUPDATE to signal the VSync event as it +provides the best indication of how atomic commits and hardware interact. + +Since DCN hardware is double-buffered the DC driver is able to program the +hardware at any point during the frame. + +The below picture illustrates the global sync signals: + +.. kernel-figure:: global_sync_vblank.svg + +These signals affect core DCN behavior. Programming them incorrectly will lead +to a number of negative consequences, most of them quite catastrophic. + +The following picture shows how global sync allows for a mailbox style of +updates, i.e. it allows for multiple re-configurations between VUpdate +events where only the last configuration programmed before the VUpdate signal +becomes effective. + +.. kernel-figure:: config_example.svg diff --git a/Documentation/gpu/amdgpu-dc/config_example.svg b/Documentation/gpu/amdgpu-dc/config_example.svg new file mode 100644 index 000000000000..cdac9858601c --- /dev/null +++ b/Documentation/gpu/amdgpu-dc/config_example.svg @@ -0,0 +1,414 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + Configurations + A + B + C + + + + + + A + B + C + C + Old config + Old config + + + VUpdate + UpdateLock + Register updatePending Status + Buf 0 + Buf 1 + + diff --git a/Documentation/gpu/amdgpu-dc/dc_pipeline_overview.svg b/Documentation/gpu/amdgpu-dc/dc_pipeline_overview.svg new file mode 100644 index 000000000000..9adecebfe65b --- /dev/null +++ b/Documentation/gpu/amdgpu-dc/dc_pipeline_overview.svg @@ -0,0 +1,1125 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + DCHUB + HUBP(n) + + + DPP(n) + + + + MPC + + + + OPTC + + + + DIO + + + + DCCG + + + + DMU + + + + + AZ + + + + MMHUBBUB + + + + DWB(n) + + + + + + + + + + + + + Global sync + Pixel data + Sideband signal + Config. Bus + + SDP + + Monitor + + OPP + + + + + + + + + + + + + dc_plane + dc_stream + + + + dc_state + + + + Code struct + + + + dc_link + + + + Floating pointcalculation + + + + bit-depthreduction/dither + } + Notes + + diff --git a/Documentation/gpu/amdgpu-dc/global_sync_vblank.svg b/Documentation/gpu/amdgpu-dc/global_sync_vblank.svg new file mode 100644 index 000000000000..48f5dc4fd5d3 --- /dev/null +++ b/Documentation/gpu/amdgpu-dc/global_sync_vblank.svg @@ -0,0 +1,485 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + To + VStartup Period + VUpdateWidth + VReadyOffset + VUpdateOffset + VSTARTUP_START + VSYNC + VBlank + VStartup + VUpdate + VReady + + + + + + + + + + From patchwork Thu Nov 25 15:38:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Siqueira Jordao X-Patchwork-Id: 12639415 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56551C433FE for ; Thu, 25 Nov 2021 15:40:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 33FDA6E9E5; Thu, 25 Nov 2021 15:39:54 +0000 (UTC) Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam08on2049.outbound.protection.outlook.com [40.107.102.49]) by gabe.freedesktop.org (Postfix) with ESMTPS id 56DDB6EA46; Thu, 25 Nov 2021 15:39:47 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=gmKWtdgXafL8ElFrvAiQlYCzNA0rdajP7vq5NgnvzPBemEFvsp3d67Djr1Zv77hfJ+3b1SSfuGqY1gULrnjqor52Csbj9lO2XPbgD3KJ8L4omDhL5wN/dGWmYYgakx1GsBgjAGquVAddnsWyde0YHqnigLW55PyrOO8g1jz2KZ1caK9yb7tZmlfSuoLTkot3zmDw2n5mMaX6ADBiOHpXFHxw5c/u5cC5x4Uh59YU1ZS2MiGU3bp5o8AegqT6ul4P6GfHzPPhgb1n70rlZ3GcNjR5XAY2q/pgxf/gDbSVoNXFOw+xw0sXD/Lt4/yvQB59H9F4bbd09B1vI9Bl7sWKCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=teXe7xsG9s3DyEDrBq7uUgxzUFjwEwKXcwGZV8sHmJs=; b=TUKzoysPBE1iFhHd638cvhzXpnm0AhRUA6xm3n8aETS/bzvzDJ/vdOsQroIlk5wZ4A5EbIGbvAlrP3fFQhFReUCW7xzgn60HlAzvkAM3NdU/wsfFS1oDDh8ljhq7HlT3Wtoeq0KnwRPw/sYmUdO43xL6y2na9l8FihHwaoioc7j2mKBCtAHlZ37GENcfjsqx8yFM5Xi3B8r8K1yE3ocgdeRzWLxT0dFnbhRTW0O5P0QwREGG25dpuQhtYLLw7ZfsprtLeMng8zwyaelbyxSZZotA6Tn1xX4DPuDAAXMRdvo/4RN2LuajsOXlz+wToQWbL93BOawQ/lyIStoi8PkZwg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=emersion.fr smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=teXe7xsG9s3DyEDrBq7uUgxzUFjwEwKXcwGZV8sHmJs=; b=gWV/+Iu7FryLVYdv/mMtpfyrzzwPpzCiHFIvBCI1sONQA41sYVp+mf8HdfZUhNFUeH/I/jYTBqqtUCqWhuV2C9o5hCUUtgTplizTrNabjm1IuoNL1tKgdou2Dhryq5K5mAKuAZEGjG/eVkFJoUtQnLq8j0kI/xe1toy0hPn53nI= Received: from BN9P221CA0006.NAMP221.PROD.OUTLOOK.COM (2603:10b6:408:10a::33) by BN8PR12MB3521.namprd12.prod.outlook.com (2603:10b6:408:9f::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4734.20; Thu, 25 Nov 2021 15:39:41 +0000 Received: from BN8NAM11FT048.eop-nam11.prod.protection.outlook.com (2603:10b6:408:10a:cafe::63) by BN9P221CA0006.outlook.office365.com (2603:10b6:408:10a::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4734.23 via Frontend Transport; Thu, 25 Nov 2021 15:39:41 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT048.mail.protection.outlook.com (10.13.177.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Thu, 25 Nov 2021 15:39:41 +0000 Received: from atma2.hitronhub.home (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 25 Nov 2021 09:39:39 -0600 From: Rodrigo Siqueira To: Simon Ser , =?utf-8?q?Michel_D=C3=A4nzer?= , Bas Nieuwenhuizen , =?utf-8?b?TWFyZWsgT2zFocOhaw==?= , Roman Gilg , Nicholas Kazlauskas , "Harry Wentland" , Mark Yacoub , Sean Paul , Pekka Paalanen Subject: [PATCH 6/6] Documentation/gpu: Add DC glossary Date: Thu, 25 Nov 2021 10:38:30 -0500 Message-ID: <20211125153830.1352994-7-Rodrigo.Siqueira@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125153830.1352994-1-Rodrigo.Siqueira@amd.com> References: <20211125153830.1352994-1-Rodrigo.Siqueira@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f530cb89-cee4-497b-e68b-08d9b029cc4a X-MS-TrafficTypeDiagnostic: BN8PR12MB3521: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:901; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: aKPF3ux+fGiB/WTcVmxIUyxtoGk/isXFc+zdFN2Kz+b+RCWWLKOjuu7Rlz0rD1DV924cm4WOYa45foxK32CieLpdmZTtZCcDa8GQv11Y3/4X+aj0z3yhfEDJ9ULqUkR3qm0NAqK0huwWZXYnjK5O6TA++pHYniSFa4dry933WQw5pfopgi3r8rujeQqyXwOll79hknRWjXOJLura3gU9zpcCukIUT5Q/EitadWoz+XlUTM2EN6Vh/EE8Ar/iZpjvdXxGJfBnUO7TuS8PFelr/CB7kl+rO+ZP9els8tMywrw4WMIEutrOQCHFnKbYu7aSC0y5TgXiVurXCbcj4ePmmLJ+JLT2iFaxE2wwsZSuhDY+x40eTdrFlThpBmYU6BEC40wH2PlsvPIarP0KYhxEiXP7kapjVyuLsOzwsJPQ4RNO3eZM55R5PiMnIlna62FEAXQauxgR99jtp2V1UleY+LfhJUDGY3Ot9rqZvJUPKuHriSywDulBVxskY8+FBNjJG6yAfUBTf1EVIynKI+N1u9uk2VKVevurd5Vii2kqU7SF4hhrlSZd57HxtGa3+VUf1WmbWhHwC/7kkrKt0ID8Pj+c47wV9Pe2XdtrPPZt4EZms6BHajRh/q3oSsd+Ckps/N6zfEndr8D37a1L3rJ0XYGOB2mUEiu2v9658XHjXNPOuhB2rKd/Y91N6WHCs31dAoGQ5kBhGHrCB7rivYFkEoDKbHOb/ahn8b9bDztSqI+6D3Znzp2kBD4pzCBLLSOa X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(110136005)(316002)(54906003)(82310400004)(921005)(81166007)(4326008)(2616005)(36860700001)(426003)(7416002)(2906002)(26005)(16526019)(186003)(336012)(47076005)(8936002)(70206006)(36756003)(356005)(83380400001)(86362001)(70586007)(8676002)(6666004)(5660300002)(508600001)(1076003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2021 15:39:41.6795 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f530cb89-cee4-497b-e68b-08d9b029cc4a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3521 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-doc@vger.kernel.org, qingqing.zhuo@amd.com, roman.li@amd.com, amd-gfx@lists.freedesktop.org, aurabindo.pillai@amd.com, nicholas.choi@amd.com, dri-devel@lists.freedesktop.org, Alex Deucher , bhawanpreet.lakha@amd.com, =?utf-8?q?Christian_K=C3=B6nig?= Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In the DC driver, we have multiple acronyms that are not obvious most of the time. This commit introduces a DC glossary in order to make it easier to navigate through our driver. Signed-off-by: Rodrigo Siqueira --- Documentation/gpu/amdgpu-dc/amdgpu-dc.rst | 2 +- Documentation/gpu/amdgpu-dc/dc-glossary.rst | 257 ++++++++++++++++++++ 2 files changed, 258 insertions(+), 1 deletion(-) create mode 100644 Documentation/gpu/amdgpu-dc/dc-glossary.rst diff --git a/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst b/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst index 2e45e83d9a2a..15405c43786a 100644 --- a/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst +++ b/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst @@ -26,4 +26,4 @@ table of content: amdgpu-dcn-overview.rst amdgpu-dm.rst amdgpu-dc-debug.rst - + dc-glossary.rst diff --git a/Documentation/gpu/amdgpu-dc/dc-glossary.rst b/Documentation/gpu/amdgpu-dc/dc-glossary.rst new file mode 100644 index 000000000000..48698fc1799f --- /dev/null +++ b/Documentation/gpu/amdgpu-dc/dc-glossary.rst @@ -0,0 +1,257 @@ +=========== +DC Glossary +=========== + +.. glossary:: + + ABM + Adaptive Backlight Modulation + + APU + Accelerated Processing Unit + + ASIC + Application-Specific Integrated Circuit + + ASSR + Alternate Scrambler Seed Reset + + AZ + Azalia (HD audio DMA engine) + + BPC + Bits Per Colour/Component + + BPP + Bits Per Pixel + + Clocks + * PCLK: Pixel Clock + * SYMCLK: Symbol Clock + * SOCCLK: GPU Engine Clock + * DISPCLK: Display Clock + * DPPCLK: DPP Clock + * DCFCLK: Display Controller Fabric Clock + * REFCLK: Real Time Reference Clock + * PPLL: Pixel PLL + * FCLK: Fabric Clock + * MCLK: Memory Clock + * CPLIB: Content Protection Library + + CRC + Cyclic Redundancy Check + + CRTC + Cathode Ray Tube Controller - commonly called "Controller" - Generates + raw stream of pixels, clocked at pixel clock + + CVT + Coordinated Video Timings + + DAL + Display Abstraction layer + + DC (Software) + Display Core + + DC (Hardware) + Display Controller + + DCC + Delta Colour Compression + + DCE + Display Controller Engine + + DCHUB + Display Controller Hub + + ARB + Arbiter + + VTG + Vertical Timing Generator + + DCN + Display Core Next + + DCCG + Display Clock Generator block + + DDC + Display Data Channel + + DFS + Digital Frequency Synthesizer + + DIO + Display IO + + DPP + Display Pipes and Planes + + DSC + Display Stream Compression (Reduce the amount of bits to represent pixel + count while at the same pixel clock) + + dGPU + discrete GPU + + DMIF + Display Memory Interface + + DML + Display Mode Library + + DMCU + Display Micro Controller Unit + + DMCUB + Display Micro-Controller Unit, version B + + DPCD + DisplayPort Configuration Data + + DPM(S) + Display Power Management (Signaling) + + DRR + Dynamic Refresh Rate + + DWB + Display writeback + + ECP + Enhanced Content Protection + + FB + Frame Buffer + + FBC + Frame Buffer Compression + + FEC + Forward Error Correction + + FRL + Fixed Rate Link + + GCO + Graphical Controller Object + + GMC + Graphic Memory Controller + + GSL + Global Swap Lock + + iGPU + integrated GPU + + IH + Interrupt Handler + + ISR + Interrupt Service Request + + ISV + Independent Software Vendor + + KMD + Kernel Mode Driver + + LB + Line Buffer + + LFC + Low Framerate Compensation + + LTTPR + Link Training Tunable Phy Repeater + + LUT + Lookup Table + + MALL + Memory Access at Last Level + + MC + Memory Controller + + MPC + Multiple pipes and plane combine + + MPO + Multi Plane Overlay + + MST + Multi Stream Transport + + NBP State + Northbridge Power State + + NBIO + North Bridge Input/Output + + ODM + Output Data Mapping + + OPM + Output Protection Manager + + OPP + Output Plane Processor + + OPTC + Output Pipe Timing Combiner + + OTG + Output Timing Generator + + PCON + Power Controller + + PGFSM + Power Gate Finite State Machine + + PPLib + PowerPlay Library + + PSR + Panel Self Refresh + + SCL + Scaler + + SDP + Scalable Data Port + + SMU + System Management Unit + + SLS + Single Large Surface + + SST + Single Stream Transport + + TMDS + Transition-Minimized Differential Signaling + + TMZ + Trusted Memory Zone + + TTU + Time to Underflow + + VRR + Variable Refresh Rate + + UVD + Unified Video Decoder + + VCE + Video Compression Engine + + VCN + Video Codec Next