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Wed, 19 Dec 2018 10:11:49 +0000 From: Yogesh Narayan Gaur To: "linux-mtd@lists.infradead.org" , "boris.brezillon@bootlin.com" , "broonie@kernel.org" , "marek.vasut@gmail.com" , "vigneshr@ti.com" , "linux-spi@vger.kernel.org" , "devicetree@vger.kernel.org" Subject: [PATCH v6 1/7] spi: add support for octal mode I/O data transfer Thread-Topic: [PATCH v6 1/7] spi: add support for octal mode I/O data transfer Thread-Index: AQHUl4NBIWyUgOasmESGX5g9nVbhyg== Date: Wed, 19 Dec 2018 10:11:49 +0000 Message-ID: <1545214186-16987-2-git-send-email-yogeshnarayan.gaur@nxp.com> References: <1545214186-16987-1-git-send-email-yogeshnarayan.gaur@nxp.com> In-Reply-To: <1545214186-16987-1-git-send-email-yogeshnarayan.gaur@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SG2PR02CA0009.apcprd02.prod.outlook.com (2603:1096:3:17::21) To VI1PR04MB5726.eurprd04.prod.outlook.com (2603:10a6:803:e4::24) authentication-results: spf=none (sender IP is ) smtp.mailfrom=yogeshnarayan.gaur@nxp.com; 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SPI_TX_OCTAL: transmit with 8 wires SPI_RX_OCTAL: receive with 8 wires Signed-off-by: Yogesh Narayan Gaur Reviewed-by: Boris Brezillon --- Changes for v6: - Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'. Changes for v5: - Modified string 'octo' with 'octal'. Changes for v4: - Rebase on top of v4.20-rc2 Changes for v3: - Modified string 'octal' with 'octo'. - Add octo mode support in spi_setup(). Changes for v2: - Incorporated review comments of Boris. drivers/spi/spi.c | 12 ++++++++++-- include/linux/spi/spi.h | 4 +++- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 6ca5940..95249b8 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -1617,6 +1617,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, case 4: spi->mode |= SPI_TX_QUAD; break; + case 8: + spi->mode |= SPI_TX_OCTAL; + break; default: dev_warn(&ctlr->dev, "spi-tx-bus-width %d not supported\n", @@ -1635,6 +1638,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, case 4: spi->mode |= SPI_RX_QUAD; break; + case 8: + spi->mode |= SPI_RX_OCTAL; + break; default: dev_warn(&ctlr->dev, "spi-rx-bus-width %d not supported\n", @@ -2823,7 +2829,8 @@ int spi_setup(struct spi_device *spi) /* if it is SPI_3WIRE mode, DUAL and QUAD should be forbidden */ if ((spi->mode & SPI_3WIRE) && (spi->mode & - (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD))) + (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL | + SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL))) return -EINVAL; /* help drivers fail *cleanly* when they need options * that aren't supported with their current controller @@ -2832,7 +2839,8 @@ int spi_setup(struct spi_device *spi) */ bad_bits = spi->mode & ~(spi->controller->mode_bits | SPI_CS_WORD); ugly_bits = bad_bits & - (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD); + (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL | + SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL); if (ugly_bits) { dev_warn(&spi->dev, "setup: ignoring unsupported mode bits %x\n", diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 6be77fa..0c1ca5d 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -154,7 +154,9 @@ struct spi_device { #define SPI_TX_QUAD 0x200 /* transmit with 4 wires */ #define SPI_RX_DUAL 0x400 /* receive with 2 wires */ #define SPI_RX_QUAD 0x800 /* receive with 4 wires */ -#define SPI_CS_WORD 0x1000 /* toggle cs after each word */ +#define SPI_CS_WORD 0x1000 /* toggle cs after each word */ +#define SPI_TX_OCTAL 0x2000 /* transmit with 8 wires */ +#define SPI_RX_OCTAL 0x4000 /* receive with 8 wires */ int irq; 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Wed, 19 Dec 2018 10:11:55 +0000 From: Yogesh Narayan Gaur To: "linux-mtd@lists.infradead.org" , "boris.brezillon@bootlin.com" , "broonie@kernel.org" , "marek.vasut@gmail.com" , "vigneshr@ti.com" , "linux-spi@vger.kernel.org" , "devicetree@vger.kernel.org" Subject: [PATCH v6 2/7] spi: spi-mem: add support for octal mode I/O data transfer Thread-Topic: [PATCH v6 2/7] spi: spi-mem: add support for octal mode I/O data transfer Thread-Index: AQHUl4NFOIKJ2LzzYEqWmI5FGNUKVg== Date: Wed, 19 Dec 2018 10:11:55 +0000 Message-ID: <1545214186-16987-3-git-send-email-yogeshnarayan.gaur@nxp.com> References: <1545214186-16987-1-git-send-email-yogeshnarayan.gaur@nxp.com> In-Reply-To: <1545214186-16987-1-git-send-email-yogeshnarayan.gaur@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SG2PR02CA0009.apcprd02.prod.outlook.com (2603:1096:3:17::21) To VI1PR04MB5726.eurprd04.prod.outlook.com (2603:10a6:803:e4::24) authentication-results: spf=none (sender IP is ) smtp.mailfrom=yogeshnarayan.gaur@nxp.com; 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Signed-off-by: Yogesh Narayan Gaur Reviewed-by: Boris Brezillon --- Changes for v6: - Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'. Changes for v5: - Modified string 'octo' with 'octal'. Changes for v4: - None Changes for v3: - Modified string 'octal' with 'octo'. Changes for v2: - Patch added in v2 version. drivers/spi/spi-mem.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 62a7b80..5e15d62 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -12,7 +12,7 @@ #include "internals.h" -#define SPI_MEM_MAX_BUSWIDTH 4 +#define SPI_MEM_MAX_BUSWIDTH 8 /** * spi_controller_dma_map_mem_op_data() - DMA-map the buffer attached to a @@ -121,6 +121,13 @@ static int spi_check_buswidth_req(struct spi_mem *mem, u8 buswidth, bool tx) break; + case 8: + if ((tx && (mode & SPI_TX_OCTAL)) || + (!tx && (mode & SPI_RX_OCTAL))) + return 0; + + break; + default: break; } From patchwork Wed Dec 19 10:12:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yogesh Narayan Gaur X-Patchwork-Id: 10737025 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C4AEC6C2 for ; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR04MB6096; H:VI1PR04MB5726.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: RjXjquseOSXBdTjRMXjPUbB/OXh6ZPUsJd7mUNrWyHmsUDM9CFcFS1EDbOeJG/Tw2Kszbbj0tKcglHLxrCZ2MP2QqOxLIvZrkzb+WZFY2ZLrb+C+4mgfwWzj4ts92GiiE/Xwfb0tXjI11XTjS8GNk99SQ0LgCOSITepARxRcKNilyS58RCMZZFAQZ2DrjiezTUIjI4xgZZlvAfPvXQSJAXpG3U0ZdrXlNJrwbD297sOhZrJc6FAnNVeyuMiheOL7HCmkcLsm8cehOrMpG1eOcwBAUGbBbLkTdjVUEJHC/VQbHEvdHdxir5/8EqAZYMvj spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5d4a77ae-142b-48ea-5456-08d6659a6af5 X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Dec 2018 10:12:02.0367 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB6096 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181219_021222_055728_8EF7B14C X-CRM114-Status: GOOD ( 15.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "mark.rutland@arm.com" , "robh@kernel.org" , Yogesh Narayan Gaur , "tudor.ambarus@microchip.com" , "linux-kernel@vger.kernel.org" , "frieder.schrempf@exceet.de" , "computersforpeace@gmail.com" , "shawnguo@kernel.org" , "linux-arm-kernel@lists.infradead.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP - Add opcodes for octal I/O commands * Read : 1-1-8 and 1-8-8 protocol * Write : 1-1-8 and 1-8-8 protocol * opcodes for 4-byte address mode command - Entry of macros in _convert_3to4_xxx function - Add flag specifying flash support octal read commands. Signed-off-by: Vignesh R Signed-off-by: Yogesh Narayan Gaur Reviewed-by: Tudor Ambarus --- Changes for v6: - Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'. Changes for v5: - Modified string 'octo' with 'octal'. Changes for v4: - None Changes for v3: - Modified string 'octal' with 'octo'. Changes for v2: - Incorporated review comments of Boris and Vignesh drivers/mtd/spi-nor/spi-nor.c | 16 ++++++++++++++-- include/linux/mtd/spi-nor.h | 16 ++++++++++++---- 2 files changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 6e13bbd..872d707 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -68,7 +68,7 @@ enum spi_nor_read_command_index { SNOR_CMD_READ_4_4_4, SNOR_CMD_READ_1_4_4_DTR, - /* Octo SPI */ + /* Octal SPI */ SNOR_CMD_READ_1_1_8, SNOR_CMD_READ_1_8_8, SNOR_CMD_READ_8_8_8, @@ -85,7 +85,7 @@ enum spi_nor_pp_command_index { SNOR_CMD_PP_1_4_4, SNOR_CMD_PP_4_4_4, - /* Octo SPI */ + /* Octal SPI */ SNOR_CMD_PP_1_1_8, SNOR_CMD_PP_1_8_8, SNOR_CMD_PP_8_8_8, @@ -278,6 +278,7 @@ struct flash_info { #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */ #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */ #define USE_CLSR BIT(14) /* use CLSR command */ +#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */ /* Part specific fixup hooks. */ const struct spi_nor_fixups *fixups; @@ -398,6 +399,8 @@ static u8 spi_nor_convert_3to4_read(u8 opcode) { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B }, { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B }, { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B }, + { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B }, + { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B }, { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B }, { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B }, @@ -414,6 +417,8 @@ static u8 spi_nor_convert_3to4_program(u8 opcode) { SPINOR_OP_PP, SPINOR_OP_PP_4B }, { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B }, { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B }, + { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B }, + { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B }, }; return spi_nor_convert_opcode(opcode, spi_nor_3to4_program, @@ -3591,6 +3596,13 @@ static int spi_nor_init_params(struct spi_nor *nor, SNOR_PROTO_1_1_4); } + if (info->flags & SPI_NOR_OCTAL_READ) { + params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8; + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8], + 0, 8, SPINOR_OP_READ_1_1_8, + SNOR_PROTO_1_1_8); + } + /* Page Program settings. */ params->hwcaps.mask |= SNOR_HWCAPS_PP; spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index fa2d89e..2353af8 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -46,9 +46,13 @@ #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */ #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */ #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */ +#define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */ +#define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */ #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */ #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */ +#define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */ +#define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */ #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ @@ -69,9 +73,13 @@ #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */ #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */ #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */ +#define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */ +#define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */ #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */ #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */ +#define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */ +#define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */ #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */ #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */ #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ @@ -458,7 +466,7 @@ struct spi_nor_hwcaps { /* *(Fast) Read capabilities. * MUST be ordered by priority: the higher bit position, the higher priority. - * As a matter of performances, it is relevant to use Octo SPI protocols first, + * As a matter of performances, it is relevant to use Octal SPI protocols first, * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly * (Slow) Read. */ @@ -479,7 +487,7 @@ struct spi_nor_hwcaps { #define SNOR_HWCAPS_READ_4_4_4 BIT(9) #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10) -#define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11) +#define SNOR_HWCPAS_READ_OCTAL GENMASK(14, 11) #define SNOR_HWCAPS_READ_1_1_8 BIT(11) #define SNOR_HWCAPS_READ_1_8_8 BIT(12) #define SNOR_HWCAPS_READ_8_8_8 BIT(13) @@ -488,7 +496,7 @@ struct spi_nor_hwcaps { /* * Page Program capabilities. * MUST be ordered by priority: the higher bit position, the higher priority. - * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the + * Like (Fast) Read capabilities, Octal/Quad SPI protocols are preferred to the * legacy SPI 1-1-1 protocol. * Note that Dual Page Programs are not supported because there is no existing * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory @@ -502,7 +510,7 @@ struct spi_nor_hwcaps { #define SNOR_HWCAPS_PP_1_4_4 BIT(18) #define SNOR_HWCAPS_PP_4_4_4 BIT(19) -#define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20) +#define SNOR_HWCAPS_PP_OCTAL GENMASK(22, 20) #define SNOR_HWCAPS_PP_1_1_8 BIT(20) #define SNOR_HWCAPS_PP_1_8_8 BIT(21) #define SNOR_HWCAPS_PP_8_8_8 BIT(22) From patchwork Wed Dec 19 10:12:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yogesh Narayan Gaur X-Patchwork-Id: 10737023 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BEF1513AD for ; Wed, 19 Dec 2018 10:14:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ABA8B2B008 for ; Wed, 19 Dec 2018 10:14:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9EBCC2B023; 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This flash, mt35xu512aba, is only complaint to SFDP JESD216B and does not seem to support newer JESD216C standard that provides auto detection of Octal mode capabilities and opcodes. Therefore, this capability is manually added using new SPI_NOR_OCTAL_READ flag. Signed-off-by: Vignesh R Signed-off-by: Yogesh Narayan Gaur Reviewed-by: Tudor Ambarus --- Changes for v6: - Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'. Changes for v5: - Modified string 'octo' with 'octal'. Changes for v4: - None Changes for v3: - Modified string 'octal' with 'octo'. Changes for v2: - Incorporated review comments of Boris and Vignesh drivers/mtd/spi-nor/spi-nor.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 872d707..53a3bcc 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1877,7 +1877,8 @@ static const struct flash_info spi_nor_ids[] = { /* Micron */ { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512, - SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES) + SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | + SPI_NOR_4B_OPCODES) }, /* PMC */ From patchwork Wed Dec 19 10:12:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yogesh Narayan Gaur X-Patchwork-Id: 10737033 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B7B2B924 for ; Wed, 19 Dec 2018 10:19:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A6C392AD35 for ; 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Assign hw-capability mask bits for octal transfer. Signed-off-by: Yogesh Narayan Gaur --- Changes for v6: - Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'. Changes for v5: - Modified string 'octo' with 'octal'. Changes for v4: - None Changes for v3: - Modified string 'octal' with 'octo'. Changes for v2: - Incorporated review comments of Boris. drivers/mtd/devices/m25p80.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c index c4a1d04..651bab6 100644 --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c @@ -195,7 +195,14 @@ static int m25p_probe(struct spi_mem *spimem) spi_mem_set_drvdata(spimem, flash); flash->spimem = spimem; - if (spi->mode & SPI_RX_QUAD) { + if (spi->mode & SPI_RX_OCTAL) { + hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8; + + if (spi->mode & SPI_TX_OCTAL) + hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 | + SNOR_HWCAPS_PP_1_1_8 | + SNOR_HWCAPS_PP_1_8_8); + } else if (spi->mode & SPI_RX_QUAD) { hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; if (spi->mode & SPI_TX_QUAD) From patchwork Wed Dec 19 10:12:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yogesh Narayan Gaur X-Patchwork-Id: 10737055 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ED48814E2 for ; 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Wed, 19 Dec 2018 10:12:20 +0000 Received: from VI1PR04MB5726.eurprd04.prod.outlook.com ([fe80::d938:811:ed7:175]) by VI1PR04MB5726.eurprd04.prod.outlook.com ([fe80::d938:811:ed7:175%3]) with mapi id 15.20.1446.018; Wed, 19 Dec 2018 10:12:20 +0000 From: Yogesh Narayan Gaur To: "linux-mtd@lists.infradead.org" , "boris.brezillon@bootlin.com" , "broonie@kernel.org" , "marek.vasut@gmail.com" , "vigneshr@ti.com" , "linux-spi@vger.kernel.org" , "devicetree@vger.kernel.org" Subject: [PATCH v6 6/7] spi: nxp-fspi: add octal mode flag bit for octal support Thread-Topic: [PATCH v6 6/7] spi: nxp-fspi: add octal mode flag bit for octal support Thread-Index: AQHUl4NTdJxg/UgGtEeSFbAm/QNYvA== Date: Wed, 19 Dec 2018 10:12:20 +0000 Message-ID: <1545214186-16987-7-git-send-email-yogeshnarayan.gaur@nxp.com> References: <1545214186-16987-1-git-send-email-yogeshnarayan.gaur@nxp.com> In-Reply-To: <1545214186-16987-1-git-send-email-yogeshnarayan.gaur@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SG2PR02CA0009.apcprd02.prod.outlook.com (2603:1096:3:17::21) To VI1PR04MB5726.eurprd04.prod.outlook.com (2603:10a6:803:e4::24) authentication-results: spf=none (sender IP is ) smtp.mailfrom=yogeshnarayan.gaur@nxp.com; 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NXP FlexSPI controller supports 8 lines Rx/Tx data transfer. Signed-off-by: Yogesh Narayan Gaur --- Changes for v6: - Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'. Changes for v5: - Modified string 'octo' with 'octal'. Changes for v4: - None Changes for v3: - Modified string 'octal' with 'octo'. Changes for v2: - None drivers/spi/spi-nxp-fspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index 6d497f4..cfd3126 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -995,8 +995,8 @@ static int nxp_fspi_probe(struct platform_device *pdev) if (!ctlr) return -ENOMEM; - ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | - SPI_TX_DUAL | SPI_TX_QUAD; + ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL | + SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL; f = spi_controller_get_devdata(ctlr); f->dev = dev; From patchwork Wed Dec 19 10:12:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yogesh Narayan Gaur X-Patchwork-Id: 10737027 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 48F4213BF for ; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR04MB6096; H:VI1PR04MB5726.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: kiXwM/6Mo1FKUDJFDh6Cvk5IfjucEiqhyrSixs8qjl060T/3Re6PVqjL8hpjr+C3/2ZuZZBRX/iynex3uZ11AUPBm/KfQMuxV+oyKOkpQ2j/bNgH/rw3xlWESGsh41h1dVRJEzT8syHtqxZt8PoOfpl65Ncm89CEgAkg1rLd4zciqtiaT8etpLaHnAaioWBNgVb48hXLiThvhNNztnwZqnjRGFeM54DTuFO038FTRoyvr7m5HJUvGRCRsLZ1Re66ZoUlSdoo0SZUQgCkPCQ4wiPNe1ldhpbxer60hGiz3AWnIpB0i+MPWaEM2Hizfmns spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 20da854b-9dde-488a-cab3-08d6659a79ae X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Dec 2018 10:12:26.4433 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB6096 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181219_021248_855816_9858A6D6 X-CRM114-Status: GOOD ( 10.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "mark.rutland@arm.com" , "robh@kernel.org" , Yogesh Narayan Gaur , "tudor.ambarus@microchip.com" , "linux-kernel@vger.kernel.org" , "frieder.schrempf@exceet.de" , "computersforpeace@gmail.com" , "shawnguo@kernel.org" , "linux-arm-kernel@lists.infradead.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Flash mt35xu512aba connected to FlexSPI controller supports 1-1-8/1-8-8 protocol. Added flag spi-rx-bus-width and spi-tx-bus-width with values as 8 and 8 respectively for both flashes connected at CS0 and CS1. Signed-off-by: Yogesh Narayan Gaur --- Changes for v6: - Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'. Changes for v5: - None Changes for v4: - None Changes for v3: - None Changes for v2: - None arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts index 3b20c97..24cc41c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -45,6 +45,8 @@ m25p,fast-read; spi-max-frequency = <20000000>; reg = <0>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <8>; }; mt35xu512aba1: flash@1 { @@ -54,6 +56,8 @@ m25p,fast-read; spi-max-frequency = <20000000>; reg = <1>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <8>; }; };