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[86.58.29.253]) by smtp.gmail.com with ESMTPSA id o12sm85907wmq.12.2021.11.29.10.26.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Nov 2021 10:26:38 -0800 (PST) From: Jernej Skrabec To: linux-media@vger.kernel.org Cc: ezequiel@vanguardiasur.com.ar, nicolas.dufresne@collabora.com, mchehab@kernel.org, robh+dt@kernel.org, mripard@kernel.org, wens@csie.org, p.zabel@pengutronix.de, andrzej.p@collabora.com, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Jernej Skrabec Subject: [PATCH v2 1/9] media: hantro: Fix probe func error path Date: Mon, 29 Nov 2021 19:26:25 +0100 Message-Id: <20211129182633.480021-2-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211129182633.480021-1-jernej.skrabec@gmail.com> References: <20211129182633.480021-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org If clocks for some reason couldn't be enabled, probe function returns immediately, without disabling PM. This obviously leaves PM ref counters unbalanced. Fix that by jumping to appropriate error path, so effects of PM functions are reversed. Fixes: 775fec69008d ("media: add Rockchip VPU JPEG encoder driver") Signed-off-by: Jernej Skrabec Acked-by: Andrzej Pietrasiewicz Reviewed-by: Ezequiel Garcia --- drivers/staging/media/hantro/hantro_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c index ab2467998d29..3d3107a39dae 100644 --- a/drivers/staging/media/hantro/hantro_drv.c +++ b/drivers/staging/media/hantro/hantro_drv.c @@ -981,7 +981,7 @@ static int hantro_probe(struct platform_device *pdev) ret = clk_bulk_prepare(vpu->variant->num_clocks, vpu->clocks); if (ret) { dev_err(&pdev->dev, "Failed to prepare clocks\n"); - return ret; + goto err_pm_disable; } ret = v4l2_device_register(&pdev->dev, &vpu->v4l2_dev); @@ -1037,6 +1037,7 @@ static int hantro_probe(struct platform_device *pdev) v4l2_device_unregister(&vpu->v4l2_dev); err_clk_unprepare: clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks); +err_pm_disable: pm_runtime_dont_use_autosuspend(vpu->dev); pm_runtime_disable(vpu->dev); return ret; From patchwork Mon Nov 29 18:26:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 12645699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65A63C433F5 for ; Mon, 29 Nov 2021 21:00:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229888AbhK2VDt (ORCPT ); Mon, 29 Nov 2021 16:03:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229999AbhK2VBr (ORCPT ); Mon, 29 Nov 2021 16:01:47 -0500 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93943C11FA35; Mon, 29 Nov 2021 10:26:42 -0800 (PST) Received: by mail-wm1-x32c.google.com with SMTP id 133so15479643wme.0; Mon, 29 Nov 2021 10:26:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uWzzP3/wZqXojr9D0rKdXZ64ct8p427xpqtRAcNwtec=; b=eaOuG6M65E3Pd/n9mztbM6SnzysPCh7Dy35mWAIAsXL5YLwSnFqRBEOe+Dh0AsFYd0 q5rNjWz7/trGczgMTJWnmHDBWXoVch4YG/9KXarUPhtYDNRHIPnemyU3cvLWPg0f3brj fX/txBUlt4dHCPEq31Ex4efQ81mFS+pPn+L3puV+ZtrpzjAQnQZdQ8bPUbP2mfXotvSi BOKvhJEtzBtvIjKzSXrXFFLQ9Zj6zZDT3ILE9gBzTpHGVyi9eYziWc028far+RMThiRv 9XOY84Fa0cdZdxDHZOGFbh/4xEVV8qoGVcFI4rRo/j9FCNFb0dhqvU1lkbJ7l5dH83oT 3giA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uWzzP3/wZqXojr9D0rKdXZ64ct8p427xpqtRAcNwtec=; b=Nfy5hiAUyw3BcryWAJ6V/bMBxS3cmPBeNEAWVJzBI6SaIl8HyUdbtsJyUlJHONw/i7 zW1ADCdQpUOzkxlSU591VPPBfXXS6S+7ZsFqdF1fpLrVH6N8qkk3nHZ+Llt5eBM1dRuO jzbCsowLUFhRfr9O9TSW3qpI02J4sTet/BAEMxhd5FjveCUauTBILnv4PMUB0gGuZzFI 7BYAsHNVH4jJdblPC+Kl/KkkJm95JPsu9jgFSXLCMVzHbSuNNUcSmFYzXzItMUn5WR/R vIpp3Q4PZtsNoLNucIthsLtwR/IhCpKj83BgqemO2pVUmtoXFSYHU3NmYHvU6McrdHZd DDhw== X-Gm-Message-State: AOAM532wx2WfinzmSjE6QvDk53AP8YRXCZtNDuQlA8o4Rgz7w8N9blFF RmU8W1qS/1oAQr6vtxfJ7KRLt0bzicsWSw== X-Google-Smtp-Source: ABdhPJzfV4IJ4BrEen7JVh4JyVgHc1mWqatybftwWR01jvpOhIrMxHGiruFZnig1i2JYb7qBJf7IhQ== X-Received: by 2002:a05:600c:221a:: with SMTP id z26mr13626wml.20.1638210401154; Mon, 29 Nov 2021 10:26:41 -0800 (PST) Received: from kista.localdomain (cpe-86-58-29-253.static.triera.net. [86.58.29.253]) by smtp.gmail.com with ESMTPSA id o12sm85907wmq.12.2021.11.29.10.26.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Nov 2021 10:26:40 -0800 (PST) From: Jernej Skrabec To: linux-media@vger.kernel.org Cc: ezequiel@vanguardiasur.com.ar, nicolas.dufresne@collabora.com, mchehab@kernel.org, robh+dt@kernel.org, mripard@kernel.org, wens@csie.org, p.zabel@pengutronix.de, andrzej.p@collabora.com, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Jernej Skrabec Subject: [PATCH v2 2/9] media: hantro: add support for reset lines Date: Mon, 29 Nov 2021 19:26:26 +0100 Message-Id: <20211129182633.480021-3-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211129182633.480021-1-jernej.skrabec@gmail.com> References: <20211129182633.480021-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Some SoCs like Allwinner H6 use reset lines for resetting Hantro G2. Add support for them. Signed-off-by: Jernej Skrabec Reviewed-by: Andrzej Pietrasiewicz Reviewed-by: Ezequiel Garcia --- drivers/staging/media/hantro/hantro.h | 3 +++ drivers/staging/media/hantro/hantro_drv.c | 15 ++++++++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h index 7da23f7f207a..33eb3e092cc1 100644 --- a/drivers/staging/media/hantro/hantro.h +++ b/drivers/staging/media/hantro/hantro.h @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -171,6 +172,7 @@ hantro_vdev_to_func(struct video_device *vdev) * @dev: Pointer to device for convenient logging using * dev_ macros. * @clocks: Array of clock handles. + * @resets: Array of reset handles. * @reg_bases: Mapped addresses of VPU registers. * @enc_base: Mapped address of VPU encoder register for convenience. * @dec_base: Mapped address of VPU decoder register for convenience. @@ -190,6 +192,7 @@ struct hantro_dev { struct platform_device *pdev; struct device *dev; struct clk_bulk_data *clocks; + struct reset_control *resets; void __iomem **reg_bases; void __iomem *enc_base; void __iomem *dec_base; diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c index 3d3107a39dae..770f4ce71d29 100644 --- a/drivers/staging/media/hantro/hantro_drv.c +++ b/drivers/staging/media/hantro/hantro_drv.c @@ -905,6 +905,10 @@ static int hantro_probe(struct platform_device *pdev) return PTR_ERR(vpu->clocks[0].clk); } + vpu->resets = devm_reset_control_array_get(&pdev->dev, false, true); + if (IS_ERR(vpu->resets)) + return PTR_ERR(vpu->resets); + num_bases = vpu->variant->num_regs ?: 1; vpu->reg_bases = devm_kcalloc(&pdev->dev, num_bases, sizeof(*vpu->reg_bases), GFP_KERNEL); @@ -978,10 +982,16 @@ static int hantro_probe(struct platform_device *pdev) pm_runtime_use_autosuspend(vpu->dev); pm_runtime_enable(vpu->dev); + ret = reset_control_deassert(vpu->resets); + if (ret) { + dev_err(&pdev->dev, "Failed to deassert resets\n"); + goto err_pm_disable; + } + ret = clk_bulk_prepare(vpu->variant->num_clocks, vpu->clocks); if (ret) { dev_err(&pdev->dev, "Failed to prepare clocks\n"); - goto err_pm_disable; + goto err_rst_assert; } ret = v4l2_device_register(&pdev->dev, &vpu->v4l2_dev); @@ -1037,6 +1047,8 @@ static int hantro_probe(struct platform_device *pdev) v4l2_device_unregister(&vpu->v4l2_dev); err_clk_unprepare: clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks); +err_rst_assert: + reset_control_assert(vpu->resets); err_pm_disable: pm_runtime_dont_use_autosuspend(vpu->dev); pm_runtime_disable(vpu->dev); @@ -1056,6 +1068,7 @@ static int hantro_remove(struct platform_device *pdev) v4l2_m2m_release(vpu->m2m_dev); v4l2_device_unregister(&vpu->v4l2_dev); clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks); + reset_control_assert(vpu->resets); pm_runtime_dont_use_autosuspend(vpu->dev); pm_runtime_disable(vpu->dev); return 0; From patchwork Mon Nov 29 18:26:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 12645701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E846C433FE for ; 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[86.58.29.253]) by smtp.gmail.com with ESMTPSA id o12sm85907wmq.12.2021.11.29.10.26.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Nov 2021 10:26:42 -0800 (PST) From: Jernej Skrabec To: linux-media@vger.kernel.org Cc: ezequiel@vanguardiasur.com.ar, nicolas.dufresne@collabora.com, mchehab@kernel.org, robh+dt@kernel.org, mripard@kernel.org, wens@csie.org, p.zabel@pengutronix.de, andrzej.p@collabora.com, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Jernej Skrabec Subject: [PATCH v2 3/9] media: hantro: vp9: use double buffering if needed Date: Mon, 29 Nov 2021 19:26:27 +0100 Message-Id: <20211129182633.480021-4-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211129182633.480021-1-jernej.skrabec@gmail.com> References: <20211129182633.480021-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Some G2 variants need double buffering to be enabled in order to work correctly, like that found in Allwinner H6 SoC. Add platform quirk for that. Reviewed-by: Andrzej Pietrasiewicz Signed-off-by: Jernej Skrabec --- drivers/staging/media/hantro/hantro.h | 2 ++ drivers/staging/media/hantro/hantro_g2_regs.h | 1 + drivers/staging/media/hantro/hantro_g2_vp9_dec.c | 2 ++ 3 files changed, 5 insertions(+) diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h index 33eb3e092cc1..d03824fa3222 100644 --- a/drivers/staging/media/hantro/hantro.h +++ b/drivers/staging/media/hantro/hantro.h @@ -73,6 +73,7 @@ struct hantro_irq { * @num_clocks: number of clocks in the array * @reg_names: array of register range names * @num_regs: number of register range names in the array + * @double_buffer: core needs double buffering */ struct hantro_variant { unsigned int enc_offset; @@ -94,6 +95,7 @@ struct hantro_variant { int num_clocks; const char * const *reg_names; int num_regs; + unsigned int double_buffer : 1; }; /** diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h index 9c857dd1ad9b..15a391a4650e 100644 --- a/drivers/staging/media/hantro/hantro_g2_regs.h +++ b/drivers/staging/media/hantro/hantro_g2_regs.h @@ -270,6 +270,7 @@ #define g2_apf_threshold G2_DEC_REG(55, 0, 0xffff) #define g2_clk_gate_e G2_DEC_REG(58, 16, 0x1) +#define g2_double_buffer_e G2_DEC_REG(58, 15, 0x1) #define g2_buswidth G2_DEC_REG(58, 8, 0x7) #define g2_max_burst G2_DEC_REG(58, 0, 0xff) diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c index e04242d10fa2..d4fc649a4da1 100644 --- a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c +++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c @@ -847,6 +847,8 @@ config_registers(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_p hantro_reg_write(ctx->dev, &g2_clk_gate_e, 1); hantro_reg_write(ctx->dev, &g2_max_cb_size, 6); hantro_reg_write(ctx->dev, &g2_min_cb_size, 3); + if (ctx->dev->variant->double_buffer) + hantro_reg_write(ctx->dev, &g2_double_buffer_e, 1); config_output(ctx, dst, dec_params); From patchwork Mon Nov 29 18:26:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 12645703 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA673C433EF for ; Mon, 29 Nov 2021 21:02:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231518AbhK2VFk (ORCPT ); Mon, 29 Nov 2021 16:05:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231747AbhK2VDk (ORCPT ); Mon, 29 Nov 2021 16:03:40 -0500 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C50AFC11FA3F; Mon, 29 Nov 2021 10:26:45 -0800 (PST) Received: by mail-wm1-x334.google.com with SMTP id o29so15437689wms.2; Mon, 29 Nov 2021 10:26:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dTZTbu7/INHWojoM1sPZJtHohD+hKsTfbuMrsdEckRA=; b=iYlIIcTqxOmRwVsDHPC9VSC5dY57bquBvptj37xB1SFCoHyH7GN0ZXdNcVaFEaZvvI d2DETtVJv7a1EgtQ+fl1C/pDtXiwmS3w2zj6wBGiKocUl4fwNUyvrJtzK5pBdsSEQ/X+ xJq2dWzhGSmhcP80l02ZqmAUMrOren5l45dGw9qWXJYdoxCe4ugM+mkej9E9UOcloxjq 445wP6ctzUPXYPuIO6fyzFWV0OrYiMrYp4EFY3PbnQA4bAh01w6opDW7GX9ATxLcR7Nd Zh02Bw4rjnFS71iuy689VYi3OVwjIXxmwQpM5YUS7qv0c0lPMrmCejt0pwJg72GVRmM+ IzTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dTZTbu7/INHWojoM1sPZJtHohD+hKsTfbuMrsdEckRA=; b=x1zzV5QhHndYYbvC4CtdOsRshXXOWtQBJmhNrRnnnbPfpU9nwSE07MBkJfPE/MFMIm ioA3CFyLIOOS37biRly3r+ci6cotu3aYdjZ7BXSTH1y4ku7M5UkLTz3opLDxqtY924+5 q+1s2bE/Pv6uTk+s/DAULFP4MMpay8LQEnfEWKyBfJ70b7kp2pCBb9a+eLtz4yfnjjcP dzuOEv8ER4jp5F76Qvdh3q5wzxvo1hEKp1Ed9QLKJrv3m0T9voj3WXQRublZOfmaO+jY LnDEiYBDI7jzTWYGGjcLdZEOnNI0wFEmJn7ZX7xREBw598ijLJbpOQ+fExRhVETLorfo oKgQ== X-Gm-Message-State: AOAM530G+kXejwJdvIJjbIKX8xk7rZ1PHNFq2wS6Sqf8swD7IHK/ungF zQJ0M6LpLzYec+u95JEYutfSwtD3BbRBuw== X-Google-Smtp-Source: ABdhPJzRtWeLfJU/YPbCIF6pvKGCkQFqTFiIUn88/kodxqQWZh47GaxImqLVAepUPyRlJ75MoMlBow== X-Received: by 2002:a1c:43c2:: with SMTP id q185mr77674wma.30.1638210403927; Mon, 29 Nov 2021 10:26:43 -0800 (PST) Received: from kista.localdomain (cpe-86-58-29-253.static.triera.net. [86.58.29.253]) by smtp.gmail.com with ESMTPSA id o12sm85907wmq.12.2021.11.29.10.26.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Nov 2021 10:26:43 -0800 (PST) From: Jernej Skrabec To: linux-media@vger.kernel.org Cc: ezequiel@vanguardiasur.com.ar, nicolas.dufresne@collabora.com, mchehab@kernel.org, robh+dt@kernel.org, mripard@kernel.org, wens@csie.org, p.zabel@pengutronix.de, andrzej.p@collabora.com, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Jernej Skrabec Subject: [PATCH v2 4/9] media: hantro: vp9: add support for legacy register set Date: Mon, 29 Nov 2021 19:26:28 +0100 Message-Id: <20211129182633.480021-5-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211129182633.480021-1-jernej.skrabec@gmail.com> References: <20211129182633.480021-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Some older G2 cores uses slightly different register set for HEVC and VP9. Since vast majority of registers and logic is the same, it doesn't make sense to introduce another drivers. Add legacy_regs quirk and implement only VP9 changes for now. HEVC changes will be introduced later, if needed. Reviewed-by: Andrzej Pietrasiewicz Signed-off-by: Jernej Skrabec --- drivers/staging/media/hantro/hantro.h | 2 + drivers/staging/media/hantro/hantro_g2_regs.h | 16 ++++ .../staging/media/hantro/hantro_g2_vp9_dec.c | 74 ++++++++++++++----- 3 files changed, 75 insertions(+), 17 deletions(-) diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h index d03824fa3222..83ed25d9657b 100644 --- a/drivers/staging/media/hantro/hantro.h +++ b/drivers/staging/media/hantro/hantro.h @@ -74,6 +74,7 @@ struct hantro_irq { * @reg_names: array of register range names * @num_regs: number of register range names in the array * @double_buffer: core needs double buffering + * @legacy_regs: core uses legacy register set */ struct hantro_variant { unsigned int enc_offset; @@ -96,6 +97,7 @@ struct hantro_variant { const char * const *reg_names; int num_regs; unsigned int double_buffer : 1; + unsigned int legacy_regs : 1; }; /** diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h index 15a391a4650e..b7c6f9877b9d 100644 --- a/drivers/staging/media/hantro/hantro_g2_regs.h +++ b/drivers/staging/media/hantro/hantro_g2_regs.h @@ -36,7 +36,13 @@ #define BUS_WIDTH_256 3 #define g2_strm_swap G2_DEC_REG(2, 28, 0xf) +#define g2_strm_swap_old G2_DEC_REG(2, 27, 0x1f) +#define g2_pic_swap G2_DEC_REG(2, 22, 0x1f) #define g2_dirmv_swap G2_DEC_REG(2, 20, 0xf) +#define g2_dirmv_swap_old G2_DEC_REG(2, 17, 0x1f) +#define g2_tab0_swap_old G2_DEC_REG(2, 12, 0x1f) +#define g2_tab1_swap_old G2_DEC_REG(2, 7, 0x1f) +#define g2_tab2_swap_old G2_DEC_REG(2, 2, 0x1f) #define g2_mode G2_DEC_REG(3, 27, 0x1f) #define g2_compress_swap G2_DEC_REG(3, 20, 0xf) @@ -45,6 +51,8 @@ #define g2_out_dis G2_DEC_REG(3, 15, 0x1) #define g2_out_filtering_dis G2_DEC_REG(3, 14, 0x1) #define g2_write_mvs_e G2_DEC_REG(3, 12, 0x1) +#define g2_tab3_swap_old G2_DEC_REG(3, 7, 0x1f) +#define g2_rscan_swap G2_DEC_REG(3, 2, 0x1f) #define g2_pic_width_in_cbs G2_DEC_REG(4, 19, 0x1fff) #define g2_pic_height_in_cbs G2_DEC_REG(4, 6, 0x1fff) @@ -58,6 +66,7 @@ #define g2_tempor_mvp_e G2_DEC_REG(5, 11, 0x1) #define g2_max_cu_qpd_depth G2_DEC_REG(5, 5, 0x3f) #define g2_cu_qpd_e G2_DEC_REG(5, 4, 0x1) +#define g2_pix_shift G2_DEC_REG(5, 0, 0xf) #define g2_stream_len G2_DEC_REG(6, 0, 0xffffffff) @@ -80,21 +89,28 @@ #define g2_const_intra_e G2_DEC_REG(8, 31, 0x1) #define g2_filt_ctrl_pres G2_DEC_REG(8, 30, 0x1) +#define g2_bit_depth_y G2_DEC_REG(8, 21, 0xf) +#define g2_bit_depth_c G2_DEC_REG(8, 17, 0xf) #define g2_idr_pic_e G2_DEC_REG(8, 16, 0x1) #define g2_bit_depth_pcm_y G2_DEC_REG(8, 12, 0xf) #define g2_bit_depth_pcm_c G2_DEC_REG(8, 8, 0xf) #define g2_bit_depth_y_minus8 G2_DEC_REG(8, 6, 0x3) #define g2_bit_depth_c_minus8 G2_DEC_REG(8, 4, 0x3) +#define g2_rs_out_bit_depth G2_DEC_REG(8, 4, 0xf) #define g2_output_8_bits G2_DEC_REG(8, 3, 0x1) #define g2_output_format G2_DEC_REG(8, 0, 0x7) +#define g2_pp_pix_shift G2_DEC_REG(8, 0, 0xf) #define g2_refidx1_active G2_DEC_REG(9, 19, 0x1f) #define g2_refidx0_active G2_DEC_REG(9, 14, 0x1f) #define g2_hdr_skip_length G2_DEC_REG(9, 0, 0x3fff) #define g2_start_code_e G2_DEC_REG(10, 31, 0x1) +#define g2_init_qp_old G2_DEC_REG(10, 25, 0x3f) #define g2_init_qp G2_DEC_REG(10, 24, 0x3f) +#define g2_num_tile_cols_old G2_DEC_REG(10, 20, 0x1f) #define g2_num_tile_cols G2_DEC_REG(10, 19, 0x1f) +#define g2_num_tile_rows_old G2_DEC_REG(10, 15, 0x1f) #define g2_num_tile_rows G2_DEC_REG(10, 14, 0x1f) #define g2_tile_e G2_DEC_REG(10, 1, 0x1) #define g2_entropy_sync_e G2_DEC_REG(10, 0, 0x1) diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c index d4fc649a4da1..91c21b634fab 100644 --- a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c +++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c @@ -150,7 +150,8 @@ static void config_output(struct hantro_ctx *ctx, dma_addr_t luma_addr, chroma_addr, mv_addr; hantro_reg_write(ctx->dev, &g2_out_dis, 0); - hantro_reg_write(ctx->dev, &g2_output_format, 0); + if (!ctx->dev->variant->legacy_regs) + hantro_reg_write(ctx->dev, &g2_output_format, 0); luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf); hantro_write_addr(ctx->dev, G2_OUT_LUMA_ADDR, luma_addr); @@ -327,6 +328,7 @@ config_tiles(struct hantro_ctx *ctx, struct hantro_aux_buf *tile_edge = &vp9_ctx->tile_edge; dma_addr_t addr; unsigned short *tile_mem; + unsigned int rows, cols; addr = misc->dma + vp9_ctx->tile_info_offset; hantro_write_addr(ctx->dev, G2_TILE_SIZES_ADDR, addr); @@ -344,17 +346,24 @@ config_tiles(struct hantro_ctx *ctx, fill_tile_info(ctx, tile_r, tile_c, sbs_r, sbs_c, tile_mem); + cols = tile_c; + rows = tile_r; hantro_reg_write(ctx->dev, &g2_tile_e, 1); - hantro_reg_write(ctx->dev, &g2_num_tile_cols, tile_c); - hantro_reg_write(ctx->dev, &g2_num_tile_rows, tile_r); - } else { tile_mem[0] = hantro_vp9_num_sbs(dst->vp9.width); tile_mem[1] = hantro_vp9_num_sbs(dst->vp9.height); + cols = 1; + rows = 1; hantro_reg_write(ctx->dev, &g2_tile_e, 0); - hantro_reg_write(ctx->dev, &g2_num_tile_cols, 1); - hantro_reg_write(ctx->dev, &g2_num_tile_rows, 1); + } + + if (ctx->dev->variant->legacy_regs) { + hantro_reg_write(ctx->dev, &g2_num_tile_cols_old, cols); + hantro_reg_write(ctx->dev, &g2_num_tile_rows_old, rows); + } else { + hantro_reg_write(ctx->dev, &g2_num_tile_cols, cols); + hantro_reg_write(ctx->dev, &g2_num_tile_rows, rows); } /* provide aux buffers even if no tiles are used */ @@ -505,8 +514,22 @@ static void config_picture_dimensions(struct hantro_ctx *ctx, struct hantro_deco static void config_bit_depth(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) { - hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8); - hantro_reg_write(ctx->dev, &g2_bit_depth_c_minus8, dec_params->bit_depth - 8); + if (ctx->dev->variant->legacy_regs) { + u8 pp_shift = 0; + + hantro_reg_write(ctx->dev, &g2_bit_depth_y, dec_params->bit_depth); + hantro_reg_write(ctx->dev, &g2_bit_depth_c, dec_params->bit_depth); + hantro_reg_write(ctx->dev, &g2_rs_out_bit_depth, dec_params->bit_depth); + + if (dec_params->bit_depth > 8) + pp_shift = 16 - dec_params->bit_depth; + + hantro_reg_write(ctx->dev, &g2_pp_pix_shift, pp_shift); + hantro_reg_write(ctx->dev, &g2_pix_shift, 0); + } else { + hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8); + hantro_reg_write(ctx->dev, &g2_bit_depth_c_minus8, dec_params->bit_depth - 8); + } } static inline bool is_lossless(const struct v4l2_vp9_quantization *quant) @@ -784,9 +807,13 @@ config_source(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_para + dec_params->compressed_header_size; stream_base = vb2_dma_contig_plane_dma_addr(&vb2_src->vb2_buf, 0); - hantro_write_addr(ctx->dev, G2_STREAM_ADDR, stream_base); tmp_addr = stream_base + headres_size; + if (ctx->dev->variant->legacy_regs) + hantro_write_addr(ctx->dev, G2_STREAM_ADDR, (tmp_addr & ~0xf)); + else + hantro_write_addr(ctx->dev, G2_STREAM_ADDR, stream_base); + start_bit = (tmp_addr & 0xf) * 8; hantro_reg_write(ctx->dev, &g2_start_bit, start_bit); @@ -794,10 +821,12 @@ config_source(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_para src_len += start_bit / 8 - headres_size; hantro_reg_write(ctx->dev, &g2_stream_len, src_len); - tmp_addr &= ~0xf; - hantro_reg_write(ctx->dev, &g2_strm_start_offset, tmp_addr - stream_base); - src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0); - hantro_reg_write(ctx->dev, &g2_strm_buffer_len, src_buf_len); + if (!ctx->dev->variant->legacy_regs) { + tmp_addr &= ~0xf; + hantro_reg_write(ctx->dev, &g2_strm_start_offset, tmp_addr - stream_base); + src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0); + hantro_reg_write(ctx->dev, &g2_strm_buffer_len, src_buf_len); + } } static void @@ -837,13 +866,24 @@ config_registers(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_p /* configure basic registers */ hantro_reg_write(ctx->dev, &g2_mode, VP9_DEC_MODE); - hantro_reg_write(ctx->dev, &g2_strm_swap, 0xf); - hantro_reg_write(ctx->dev, &g2_dirmv_swap, 0xf); - hantro_reg_write(ctx->dev, &g2_compress_swap, 0xf); + if (!ctx->dev->variant->legacy_regs) { + hantro_reg_write(ctx->dev, &g2_strm_swap, 0xf); + hantro_reg_write(ctx->dev, &g2_dirmv_swap, 0xf); + hantro_reg_write(ctx->dev, &g2_compress_swap, 0xf); + hantro_reg_write(ctx->dev, &g2_ref_compress_bypass, 1); + } else { + hantro_reg_write(ctx->dev, &g2_strm_swap_old, 0x1f); + hantro_reg_write(ctx->dev, &g2_pic_swap, 0x10); + hantro_reg_write(ctx->dev, &g2_dirmv_swap_old, 0x10); + hantro_reg_write(ctx->dev, &g2_tab0_swap_old, 0x10); + hantro_reg_write(ctx->dev, &g2_tab1_swap_old, 0x10); + hantro_reg_write(ctx->dev, &g2_tab2_swap_old, 0x10); + hantro_reg_write(ctx->dev, &g2_tab3_swap_old, 0x10); + hantro_reg_write(ctx->dev, &g2_rscan_swap, 0x10); + } hantro_reg_write(ctx->dev, &g2_buswidth, BUS_WIDTH_128); hantro_reg_write(ctx->dev, &g2_max_burst, 16); hantro_reg_write(ctx->dev, &g2_apf_threshold, 8); - hantro_reg_write(ctx->dev, &g2_ref_compress_bypass, 1); hantro_reg_write(ctx->dev, &g2_clk_gate_e, 1); hantro_reg_write(ctx->dev, &g2_max_cb_size, 6); hantro_reg_write(ctx->dev, &g2_min_cb_size, 3); From patchwork Mon Nov 29 18:26:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 12645705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5ECACC433EF for ; Mon, 29 Nov 2021 21:02:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231887AbhK2VFs (ORCPT ); Mon, 29 Nov 2021 16:05:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232005AbhK2VDr (ORCPT ); Mon, 29 Nov 2021 16:03:47 -0500 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5F3CC125302; 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[86.58.29.253]) by smtp.gmail.com with ESMTPSA id o12sm85907wmq.12.2021.11.29.10.26.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Nov 2021 10:26:45 -0800 (PST) From: Jernej Skrabec To: linux-media@vger.kernel.org Cc: ezequiel@vanguardiasur.com.ar, nicolas.dufresne@collabora.com, mchehab@kernel.org, robh+dt@kernel.org, mripard@kernel.org, wens@csie.org, p.zabel@pengutronix.de, andrzej.p@collabora.com, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Jernej Skrabec Subject: [PATCH v2 5/9] media: hantro: move postproc enablement for old cores Date: Mon, 29 Nov 2021 19:26:29 +0100 Message-Id: <20211129182633.480021-6-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211129182633.480021-1-jernej.skrabec@gmail.com> References: <20211129182633.480021-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Older G2 cores, like that in Allwinner H6, seem to have issue with latching postproc register values if this is first thing done in job. Moving that to the end solves the issue. Signed-off-by: Jernej Skrabec Reviewed-by: Andrzej Pietrasiewicz Reviewed-by: Ezequiel Garcia --- drivers/staging/media/hantro/hantro.h | 2 ++ drivers/staging/media/hantro/hantro_drv.c | 9 ++++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h index 83ed25d9657b..06d0f3597694 100644 --- a/drivers/staging/media/hantro/hantro.h +++ b/drivers/staging/media/hantro/hantro.h @@ -75,6 +75,7 @@ struct hantro_irq { * @num_regs: number of register range names in the array * @double_buffer: core needs double buffering * @legacy_regs: core uses legacy register set + * @late_postproc: postproc must be set up at the end of the job */ struct hantro_variant { unsigned int enc_offset; @@ -98,6 +99,7 @@ struct hantro_variant { int num_regs; unsigned int double_buffer : 1; unsigned int legacy_regs : 1; + unsigned int late_postproc : 1; }; /** diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c index 770f4ce71d29..33bf78be145b 100644 --- a/drivers/staging/media/hantro/hantro_drv.c +++ b/drivers/staging/media/hantro/hantro_drv.c @@ -130,7 +130,7 @@ void hantro_start_prepare_run(struct hantro_ctx *ctx) v4l2_ctrl_request_setup(src_buf->vb2_buf.req_obj.req, &ctx->ctrl_handler); - if (!ctx->is_encoder) { + if (!ctx->is_encoder && !ctx->dev->variant->late_postproc) { if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt)) hantro_postproc_enable(ctx); else @@ -142,6 +142,13 @@ void hantro_end_prepare_run(struct hantro_ctx *ctx) { struct vb2_v4l2_buffer *src_buf; + if (!ctx->is_encoder && ctx->dev->variant->late_postproc) { + if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt)) + hantro_postproc_enable(ctx); + else + hantro_postproc_disable(ctx); + } + src_buf = hantro_get_src_buf(ctx); v4l2_ctrl_request_complete(src_buf->vb2_buf.req_obj.req, &ctx->ctrl_handler); From patchwork Mon Nov 29 18:26:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 12645709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B639C433F5 for ; Mon, 29 Nov 2021 21:02:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232048AbhK2VFs (ORCPT ); Mon, 29 Nov 2021 16:05:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232032AbhK2VDs (ORCPT ); Mon, 29 Nov 2021 16:03:48 -0500 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D98D5C125307; Mon, 29 Nov 2021 10:26:47 -0800 (PST) Received: by mail-wr1-x42d.google.com with SMTP id v11so38830562wrw.10; Mon, 29 Nov 2021 10:26:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sfAAyurwbMN8Wc59AsqGd+iq2BYgkQGpfgJfPJ1lW7c=; b=fLt2iFzUdSChTr/aTeldb9kjU60F46BE43DvUyjznt5ELtiK96hsZ10RUuslx7bqEb u5FmjI/zZ/xHZjKI/lmTzGK4k3SyK54Y7j38OxNHM7VblYS7ywAr3YVumRiMD/AIAQPE nB+fyJlmBmpoF1/ADF6MZWDNHkCy5Hm+3pcAMST4d6R4G/4IcR8UixVxZ5IY7sLAXa7S wqbP/SLYIbLM1QrCuto14PR9h+qNVTlpYcpXYUYC3xB7sGryPv15sGDUW4LbUfMcztC4 Omb4ABKSnHumX/cCIICxETDIinB1++F0Sjkzx69/BMR9IExepaUYrNxJUO0TaIaZilfz lH3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sfAAyurwbMN8Wc59AsqGd+iq2BYgkQGpfgJfPJ1lW7c=; b=CVE9y94IeuXub/xoZlPPZ3OtVNNsqjDflh3kXY/ePSvyJjFEQBnP1LBnRFB0CeY/Am l7T3IK+yxMbazOp1+ubW6lMYix7NBSL2iEYtyFDwGa7yf4Ofuhb066zsx+/XqiX6up7M bT/8p3doqJH/NDhSV1xlMFrAPmr+fT/85QoGe1ail5zmikvgJWFMMjtEzslc/mGruhAu McB/HmyO9dB95iTX9wwPeO3QlxhPFWt+sQd4nF5xO2K+3W6isTlx99s3ZCLRS2Wk2n0o n2Wfz5FdLr5sqMbVHzP7Lh+d6ctFkD/44fZ7X1fI4n0JV2247QRlsFx0lQJjN7aM2tg/ fFuA== X-Gm-Message-State: AOAM531D3lofKtRDliaeVy/Rl1OYMa4FnS0zYXOofBd0nmXFQqAl3Wzj UASKclltJBAJelgFkACBP2eyCTleHa6/dg== X-Google-Smtp-Source: ABdhPJzfTwh2g5WVNC332WqhJS6YiHqknDrm94kLGyptSuUtiKwlqNGHB6BzHGMR2MpBNhVitm8PBg== X-Received: by 2002:adf:d1e2:: with SMTP id g2mr37291036wrd.105.1638210406497; Mon, 29 Nov 2021 10:26:46 -0800 (PST) Received: from kista.localdomain (cpe-86-58-29-253.static.triera.net. [86.58.29.253]) by smtp.gmail.com with ESMTPSA id o12sm85907wmq.12.2021.11.29.10.26.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Nov 2021 10:26:46 -0800 (PST) From: Jernej Skrabec To: linux-media@vger.kernel.org Cc: ezequiel@vanguardiasur.com.ar, nicolas.dufresne@collabora.com, mchehab@kernel.org, robh+dt@kernel.org, mripard@kernel.org, wens@csie.org, p.zabel@pengutronix.de, andrzej.p@collabora.com, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Jernej Skrabec Subject: [PATCH v2 6/9] media: hantro: Convert imx8m_vpu_g2_irq to helper Date: Mon, 29 Nov 2021 19:26:30 +0100 Message-Id: <20211129182633.480021-7-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211129182633.480021-1-jernej.skrabec@gmail.com> References: <20211129182633.480021-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org It turns out that imx8m_vpu_g2_irq() doesn't depend on any platform specifics and can be used with other G2 platform drivers too. Move it to common code. Signed-off-by: Jernej Skrabec Reviewed-by: Andrzej Pietrasiewicz Reviewed-by: Ezequiel Garcia --- drivers/staging/media/hantro/hantro_g2.c | 18 ++++++++++++++++++ drivers/staging/media/hantro/hantro_hw.h | 1 + drivers/staging/media/hantro/imx8m_vpu_hw.c | 20 +------------------- 3 files changed, 20 insertions(+), 19 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_g2.c b/drivers/staging/media/hantro/hantro_g2.c index 6f3e1f797f83..ee5f14c5f8f2 100644 --- a/drivers/staging/media/hantro/hantro_g2.c +++ b/drivers/staging/media/hantro/hantro_g2.c @@ -24,3 +24,21 @@ void hantro_g2_check_idle(struct hantro_dev *vpu) } } } + +irqreturn_t hantro_g2_irq(int irq, void *dev_id) +{ + struct hantro_dev *vpu = dev_id; + enum vb2_buffer_state state; + u32 status; + + status = vdpu_read(vpu, G2_REG_INTERRUPT); + state = (status & G2_REG_INTERRUPT_DEC_RDY_INT) ? + VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; + + vdpu_write(vpu, 0, G2_REG_INTERRUPT); + vdpu_write(vpu, G2_REG_CONFIG_DEC_CLK_GATE_E, G2_REG_CONFIG); + + hantro_irq_done(vpu, state); + + return IRQ_HANDLED; +} diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h index dbe51303724b..c33b1f5df37b 100644 --- a/drivers/staging/media/hantro/hantro_hw.h +++ b/drivers/staging/media/hantro/hantro_hw.h @@ -413,5 +413,6 @@ void hantro_g2_vp9_dec_done(struct hantro_ctx *ctx); int hantro_vp9_dec_init(struct hantro_ctx *ctx); void hantro_vp9_dec_exit(struct hantro_ctx *ctx); void hantro_g2_check_idle(struct hantro_dev *vpu); +irqreturn_t hantro_g2_irq(int irq, void *dev_id); #endif /* HANTRO_HW_H_ */ diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c index 1a43f6fceef9..f5991b8e553a 100644 --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c @@ -191,24 +191,6 @@ static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id) return IRQ_HANDLED; } -static irqreturn_t imx8m_vpu_g2_irq(int irq, void *dev_id) -{ - struct hantro_dev *vpu = dev_id; - enum vb2_buffer_state state; - u32 status; - - status = vdpu_read(vpu, G2_REG_INTERRUPT); - state = (status & G2_REG_INTERRUPT_DEC_RDY_INT) ? - VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; - - vdpu_write(vpu, 0, G2_REG_INTERRUPT); - vdpu_write(vpu, G2_REG_CONFIG_DEC_CLK_GATE_E, G2_REG_CONFIG); - - hantro_irq_done(vpu, state); - - return IRQ_HANDLED; -} - static int imx8mq_vpu_hw_init(struct hantro_dev *vpu) { vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1]; @@ -280,7 +262,7 @@ static const struct hantro_irq imx8mq_irqs[] = { }; static const struct hantro_irq imx8mq_g2_irqs[] = { - { "g2", imx8m_vpu_g2_irq }, + { "g2", hantro_g2_irq }, }; static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" }; From patchwork Mon Nov 29 18:26:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 12645707 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70491C4332F for ; Mon, 29 Nov 2021 21:02:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232249AbhK2VFu (ORCPT ); Mon, 29 Nov 2021 16:05:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232040AbhK2VDs (ORCPT ); Mon, 29 Nov 2021 16:03:48 -0500 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7EFD7C12530B; Mon, 29 Nov 2021 10:26:49 -0800 (PST) Received: by mail-wr1-x431.google.com with SMTP id a18so38868883wrn.6; Mon, 29 Nov 2021 10:26:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/ttdy58tm+LmXBv1FcpjRYVHwwZt4Hb7jA/LU/P8ugo=; b=GT26leHjJpkOtelhjyR9gLeFjKdc7gTo+QE2VS7AFybVpDHwh2PozKE1zwaNK4QzDL 3dJ/Q50TckmgrhdX20Uc3DNOOh+patKlwsoxAPFpxrob5PwZdyD7qahwm4ZSb11pYRdo VmXvg7DHyqxFhQ6vQM63ZmYNJUs8jacafS0cR1lLm6g7ikLbVI94JKwAyxXME52g8V44 FAaT+sVskEjC3znsRBO/44prR8E29w4CSmA/PfNdXCyX7rRlr87YyOCotYtPHKjDZ0E+ Eeb3w5YCJeGJSTxbcaYM+FiNMyOrZDhe+PavEpADo8mh+c6gPZON0MYj5PAgbUqs2YdG J4Bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/ttdy58tm+LmXBv1FcpjRYVHwwZt4Hb7jA/LU/P8ugo=; b=EI0JOQSNFg73BpTpakm/Y08SCCU40PpkF20mCRCcj80USThvq/VJXuz2xP/+f67m7b l6kzdV7v1egZvcgtmTTuL7GcrJOXVGfGuWWWLl/7KpgkFrxOUQp3gwc0qyV5iGUeAgHj wGu7VHgvrraKWiCj4WG62BGK635yd8EMYoVt8tRW4nM2nUe9qJj5+OQVFZC8bZ74pTQV JdUy7YTMMt30gKGrSuebyoNgeFeBok76jGM0KQzSuu8AXEu+1LLDNVdqf9S9SjX0U6eF rMaKC9oiBQpl8NbW02/Kk9Ocddu6PDpZSFkWlAOiiBwhggUnq0evomn3mwuVp8Bi9yCe /Eww== X-Gm-Message-State: AOAM532mVLr2K/JzTUw1FQkrQKOcZI0O+fk04PJRSw9zhEI8WvTsY8UE vr9TACfiAxAdjZ8pYDvlLL8c9heUy1YBdQ== X-Google-Smtp-Source: ABdhPJxJjHQhsAjD+1u1olPTV9PDVp6oC2fPjSoeFCbNRtlMuQSFYOaki5HkEpUDwcfnV2Z955wceg== X-Received: by 2002:adf:edc6:: with SMTP id v6mr36102165wro.461.1638210408159; Mon, 29 Nov 2021 10:26:48 -0800 (PST) Received: from kista.localdomain (cpe-86-58-29-253.static.triera.net. [86.58.29.253]) by smtp.gmail.com with ESMTPSA id o12sm85907wmq.12.2021.11.29.10.26.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Nov 2021 10:26:47 -0800 (PST) From: Jernej Skrabec To: linux-media@vger.kernel.org Cc: ezequiel@vanguardiasur.com.ar, nicolas.dufresne@collabora.com, mchehab@kernel.org, robh+dt@kernel.org, mripard@kernel.org, wens@csie.org, p.zabel@pengutronix.de, andrzej.p@collabora.com, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Jernej Skrabec Subject: [PATCH v2 7/9] media: dt-bindings: allwinner: document H6 Hantro G2 binding Date: Mon, 29 Nov 2021 19:26:31 +0100 Message-Id: <20211129182633.480021-8-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211129182633.480021-1-jernej.skrabec@gmail.com> References: <20211129182633.480021-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Allwinner H6 contains older Hantro G2 core, primarly used for VP9 video decoding. It's unclear for now if HEVC is also supported. Describe it's binding. Signed-off-by: Jernej Skrabec Reviewed-by: Rob Herring --- .../media/allwinner,sun50i-h6-vpu-g2.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/allwinner,sun50i-h6-vpu-g2.yaml diff --git a/Documentation/devicetree/bindings/media/allwinner,sun50i-h6-vpu-g2.yaml b/Documentation/devicetree/bindings/media/allwinner,sun50i-h6-vpu-g2.yaml new file mode 100644 index 000000000000..24d7bf21499e --- /dev/null +++ b/Documentation/devicetree/bindings/media/allwinner,sun50i-h6-vpu-g2.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/media/allwinner,sun50i-h6-vpu-g2.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Hantro G2 VPU codec implemented on Allwinner H6 SoC + +maintainers: + - Jernej Skrabec + +description: + Hantro G2 video decode accelerator present on Allwinner H6 SoC. + +properties: + compatible: + const: allwinner,sun50i-h6-vpu-g2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Bus Clock + - description: Module Clock + + clock-names: + items: + - const: bus + - const: mod + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + + video-codec-g2@1c00000 { + compatible = "allwinner,sun50i-h6-vpu-g2"; + reg = <0x01c00000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_VP9>; + }; + +... From patchwork Mon Nov 29 18:26:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 12645711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EC18C4332F for ; Mon, 29 Nov 2021 21:02:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230319AbhK2VFz (ORCPT ); Mon, 29 Nov 2021 16:05:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230334AbhK2VDv (ORCPT ); Mon, 29 Nov 2021 16:03:51 -0500 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB695C12530D; Mon, 29 Nov 2021 10:26:50 -0800 (PST) Received: by mail-wr1-x433.google.com with SMTP id v11so38830808wrw.10; Mon, 29 Nov 2021 10:26:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YMHGW0dp6anAYz4rgdfyvi7/royFZ1sMFGeiqfNvQIU=; b=gElgIbxSyC9FCiyNceHH6WUzrchdMEEscgLDLdrverSUlSVn0bMJs72FU1EHG3PXbF jvP2hmBCSfjUma2EpXMyAigpBf9S6fcuwf4LXInhKDjOqwv9n7BfbywQYwdNcZJh984L IeshE+w+JmothVVWlpUkzzLq31xIxU1GC8LiJ8/NmMBw7Tuvva/wk4fUXcanzEr507YY 8V53voQSb0zVnXOUmUcTf08RR+VsHzmXsiXYsUg0HZeouzUy7TkkPfIz/hSNeSod1hUB Lfg2THnoQvQGe9KDd8XDSWEomXsOz55vZ3l41+OhY4r1U7wN1VXAduXAvxJzwnd3VaKe gJjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YMHGW0dp6anAYz4rgdfyvi7/royFZ1sMFGeiqfNvQIU=; b=i+vpBXXCuglwKJBEi2SF8qLTWrrExs/jWBqsEtJWecIh7vUUjce6V8i4pGaN1RbKiL 7Fdw56Zk1OK4K2Q9csLhG/DB+69FG1FXw5sllsDQBq6ZEUVkXFwTlF3WD3UxBUyMAoeZ 8S8sAdMCSmFWn60Za6OWnMWh2nkkQI6tyXT8QNwpgXrwfP2L36cqV2Hy8kUs6XhTA20N dJeftONnLCiBQ16jW4LW0rWAoZ+BD/kHIh4DoCQ6tAS6/b8S8tXxRuRN5UWpWZ1C9CDx tdpek8hqG5yti/bkHvi9G7tK4B0Jcydt7z6mQSh6aUX/1bCupRgferxmyCmh46CZPDcY 1eLA== X-Gm-Message-State: AOAM5323jqNE+rxGDz28M7HDBKDtcG7iKRuDT11oEigU/gOSfKETnmBR pEM1N4Ez/d4nyC1EmmpEa19e60T+u5fGtg== X-Google-Smtp-Source: ABdhPJw+PDB4R36ntcKkMsy30k0CBQkS2mehLtHVZDkx2QtUgjFMVp+NBWOFc4VjG75Bch+WIoFIZQ== X-Received: by 2002:adf:eb42:: with SMTP id u2mr37209227wrn.521.1638210409597; Mon, 29 Nov 2021 10:26:49 -0800 (PST) Received: from kista.localdomain (cpe-86-58-29-253.static.triera.net. [86.58.29.253]) by smtp.gmail.com with ESMTPSA id o12sm85907wmq.12.2021.11.29.10.26.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Nov 2021 10:26:49 -0800 (PST) From: Jernej Skrabec To: linux-media@vger.kernel.org Cc: ezequiel@vanguardiasur.com.ar, nicolas.dufresne@collabora.com, mchehab@kernel.org, robh+dt@kernel.org, mripard@kernel.org, wens@csie.org, p.zabel@pengutronix.de, andrzej.p@collabora.com, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Jernej Skrabec Subject: [PATCH v2 8/9] media: hantro: Add support for Allwinner H6 Date: Mon, 29 Nov 2021 19:26:32 +0100 Message-Id: <20211129182633.480021-9-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211129182633.480021-1-jernej.skrabec@gmail.com> References: <20211129182633.480021-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Allwinner H6 has a Hantro G2 core used for VP9 decoding. It's not clear at this time if HEVC is also supported or not. Signed-off-by: Jernej Skrabec Acked-by: Andrzej Pietrasiewicz Reviewed-by: Ezequiel Garcia --- drivers/staging/media/hantro/Kconfig | 10 ++- drivers/staging/media/hantro/Makefile | 3 + drivers/staging/media/hantro/hantro_drv.c | 3 + drivers/staging/media/hantro/hantro_hw.h | 1 + drivers/staging/media/hantro/sunxi_vpu_hw.c | 86 +++++++++++++++++++++ 5 files changed, 102 insertions(+), 1 deletion(-) create mode 100644 drivers/staging/media/hantro/sunxi_vpu_hw.c diff --git a/drivers/staging/media/hantro/Kconfig b/drivers/staging/media/hantro/Kconfig index 00a57d88c92e..3c5d833322c8 100644 --- a/drivers/staging/media/hantro/Kconfig +++ b/drivers/staging/media/hantro/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 config VIDEO_HANTRO tristate "Hantro VPU driver" - depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || COMPILE_TEST + depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || ARCH_SUNXI || COMPILE_TEST depends on VIDEO_DEV && VIDEO_V4L2 select MEDIA_CONTROLLER select MEDIA_CONTROLLER_REQUEST_API @@ -40,3 +40,11 @@ config VIDEO_HANTRO_ROCKCHIP default y help Enable support for RK3288, RK3328, and RK3399 SoCs. + +config VIDEO_HANTRO_SUNXI + bool "Hantro VPU Allwinner support" + depends on VIDEO_HANTRO + depends on ARCH_SUNXI || COMPILE_TEST + default y + help + Enable support for H6 SoC. diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile index 28af0a1ee4bf..ebd5ede7bef7 100644 --- a/drivers/staging/media/hantro/Makefile +++ b/drivers/staging/media/hantro/Makefile @@ -33,3 +33,6 @@ hantro-vpu-$(CONFIG_VIDEO_HANTRO_SAMA5D4) += \ hantro-vpu-$(CONFIG_VIDEO_HANTRO_ROCKCHIP) += \ rockchip_vpu_hw.o + +hantro-vpu-$(CONFIG_VIDEO_HANTRO_SUNXI) += \ + sunxi_vpu_hw.o diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c index 33bf78be145b..6a51f39dde56 100644 --- a/drivers/staging/media/hantro/hantro_drv.c +++ b/drivers/staging/media/hantro/hantro_drv.c @@ -620,6 +620,9 @@ static const struct of_device_id of_hantro_match[] = { #endif #ifdef CONFIG_VIDEO_HANTRO_SAMA5D4 { .compatible = "microchip,sama5d4-vdec", .data = &sama5d4_vdec_variant, }, +#endif +#ifdef CONFIG_VIDEO_HANTRO_SUNXI + { .compatible = "allwinner,sun50i-h6-vpu-g2", .data = &sunxi_vpu_variant, }, #endif { /* sentinel */ } }; diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h index c33b1f5df37b..c92a6ec4b187 100644 --- a/drivers/staging/media/hantro/hantro_hw.h +++ b/drivers/staging/media/hantro/hantro_hw.h @@ -308,6 +308,7 @@ extern const struct hantro_variant rk3288_vpu_variant; extern const struct hantro_variant rk3328_vpu_variant; extern const struct hantro_variant rk3399_vpu_variant; extern const struct hantro_variant sama5d4_vdec_variant; +extern const struct hantro_variant sunxi_vpu_variant; extern const struct hantro_postproc_ops hantro_g1_postproc_ops; extern const struct hantro_postproc_ops hantro_g2_postproc_ops; diff --git a/drivers/staging/media/hantro/sunxi_vpu_hw.c b/drivers/staging/media/hantro/sunxi_vpu_hw.c new file mode 100644 index 000000000000..90633406c4eb --- /dev/null +++ b/drivers/staging/media/hantro/sunxi_vpu_hw.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Allwinner Hantro G2 VPU codec driver + * + * Copyright (C) 2021 Jernej Skrabec + */ + +#include + +#include "hantro.h" + +static const struct hantro_fmt sunxi_vpu_postproc_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_NV12, + .codec_mode = HANTRO_MODE_NONE, + .postprocessed = true, + }, +}; + +static const struct hantro_fmt sunxi_vpu_dec_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_NV12_4L4, + .codec_mode = HANTRO_MODE_NONE, + }, + { + .fourcc = V4L2_PIX_FMT_VP9_FRAME, + .codec_mode = HANTRO_MODE_VP9_DEC, + .max_depth = 2, + .frmsize = { + .min_width = 48, + .max_width = 3840, + .step_width = MB_DIM, + .min_height = 48, + .max_height = 2160, + .step_height = MB_DIM, + }, + }, +}; + +static int sunxi_vpu_hw_init(struct hantro_dev *vpu) +{ + clk_set_rate(vpu->clocks[0].clk, 300000000); + + return 0; +} + +static void sunxi_vpu_reset(struct hantro_ctx *ctx) +{ + struct hantro_dev *vpu = ctx->dev; + + reset_control_reset(vpu->resets); +} + +static const struct hantro_codec_ops sunxi_vpu_codec_ops[] = { + [HANTRO_MODE_VP9_DEC] = { + .run = hantro_g2_vp9_dec_run, + .done = hantro_g2_vp9_dec_done, + .reset = sunxi_vpu_reset, + .init = hantro_vp9_dec_init, + .exit = hantro_vp9_dec_exit, + }, +}; + +static const struct hantro_irq sunxi_irqs[] = { + { NULL, hantro_g2_irq }, +}; + +static const char * const sunxi_clk_names[] = { "mod", "bus" }; + +const struct hantro_variant sunxi_vpu_variant = { + .dec_fmts = sunxi_vpu_dec_fmts, + .num_dec_fmts = ARRAY_SIZE(sunxi_vpu_dec_fmts), + .postproc_fmts = sunxi_vpu_postproc_fmts, + .num_postproc_fmts = ARRAY_SIZE(sunxi_vpu_postproc_fmts), + .postproc_ops = &hantro_g2_postproc_ops, + .codec = HANTRO_VP9_DECODER, + .codec_ops = sunxi_vpu_codec_ops, + .init = sunxi_vpu_hw_init, + .irqs = sunxi_irqs, + .num_irqs = ARRAY_SIZE(sunxi_irqs), + .clk_names = sunxi_clk_names, + .num_clocks = ARRAY_SIZE(sunxi_clk_names), + .double_buffer = 1, + .legacy_regs = 1, + .late_postproc = 1, +}; From patchwork Mon Nov 29 18:26:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 12645713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8767C433F5 for ; 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[86.58.29.253]) by smtp.gmail.com with ESMTPSA id o12sm85907wmq.12.2021.11.29.10.26.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Nov 2021 10:26:50 -0800 (PST) From: Jernej Skrabec To: linux-media@vger.kernel.org Cc: ezequiel@vanguardiasur.com.ar, nicolas.dufresne@collabora.com, mchehab@kernel.org, robh+dt@kernel.org, mripard@kernel.org, wens@csie.org, p.zabel@pengutronix.de, andrzej.p@collabora.com, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Jernej Skrabec Subject: [PATCH v2 9/9] arm64: dts: allwinner: h6: Add Hantro G2 node Date: Mon, 29 Nov 2021 19:26:33 +0100 Message-Id: <20211129182633.480021-10-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211129182633.480021-1-jernej.skrabec@gmail.com> References: <20211129182633.480021-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org H6 SoC has a second VPU, dedicated to VP9 decoding. It's a slightly older design, though. Signed-off-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 4c4547f7d0c7..878061e75098 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -153,6 +153,15 @@ mixer0_out_tcon_top_mixer0: endpoint { }; }; + video-codec-g2@1c00000 { + compatible = "allwinner,sun50i-h6-vpu-g2"; + reg = <0x01c00000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_VP9>; + }; + video-codec@1c0e000 { compatible = "allwinner,sun50i-h6-video-engine"; reg = <0x01c0e000 0x2000>;