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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 01/22] x86/cpufeatures: add AMD Collaborative Processor Performance Control feature flag Date: Tue, 30 Nov 2021 20:36:20 +0800 Message-ID: <20211130123641.1449041-2-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9783c71a-336e-4bef-5584-08d9b3fe2017 X-MS-TrafficTypeDiagnostic: CY4PR12MB1896: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jI55RhBrBzR0WNtjJRKAgnE2j+dWND/LmkkqYwsHaYIWDFMf0shMio87dghh+pBHl6vwB7bC1eoRYaok4iZ7i31Jp6j8G9oSybhBrRZnT/upuqhJ5o9j7bbGG/OCFWAk2ZVwdeZTCzGPi42OPtJrs0cXT/58UHfhCJxCPm9UJ8RAdDGQ+fczjueGrM3SPuJtovFdafmTHyAy8OatN8tQYUto09pf6zhmO1Hx5ZsTymFBvepkgy3TFx//HZBL768HPT+k848cuS7gBQ8/2oOiPTRXwVG1YOUy65o25ljlvh0KkXqee46vEs5QHpuKLr2J98icg0LKeUe0Ru8AAhugA89U2bAmNu+FjNxj2FpXtVqPyRsUPvVSxEhU9HVAXhSM6GXeN8as9qXYMCMCH9lEoEE2vpFMQpUsaTZbaRTP/7hWTFMkU2TYFnU7W4cW25o3Z3Umairvkv+KlE2/W1xgOFQqYTPZPTfIr068qx0i6CQy89c++0CNAPClWXwpGkCTRkDHHwICXJUjdYy4bva+I4SgZGQJiMgN7RMnVVXpGhxg7za18f4PPSdzvzP33TraV18XRJFEfPbRuYrdVMFzSk0wVtpLFPPIhLYsJ4Y460pY/N/3X81Ic9I5ilkeafwBS0lMOvlJKL6KGrlzvpoAIBwbVt80ZpfOk3XMYyRU4WoXK1WXUD/h5a0OfyrUxwAjzk4sqAYFW3u1hc2voUpIoBXm+4IMiQLHIz+wpsTlDeeFt0h+GB/lHD4+iJWMY4xSc9JsK2qBb4YHD8gW5eC8I/ODoDZMq5/9zmbDd92/oDA= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(40470700001)(8936002)(8676002)(5660300002)(82310400004)(2906002)(26005)(356005)(186003)(16526019)(426003)(336012)(6666004)(40460700001)(316002)(36756003)(2616005)(110136005)(47076005)(1076003)(36860700001)(81166007)(7696005)(86362001)(70586007)(70206006)(54906003)(4326008)(508600001)(7416002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:37:08.7343 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9783c71a-336e-4bef-5584-08d9b3fe2017 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1896 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add Collaborative Processor Performance Control feature flag for AMD processors. This feature flag will be used on the following amd-pstate driver. The amd-pstate driver has two approaches to implement the frequency control behavior. That depends on the CPU hardware implementation. One is "Full MSR Support" and another is "Shared Memory Support". The feature flag indicates the current processors with "Full MSR Support". Acked-by: Borislav Petkov Signed-off-by: Huang Rui --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index d5b5f2ab87a0..18de5f76f198 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -315,6 +315,7 @@ #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ +#define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ From patchwork Tue Nov 30 12:36:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12647183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92E09C433F5 for ; Tue, 30 Nov 2021 12:37:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241665AbhK3Mkl (ORCPT ); Tue, 30 Nov 2021 07:40:41 -0500 Received: from mail-bn1nam07on2056.outbound.protection.outlook.com ([40.107.212.56]:25730 "EHLO NAM02-BN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241669AbhK3Mkf (ORCPT ); Tue, 30 Nov 2021 07:40:35 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=N8xWhW/Rn+gd3lx9tLlGaHs/oRjUrbggO+XSl1r3z/Mclzm4xkQyYdYhvfngsLvtNwqpBECrFOPA6i3RVzz+liEdW+rw6w44Y9npwlotxAoUBJKP4+0bhQl6Ay3xNOyqc3Gir5/ss6YRDb2tX7h+8mQQ//9BUuUQeaTQcEoKN07T6u471r9bmLtraTHnASX2AqoYifUwzW7fj9GPN/v5TbZhWo5YGqqI4Ct+SEb/6zWosA8BfAZ7yXR4BH8M/6FX99B9DMEf6pJM3ONQVBkjbmXCSk6DKpdjQsio5s+w4fCI6+Sj/AOP9ZTxo9fnERLIPfxvi5PgkwmLqXD/BL5jmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=E8kgyOkrddODGeP9fLYswG8P2mhNQkaTgXSoOqeB0ZY=; b=FJLwutf07a5xilT8W3icv/ZORC4RXN5gvQWOFhagK2QjqEAzgyrkKBD/QQAUFDgzucphLANcCYVPCz/R2FZf0JN6FF86iV5AZqqjAKmaguYndKycn3dZy8VX7ugGliPl1LbI8c2DASWM4hQ4IFZTFcU7B6IIDH7mAo0flqWQk8SW43ed3BXy8Y0jj/zmv8W4Gls4g7kFqKojH6ZckD5sdmcjLJJHk79Hl+f2v/NeNwd6tIeO22I8FXOPIjkIdlGYSkxRlURY+gUutrGFfq7lz/pjnHzQ5+AVelcM9whIvepAGOysLkwIotMtad9V8qFkN1OKQCWWhz9g6zwtwn8Hng== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=E8kgyOkrddODGeP9fLYswG8P2mhNQkaTgXSoOqeB0ZY=; b=Wvim3lBvbEIzmRJZBIpsyD3e2+aSVyLtnBr/I7VlXX7f87WzlyVHHrc2m9YLhFDfXTSDxuv7p7dZTjaxRR5fRjZ0WtDy5Hu0HTxp7y82tVodHQKLbrb+8RKpLpAnvrixtpVQEMCeHEvFu5uyMpCheNJ8dBm/NryEfWIZv2JLGfU= Received: from BN6PR22CA0070.namprd22.prod.outlook.com (2603:10b6:404:ca::32) by MW3PR12MB4506.namprd12.prod.outlook.com (2603:10b6:303:53::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4755.11; Tue, 30 Nov 2021 12:37:12 +0000 Received: from BN8NAM11FT052.eop-nam11.prod.protection.outlook.com (2603:10b6:404:ca:cafe::55) by BN6PR22CA0070.outlook.office365.com (2603:10b6:404:ca::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4734.23 via Frontend Transport; Tue, 30 Nov 2021 12:37:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT052.mail.protection.outlook.com (10.13.177.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Tue, 30 Nov 2021 12:37:12 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 30 Nov 2021 06:37:07 -0600 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 02/22] x86/msr: add AMD CPPC MSR definitions Date: Tue, 30 Nov 2021 20:36:21 +0800 Message-ID: <20211130123641.1449041-3-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f36b207d-ed55-4cae-5d70-08d9b3fe2200 X-MS-TrafficTypeDiagnostic: MW3PR12MB4506: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1107; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iSAgXcVkgFrr6Vby8ZlafW3PHqLol0sOJRZdUijqp4+3amJZ5aWw1dHmKQbqHC1cfjs2XKhnU8wlJAZd6ALojFHj1Mo+LaE8H1t4YHAcFBBhYt5jb74NWiBsOSrnt9cHyNlEwWYKkWaeP6jKjXsJmpUUAK2fBvoWgEkyyMVfgIgTmglcPgBooNgW5r8+TxzHOFyhRvcFTSk6AoZ8gKsHWjfyZcSWXQlmqL0J6BhdrmXOQVZ+BvPTKGW4jCKpg5da94FxKguW8+TQechKFXkjb7Nk1uuSp7v5Y9NopNoVY8igPCJWC0qV9ejN3eKlGqAqrJmd3etY567mYAfMSeF9w/Bha6N0RmiPuq4crsA8FzRBM4z7ALTh+dxs8H6hSMRRy9ajIQe1iA6EqUJ6hxmQWV4shkBpNnMlXcHgvJZ7QaNDg/jsNhloMCZ+9e9d0wbLEo8Lm4C1zIdEfmjVZqspMNAZiooTc4hOCDikOFTIuiMTJLqVRcxgOKBgVH/tn7BkUfgqH762xLZ/l3AkinNPk5LnHxXPFjQi0MgIaCKcFe3CGrANeztOt4tLUYZi3IayvGfeFmz0d6tSMi41Ezh262RS/cc3O4BQ5+5gI2yPWZ7eZTqVOwvJW44ra+W7ptTIesB5T76RcQfCGB8NEqanpujXiuw83To9ojiSLYIwrJAwwcleRwzfZ0Iu0RElEsjeJwZ7kfLsmYspCTtUlM2P+1xaj7cwwXUpTlQiYf8w5M1cmVgHZgHYDA2Hlt5ldzkok7/5OIGIKRFS6x5gSFxedv/xm5z9L2rPhcdT4Y384ZI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(82310400004)(47076005)(7696005)(54906003)(508600001)(110136005)(36860700001)(36756003)(86362001)(40460700001)(316002)(356005)(2906002)(81166007)(4326008)(16526019)(70586007)(70206006)(426003)(336012)(1076003)(5660300002)(7416002)(8936002)(26005)(2616005)(186003)(6666004)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:37:12.2710 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f36b207d-ed55-4cae-5d70-08d9b3fe2200 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT052.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4506 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org AMD CPPC (Collaborative Processor Performance Control) function uses MSR registers to manage the performance hints. So add the MSR register macro here. Signed-off-by: Huang Rui --- arch/x86/include/asm/msr-index.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 01e2650b9585..e7945ef6a8df 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -486,6 +486,23 @@ #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f +/* AMD Collaborative Processor Performance Control MSRs */ +#define MSR_AMD_CPPC_CAP1 0xc00102b0 +#define MSR_AMD_CPPC_ENABLE 0xc00102b1 +#define MSR_AMD_CPPC_CAP2 0xc00102b2 +#define MSR_AMD_CPPC_REQ 0xc00102b3 +#define MSR_AMD_CPPC_STATUS 0xc00102b4 + +#define CAP1_LOWEST_PERF(x) (((x) >> 0) & 0xff) +#define CAP1_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) +#define CAP1_NOMINAL_PERF(x) (((x) >> 16) & 0xff) +#define CAP1_HIGHEST_PERF(x) (((x) >> 24) & 0xff) + +#define REQ_MAX_PERF(x) (((x) & 0xff) << 0) +#define REQ_MIN_PERF(x) (((x) & 0xff) << 8) +#define REQ_DES_PERF(x) (((x) & 0xff) << 16) +#define REQ_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) + /* Fam 17h MSRs */ #define MSR_F17H_IRPERF 0xc00000e9 From patchwork Tue Nov 30 12:36:22 2021 Content-Type: text/plain; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT013.mail.protection.outlook.com (10.13.176.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Tue, 30 Nov 2021 12:37:17 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 30 Nov 2021 06:37:11 -0600 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 03/22] ACPI: CPPC: implement support for SystemIO registers Date: Tue, 30 Nov 2021 20:36:22 +0800 Message-ID: <20211130123641.1449041-4-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2323b4a7-2665-4850-30a2-08d9b3fe2512 X-MS-TrafficTypeDiagnostic: CO6PR12MB5473: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3513; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CnKIjCGqT2hiztbG71ERF94E3efD4yAd4HAENlrSjyURMgPXlkz+uZQSQkeIG2WzZDWBFvmiUuolwz7beaqs8cY2FP9orU5wDbqAGoMXTU1VxKY7FA/LHvkAecnRcHiHoWdWBuJtT/8q91dxp7XAFfVTtXI3E4QJH+8tbM/MrugtV4lJV2vihCJUbl0/RbF2WPpYHli9kqPLp8OXmmUZoZeg4tAxGlBghXIaMgtPOdkcLoSbShtBAkx4pKKn3ORLbfbXbErfbWFqjHMORjDMF1IriYxpP+il2x/mq6ysfgFciWxPXePasNuKGmcROaj9psh2D6ogfrOazEvy+eQmp1J0K2xnjyLbE+chfNqtyMHNpNfwNaH7CMksr4AyUXnBwR4RDtGD7/WVoBFKj5hMsFnH70g213h3PWrAZWHV8YvlFZhgXEZ37oG1dWfLgegHGPo6ioauEH5FOJoIMJUIaqqgU6tQg9MSko/YIQJmUYkmNi6Pg9i37VIt8ZjfG1rZ6/ETqOda+/uJk7CYR2Ma4utgIk2F9JLBDMcZlk8ygFQT9CsVSvOZ2m5swekHJv1mVI1sBs7lLJItn81wfkRoKBIWs7MWiKqrPu8F3+GG2b3lW3n5QgYGy6ooHgwbk7PwhKE+hVYzE4wytdgvBnZYj53xstwBRqnCzfNOGqPNzrrORwRDA1vQrYpNDey7/0KKw6PhEL0y54zRnnTHhzEqgJrIOf1qNpKrRfMMZcvMDnuLbtexXLx/VxQPpi+uL3Vikl6gZOvI1ii8FpNfzWqKcyJbwyXrayrIvO2+bWk6XSw= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(186003)(7696005)(7416002)(8676002)(83380400001)(2616005)(426003)(356005)(70586007)(86362001)(81166007)(8936002)(70206006)(36756003)(16526019)(2906002)(316002)(36860700001)(336012)(82310400004)(54906003)(5660300002)(1076003)(40460700001)(508600001)(6666004)(26005)(4326008)(110136005)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:37:17.4210 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2323b4a7-2665-4850-30a2-08d9b3fe2512 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR12MB5473 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Steven Noonan According to the ACPI v6.2 (and later) specification, SystemIO can be used for _CPC registers. This teaches cppc_acpi how to handle such registers. This patch was tested using the amd_pstate driver on my Zephyrus G15 (model GA503QS) using the current version 410 BIOS, which uses a SystemIO register for the HighestPerformance element in _CPC. Signed-off-by: Steven Noonan Signed-off-by: Huang Rui --- drivers/acpi/cppc_acpi.c | 46 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 43 insertions(+), 3 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index a85c351589be..ca62c3dc9899 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -746,9 +746,24 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr) goto out_free; cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr; } + } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { + if (gas_t->access_width < 1 || gas_t->access_width > 3) { + /* 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit. SystemIO doesn't + * implement 64-bit registers. + */ + pr_debug("Invalid access width %d for SystemIO register\n", + gas_t->access_width); + goto out_free; + } + if (gas_t->address & ~0xFFFFULL) { + /* SystemIO registers use 16-bit integer addresses */ + pr_debug("Invalid IO port %llu for SystemIO register\n", + gas_t->address); + goto out_free; + } } else { if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) { - /* Support only PCC ,SYS MEM and FFH type regs */ + /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */ pr_debug("Unsupported register type: %d\n", gas_t->space_id); goto out_free; } @@ -923,7 +938,20 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) } *val = 0; - if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) + + if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { + u32 width = 8 << (reg->access_width - 1); + acpi_status status; + + status = acpi_os_read_port((acpi_io_address)reg->address, (u32 *)val, width); + + if (status != AE_OK) { + pr_debug("Error: Failed to read SystemIO port %llx\n", reg->address); + return -EFAULT; + } + + return 0; + } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) vaddr = reg_res->sys_mem_vaddr; @@ -962,7 +990,19 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); struct cpc_reg *reg = ®_res->cpc_entry.reg; - if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) + if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { + u32 width = 8 << (reg->access_width - 1); + acpi_status status; + + status = acpi_os_write_port((acpi_io_address)reg->address, (u32)val, width); + + if (status != AE_OK) { + pr_debug("Error: Failed to write SystemIO port %llx\n", reg->address); + return -EFAULT; + } + + return 0; + } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) vaddr = reg_res->sys_mem_vaddr; From patchwork Tue Nov 30 12:36:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12647187 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86D5DC433F5 for ; Tue, 30 Nov 2021 12:37:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241681AbhK3Mkr (ORCPT ); Tue, 30 Nov 2021 07:40:47 -0500 Received: from mail-mw2nam12on2072.outbound.protection.outlook.com ([40.107.244.72]:60512 "EHLO NAM12-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241674AbhK3Mko (ORCPT ); Tue, 30 Nov 2021 07:40:44 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; 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Tue, 30 Nov 2021 12:37:21 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT025.mail.protection.outlook.com (10.13.177.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Tue, 30 Nov 2021 12:37:21 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 30 Nov 2021 06:37:16 -0600 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 04/22] ACPI: CPPC: Check present CPUs for determining _CPC is valid Date: Tue, 30 Nov 2021 20:36:23 +0800 Message-ID: <20211130123641.1449041-5-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 728a1f63-7c0a-4825-52aa-08d9b3fe275e X-MS-TrafficTypeDiagnostic: DM6PR12MB3051: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HRAoRO3bkXg7GQhvdi5USBXu58MlyxgCOTUWhhOJGJdv6EG/Oo1NOcz6ankgr+dh4i4fjH+kKJvHEDtkzLGOOJgjcxfMxtj/H0ZuxETaVTCeL0iIcZpFICLG6KgtJUOnDcvYiIq0ha5r3H2+/ShLNfkHehkZMAUFgBi+bDSMK1DMct4XBbtWnUkwgFwpOEou1xJqRQmS2JqpuKIt3B5hNRgtrgCnFqFkS6U5iDtIDK21ZqsVrw43j9uQ+cPX+MzK3OY71N2H0MngGWUwLBTNB8TMjIcZGvyWqlyvm5OGj3VVihBkrN0RGsHxwKrezHgafaK5UZinoq2p72v1Lx/x5QRBx2EaAtNVbtW2sen0qhdPwHtJmsPRCnYw2nrI0j8VMyC0HGHZK6NryHfQTy2R6ILz4OrQY8PcNeW351ArU6giP1F6iXgDXrot7heHkVlyB0qTei7vhfQQRZqH5VgfmFxnwB812jtVAQ16zhYHvuZPonA0YcAvWLZewB2gjltXOdsrlpuh0UQvQPooddI+W1we+LP42TD18pbX1cn+o6VyJbHmzZN5YguS2LhNZyWSSLZB7MQxo6VBM/+SyXHy1/eawW1pnBJOnVCZF2jjvkLkzgEhtDM1UadiLYWjAQtnxCxrkvzVgviFMDGB+byeS7SApiCrjFw0NYWQs+/n14e6tBpogWltVyC1yfgU9d/407a6pXIhSn9ftwfwu1kag4+VQGLwO5L0wnsDERPbUn4P9pHjk1eFkEMtlR/iLMK5yLmlPx3xJI42pvMEXlyZymsBTFX/06a9g7EwZ49/wWM= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(186003)(81166007)(83380400001)(70586007)(6666004)(36860700001)(82310400004)(4326008)(36756003)(508600001)(2616005)(16526019)(26005)(47076005)(426003)(336012)(7416002)(1076003)(5660300002)(7696005)(356005)(86362001)(54906003)(110136005)(8676002)(316002)(8936002)(2906002)(70206006)(40460700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:37:21.2744 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 728a1f63-7c0a-4825-52aa-08d9b3fe275e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3051 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Mario Limonciello As this is a static check, it should be based upon what is currently present on the system. This makes probeing more deterministic. While local APIC flags field (lapic_flags) of cpu core in MADT table is 0, then the cpu core won't be enabled. In this case, _CPC won't be found in this core, and return back to _CPC invalid with walking through possible cpus (include disable cpus). This is not expected, so switch to check present CPUs instead. Reported-by: Jinzhou Su Signed-off-by: Mario Limonciello Signed-off-by: Huang Rui --- drivers/acpi/cppc_acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index ca62c3dc9899..a46f227dc254 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -411,7 +411,7 @@ bool acpi_cpc_valid(void) struct cpc_desc *cpc_ptr; int cpu; - for_each_possible_cpu(cpu) { + for_each_present_cpu(cpu) { cpc_ptr = per_cpu(cpc_desc_ptr, cpu); if (!cpc_ptr) return false; From patchwork Tue Nov 30 12:36:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12647189 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2AB3C433EF for ; Tue, 30 Nov 2021 12:37:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241672AbhK3MlF (ORCPT ); Tue, 30 Nov 2021 07:41:05 -0500 Received: from mail-bn7nam10on2053.outbound.protection.outlook.com ([40.107.92.53]:9505 "EHLO NAM10-BN7-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241709AbhK3Mku (ORCPT ); Tue, 30 Nov 2021 07:40:50 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=AD2tI7yuzSe2hzEKhDB4ib4Dh998LTf0w4ub6o+qnluweaf6yrmHhTk7ANipwznsyquQan7U9i2m71J44NegTOTREIZnemTUsKbpXtI878AlK4nWwI4eVHoli1u5HLu1/pHpo8JxP2oVLLJuNZknCsA+e0MgMezRSW9z+O1Y9KHICJdLuDhhtzM1v/IxsEy/BN5VzmbuhRaBYhxKb6M2k+f0MSiA91MEzwD53U0oxNK34o7i+TNgQ7LiyAGOV1/UhGgKm5ZfAbw04wtTW45TKHVTT+/1NFSYqdiL3N04D7EraHzOfDldxXEfhFelWrxmEwOwzZFYaIlpEB5KF+A5IQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MWkb2gJJa01lVW9tULlBzYKUUQMaGUZN8bXnAgokfoU=; b=K6NsLDP91i8Wi1Q8ELWR4X9GL3r1YaPiWNGAkqfjYI3Y68w5hpyLsykm3sIlSRHbbJ1+DLmPWS3ZyRST0qfBfnHYi12dRuAI+Mfxkc5lFRhy5j+kvz9z2ZbMzwKjnCR0hn1HEQSIja+AdbsOgeyjaUSND69Oqdsa/tH5N2qs+nXbgHT79sDvnYmlxWJmTrkwjc4AqjeJaU80eSLFRd/TeW9GEx5PQ0+TFsi8A134o97iY2cMGL6J1/JdcXaZgYY6coXLwm/Qhc+odYgdqGmzDHllpkCqV9vXb++dJP+XOfWXMs+eoZ4WaW9nmOZ3uFinT36vB945tprotVyvp79/fQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MWkb2gJJa01lVW9tULlBzYKUUQMaGUZN8bXnAgokfoU=; b=n5aSsGE0r+cIh2taZDlAu3x9nBGquaBjEDsNmllxioqiJC7U84ZD6GRjJ/E2ZOv60hg1LwZUQ+C+A0HWP7TLKNAx5y17aKy5HJ3A+kqSXrfBZr/JYtkRRx9GJ4oWu9ZJ5KEGXhnNxy0In4sK9e+123Z1yui0eK2Yz1Bm6oLrrYA= Received: from BN6PR22CA0049.namprd22.prod.outlook.com (2603:10b6:404:ca::11) by MW2PR12MB2444.namprd12.prod.outlook.com (2603:10b6:907:11::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4734.24; Tue, 30 Nov 2021 12:37:26 +0000 Received: from BN8NAM11FT052.eop-nam11.prod.protection.outlook.com (2603:10b6:404:ca:cafe::5d) by BN6PR22CA0049.outlook.office365.com (2603:10b6:404:ca::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4734.24 via Frontend Transport; Tue, 30 Nov 2021 12:37:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT052.mail.protection.outlook.com (10.13.177.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Tue, 30 Nov 2021 12:37:25 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 30 Nov 2021 06:37:21 -0600 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 05/22] ACPI: CPPC: add cppc enable register function Date: Tue, 30 Nov 2021 20:36:24 +0800 Message-ID: <20211130123641.1449041-6-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f959d106-0c03-4cb4-1f06-08d9b3fe29f6 X-MS-TrafficTypeDiagnostic: MW2PR12MB2444: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: WJ5WMdGgwFi+3Ax/aaXlZbhvHRAqYR/uQimtwMk7kkaC1JcYARJGQLFhgfFDMzNKICC87OhHZnHSx+EcRRTPjH9IM5E07HR4ewXn0qr7LUxiA5Yt6vLJCXWq2B7orVANuTvAYi9NsKT2N1M05Jqgsv1d+B3Is/q/zH2ottCWmo1PLs0f1IZAUnKJbxU/pH07BeiLuA01h5v/pCtrpUqB/OIn8cYnWfOjpPdYkIe9AF1futwiLuns/TfuWjwHUEqclQmeHHhuFRGSztuIt6ZXRAMf5Idj6PfW+em5K/CIPfio21uH+/cvvTnGwgIOIk6uz8HB4KRb1kyODojg9pVOeMSr4b/t/5DcyitxtEGj+90y25pC8i5oW0g3d/snvMr0CbeeXnmgZZFEVD7pvVnfN2fUa8uu4DLJWGm4Sf/YIpwD4R1oFOgVWWpgHaaKd+q7BQeO39OJLRLP5EHDuZ6zjpwKWZuVE/exDOCSEuBI1WJHfpWIfheXE5wkzo9CWacwOevM3KCxNipuWT/B3taUnFazoXAUZ+RdLykoWIrt9P97Cd6JB/p4vi9cbcdIeXXgZOVJ87fG/ugNsAbDzsHs9YJ0YP8wrLd/zQYpv7M+2cp27R3id3nnAiNE+8tiNHM+MY5BRhHR4ec9CICo31jedYZyrRzphbtAbFnaPdYElZivhtGa/JlBBxdsEDV/jnyddMzbgPitmGYNApO5c0vojBL4WsDxRRMQ076wRPhHAjmGZArDaeIv39puowZ5FxaYCFvwjJF+Qqe9Vgv1rC9XR3zdZzYnTAZGrIo0J11D6XY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(54906003)(47076005)(110136005)(316002)(2616005)(82310400004)(70586007)(186003)(508600001)(7416002)(81166007)(83380400001)(16526019)(86362001)(426003)(36860700001)(36756003)(7696005)(8676002)(5660300002)(26005)(1076003)(8936002)(2906002)(356005)(336012)(70206006)(40460700001)(4326008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:37:25.6256 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f959d106-0c03-4cb4-1f06-08d9b3fe29f6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT052.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR12MB2444 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Jinzhou Su Add a new function to enable CPPC feature. This function will write Continuous Performance Control package EnableRegister field on the processor. CPPC EnableRegister register described in section 8.4.7.1 of ACPI 6.4: This element is optional. If supported, contains a resource descriptor with a single Register() descriptor that describes a register to which OSPM writes a One to enable CPPC on this processor. Before this register is set, the processor will be controlled by legacy mechanisms (ACPI Pstates, firmware, etc.). This register will be used for AMD processors to enable amd-pstate function instead of legacy ACPI P-States. Signed-off-by: Jinzhou Su Signed-off-by: Huang Rui --- drivers/acpi/cppc_acpi.c | 45 ++++++++++++++++++++++++++++++++++++++++ include/acpi/cppc_acpi.h | 5 +++++ 2 files changed, 50 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index a46f227dc254..003df9fba122 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1262,6 +1262,51 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) } EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); +/** + * cppc_set_enable - Set to enable CPPC on the processor by writing the + * Continuous Performance Control package EnableRegister field. + * @cpu: CPU for which to enable CPPC register. + * @enable: 0 - disable, 1 - enable CPPC feature on the processor. + * + * Return: 0 for success, -ERRNO or -EIO otherwise. + */ +int cppc_set_enable(int cpu, bool enable) +{ + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cpc_register_resource *enable_reg; + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = -EINVAL; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpu); + return -EINVAL; + } + + enable_reg = &cpc_desc->cpc_regs[ENABLE]; + + if (CPC_IN_PCC(enable_reg)) { + + if (pcc_ss_id < 0) + return -EIO; + + ret = cpc_write(cpu, enable_reg, enable); + if (ret) + return ret; + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + /* after writing CPC, transfer the ownership of PCC to platfrom */ + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); + up_write(&pcc_ss_data->pcc_lock); + return ret; + } + + return cpc_write(cpu, enable_reg, enable); +} +EXPORT_SYMBOL_GPL(cppc_set_enable); + /** * cppc_set_perf - Set a CPU's performance controls. * @cpu: CPU for which to set performance controls. diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index bc159a9b4a73..92b7ea8d8f5e 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -138,6 +138,7 @@ extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); extern int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); +extern int cppc_set_enable(int cpu, bool enable); extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); extern bool acpi_cpc_valid(void); extern int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data); @@ -162,6 +163,10 @@ static inline int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) { return -ENOTSUPP; } +static inline int cppc_set_enable(int cpu, bool enable) +{ + return -ENOTSUPP; +} static inline int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps) { return -ENOTSUPP; From patchwork Tue Nov 30 12:36:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12647193 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66F44C433FE for ; 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Tue, 30 Nov 2021 06:37:25 -0600 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 06/22] cpufreq: amd: introduce a new amd pstate driver to support future processors Date: Tue, 30 Nov 2021 20:36:25 +0800 Message-ID: <20211130123641.1449041-7-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f9ee3fb1-1ce4-41e4-8f8c-08d9b3fe2e92 X-MS-TrafficTypeDiagnostic: SN6PR12MB4734: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CtJdZ1K5gjqW6gdnsztuKYJJAa8SnSC1vDUUEZ5Z8wwLFJRMd9jlrKkwT2qSPfhv8tybtt2wbz+7vNzYWrZiO6ZLOri/WnQtEtMTjjx0fzM7Qc0STjD4xMvcsZ2NTXbQJ0/pBnjkf3vT8Zhg4ZZ2byLiJoKyg0AqqYiZgwCEobw7kdcRlcXOMPM5ATOpD4vBj9rHvWLwFo1YkOZ90lRllqQ+68EqhrDSGfxBQlP5Z5zjwD18VtwmvPNl4tzQBI4oR1xteKLBEY8k1a/NQySiNSQaNEfxzci2ZJO5tD4A4qCOsuUCFXabJWYbTH1ODSCtvZDSQomoVFsHPZ8pwAZ0Wom977YnsY+DNR2bIMYGkOmpbyB5ctcwCUb1K0znV7DjiCYxA4FAFzF3ssfAg4lgsU5GP/AVYxzOlP57XODprGB81W4OzRgQKCg05GO88RtG6EYMoW9Hu2n69nSAmTc5BwjGTWl21w5WXjWNcr8Ayf9FLxH3ohjuM3FAyumMmpSDcn0BoaS79x1Qtc+4FCQfeuEj63mb5ZD4yG11BZq5bEVbM+ZMx7jstm2JNHl1mKSbMwCeNvIBxZmb0hkYUiqz512YgIv6LSgDbrl+OqnAJQ+bYNT9kXFDMuM73ztYRmUve5etMuGvcquJUdGU8+VZ+Eeo/L3pTTl7wH5h/yAeDSzumEl3VGFONXGTw79h27QTXI3ECH4nANSUzfocCehxbhVnygYtssxAO4XFmHX1cZ4UVo3HLdeB4jRsDswl9breWQABHjjX1UmoeiqcfyuleO7c3DqeWE0kvqlZcR5bA5tXHGYkaCJ9jgyk3HI2RAee0mJ/pgWsmjmJoWNTxyTZb4lnapGVwFInWynouFqlh+VPgszab8MDlnUgi26tHd6+ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(186003)(4326008)(83380400001)(508600001)(7696005)(7416002)(8936002)(47076005)(86362001)(26005)(5660300002)(426003)(16526019)(70586007)(70206006)(36756003)(966005)(54906003)(82310400004)(336012)(36860700001)(30864003)(81166007)(316002)(2906002)(2616005)(356005)(8676002)(40460700001)(110136005)(1076003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:37:33.2568 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f9ee3fb1-1ce4-41e4-8f8c-08d9b3fe2e92 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB4734 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org amd-pstate is the AMD CPU performance scaling driver that introduces a new CPU frequency control mechanism on AMD Zen based CPU series in Linux kernel. The new mechanism is based on Collaborative processor performance control (CPPC) which is finer grain frequency management than legacy ACPI hardware P-States. Current AMD CPU platforms are using the ACPI P-states driver to manage CPU frequency and clocks with switching only in 3 P-states. AMD P-States is to replace the ACPI P-states controls, allows a flexible, low-latency interface for the Linux kernel to directly communicate the performance hints to hardware. "amd-pstate" leverages the Linux kernel governors such as *schedutil*, *ondemand*, etc. to manage the performance hints which are provided by CPPC hardware functionality. The first version for amd-pstate is to support one of the Zen3 processors, and we will support more in future after we verify the hardware and SBIOS functionalities. There are two types of hardware implementations for amd-pstate: one is full MSR support and another is shared memory support. It can use X86_FEATURE_CPPC feature flag to distinguish the different types. Using the new AMD P-States method + kernel governors (*schedutil*, *ondemand*, ...) to manage the frequency update is the most appropriate bridge between AMD Zen based hardware processor and Linux kernel, the processor is able to adjust to the most efficiency frequency according to the kernel scheduler loading. Please check the detailed CPU feature and MSR register description in Processor Programming Reference (PPR) for AMD Family 19h Model 51h, Revision A1 Processors: https://www.amd.com/system/files/TechDocs/56569-A1-PUB.zip Signed-off-by: Huang Rui --- drivers/cpufreq/Kconfig.x86 | 17 ++ drivers/cpufreq/Makefile | 1 + drivers/cpufreq/amd-pstate.c | 398 +++++++++++++++++++++++++++++++++++ 3 files changed, 416 insertions(+) create mode 100644 drivers/cpufreq/amd-pstate.c diff --git a/drivers/cpufreq/Kconfig.x86 b/drivers/cpufreq/Kconfig.x86 index 92701a18bdd9..21837eb1698b 100644 --- a/drivers/cpufreq/Kconfig.x86 +++ b/drivers/cpufreq/Kconfig.x86 @@ -34,6 +34,23 @@ config X86_PCC_CPUFREQ If in doubt, say N. +config X86_AMD_PSTATE + tristate "AMD Processor P-State driver" + depends on X86 + select ACPI_PROCESSOR if ACPI + select ACPI_CPPC_LIB if X86_64 && ACPI + select CPU_FREQ_GOV_SCHEDUTIL if SMP + help + This driver adds a CPUFreq driver which utilizes a fine grain + processor performance frequency control range instead of legacy + performance levels. This driver supports the AMD processors with + _CPC object in the SBIOS. + + For details, take a look at: + . + + If in doubt, say N. + config X86_ACPI_CPUFREQ tristate "ACPI Processor P-States driver" depends on ACPI_PROCESSOR diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 48ee5859030c..c8d307010922 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_CPUFREQ_DT_PLATDEV) += cpufreq-dt-platdev.o # speedstep-* is preferred over p4-clockmod. obj-$(CONFIG_X86_ACPI_CPUFREQ) += acpi-cpufreq.o +obj-$(CONFIG_X86_AMD_PSTATE) += amd-pstate.o obj-$(CONFIG_X86_POWERNOW_K8) += powernow-k8.o obj-$(CONFIG_X86_PCC_CPUFREQ) += pcc-cpufreq.o obj-$(CONFIG_X86_POWERNOW_K6) += powernow-k6.o diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c new file mode 100644 index 000000000000..20ffbc30118f --- /dev/null +++ b/drivers/cpufreq/amd-pstate.c @@ -0,0 +1,398 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * amd-pstate.c - AMD Processor P-state Frequency Driver + * + * Copyright (C) 2021 Advanced Micro Devices, Inc. All Rights Reserved. + * + * Author: Huang Rui + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#define AMD_PSTATE_TRANSITION_LATENCY 0x20000 +#define AMD_PSTATE_TRANSITION_DELAY 500 + +static struct cpufreq_driver amd_pstate_driver; + +struct amd_cpudata { + int cpu; + + struct freq_qos_request req[2]; + + u64 cppc_req_cached; + + u32 highest_perf; + u32 nominal_perf; + u32 lowest_nonlinear_perf; + u32 lowest_perf; + + u32 max_freq; + u32 min_freq; + u32 nominal_freq; + u32 lowest_nonlinear_freq; +}; + +static inline int pstate_enable(bool enable) +{ + return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable); +} + +DEFINE_STATIC_CALL(amd_pstate_enable, pstate_enable); + +static inline int amd_pstate_enable(bool enable) +{ + return static_call(amd_pstate_enable)(enable); +} + +static int pstate_init_perf(struct amd_cpudata *cpudata) +{ + u64 cap1; + + int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, + &cap1); + if (ret) + return ret; + + /* + * TODO: Introduce AMD specific power feature. + * + * CPPC entry doesn't indicate the highest performance in some ASICs. + */ + WRITE_ONCE(cpudata->highest_perf, amd_get_highest_perf()); + + WRITE_ONCE(cpudata->nominal_perf, CAP1_NOMINAL_PERF(cap1)); + WRITE_ONCE(cpudata->lowest_nonlinear_perf, CAP1_LOWNONLIN_PERF(cap1)); + WRITE_ONCE(cpudata->lowest_perf, CAP1_LOWEST_PERF(cap1)); + + return 0; +} + +DEFINE_STATIC_CALL(amd_pstate_init_perf, pstate_init_perf); + +static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata) +{ + return static_call(amd_pstate_init_perf)(cpudata); +} + +static void pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf, + u32 des_perf, u32 max_perf, bool fast_switch) +{ + if (fast_switch) + wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached)); + else + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, + READ_ONCE(cpudata->cppc_req_cached)); +} + +DEFINE_STATIC_CALL(amd_pstate_update_perf, pstate_update_perf); + +static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata, + u32 min_perf, u32 des_perf, + u32 max_perf, bool fast_switch) +{ + static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf, + max_perf, fast_switch); +} + +static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, + u32 des_perf, u32 max_perf, bool fast_switch) +{ + u64 prev = READ_ONCE(cpudata->cppc_req_cached); + u64 value = prev; + + value &= ~REQ_MIN_PERF(~0L); + value |= REQ_MIN_PERF(min_perf); + + value &= ~REQ_DES_PERF(~0L); + value |= REQ_DES_PERF(des_perf); + + value &= ~REQ_MAX_PERF(~0L); + value |= REQ_MAX_PERF(max_perf); + + if (value == prev) + return; + + WRITE_ONCE(cpudata->cppc_req_cached, value); + + amd_pstate_update_perf(cpudata, min_perf, des_perf, + max_perf, fast_switch); +} + +static int amd_pstate_verify(struct cpufreq_policy_data *policy) +{ + cpufreq_verify_within_cpu_limits(policy); + + return 0; +} + +static int amd_pstate_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + struct cpufreq_freqs freqs; + struct amd_cpudata *cpudata = policy->driver_data; + unsigned long max_perf, min_perf, des_perf, cap_perf; + + if (!cpudata->max_freq) + return -ENODEV; + + cap_perf = READ_ONCE(cpudata->highest_perf); + min_perf = READ_ONCE(cpudata->lowest_nonlinear_perf); + max_perf = cap_perf; + + freqs.old = policy->cur; + freqs.new = target_freq; + + des_perf = DIV_ROUND_CLOSEST(target_freq * cap_perf, + cpudata->max_freq); + + cpufreq_freq_transition_begin(policy, &freqs); + amd_pstate_update(cpudata, min_perf, des_perf, + max_perf, false); + cpufreq_freq_transition_end(policy, &freqs, false); + + return 0; +} + +static int amd_get_min_freq(struct amd_cpudata *cpudata) +{ + struct cppc_perf_caps cppc_perf; + + int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); + if (ret) + return ret; + + /* Switch to khz */ + return cppc_perf.lowest_freq * 1000; +} + +static int amd_get_max_freq(struct amd_cpudata *cpudata) +{ + struct cppc_perf_caps cppc_perf; + u32 max_perf, max_freq, nominal_freq, nominal_perf; + u64 boost_ratio; + + int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); + if (ret) + return ret; + + nominal_freq = cppc_perf.nominal_freq; + nominal_perf = READ_ONCE(cpudata->nominal_perf); + max_perf = READ_ONCE(cpudata->highest_perf); + + boost_ratio = div_u64(max_perf << SCHED_CAPACITY_SHIFT, + nominal_perf); + + max_freq = nominal_freq * boost_ratio >> SCHED_CAPACITY_SHIFT; + + /* Switch to khz */ + return max_freq * 1000; +} + +static int amd_get_nominal_freq(struct amd_cpudata *cpudata) +{ + struct cppc_perf_caps cppc_perf; + + int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); + if (ret) + return ret; + + /* Switch to khz */ + return cppc_perf.nominal_freq * 1000; +} + +static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata) +{ + struct cppc_perf_caps cppc_perf; + u32 lowest_nonlinear_freq, lowest_nonlinear_perf, + nominal_freq, nominal_perf; + u64 lowest_nonlinear_ratio; + + int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); + if (ret) + return ret; + + nominal_freq = cppc_perf.nominal_freq; + nominal_perf = READ_ONCE(cpudata->nominal_perf); + + lowest_nonlinear_perf = cppc_perf.lowest_nonlinear_perf; + + lowest_nonlinear_ratio = div_u64(lowest_nonlinear_perf << SCHED_CAPACITY_SHIFT, + nominal_perf); + + lowest_nonlinear_freq = nominal_freq * lowest_nonlinear_ratio >> SCHED_CAPACITY_SHIFT; + + /* Switch to khz */ + return lowest_nonlinear_freq * 1000; +} + +static int amd_pstate_cpu_init(struct cpufreq_policy *policy) +{ + int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; + struct device *dev; + struct amd_cpudata *cpudata; + + dev = get_cpu_device(policy->cpu); + if (!dev) + return -ENODEV; + + cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL); + if (!cpudata) + return -ENOMEM; + + cpudata->cpu = policy->cpu; + + ret = amd_pstate_init_perf(cpudata); + if (ret) + goto free_cpudata1; + + min_freq = amd_get_min_freq(cpudata); + max_freq = amd_get_max_freq(cpudata); + nominal_freq = amd_get_nominal_freq(cpudata); + lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata); + + if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) { + dev_err(dev, "min_freq(%d) or max_freq(%d) value is incorrect\n", + min_freq, max_freq); + ret = -EINVAL; + goto free_cpudata1; + } + + policy->cpuinfo.transition_latency = AMD_PSTATE_TRANSITION_LATENCY; + policy->transition_delay_us = AMD_PSTATE_TRANSITION_DELAY; + + policy->min = min_freq; + policy->max = max_freq; + + policy->cpuinfo.min_freq = min_freq; + policy->cpuinfo.max_freq = max_freq; + + /* It will be updated by governor */ + policy->cur = policy->cpuinfo.min_freq; + + ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], + FREQ_QOS_MIN, policy->cpuinfo.min_freq); + if (ret < 0) { + dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); + goto free_cpudata1; + } + + ret = freq_qos_add_request(&policy->constraints, &cpudata->req[1], + FREQ_QOS_MAX, policy->cpuinfo.max_freq); + if (ret < 0) { + dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); + goto free_cpudata2; + } + + /* Initial processor data capability frequencies */ + cpudata->max_freq = max_freq; + cpudata->min_freq = min_freq; + cpudata->nominal_freq = nominal_freq; + cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq; + + policy->driver_data = cpudata; + + return 0; + +free_cpudata2: + freq_qos_remove_request(&cpudata->req[0]); +free_cpudata1: + kfree(cpudata); + return ret; +} + +static int amd_pstate_cpu_exit(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata; + + cpudata = policy->driver_data; + + freq_qos_remove_request(&cpudata->req[1]); + freq_qos_remove_request(&cpudata->req[0]); + kfree(cpudata); + + return 0; +} + +static struct cpufreq_driver amd_pstate_driver = { + .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, + .verify = amd_pstate_verify, + .target = amd_pstate_target, + .init = amd_pstate_cpu_init, + .exit = amd_pstate_cpu_exit, + .name = "amd-pstate", +}; + +static int __init amd_pstate_init(void) +{ + int ret; + + if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) + return -ENODEV; + + if (!acpi_cpc_valid()) { + pr_debug("the _CPC object is not present in SBIOS\n"); + return -ENODEV; + } + + /* don't keep reloading if cpufreq_driver exists */ + if (cpufreq_get_current_driver()) + return -EEXIST; + + /* capability check */ + if (!boot_cpu_has(X86_FEATURE_CPPC)) { + pr_debug("AMD CPPC MSR based functionality is not supported\n"); + return -ENODEV; + } + + /* enable amd pstate feature */ + ret = amd_pstate_enable(true); + if (ret) { + pr_err("failed to enable amd-pstate with return %d\n", ret); + return ret; + } + + ret = cpufreq_register_driver(&amd_pstate_driver); + if (ret) + pr_err("failed to register amd_pstate_driver with return %d\n", + ret); + + return ret; +} + +static void __exit amd_pstate_exit(void) +{ + cpufreq_unregister_driver(&amd_pstate_driver); + + amd_pstate_enable(false); +} + +module_init(amd_pstate_init); +module_exit(amd_pstate_exit); + +MODULE_AUTHOR("Huang Rui "); +MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver"); +MODULE_LICENSE("GPL"); From patchwork Tue Nov 30 12:36:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12647191 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B651C433EF for ; Tue, 30 Nov 2021 12:37:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241704AbhK3MlI (ORCPT ); Tue, 30 Nov 2021 07:41:08 -0500 Received: from mail-bn8nam08on2072.outbound.protection.outlook.com ([40.107.100.72]:31328 "EHLO NAM04-BN8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241732AbhK3Mk5 (ORCPT ); Tue, 30 Nov 2021 07:40:57 -0500 ARC-Seal: i=1; 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Tue, 30 Nov 2021 12:37:34 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT028.mail.protection.outlook.com (10.13.176.225) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Tue, 30 Nov 2021 12:37:34 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 30 Nov 2021 06:37:30 -0600 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 07/22] cpufreq: amd: add fast switch function for amd-pstate Date: Tue, 30 Nov 2021 20:36:26 +0800 Message-ID: <20211130123641.1449041-8-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1628b16a-ff6f-452a-ca0c-08d9b3fe2f7c X-MS-TrafficTypeDiagnostic: DM5PR12MB1706: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2803; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gL+573lm3TxsYXa70C6MMh1Pb6C/Hnpi1SxarKAvneZiHo7wWiWYVpFghxpvc5nS6WcrWy7eIUPtyXr5wTJHHGJS0mBGmgggRDWrHVo0RAn0FH8aMNAmtMLUORhMA8E5EDrObE2eN8SWx4YgqymNoPcFMa0O46rGXgQZ2Y7sGFyFBX6ArEAeiA3dFdyXpykuKyYIeNJ/zzO3ZLac3qnzCgrotGvfE38m7GA624ajEZgGrE0koVuINocIMkF+4XxXz4AuJ0gXefE8AaLA+oTkcofwIvIJIblpANXgcHDtGYDVW3T7UABZNobRlG0VQqQfltTcXYJL7s9X3mz9D6btAbJ4xnEfvpDx8NnrKcyLSXfX3hY3IViWPcMyOwVNrb6CPZapcXo0+9T1QrLrs60cdwXjFQHWOGCs5JPn8Z5WL+eJ9fAp1Xikatt5yXk0et+NhjQA7Bpmkxn0fIoYq4iCzwhE02Wyp3Y7DLj1oaMhwLFFCmljD5GtyS49Q2T+bwbpcaXmap5KBmQr/9/ezPNNYoXHkxegmjqFVGsjs1oCwRg107iWh6LQuB5TDvNrqeiZ435D+AdzyEF/8uuz4Kwb6mztujCLVq9Lu+VFDNSRTr98aL0Q76lz3u/eRbdB1kLk3hPlISQzgnRmOzmq6WHyhOUrZOsgYUzB6mc0/pHVLbC1FNLBG1Qogom5qaoagVl3Gg36ZTKcKfD3BKkrdnVQNStiR8odzlrguqNkhMknTCAg1nVIi6cOT88oYmVWxxp5ISigzeX/0NUETsn2aCMU9ZIL+2WblW6IRDIswkFRQjU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(40470700001)(7696005)(2616005)(1076003)(8676002)(7416002)(47076005)(86362001)(36756003)(356005)(81166007)(110136005)(186003)(5660300002)(36860700001)(54906003)(82310400004)(336012)(70586007)(83380400001)(70206006)(2906002)(316002)(26005)(6666004)(16526019)(508600001)(8936002)(426003)(4326008)(40460700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:37:34.5800 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1628b16a-ff6f-452a-ca0c-08d9b3fe2f7c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1706 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce the fast switch function for amd-pstate on the AMD processors which support the full MSR register control. It's able to decrease the latency on interrupt context. Signed-off-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 20ffbc30118f..cab266b8bf35 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -177,6 +177,39 @@ static int amd_pstate_target(struct cpufreq_policy *policy, return 0; } +static void amd_pstate_adjust_perf(unsigned int cpu, + unsigned long _min_perf, + unsigned long target_perf, + unsigned long capacity) +{ + unsigned long max_perf, min_perf, des_perf, + cap_perf, lowest_nonlinear_perf; + struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); + struct amd_cpudata *cpudata = policy->driver_data; + + cap_perf = READ_ONCE(cpudata->highest_perf); + lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf); + + des_perf = cap_perf; + if (target_perf < capacity) + des_perf = DIV_ROUND_UP(cap_perf * target_perf, capacity); + + min_perf = READ_ONCE(cpudata->highest_perf); + if (_min_perf < capacity) + min_perf = DIV_ROUND_UP(cap_perf * _min_perf, capacity); + + if (min_perf < lowest_nonlinear_perf) + min_perf = lowest_nonlinear_perf; + + max_perf = cap_perf; + if (max_perf < min_perf) + max_perf = min_perf; + + des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf); + + amd_pstate_update(cpudata, min_perf, des_perf, max_perf, true); +} + static int amd_get_min_freq(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; @@ -293,6 +326,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) /* It will be updated by governor */ policy->cur = policy->cpuinfo.min_freq; + policy->fast_switch_possible = true; + ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], FREQ_QOS_MIN, policy->cpuinfo.min_freq); if (ret < 0) { @@ -341,6 +376,7 @@ static struct cpufreq_driver amd_pstate_driver = { .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, .verify = amd_pstate_verify, .target = amd_pstate_target, + .adjust_perf = amd_pstate_adjust_perf, .init = amd_pstate_cpu_init, .exit = amd_pstate_cpu_exit, .name = "amd-pstate", From patchwork Tue Nov 30 12:36:27 2021 Content-Type: text/plain; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT063.mail.protection.outlook.com (10.13.177.110) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Tue, 30 Nov 2021 12:37:39 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 30 Nov 2021 06:37:34 -0600 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 08/22] cpufreq: amd: introduce the support for the processors with shared memory solution Date: Tue, 30 Nov 2021 20:36:27 +0800 Message-ID: <20211130123641.1449041-9-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1b16d09c-0130-46ba-ff43-08d9b3fe3226 X-MS-TrafficTypeDiagnostic: DM6PR12MB3113: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /YgQahlvxlsvTfugCfxYsbZVe3AHOF3MMU+t6Mfzs0n5UPmaavzOLNB7dNxLWJ+4e+01GXPFpOO423WvQyPOyfLwsBdrYN/g4ahN8LvsnfaSnU8mAgvZsuBOYWv8A0Kc0ydvYpNJGAqgv1YnaJYvga5Z3POi3bhDjj/8jOpZdhE4Aa9qVltgvG4uK7AGjv6rSH/U7BGcM0uMCGMCCbbV0mTRzpfeML/w04dm4ZziTJZUm/3vcEhhkhO9meeIQiGvyKCxUWbcuFJDm+EJ4Au0W3QxPx4KiggSVMeshuZgWKQdktgtjSPH8G3wZd1nMt4SmB/H78jW6C3OvxlcTxGWbP+f9PqHLml2wlccV78Ey5Yn8m7EbmqzNuWZmWKThPVAcOcySeEiA+e76kGMBjZzLtvzUmg1OOUGL5MIQl3iJsA7MHOBQV9yC+7F++p+dmcPnfHA2urNmHiIU/kp6NxbFrhqGevITIxFlWVF19o56rEZ+U4ACrvEkOJQxbV5/ZZYlCFjpQxIkgT6LPZEf+3c5bXjJ/h24dCm8aZ2kgJlPEU61vyzjtJLOSbdy/w9orGf8TGmiLoYyiLLGnnN7UOZghvbM2cvq0JzoHUxyel3LvRPsht/aHr9RLN2psa4SUN7JfWCnit3Ynwibh6LCqxA+mbYt0g/K92xvYiQa/7FW4Z9cgcvUHkYr2IcX72kchRjXtW+/7dZ+5ZOgUvFL3KqcBEd4iVpV9rS/xAD2+TQEepyQgI7x6mCW2hM0+JRUUW8lZjS+IEFimvhK9sx1V6qgTpGNjljMQu1qVJP44WyvSM= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(5660300002)(2616005)(110136005)(426003)(186003)(508600001)(7416002)(16526019)(356005)(4326008)(8936002)(26005)(54906003)(86362001)(83380400001)(316002)(1076003)(8676002)(6666004)(81166007)(36756003)(336012)(82310400004)(36860700001)(70206006)(47076005)(2906002)(40460700001)(7696005)(70586007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:37:39.3307 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b16d09c-0130-46ba-ff43-08d9b3fe3226 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3113 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org In some of Zen2 and Zen3 based processors, they are using the shared memory that exposed from ACPI SBIOS. In this kind of the processors, there is no MSR support, so we add acpi cppc function as the backend for them. It is using a module param (shared_mem) to enable related processors manually. We will enable this by default once we address performance issue on this solution. Signed-off-by: Jinzhou Su Signed-off-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 72 ++++++++++++++++++++++++++++++++++-- 1 file changed, 68 insertions(+), 4 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index cab266b8bf35..68991c450fd5 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -35,6 +35,19 @@ #define AMD_PSTATE_TRANSITION_LATENCY 0x20000 #define AMD_PSTATE_TRANSITION_DELAY 500 +/* TODO: We need more time to fine tune processors with shared memory solution + * with community together. + * + * There are some performance drops on the CPU benchmarks which reports from + * Suse. We are co-working with them to fine tune the shared memory solution. So + * we disable it by default to go acpi-cpufreq on these processors and add a + * module parameter to be able to enable it manually for debugging. + */ +static bool shared_mem = false; +module_param(shared_mem, bool, 0444); +MODULE_PARM_DESC(shared_mem, + "enable amd-pstate on processors with shared memory solution (false = disabled (default), true = enabled)"); + static struct cpufreq_driver amd_pstate_driver; struct amd_cpudata { @@ -60,6 +73,19 @@ static inline int pstate_enable(bool enable) return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable); } +static int cppc_enable(bool enable) +{ + int cpu, ret = 0; + + for_each_online_cpu(cpu) { + ret = cppc_set_enable(cpu, enable); + if (ret) + return ret; + } + + return ret; +} + DEFINE_STATIC_CALL(amd_pstate_enable, pstate_enable); static inline int amd_pstate_enable(bool enable) @@ -90,6 +116,24 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) return 0; } +static int cppc_init_perf(struct amd_cpudata *cpudata) +{ + struct cppc_perf_caps cppc_perf; + + int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); + if (ret) + return ret; + + WRITE_ONCE(cpudata->highest_perf, amd_get_highest_perf()); + + WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); + WRITE_ONCE(cpudata->lowest_nonlinear_perf, + cppc_perf.lowest_nonlinear_perf); + WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf); + + return 0; +} + DEFINE_STATIC_CALL(amd_pstate_init_perf, pstate_init_perf); static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata) @@ -107,6 +151,19 @@ static void pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf, READ_ONCE(cpudata->cppc_req_cached)); } +static void cppc_update_perf(struct amd_cpudata *cpudata, + u32 min_perf, u32 des_perf, + u32 max_perf, bool fast_switch) +{ + struct cppc_perf_ctrls perf_ctrls; + + perf_ctrls.max_perf = max_perf; + perf_ctrls.min_perf = min_perf; + perf_ctrls.desired_perf = des_perf; + + cppc_set_perf(cpudata->cpu, &perf_ctrls); +} + DEFINE_STATIC_CALL(amd_pstate_update_perf, pstate_update_perf); static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata, @@ -326,7 +383,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) /* It will be updated by governor */ policy->cur = policy->cpuinfo.min_freq; - policy->fast_switch_possible = true; + if (boot_cpu_has(X86_FEATURE_CPPC)) + policy->fast_switch_possible = true; ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], FREQ_QOS_MIN, policy->cpuinfo.min_freq); @@ -376,7 +434,6 @@ static struct cpufreq_driver amd_pstate_driver = { .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, .verify = amd_pstate_verify, .target = amd_pstate_target, - .adjust_perf = amd_pstate_adjust_perf, .init = amd_pstate_cpu_init, .exit = amd_pstate_cpu_exit, .name = "amd-pstate", @@ -399,8 +456,15 @@ static int __init amd_pstate_init(void) return -EEXIST; /* capability check */ - if (!boot_cpu_has(X86_FEATURE_CPPC)) { - pr_debug("AMD CPPC MSR based functionality is not supported\n"); + if (boot_cpu_has(X86_FEATURE_CPPC)) { + pr_debug("AMD CPPC MSR based functionality is supported\n"); + amd_pstate_driver.adjust_perf = amd_pstate_adjust_perf; + } else if (shared_mem) { + static_call_update(amd_pstate_enable, cppc_enable); + static_call_update(amd_pstate_init_perf, cppc_init_perf); + static_call_update(amd_pstate_update_perf, cppc_update_perf); + } else { + pr_info("This processor supports shared memory solution, you can enable it with amd_pstate.shared_mem=1\n"); return -ENODEV; } From patchwork Tue Nov 30 12:36:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12647197 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2EA3C433F5 for ; Tue, 30 Nov 2021 12:38:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241843AbhK3MlX (ORCPT ); Tue, 30 Nov 2021 07:41:23 -0500 Received: from mail-bn1nam07on2084.outbound.protection.outlook.com ([40.107.212.84]:38403 "EHLO NAM02-BN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241710AbhK3MlG (ORCPT ); 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Tue, 30 Nov 2021 12:37:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT038.mail.protection.outlook.com (10.13.176.246) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Tue, 30 Nov 2021 12:37:43 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 30 Nov 2021 06:37:39 -0600 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 09/22] cpufreq: amd: add trace for amd-pstate module Date: Tue, 30 Nov 2021 20:36:28 +0800 Message-ID: <20211130123641.1449041-10-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 96306f62-5cfa-4854-6c63-08d9b3fe34c4 X-MS-TrafficTypeDiagnostic: DM5PR12MB1833: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:635; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: G4UB27Qr5/d00KUUEArs9/Kae0XMvgYkeDmTxj0q9cu5/97DEpMcIIM6uXPIqGM8pzjZqzEgtNvSqIYc8+FZuHtV3K1eB5+yuqz+KI6+IwlJJXhe3tZJDQWxvq/CYJvI0TxPU3sNg3cdEh8qLbna+e3bmWxCDGf7F/MUzipwM/iQ3pjAUdeu/mt2Pv1X/P0sg5Sd58vpJb1iLW1y/Ale1TE00C6OKfmLY1srRo/FkXHIC/0LPAHRFSG/I90rrpTlW7/c30+Xw2RHmn33/2YxvJr/qKFUk2YSE2K6LUXKNdSfqcf8+2jQFQxiiHR9WmImykc3HToCJtkGcgDlWA5MHEnW1KhzPSc68j4yp4yJ4JtjqbkVeyX8kDp0dgAh3IwmyuJ6COcQ6BBQ/okr8d9SFo5apoE3Ts0+jWAqeDSjzT10zWVLL43OLcyR/sdWVQQk6X0Ljshv1Wnbp2LtJRETjpLcbxx/emZxCwClNfmk6iwlD5OMMOKdiv5gxz+q2EqrnggOP97aedvmFLyYO+FuNxziBZAc7QaiUg6SfwZZwM/f4FztozsLRdxGr5Q90DdtO9UgeiLAKIlEOn/UuocxoSnKkcdH/fGO12LvnnWbj/PpyqVcODPDKI38yBBA0piBajJYxlclgLqdgn/ZKUk1JLTAr7wtgW1GO+8ARAw5I+rZCPv89K65WSjKn20FjpSg65+SjEUambSlsBDIbsvCJNnDairMktuAnYGzHQAqkJ2RAynxnvWkmIJMcqJY7gQRkFF5sgU84N9LZS5O2g3+wZYktKWRl3gtSgiGhwtYoJ8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(40470700001)(7696005)(2906002)(186003)(16526019)(426003)(70206006)(36756003)(508600001)(26005)(1076003)(86362001)(4326008)(82310400004)(5660300002)(70586007)(8936002)(8676002)(110136005)(6666004)(336012)(7416002)(316002)(54906003)(47076005)(356005)(36860700001)(81166007)(2616005)(40460700001)(83380400001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:37:43.7559 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96306f62-5cfa-4854-6c63-08d9b3fe34c4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1833 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add trace event to monitor the performance value changes which is controlled by cpu governors. Signed-off-by: Huang Rui --- drivers/cpufreq/Makefile | 6 ++- drivers/cpufreq/amd-pstate-trace.c | 2 + drivers/cpufreq/amd-pstate-trace.h | 77 ++++++++++++++++++++++++++++++ drivers/cpufreq/amd-pstate.c | 4 ++ 4 files changed, 88 insertions(+), 1 deletion(-) create mode 100644 drivers/cpufreq/amd-pstate-trace.c create mode 100644 drivers/cpufreq/amd-pstate-trace.h diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index c8d307010922..285de70af877 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -17,6 +17,10 @@ obj-$(CONFIG_CPU_FREQ_GOV_ATTR_SET) += cpufreq_governor_attr_set.o obj-$(CONFIG_CPUFREQ_DT) += cpufreq-dt.o obj-$(CONFIG_CPUFREQ_DT_PLATDEV) += cpufreq-dt-platdev.o +# Traces +CFLAGS_amd-pstate-trace.o := -I$(src) +amd_pstate-y := amd-pstate.o amd-pstate-trace.o + ################################################################################## # x86 drivers. # Link order matters. K8 is preferred to ACPI because of firmware bugs in early @@ -25,7 +29,7 @@ obj-$(CONFIG_CPUFREQ_DT_PLATDEV) += cpufreq-dt-platdev.o # speedstep-* is preferred over p4-clockmod. obj-$(CONFIG_X86_ACPI_CPUFREQ) += acpi-cpufreq.o -obj-$(CONFIG_X86_AMD_PSTATE) += amd-pstate.o +obj-$(CONFIG_X86_AMD_PSTATE) += amd_pstate.o obj-$(CONFIG_X86_POWERNOW_K8) += powernow-k8.o obj-$(CONFIG_X86_PCC_CPUFREQ) += pcc-cpufreq.o obj-$(CONFIG_X86_POWERNOW_K6) += powernow-k6.o diff --git a/drivers/cpufreq/amd-pstate-trace.c b/drivers/cpufreq/amd-pstate-trace.c new file mode 100644 index 000000000000..891b696dcd69 --- /dev/null +++ b/drivers/cpufreq/amd-pstate-trace.c @@ -0,0 +1,2 @@ +#define CREATE_TRACE_POINTS +#include "amd-pstate-trace.h" diff --git a/drivers/cpufreq/amd-pstate-trace.h b/drivers/cpufreq/amd-pstate-trace.h new file mode 100644 index 000000000000..647505957d4f --- /dev/null +++ b/drivers/cpufreq/amd-pstate-trace.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * amd-pstate-trace.h - AMD Processor P-state Frequency Driver Tracer + * + * Copyright (C) 2021 Advanced Micro Devices, Inc. All Rights Reserved. + * + * Author: Huang Rui + */ + +#if !defined(_AMD_PSTATE_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _AMD_PSTATE_TRACE_H + +#include +#include +#include + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM amd_cpu + +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_FILE amd-pstate-trace + +#define TPS(x) tracepoint_string(x) + +TRACE_EVENT(amd_pstate_perf, + + TP_PROTO(unsigned long min_perf, + unsigned long target_perf, + unsigned long capacity, + unsigned int cpu_id, + bool changed, + bool fast_switch + ), + + TP_ARGS(min_perf, + target_perf, + capacity, + cpu_id, + changed, + fast_switch + ), + + TP_STRUCT__entry( + __field(unsigned long, min_perf) + __field(unsigned long, target_perf) + __field(unsigned long, capacity) + __field(unsigned int, cpu_id) + __field(bool, changed) + __field(bool, fast_switch) + ), + + TP_fast_assign( + __entry->min_perf = min_perf; + __entry->target_perf = target_perf; + __entry->capacity = capacity; + __entry->cpu_id = cpu_id; + __entry->changed = changed; + __entry->fast_switch = fast_switch; + ), + + TP_printk("amd_min_perf=%lu amd_des_perf=%lu amd_max_perf=%lu cpu_id=%u changed=%s fast_switch=%s", + (unsigned long)__entry->min_perf, + (unsigned long)__entry->target_perf, + (unsigned long)__entry->capacity, + (unsigned int)__entry->cpu_id, + (__entry->changed) ? "true" : "false", + (__entry->fast_switch) ? "true" : "false" + ) +); + +#endif /* _AMD_PSTATE_TRACE_H */ + +/* This part must be outside protection */ +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . + +#include diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 68991c450fd5..72a4e2258fe7 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -31,6 +31,7 @@ #include #include #include +#include "amd-pstate-trace.h" #define AMD_PSTATE_TRANSITION_LATENCY 0x20000 #define AMD_PSTATE_TRANSITION_DELAY 500 @@ -189,6 +190,9 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, value &= ~REQ_MAX_PERF(~0L); value |= REQ_MAX_PERF(max_perf); + trace_amd_pstate_perf(min_perf, des_perf, max_perf, + cpudata->cpu, (value != prev), fast_switch); + if (value == prev) return; From patchwork Tue Nov 30 12:36:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12647199 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D5E7C433FE for ; Tue, 30 Nov 2021 12:38:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241853AbhK3Ml0 (ORCPT ); Tue, 30 Nov 2021 07:41:26 -0500 Received: from mail-mw2nam12on2083.outbound.protection.outlook.com ([40.107.244.83]:34144 "EHLO NAM12-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233024AbhK3MlM (ORCPT ); Tue, 30 Nov 2021 07:41:12 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=cX7YQesLK0VAiF/4s9D56vv02L9Km6KDGX5u4cyZbz9MTHlwdUck3DPq8xgJqf3fcYfhHfi9JKUAD2syEzUygSUOVs/egNGOOWneXGnnwqiGxixRl4OQ1shtpDtUJs5UTFqWn4Y/ztbPHxu91EQMqT19nns+wAafSeVcC5ik8ihR7UL+aQOvA9sS705Aqwgf4X+DNdzll3+XL9ES+3al8WF9GVnBNhlhjnbodo7KQE0SXJyJHmcSUwO22Dr3PmyKfu5tRUaXVQ/vWiBlhjiqQci3JZzLxQT8Ar+PLvglDWyNvUCx+YjxLMSfpAZrduAPlckg6whyIlPvsH12ZauhyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/W0eRJjp6bEZWY5A7Hs+79XaNsUs9UyUf+dVkRNMdV4=; b=Vo3dAQQkOSzhdIVsNugOfl2zO5s05W1y29OLy9ngra6qW4zHjDLG/QQ5Q3pNulYyBaT1X836+vCPiAPUJOLtqrRrUc90TNPF7dkgWY6p/RbrrXCqv9FoRBtffZfujLJ4F82WYHs2HrJNy1adFDOFn3fcVX74Qb04jkQiSFycm5bNZU0LNLAEBPJVZ/La0Vs++1RhCn45eKRRXgMciJsZpuatJseYGmdBf+ixnwVi3eV/qPpvqEUSXrMJiIUSVIcYNUKz3wgwc3mgdld1b6sJji2lgQTq6muPi13fCuE9s5IZL2Vwy1CST6V5jyKkZtqzKxdErRwNMCWt537dFD+Rrg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/W0eRJjp6bEZWY5A7Hs+79XaNsUs9UyUf+dVkRNMdV4=; b=vRl0++dz623tH5GZHta5G/uMJf2m6YHdPEB/5mup6497rtnRNZjkfsKV1IkZoMMzajIr7CB0ju0QGBCROEwXYZE5B0HF91n/8GhiQAN4AYTY5H9RXe8FbWGqFvbhBL3gA26Zx+ckEvdTuE1XY6Z2yrq0BxacSh/AzRVjQV4Ufpo= Received: from BN6PR14CA0013.namprd14.prod.outlook.com (2603:10b6:404:79::23) by MN2PR12MB4013.namprd12.prod.outlook.com (2603:10b6:208:163::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4734.22; Tue, 30 Nov 2021 12:37:47 +0000 Received: from BN8NAM11FT012.eop-nam11.prod.protection.outlook.com (2603:10b6:404:79:cafe::24) by BN6PR14CA0013.outlook.office365.com (2603:10b6:404:79::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4734.24 via Frontend Transport; Tue, 30 Nov 2021 12:37:48 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT012.mail.protection.outlook.com (10.13.177.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Tue, 30 Nov 2021 12:37:48 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 30 Nov 2021 06:37:43 -0600 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 10/22] cpufreq: amd: add boost mode support for amd-pstate Date: Tue, 30 Nov 2021 20:36:29 +0800 Message-ID: <20211130123641.1449041-11-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 35b97b56-f8eb-42dd-c067-08d9b3fe375e X-MS-TrafficTypeDiagnostic: MN2PR12MB4013: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2331; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: m5ZTvHaypjfiRisM63C88g8AaqL8YLUsme7pR5qzYnwmBzcUb0oZZc2WCPBhzTAB0U22sx9JjeRSsjrXgZEaD6RSOeq6IsueLpWPgratoJUXtmqq1eIzcVon3wYUXh8Oo/Eq9tQ8UF8XaFxZoaWbwo2HnvodOLUEiekeajucL94mb835i5HXeBB66wWXLcXWOGNs+3NeHDFI18bf/skwDiiN5rBA0d82a3UBKnBQSj7vW69yRo3Mfb0JxNkXL+QsIosPNHROKEizH9JZArLzGoOqJJDNzf9MHRykWijYQ3s6MYhqTl/4QJCwLTWh0vHqLpA6+ZEdeZwOcngWXPRKJdpcs4I/6ZQUTivuH0u7cQ6of/BKyJVgAdDhbk2yieri0yVkylSSID13tCycn2R7fbpq20NYXZ3twCLDHU3xbfFiMJ//Lr4JXoxK+cGpqZm30D3EqQjUDU0rOWyxUpkm4wrLLVzhzS9evshxNTNmZX13xYl9FlEhCH/nkp7xQy8HBWeH0n5ZFa92qCt7jgSTnG6atQHazrT2jOhUCMRavaD3E0OL8clb53JfxNqV2bb4i/iwa45wcR0z+d4kdkjlnnK6tpPhXZ02twoQO7w0cWxdi26kINATFM6BSh0Hw+vHW6Lyyo5MXwo01QdisLp33tlit9JJ5xUn/ZQr+f0FlPR621MS05tUEyAHfP12FWi2TmbPctdrFKWc1hztHCDDNWZp45eX5AEt2KeXNONcfgHl4VAfIYoSO6ejgjqFLEQhfwXsamnJAp2RewBpBysJusJhoShIvhdB7tgwWM4sL0o= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(356005)(186003)(16526019)(2906002)(8676002)(6666004)(83380400001)(7696005)(40460700001)(82310400004)(36860700001)(86362001)(26005)(47076005)(4326008)(7416002)(81166007)(54906003)(110136005)(1076003)(316002)(70206006)(70586007)(336012)(8936002)(508600001)(36756003)(2616005)(426003)(5660300002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:37:48.1227 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 35b97b56-f8eb-42dd-c067-08d9b3fe375e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4013 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org If the sbios supports the boost mode of amd-pstate, let's switch to boost enabled by default. Signed-off-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 44 ++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 72a4e2258fe7..c5d786af199d 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -67,6 +67,8 @@ struct amd_cpudata { u32 min_freq; u32 nominal_freq; u32 lowest_nonlinear_freq; + + bool boost_supported; }; static inline int pstate_enable(bool enable) @@ -343,6 +345,45 @@ static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata) return lowest_nonlinear_freq * 1000; } +static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) +{ + struct amd_cpudata *cpudata = policy->driver_data; + int ret; + + if (!cpudata->boost_supported) { + pr_err("Boost mode is not supported by this processor or SBIOS\n"); + return -EINVAL; + } + + if (state) + policy->cpuinfo.max_freq = cpudata->max_freq; + else + policy->cpuinfo.max_freq = cpudata->nominal_freq; + + policy->max = policy->cpuinfo.max_freq; + + ret = freq_qos_update_request(&cpudata->req[1], + policy->cpuinfo.max_freq); + if (ret < 0) + return ret; + + return 0; +} + +static void amd_pstate_boost_init(struct amd_cpudata *cpudata) +{ + u32 highest_perf, nominal_perf; + + highest_perf = READ_ONCE(cpudata->highest_perf); + nominal_perf = READ_ONCE(cpudata->nominal_perf); + + if (highest_perf <= nominal_perf) + return; + + cpudata->boost_supported = true; + amd_pstate_driver.boost_enabled = true; +} + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; @@ -412,6 +453,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) policy->driver_data = cpudata; + amd_pstate_boost_init(cpudata); + return 0; free_cpudata2: @@ -440,6 +483,7 @@ static struct cpufreq_driver amd_pstate_driver = { .target = amd_pstate_target, .init = amd_pstate_cpu_init, .exit = amd_pstate_cpu_exit, + .set_boost = amd_pstate_set_boost, .name = "amd-pstate", }; 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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 11/22] cpufreq: amd: add amd-pstate frequencies attributes Date: Tue, 30 Nov 2021 20:36:30 +0800 Message-ID: <20211130123641.1449041-12-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1d0f7a45-62c6-4c9d-b3ad-08d9b3fe39fb X-MS-TrafficTypeDiagnostic: BN8PR12MB3507: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wygKUhZl2DoI2KNUyapzSEHWBy8D3CV39OdSZA1GLHl+njUOnFVxoieHrvdGQEb5oUMciRA/9He0O3VlVTFEGEwGe1tlCyyqHeBM14f3sbHCkojzrreUB+qUYSQ7Cgxlvtzv/awNeaxjpY9Z/Yz1S1wiJPbyVhty2PpI5IrnM1Ll9Fr2QrPxOVejwX5cj50fAN6mWlUCpBFe8kpYgl1P1Ujm1807l7WFPpIYeBmZovt/RU2/x/pfAa0bjcg7z2N1nsJRj+DuO87KksCkHn++qanO00fmx5o9uJ5+W7widstcd1+9kgUeLqpMgiVrUiHyGibOyTxTAg7heM8rB+F54cNX5r04HLEMqEp/doR9gTVzWVLCKhq4yLTt751NYl1KPPWdRQSaIxTPUM7QVeDmksN1+SlKMlLbfwiq/dOPz0CySth94eJ56TGKuHwuaer+idU+2larToZhfW0tYcJWxPiupCuJRjpTmztXtJzfd8dLdcc9cRv0xAAfphFjvsvAhAlRDmNyUFj0x7kCa9jXAo2Rnay72aIlKIhWIEI/I77ZC1Vu+2wbvg6UzLhI3U8pG374sAK+yJQUdP6Bji/ydZGKYjFizMTBg58ZnGkEiLa7QtOoT6PCEpUjdbzfVfQyGmL//BnFxeRwaObMkhuZlnaOXJDivkUMVfQH2dnLpEX/JLCGVs8KNO24/mZYhyGWa4kDzmzLuI0t5WQnlhp/pJGBvcTZG4XZEijOUn8EzETeTokme2uPvyhSldR741EF8yQXfCckvogF8gphuODt4HWsJGHu3ZtkxQxSfPCkWvU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(40470700001)(16526019)(5660300002)(8936002)(4326008)(7416002)(186003)(47076005)(356005)(426003)(110136005)(36756003)(8676002)(86362001)(7696005)(2906002)(70206006)(54906003)(36860700001)(70586007)(82310400004)(83380400001)(1076003)(6666004)(508600001)(336012)(26005)(316002)(2616005)(40460700001)(81166007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:37:52.5068 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1d0f7a45-62c6-4c9d-b3ad-08d9b3fe39fb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3507 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce sysfs attributes to get the different level processor frequencies. Signed-off-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 46 ++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index c5d786af199d..d462d5a28e08 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -477,6 +477,51 @@ static int amd_pstate_cpu_exit(struct cpufreq_policy *policy) return 0; } +/* Sysfs attributes */ + +/* This frequency is to indicate the maximum hardware frequency. + * If boost is not active but supported, the frequency will be larger than the + * one in cpuinfo. + */ +static ssize_t show_amd_pstate_max_freq(struct cpufreq_policy *policy, + char *buf) +{ + int max_freq; + struct amd_cpudata *cpudata; + + cpudata = policy->driver_data; + + max_freq = amd_get_max_freq(cpudata); + if (max_freq < 0) + return max_freq; + + return sprintf(&buf[0], "%u\n", max_freq); +} + +static ssize_t show_amd_pstate_lowest_nonlinear_freq(struct cpufreq_policy *policy, + char *buf) +{ + int freq; + struct amd_cpudata *cpudata; + + cpudata = policy->driver_data; + + freq = amd_get_lowest_nonlinear_freq(cpudata); + if (freq < 0) + return freq; + + return sprintf(&buf[0], "%u\n", freq); +} + +cpufreq_freq_attr_ro(amd_pstate_max_freq); +cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); + +static struct freq_attr *amd_pstate_attr[] = { + &amd_pstate_max_freq, + &amd_pstate_lowest_nonlinear_freq, + NULL, +}; + static struct cpufreq_driver amd_pstate_driver = { .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, .verify = amd_pstate_verify, @@ -485,6 +530,7 @@ static struct cpufreq_driver amd_pstate_driver = { .exit = amd_pstate_cpu_exit, .set_boost = amd_pstate_set_boost, .name = "amd-pstate", + .attr = amd_pstate_attr, }; static int __init amd_pstate_init(void) From patchwork Tue Nov 30 12:36:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12647203 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 621BFC433F5 for ; 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Tue, 30 Nov 2021 06:37:52 -0600 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 12/22] cpufreq: amd: add amd-pstate performance attributes Date: Tue, 30 Nov 2021 20:36:31 +0800 Message-ID: <20211130123641.1449041-13-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: db7ba157-87d4-4943-a8dd-08d9b3fe3ca0 X-MS-TrafficTypeDiagnostic: SN6PR12MB2701: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3513; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0e/HjG3qldqD5zWUizZn9TizoN18VpSs++4arALHmB6z1j4CBGL6LX261M4Ws4c3tbYNuprGxv2xVJJGPLq000jQ3w7G+SoZh55/6Xta1BoROw1gt8X0HS2WMfQyXs/d0nU6Y+grlgH/Uqrv3hZHOA08JbdssGVUVQOjZYB/uNT+tl7i1puSs/FUTY25YQJ7yv41EID5sRM/aTOAQgXCG27S3ErxYdcBHgL3maQaRumKV6zIYrbBfGClEV8yUekPjvesNrfER7xS+6bgSTsGrtZFH8TY4iRPk4B6+Rb1IldOzpbPTXNzCip97NBrBfPsUYAKOlnQMOEfKSPkKO7dw2K3ew8roC+imm3VnF9zMC2ySvrva9duwRvh2XOe0eJHhiB4MgT9uFt4le1JKb8snE2wEfN/hZBZ/yfr/Lg7lAIS6bkEnarHXmZlsobbgvKENZp6As1PnzNDZkEAMDoTH9h9SA+TNvUEx5ZgG0aYJPOG8GJlDRtKYeUfAu3Iy2Qas/xpWKYFlUGEounjYenTYM27EL9G35fTuX6xUdG+MrenV0etZhhfqHNGn3Sor5Q3lCmjBFyZxiPjTUNciMXNvveCtD3FwIIF0z8Al6wkGK2Va+r9i7y3KXTAQpxtpYc931oWVQnbGETqos7DneuW8RK7TslW8oW8oawnNNrWY5sALGQI8uNuQAH09tAHyKJUD++HVUbUzlWBvc8w2YOH7Ru4ozx8kBxFO9kzf9TYH43VW8YP1wbwG5EsRObNaKVakjq253LJVRUQfROvKGPV+cvD8JlXjNx2gCxNyvqx8+w= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(82310400004)(7416002)(508600001)(36860700001)(6666004)(2616005)(86362001)(81166007)(7696005)(83380400001)(356005)(70586007)(16526019)(8936002)(36756003)(2906002)(70206006)(1076003)(110136005)(54906003)(47076005)(186003)(316002)(8676002)(426003)(5660300002)(336012)(40460700001)(26005)(4326008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:37:56.9413 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: db7ba157-87d4-4943-a8dd-08d9b3fe3ca0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT023.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2701 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce sysfs attributes to get the different level amd-pstate performances. Signed-off-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index d462d5a28e08..c70274ae4046 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -513,12 +513,29 @@ static ssize_t show_amd_pstate_lowest_nonlinear_freq(struct cpufreq_policy *poli return sprintf(&buf[0], "%u\n", freq); } +/* In some of ASICs, the highest_perf is not the one in the _CPC table, so we + * need to expose it to sysfs. + */ +static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, + char *buf) +{ + u32 perf; + struct amd_cpudata *cpudata = policy->driver_data; + + perf = READ_ONCE(cpudata->highest_perf); + + return sprintf(&buf[0], "%u\n", perf); +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); +cpufreq_freq_attr_ro(amd_pstate_highest_perf); + static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, &amd_pstate_lowest_nonlinear_freq, + &amd_pstate_highest_perf, NULL, }; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT014.mail.protection.outlook.com (10.13.177.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Tue, 30 Nov 2021 12:38:02 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 30 Nov 2021 06:37:56 -0600 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 13/22] cpupower: add AMD P-state capability flag Date: Tue, 30 Nov 2021 20:36:32 +0800 Message-ID: <20211130123641.1449041-14-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a1fadc4e-8fbe-4506-e31c-08d9b3fe3fbc X-MS-TrafficTypeDiagnostic: DM5PR12MB4662: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1265; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Mhk1VUqvhW+9qGd1RgDxZyHrr+HBroXTx+ASWWph2kW1tKCFoOLVqq73OyB+5pnKaVnt12eiqIEwFUjahnq8Zx8CLlrA0qZ0HGHNXfj/7pEf72sW6wyh+8Pv3qjI7ZX+BGLjeuwxqXjUQgRC1iuMaScBaAt+b7Md7Inm68O3VMh4DBEjlMQmtLtbyQCo0rlfN89jpFY5RvZtwq+sKQTH3qXlpvvyeyh6w/a0N7RY82N0zmrs/pFIkLihm3pAQBiLHhkTKKa6kpun/gDQqlhlRXtKBHNHXroOli3zApQkh1pHr4pnnBqrvVHCdVC3yRpAHnwGGz96mcqMHhuXO2rBUHFkbhRDeKfHX286ag41c9/StCpDqfcpx+AYwJta9Pyag20juJreqCbmxIP2ZAN5gkYvkyEmu/75kvabZqRyalLXbbFfbCwWn+ac+yetfQreY6ik3aRrUBVn/jLGjplnhoRXPd+CbPqsi1rsb+G6QOrRefYAx8grK3FlkCYQRImJigcAp8SDM/NIXlxXsCZvIx3e57ffTagvCrEbe0T2sHzQxAQ3S4ZPo4rTPSoglw8pG7nhYKxNdfht8doe2CCYcm6mLHaA6OlpLjT+/kyPsnlqFHNylx0jIa3Z485wjLkUn0z0QLo656NXrkokKddUoqnsTmdus2USCRq/5LtI83ElzdlnmcQwm2pefdmzbfnyLyE9h6eYGCoF30zr0biJ2nf2LWEIxfX/GWIL5h6yvrskL30X2n4Q0IxyI9+CFUiUr4rZvRpvkDRy4QC2xiQ1PipG81tYNMide2xTePrFHQQ= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(40470700001)(508600001)(70206006)(36860700001)(426003)(70586007)(356005)(4326008)(8676002)(4744005)(5660300002)(36756003)(82310400004)(47076005)(16526019)(7416002)(1076003)(7696005)(110136005)(26005)(6666004)(2616005)(186003)(316002)(2906002)(81166007)(336012)(40460700001)(86362001)(54906003)(8936002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:38:02.1614 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1fadc4e-8fbe-4506-e31c-08d9b3fe3fbc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT014.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB4662 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add AMD P-state capability flag in cpupower to indicate AMD new P-state kernel module support on Ryzen processors. Signed-off-by: Huang Rui --- tools/power/cpupower/utils/helpers/helpers.h | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/power/cpupower/utils/helpers/helpers.h b/tools/power/cpupower/utils/helpers/helpers.h index 33ffacee7fcb..b4813efdfb00 100644 --- a/tools/power/cpupower/utils/helpers/helpers.h +++ b/tools/power/cpupower/utils/helpers/helpers.h @@ -73,6 +73,7 @@ enum cpupower_cpu_vendor {X86_VENDOR_UNKNOWN = 0, X86_VENDOR_INTEL, #define CPUPOWER_CAP_AMD_HW_PSTATE 0x00000100 #define CPUPOWER_CAP_AMD_PSTATEDEF 0x00000200 #define CPUPOWER_CAP_AMD_CPB_MSR 0x00000400 +#define CPUPOWER_CAP_AMD_PSTATE 0x00000800 #define CPUPOWER_AMD_CPBDIS 0x02000000 From patchwork Tue Nov 30 12:36:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12647207 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80445C433FE for ; Tue, 30 Nov 2021 12:38:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241722AbhK3MmJ (ORCPT ); Tue, 30 Nov 2021 07:42:09 -0500 Received: from mail-dm3nam07on2051.outbound.protection.outlook.com ([40.107.95.51]:58528 "EHLO NAM02-DM3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241775AbhK3Ml1 (ORCPT ); Tue, 30 Nov 2021 07:41:27 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=BirXbAk8BK3JOq8G7gY9RFetRJR/09br1iIijttx2/qD0pGk1y1ttBqAAqjgUu2djquGlylEgZTFu5VdJPd6Z4xnqLyLHC+UEaPwPXnUVtDrLNgRTB3LKdFIP8oUF8GlrjV61v6+oO0GrcN4tdjC7rkTVqGL6PQOBZKZfre+KK+UYFxHs5hqS3E5s6RMCC747eXPs8FOdJ6Dw42PSH2mEkz/3lREZn6Oue6NrHP2nOfPngUKTx2nRrT5etxtSMwsxWN1YUk1hRCqi6Mmea3os3WUt2FmSlEVoOB9eSG8oOChMipPugSE+VfRJW/yFo+V/9sZJCfk1u2/VDlQq4PntQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=UcWX6wnAZ9kKR3lnWrFfRGLYbt7fR1JVVSvMwIGnjnk=; b=jNWuG5kOIzEzWObOcbTgeX690cjt6kCCHukkFjK9oerY8gaW/VM6IgDasJ1FbqGK21sUjsEFoA8SCsH7ct46ddumZ6OKk6RLh5aE89xiTwJwBXne3fpiVyDsagVqydRg9o3w+pCPcUGh8oqM5DSuKOGmMZtyrRMQ6+49Z/9vrF0dRgDA30qLyBINI6g3ggi9L+NL/ruzrbCPPThUucWXmnO09DtEjsRecEbrdJWLtnPp/WPq/B7SSLfrxw+0Mm7b1Xzwg5N38iDGFL3fCPD+9FSKyWg7kjA+V+PRKLTgai5UlrwJhnugE4eSgmsKrIi4B5TZ5ELGDKq+wI12wUxTsw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UcWX6wnAZ9kKR3lnWrFfRGLYbt7fR1JVVSvMwIGnjnk=; b=Es8n1eQHzS7yOhctH7EzGrRxk1EYQdHzpx1rJnIUg0atmYkfAD6+O/beKm3qz+qMqYxbPQ58RO0W6NPUj2CHpKgWIWxFvt2u5PPxQpTH3cKzDrKaYBRnf9vM9+ueIpwuFGIFgzPRzgTvsSjMRMXeyyc6w4Ka9vzEadJrGoXouv0= Received: from BN6PR16CA0024.namprd16.prod.outlook.com (2603:10b6:404:f5::34) by BN6PR12MB1409.namprd12.prod.outlook.com (2603:10b6:404:1e::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4734.23; Tue, 30 Nov 2021 12:38:05 +0000 Received: from BN8NAM11FT018.eop-nam11.prod.protection.outlook.com (2603:10b6:404:f5:cafe::20) by BN6PR16CA0024.outlook.office365.com (2603:10b6:404:f5::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4734.23 via Frontend Transport; Tue, 30 Nov 2021 12:38:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT018.mail.protection.outlook.com (10.13.176.89) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Tue, 30 Nov 2021 12:38:05 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 30 Nov 2021 06:38:01 -0600 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 14/22] cpupower: add the function to check amd-pstate enabled Date: Tue, 30 Nov 2021 20:36:33 +0800 Message-ID: <20211130123641.1449041-15-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 39dc3321-c659-4562-421a-08d9b3fe41dd X-MS-TrafficTypeDiagnostic: BN6PR12MB1409: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2733; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: scpqJyMC9sKj0SuZstb1YVbM93yPukPtRnKLfj/1er4fMU8l/W/uasj+Ec0r8k3tJE+huGz9HGwO6heQ9pLctmWyVaTGqUY8EZCGYccv113ucsuRU99aopr6u3cy7k78LiCqSxAm3URPaqh8RqpQTQxgOr70KUX4bc4bsL4u5JG9IvirbVGxAze7G4CS8BjW3do5jk83YeNlxERmUb0VMapXAoLYUAxpUtvf28RwwKb21UJ/dS0CGjAosdn/HStLajVG3RiNBid/FbzzVRfLcoNUMZB5m5ovhvitBYneO2VkPi3hm7qGcixgsdhNT7/Jqp0xirtKuueOGAvid0a21UPmaQCMp5djcmJufaxvvNAW7WRuIpGUGGpZovZzPkRzckITfMXhjaod2HU3bwZvEgplK0l3XwQ4RdMiE+r0xTxvSfWdt2N0iTEgoWKZ2UG01B/nx5Tkb4MmzvH3CmOSdoTfIDikqgCw0trmlD3HtS1bxvuAul3LZBZAaRT5fZtXcW5XfV87ksKTHJE4VAdCXDAEFFQYsTd3w1nH4OXgdr1mYBlBzXDtXOmzPijpEd158In2r3wG2SQ7zCMmtnbSHn2n9MLOuQSWX5rtR4hEFUVAGErQxXCM98/IBG29A80LZG5TmbbTVsFcFcFS7TJnkAaeAPjK9h0Aj4UyAyM61Od8vePvizEOTZh1LkY/obXw2ybFT/IRy+1+t9einGJtmEjxSAlFK57Cfk+LHpSuLucybG8aKW3uiYK8cbNZm7Vat5z/5ZmJUTt65yDTr1uqrc4dyI2uSFTrI0EXJb2wAws= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(86362001)(5660300002)(26005)(70586007)(6666004)(2616005)(47076005)(82310400004)(70206006)(186003)(356005)(336012)(426003)(110136005)(36756003)(81166007)(36860700001)(316002)(8936002)(7696005)(8676002)(7416002)(4326008)(1076003)(2906002)(54906003)(508600001)(16526019)(40460700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:38:05.7286 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39dc3321-c659-4562-421a-08d9b3fe41dd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT018.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1409 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The processor with amd-pstate function also supports legacy ACPI hardware P-States feature as well. Once driver sets amd-pstate eanbled, the processor will respond the finer grain amd-pstate feature instead of legacy ACPI P-States. So it introduces the cpupower_amd_pstate_enabled() to check whether the current kernel enables amd-pstate or acpi-cpufreq module. Signed-off-by: Huang Rui --- tools/power/cpupower/utils/helpers/helpers.h | 10 ++++++++++ tools/power/cpupower/utils/helpers/misc.c | 18 ++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/tools/power/cpupower/utils/helpers/helpers.h b/tools/power/cpupower/utils/helpers/helpers.h index b4813efdfb00..e03cc97297aa 100644 --- a/tools/power/cpupower/utils/helpers/helpers.h +++ b/tools/power/cpupower/utils/helpers/helpers.h @@ -11,6 +11,7 @@ #include #include +#include #include "helpers/bitmask.h" #include @@ -136,6 +137,12 @@ extern int decode_pstates(unsigned int cpu, int boost_states, extern int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active, int * states); + +/* AMD P-States stuff **************************/ +extern bool cpupower_amd_pstate_enabled(void); + +/* AMD P-States stuff **************************/ + /* * CPUID functions returning a single datum */ @@ -168,6 +175,9 @@ static inline int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active, int * states) { return -1; } +static inline bool cpupower_amd_pstate_enabled(void) +{ return false; } + /* cpuid and cpuinfo helpers **************************/ static inline unsigned int cpuid_eax(unsigned int op) { return 0; }; diff --git a/tools/power/cpupower/utils/helpers/misc.c b/tools/power/cpupower/utils/helpers/misc.c index fc6e34511721..0c483cdefcc2 100644 --- a/tools/power/cpupower/utils/helpers/misc.c +++ b/tools/power/cpupower/utils/helpers/misc.c @@ -3,9 +3,11 @@ #include #include #include +#include #include "helpers/helpers.h" #include "helpers/sysfs.h" +#include "cpufreq.h" #if defined(__i386__) || defined(__x86_64__) @@ -83,6 +85,22 @@ int cpupower_intel_set_perf_bias(unsigned int cpu, unsigned int val) return 0; } +bool cpupower_amd_pstate_enabled(void) +{ + char *driver = cpufreq_get_driver(0); + bool ret = false; + + if (!driver) + return ret; + + if (!strcmp(driver, "amd-pstate")) + ret = true; + + cpufreq_put_driver(driver); + + return ret; +} + #endif /* #if defined(__i386__) || defined(__x86_64__) */ /* get_cpustate From patchwork Tue Nov 30 12:36:34 2021 Content-Type: text/plain; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT006.mail.protection.outlook.com (10.13.177.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Tue, 30 Nov 2021 12:38:10 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 30 Nov 2021 06:38:05 -0600 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 15/22] cpupower: initial AMD P-state capability Date: Tue, 30 Nov 2021 20:36:34 +0800 Message-ID: <20211130123641.1449041-16-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 41666914-3079-4723-28a9-08d9b3fe447f X-MS-TrafficTypeDiagnostic: DM8PR12MB5494: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1923; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HTvCtvCyl1iekVT0/l8HX0de38Gtn87bRnLcForDWy6zubTyuKemFb2c7WEs0kDOSnguYOa2JejU8XpEXzyB3fr1/pGft00iI1uBLzS4Ra9jspi9nslL2zqMmbHVFnuGmWat/m5fy1aCCjMxVr6q8cWMvgf3vpIdxSaiQLj3OTmPn2weIh12hsM9QQNoE0brfbaE8LNn2EkkfWQSrJzSrGQLVx8zH+mk/f37rCZRTv/dTi7x1DYXOvvw9H7le612T4DNoL4sujnrS2lH1xLkA8niRYHYQdKiEO6ennj/rwxt/3Zmci6tWAVkm1nu9z/6GUV6oP4l7MtxQH8aJzLjs3dAnLDfUO5bjrr1Wb4w/f15H4s8twxBTGCvb8ZABSngnn+Q/w20MWV/N/9zFaGDxP4smseL8xZdmf7E3MkCsB3W/E+9Ws2XtgrfEViPrNHEccsFWupOFnyg/u7EULRFuG/CkKgt6288nxVwa6VBWJ4V8lUiR9U0gpHM13yeduAvb5avnvmjn5OAIZeJzNojYK7zL3Fyi0T6ukUl6M+ChjjIefdeBpWA0lNmo2+rMg/kXSgcRYR5JGtdfSIiamOCEXAyY7v7b3v4BThikH5NsOy320cWI1lyU9tDNVwHlR4313T0RYjUnXt7MauqXO2c/o1CndhqNoOt7gwhFriZUkqIc74IWOziFfImW+UMNRF5lDHeyMmmVuC4Y52tel32jhd+XZY96QCUTpH52bcMWL6obLVcDfw5SxoHCh1Tj1QvMyywI9PhrcvuHFbIvBSsnQoTw5fXQr77NgZxAHaRNx4= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(7416002)(86362001)(508600001)(1076003)(70586007)(356005)(2906002)(2616005)(36756003)(47076005)(70206006)(6666004)(8936002)(81166007)(5660300002)(26005)(426003)(36860700001)(82310400004)(16526019)(336012)(4326008)(8676002)(186003)(110136005)(316002)(7696005)(40460700001)(54906003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:38:10.1455 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41666914-3079-4723-28a9-08d9b3fe447f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT006.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5494 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org If kernel starts the amd-pstate module, the cpupower will initial the capability flag as CPUPOWER_CAP_AMD_PSTATE. And once amd-pstate capability is set, it won't need to set legacy ACPI relative capabilities anymore. Signed-off-by: Huang Rui --- tools/power/cpupower/utils/helpers/cpuid.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/tools/power/cpupower/utils/helpers/cpuid.c b/tools/power/cpupower/utils/helpers/cpuid.c index 72eb43593180..2a6dc104e76b 100644 --- a/tools/power/cpupower/utils/helpers/cpuid.c +++ b/tools/power/cpupower/utils/helpers/cpuid.c @@ -149,6 +149,19 @@ int get_cpu_info(struct cpupower_cpu_info *cpu_info) if (ext_cpuid_level >= 0x80000008 && cpuid_ebx(0x80000008) & (1 << 4)) cpu_info->caps |= CPUPOWER_CAP_AMD_RDPRU; + + if (cpupower_amd_pstate_enabled()) { + cpu_info->caps |= CPUPOWER_CAP_AMD_PSTATE; + + /* + * If AMD P-state is enabled, the firmware will treat + * AMD P-state function as high priority. + */ + cpu_info->caps &= ~CPUPOWER_CAP_AMD_CPB; + cpu_info->caps &= ~CPUPOWER_CAP_AMD_CPB_MSR; + cpu_info->caps &= ~CPUPOWER_CAP_AMD_HW_PSTATE; + cpu_info->caps &= ~CPUPOWER_CAP_AMD_PSTATEDEF; + } } if (cpu_info->vendor == X86_VENDOR_INTEL) { From patchwork Tue Nov 30 12:36:35 2021 Content-Type: text/plain; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT064.mail.protection.outlook.com (10.13.176.160) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Tue, 30 Nov 2021 12:38:14 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 30 Nov 2021 06:38:09 -0600 From: Huang Rui To: "Rafael J . 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Signed-off-by: Huang Rui --- tools/power/cpupower/lib/cpufreq.c | 21 +++++++++++++++------ tools/power/cpupower/lib/cpufreq.h | 12 ++++++++++++ 2 files changed, 27 insertions(+), 6 deletions(-) diff --git a/tools/power/cpupower/lib/cpufreq.c b/tools/power/cpupower/lib/cpufreq.c index c3b56db8b921..c011bca27041 100644 --- a/tools/power/cpupower/lib/cpufreq.c +++ b/tools/power/cpupower/lib/cpufreq.c @@ -83,20 +83,21 @@ static const char *cpufreq_value_files[MAX_CPUFREQ_VALUE_READ_FILES] = { [STATS_NUM_TRANSITIONS] = "stats/total_trans" }; - -static unsigned long sysfs_cpufreq_get_one_value(unsigned int cpu, - enum cpufreq_value which) +unsigned long cpufreq_get_sysfs_value_from_table(unsigned int cpu, + const char **table, + unsigned index, + unsigned size) { unsigned long value; unsigned int len; char linebuf[MAX_LINE_LEN]; char *endp; - if (which >= MAX_CPUFREQ_VALUE_READ_FILES) + if (!table || index >= size || !table[index]) return 0; - len = sysfs_cpufreq_read_file(cpu, cpufreq_value_files[which], - linebuf, sizeof(linebuf)); + len = sysfs_cpufreq_read_file(cpu, table[index], linebuf, + sizeof(linebuf)); if (len == 0) return 0; @@ -109,6 +110,14 @@ static unsigned long sysfs_cpufreq_get_one_value(unsigned int cpu, return value; } +static unsigned long sysfs_cpufreq_get_one_value(unsigned int cpu, + enum cpufreq_value which) +{ + return cpufreq_get_sysfs_value_from_table(cpu, cpufreq_value_files, + which, + MAX_CPUFREQ_VALUE_READ_FILES); +} + /* read access to files which contain one string */ enum cpufreq_string { diff --git a/tools/power/cpupower/lib/cpufreq.h b/tools/power/cpupower/lib/cpufreq.h index 95f4fd9e2656..107668c0c454 100644 --- a/tools/power/cpupower/lib/cpufreq.h +++ b/tools/power/cpupower/lib/cpufreq.h @@ -203,6 +203,18 @@ int cpufreq_modify_policy_governor(unsigned int cpu, char *governor); int cpufreq_set_frequency(unsigned int cpu, unsigned long target_frequency); +/* + * get the sysfs value from specific table + * + * Read the value with the sysfs file name from specific table. Does + * only work if the cpufreq driver has the specific sysfs interfaces. + */ + +unsigned long cpufreq_get_sysfs_value_from_table(unsigned int cpu, + const char **table, + unsigned index, + unsigned size); + #ifdef __cplusplus } #endif From patchwork Tue Nov 30 12:36:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12647217 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB59DC433F5 for ; Tue, 30 Nov 2021 12:39:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241902AbhK3Mm3 (ORCPT ); Tue, 30 Nov 2021 07:42:29 -0500 Received: from mail-dm3nam07on2050.outbound.protection.outlook.com ([40.107.95.50]:27617 "EHLO NAM02-DM3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241919AbhK3Mlk (ORCPT ); Tue, 30 Nov 2021 07:41:40 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=fmJ2Ucwe3J5NSundCL6WjuW2dE56EczhOSJVileIn783MERVd/9rrh8XZwJQd8ZsztUzfxVcuv3C/ooVIQNDwC0rUzfWB41yHvpIr9o23qxUqF/eciUKlvb3TW6uTLik+kgUDblL7gYHgQqCpjWAcDBwSixWMeSSH1laVzQJ0bimNEFl7807Cd+v7rLcv+OJbkBLPlT4HmI9p6Tme23v5NlNYjEjbmAyuRGwj8Bd8OTpI6wyogDGVNRC8fXqiRjy2t2OtGhBwy4TjRQ0qJ2Zzo2/jRy1tmOcJrOBNBIJz+/lO3HzId7e1lZlrMVext7A7zvH0iLnZ8QHHM8HSE3cZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0k/zus4Ykvg9YQ8ScAPNoaxGrxYCilniKi+hCW4Rdes=; b=chQDhUyijsf/aE7M6vmwhLLZJD3n+b4uqvLy0ftXvnF7rrIU7PGdP4U/u9dHfA/SkhyVDq/Tc/yRZEsMheJCYap9K9EHygrdQevLngU1dDtd4qtc6qAacwbgSrwHYMeKdhpsLpdtc0zExEgjL2lP90EmwByhZY5jxYAbXTkJnPEBVAJIa1463k3VBT2hC1KFuFlT/yKRnqeiwn/Se/qI21LycZt1I9pd0+mi7Q71RsoXkYK77Y5ydXi2oJz2W1bYYmaXGiuTLTnOkr2E83zzZGcxjpaQdE0FeJFCJJU8wjZ7M2aHJKu8Hz5l/Kmm0Ql5eLugiQDCxJsgDp/ZZmKang== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0k/zus4Ykvg9YQ8ScAPNoaxGrxYCilniKi+hCW4Rdes=; b=Tri7wOsxfExQ7cNaSkfinw/ZzMmTOD7ZgrwybEmgK9wIvV01j8npJZ0zIPcOKqLLSHCpBl0TdlHOZ6sg8YRi/ha7eEiWigyyjP4eYHvz1yWVoj+htkSgpxLBc09v5FtmJ3JCAgwDoYQDcK1GhC0jI11CkLN2j4bExTIA4MS9/dc= Received: from BN8PR04CA0029.namprd04.prod.outlook.com (2603:10b6:408:70::42) by DM8PR12MB5413.namprd12.prod.outlook.com (2603:10b6:8:3b::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4755.11; Tue, 30 Nov 2021 12:38:19 +0000 Received: from BN8NAM11FT025.eop-nam11.prod.protection.outlook.com (2603:10b6:408:70:cafe::d0) by BN8PR04CA0029.outlook.office365.com (2603:10b6:408:70::42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4734.23 via Frontend Transport; Tue, 30 Nov 2021 12:38:19 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT025.mail.protection.outlook.com (10.13.177.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Tue, 30 Nov 2021 12:38:19 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 30 Nov 2021 06:38:14 -0600 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 17/22] cpupower: introduce acpi cppc library Date: Tue, 30 Nov 2021 20:36:36 +0800 Message-ID: <20211130123641.1449041-18-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 886c1bea-e9ad-4c2b-9a1e-08d9b3fe49d1 X-MS-TrafficTypeDiagnostic: DM8PR12MB5413: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2331; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Yg/1jQtvT5qWVvXZB8DjMn9KRJowdIrt7AObGK8W7ey4OaXrmoDGHb4kWb5UNSVFbEMCNGwiIRwUVkRUKsntXyWBeItGKhF/tWuqXXxjnVBCe5MzDFz6mzfVft8RYldyJLnXwGPztWtDOqKbMbjyMiJlLXbo2mNqnF5RoIIxW8dCPOe8poMsCjUtFilj2iOr3vcNvLKQn67+T8f7z2IH1Ny8zb0zcmAXHsfGzBeixMYO1OF5FTb6nCIG9MpnD8zaABLAV2VhxWtolSnCKPNiBrAX6N0Mbce3CJKeLigHP7tB/du2+uDYUUS05GPcKTUacxml3ZKGNukbGP+TEdnsE0T9MbUL8/lmcAhfsS7riZGHBwkBEQfQKGym55nr/gtfnmJTr9ajgIRKfQidOYXyH1B3FiUbqPPSebYPbdPupC60eA6BUyUOxhWSqR16Kkno2QRYi4fi4sYIzOXXQoV/9y/2C7uTZN5ylB81UOWZ0VBcVs9btI5jgDaf/1KP5nF+kol8CoaYyvQg/uCChmXI6jSlTFngxPbXwLxa0tN8h0xwb/s4E5ciF54+v8oFRpUTf+/vsbio9wQExpFnEpQXM5xwuy/pwz45xLTQXv3q5OgbCF+zpaHsyl2LlgpG53JiJ/0zgJCNsRu9RCh4tvYlETsBsHlfBZuXWfhdDk4+5D9U1i+aIzIj4HxZIFUYFJzSnmTOKKG+KMgoX3oyoSaf7WY94uHUtMvAxjJkl5MbVZwIAzIJDhRcvS4O1N83QPY5zVUhFarInnzOcXZOlWOcfLlZ4xAheS0NS21XRB9Ia2c= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(83380400001)(356005)(426003)(2616005)(8676002)(81166007)(336012)(86362001)(36860700001)(70586007)(70206006)(6666004)(54906003)(1076003)(2906002)(7696005)(47076005)(36756003)(4326008)(82310400004)(7416002)(5660300002)(40460700001)(110136005)(16526019)(186003)(8936002)(508600001)(26005)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:38:19.0734 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 886c1bea-e9ad-4c2b-9a1e-08d9b3fe49d1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5413 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Kernel ACPI subsytem introduced the sysfs attributes for acpi cppc library in below path: /sys/devices/system/cpu/cpuX/acpi_cppc/ And these attributes will be used for amd-pstate driver to provide some performance and frequency values. Signed-off-by: Huang Rui --- tools/power/cpupower/Makefile | 6 +-- tools/power/cpupower/lib/acpi_cppc.c | 59 ++++++++++++++++++++++++++++ tools/power/cpupower/lib/acpi_cppc.h | 21 ++++++++++ 3 files changed, 83 insertions(+), 3 deletions(-) create mode 100644 tools/power/cpupower/lib/acpi_cppc.c create mode 100644 tools/power/cpupower/lib/acpi_cppc.h diff --git a/tools/power/cpupower/Makefile b/tools/power/cpupower/Makefile index 3b1594447f29..e9b6de314654 100644 --- a/tools/power/cpupower/Makefile +++ b/tools/power/cpupower/Makefile @@ -143,9 +143,9 @@ UTIL_HEADERS = utils/helpers/helpers.h utils/idle_monitor/cpupower-monitor.h \ utils/helpers/bitmask.h \ utils/idle_monitor/idle_monitors.h utils/idle_monitor/idle_monitors.def -LIB_HEADERS = lib/cpufreq.h lib/cpupower.h lib/cpuidle.h -LIB_SRC = lib/cpufreq.c lib/cpupower.c lib/cpuidle.c -LIB_OBJS = lib/cpufreq.o lib/cpupower.o lib/cpuidle.o +LIB_HEADERS = lib/cpufreq.h lib/cpupower.h lib/cpuidle.h lib/acpi_cppc.h +LIB_SRC = lib/cpufreq.c lib/cpupower.c lib/cpuidle.c lib/acpi_cppc.c +LIB_OBJS = lib/cpufreq.o lib/cpupower.o lib/cpuidle.o lib/acpi_cppc.o LIB_OBJS := $(addprefix $(OUTPUT),$(LIB_OBJS)) override CFLAGS += -pipe diff --git a/tools/power/cpupower/lib/acpi_cppc.c b/tools/power/cpupower/lib/acpi_cppc.c new file mode 100644 index 000000000000..a07a8922eca2 --- /dev/null +++ b/tools/power/cpupower/lib/acpi_cppc.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cpupower_intern.h" +#include "acpi_cppc.h" + +/* ACPI CPPC sysfs access ***********************************************/ + +static int acpi_cppc_read_file(unsigned int cpu, const char *fname, + char *buf, size_t buflen) +{ + char path[SYSFS_PATH_MAX]; + + snprintf(path, sizeof(path), PATH_TO_CPU "cpu%u/acpi_cppc/%s", + cpu, fname); + return cpupower_read_sysfs(path, buf, buflen); +} + +static const char *acpi_cppc_value_files[] = { + [HIGHEST_PERF] = "highest_perf", + [LOWEST_PERF] = "lowest_perf", + [NOMINAL_PERF] = "nominal_perf", + [LOWEST_NONLINEAR_PERF] = "lowest_nonlinear_perf", + [LOWEST_FREQ] = "lowest_freq", + [NOMINAL_FREQ] = "nominal_freq", + [REFERENCE_PERF] = "reference_perf", + [WRAPAROUND_TIME] = "wraparound_time" +}; + +unsigned long acpi_cppc_get_data(unsigned cpu, enum acpi_cppc_value which) +{ + unsigned long long value; + unsigned int len; + char linebuf[MAX_LINE_LEN]; + char *endp; + + if (which >= MAX_CPPC_VALUE_FILES) + return 0; + + len = acpi_cppc_read_file(cpu, acpi_cppc_value_files[which], + linebuf, sizeof(linebuf)); + if (len == 0) + return 0; + + value = strtoull(linebuf, &endp, 0); + + if (endp == linebuf || errno == ERANGE) + return 0; + + return value; +} diff --git a/tools/power/cpupower/lib/acpi_cppc.h b/tools/power/cpupower/lib/acpi_cppc.h new file mode 100644 index 000000000000..576291155224 --- /dev/null +++ b/tools/power/cpupower/lib/acpi_cppc.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ACPI_CPPC_H__ +#define __ACPI_CPPC_H__ + +enum acpi_cppc_value { + HIGHEST_PERF, + LOWEST_PERF, + NOMINAL_PERF, + LOWEST_NONLINEAR_PERF, + LOWEST_FREQ, + NOMINAL_FREQ, + REFERENCE_PERF, + WRAPAROUND_TIME, + MAX_CPPC_VALUE_FILES +}; + +extern unsigned long acpi_cppc_get_data(unsigned cpu, + enum acpi_cppc_value which); + +#endif /* _ACPI_CPPC_H */ From patchwork Tue Nov 30 12:36:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12647219 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D8CBC433F5 for ; Tue, 30 Nov 2021 12:39:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241942AbhK3Mmf (ORCPT ); Tue, 30 Nov 2021 07:42:35 -0500 Received: from mail-bn8nam11on2055.outbound.protection.outlook.com ([40.107.236.55]:44819 "EHLO NAM11-BN8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241943AbhK3Mlp (ORCPT ); Tue, 30 Nov 2021 07:41:45 -0500 ARC-Seal: i=1; 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Tue, 30 Nov 2021 12:38:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT064.mail.protection.outlook.com (10.13.176.160) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Tue, 30 Nov 2021 12:38:23 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 30 Nov 2021 06:38:18 -0600 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 18/22] cpupower: add amd-pstate sysfs definition and access helper Date: Tue, 30 Nov 2021 20:36:37 +0800 Message-ID: <20211130123641.1449041-19-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0a79cbbd-aa6b-4955-c17d-08d9b3fe4c6d X-MS-TrafficTypeDiagnostic: DM6PR12MB4484: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LuuE6/gkkT7xpLXimDyjbmz+F3S4V/ao/kTu1j79geV/5V/s6/N0jn2TjWVcRvc35QZM7egjeKRMnABwmqOYzawi7tG38Bh//8DCkL5xKOkFy95dB4MdrYc/PInsxtAjTn4iJI4U/+uJhmBrzupDk+n1Ln/yhXBKlzrhOTH881OHa2PAA36JzNsQWREBGGCd8f3zImMzeoQeF4u9z4JnmwdB+nHTz7g/9emEnwFQHWcl3YvWPAGuAT/XnahSZwKawTpSKNAx7EIphVOmckNO/ec7HrmN9WkFXCQhD8ipOBwqSFhWt9mtw48KedVxzXixBu/ucNdMK4z2AHnf1ilYciCILcP9KI5MlHcNm04d7GLWsahzmSy2fes1NptOnlgX0s4QegPAm10McufoaXw7H1GBMiHqhJ9Uk86Rav+3IuZkF9Pl6krYp3CQo4C8C0hTTSdoUUkjuE9sJeYyG+AuNArcVG2Ozikqy1Y5Lwf6MhRkkgzm9MT8UG4wCOdr2Gr5RibJdTr3id9Ay4F823OUs1qjAQmDkS4GDKOKFFwcXXeK+xmyZ6x4J4p61u5I/PXNnplmXr920xgeIoRUKLpBTNIB7MKq7o3N/ceY25wP4MAymlvZzquAdlcyiQjDpcKlRndUwdHVMoRRAMoGRpz4jtXk+j+erO5rRuSiD3XZ5RzDX7Dryt944PR28gYv6G7G5vXzeZ9gsFBIkBJ2tbwrLcjhacyKUdyjSVTVxG1F8fVZkX5S4aXuwwgGeu8X2B4/fNlI4dls4t3fvvDTzJix/HL04TUUWcfumSifjRdxr6c= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(40460700001)(316002)(16526019)(5660300002)(86362001)(186003)(1076003)(2616005)(6666004)(336012)(426003)(54906003)(4326008)(110136005)(82310400004)(47076005)(36756003)(70206006)(83380400001)(8936002)(356005)(81166007)(2906002)(36860700001)(70586007)(508600001)(7696005)(7416002)(26005)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:38:23.4522 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0a79cbbd-aa6b-4955-c17d-08d9b3fe4c6d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4484 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce the marco definitions and access helper function for amd-pstate sysfs interfaces such as each performance goals and frequency levels in amd helper file. They will be used to read the sysfs attribute from amd-pstate cpufreq driver for cpupower utilities. Signed-off-by: Huang Rui --- tools/power/cpupower/utils/helpers/amd.c | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/tools/power/cpupower/utils/helpers/amd.c b/tools/power/cpupower/utils/helpers/amd.c index 97f2c857048e..14c658daba4b 100644 --- a/tools/power/cpupower/utils/helpers/amd.c +++ b/tools/power/cpupower/utils/helpers/amd.c @@ -8,7 +8,10 @@ #include #include "helpers/helpers.h" +#include "cpufreq.h" +#include "acpi_cppc.h" +/* ACPI P-States Helper Functions for AMD Processors ***************/ #define MSR_AMD_PSTATE_STATUS 0xc0010063 #define MSR_AMD_PSTATE 0xc0010064 #define MSR_AMD_PSTATE_LIMIT 0xc0010061 @@ -146,4 +149,31 @@ int amd_pci_get_num_boost_states(int *active, int *states) pci_cleanup(pci_acc); return 0; } + +/* ACPI P-States Helper Functions for AMD Processors ***************/ + +/* AMD P-States Helper Functions ***************/ +enum amd_pstate_value { + AMD_PSTATE_HIGHEST_PERF, + AMD_PSTATE_MAX_FREQ, + AMD_PSTATE_LOWEST_NONLINEAR_FREQ, + MAX_AMD_PSTATE_VALUE_READ_FILES, +}; + +static const char *amd_pstate_value_files[MAX_AMD_PSTATE_VALUE_READ_FILES] = { + [AMD_PSTATE_HIGHEST_PERF] = "amd_pstate_highest_perf", + [AMD_PSTATE_MAX_FREQ] = "amd_pstate_max_freq", + [AMD_PSTATE_LOWEST_NONLINEAR_FREQ] = "amd_pstate_lowest_nonlinear_freq", +}; + +static unsigned long amd_pstate_get_data(unsigned int cpu, + enum amd_pstate_value value) +{ + return cpufreq_get_sysfs_value_from_table(cpu, + amd_pstate_value_files, + value, + MAX_AMD_PSTATE_VALUE_READ_FILES); +} + +/* AMD P-States Helper Functions ***************/ #endif /* defined(__i386__) || defined(__x86_64__) */ From patchwork Tue Nov 30 12:36:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12647221 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E6EAC433EF for ; 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Tue, 30 Nov 2021 06:38:23 -0600 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 19/22] cpupower: enable boost state support for amd-pstate module Date: Tue, 30 Nov 2021 20:36:38 +0800 Message-ID: <20211130123641.1449041-20-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c1a81d19-0de6-46bd-01e5-08d9b3fe4f10 X-MS-TrafficTypeDiagnostic: MWHPR12MB1613: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BXigq1cRT5DH/WTBmOTl0mcScxBib8pzxGbylUeN9VDbeVhy1E9+3nwjtRNHbvnbJzGxKYx6Ar/w2VdfTseEwXp4KuzwbeBL0YePRz4DbOSSE6oClHYmjmPTxtH5ldi4MW1sSNGtyJYMClMbzB9S2HJ64ZVDtKf02WpGvO3s+3Oc5bmACnncC0djaMgzrDmKb2SNbAQ8hRkSuWwkToyq0/8PBVYwRKXk6bcQfTx2HrfRDumrOO/wZx/wiVIEo5a8SfG0DND4UfwNW4xrUFBLGZ02HbK0lli2U5qVlo3/x+g02U491E0IC/VaYYhqhzs6m3gHfJDseUED86tZqjmRhMYzaz0gY0mu4MO1sDQXu9CkCgMZsc2gJVndglaN3y/DRYBmNuEeDWL3z1rnVNbCPuYN1GWopjTp0Dww8O5c+bgu7VJ+Us4yCt5WJXQ9rFeCAyt8sdR7pyhh7HRauE7WSjHPKVu9YDTfgVHh7M9AwE8Itsmzs8gVIJNAX26vpM27nxnLHuaTTsRIuKMmAwm95VWnhsQbl1ayFA1VPSqqrr6Xq/qjFdwh+5BgN4rQx68LJu9bjXvv3EzMbxNvk1workQpbBgF1sNDDZ4rQun3YiN/tyYHW1WwOZE7Jet+mj5d+s+boqW+ATOUn0NrCvWuc9qGQeN6cDQRxIzpXU1Gy4WxKZcaRV/aXQ12f1I1gsx9XXy3ZjiWpZfCfQPsNiMbDkAAa1mPpun8cO+digbX9iemFJyVVKD9A4HkXKNktuBIjX2gnNTAlzT5WtNbH+MwR3oOi/M3OU5Vkg8sPHTDbyU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(36860700001)(4326008)(336012)(8936002)(2616005)(82310400004)(7696005)(26005)(2906002)(356005)(47076005)(36756003)(16526019)(8676002)(5660300002)(508600001)(81166007)(426003)(7416002)(1076003)(316002)(110136005)(54906003)(70586007)(70206006)(6666004)(186003)(86362001)(40460700001)(83380400001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:38:27.8720 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c1a81d19-0de6-46bd-01e5-08d9b3fe4f10 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1613 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The legacy ACPI hardware P-States function has 3 P-States on ACPI table, the CPU frequency only can be switched between the 3 P-States. While the processor supports the boost state, it will have another boost state that the frequency can be higher than P0 state, and the state can be decoded by the function of decode_pstates() and read by amd_pci_get_num_boost_states(). However, the new AMD P-States function is different than legacy ACPI hardware P-State on AMD processors. That has a finer grain frequency range between the highest and lowest frequency. And boost frequency is actually the frequency which is mapped on highest performance ratio. The similiar previous P0 frequency is mapped on nominal performance ratio. If the highest performance on the processor is higher than nominal performance, then we think the current processor supports the boost state. And it uses amd_pstate_boost_init() to initialize boost for AMD P-States function. Signed-off-by: Huang Rui --- tools/power/cpupower/utils/helpers/amd.c | 18 ++++++++++++++++++ tools/power/cpupower/utils/helpers/helpers.h | 5 +++++ tools/power/cpupower/utils/helpers/misc.c | 2 ++ 3 files changed, 25 insertions(+) diff --git a/tools/power/cpupower/utils/helpers/amd.c b/tools/power/cpupower/utils/helpers/amd.c index 14c658daba4b..bde6065cabf4 100644 --- a/tools/power/cpupower/utils/helpers/amd.c +++ b/tools/power/cpupower/utils/helpers/amd.c @@ -175,5 +175,23 @@ static unsigned long amd_pstate_get_data(unsigned int cpu, MAX_AMD_PSTATE_VALUE_READ_FILES); } +void amd_pstate_boost_init(unsigned int cpu, int *support, int *active) +{ + unsigned long highest_perf, nominal_perf, cpuinfo_min, + cpuinfo_max, amd_pstate_max; + + highest_perf = amd_pstate_get_data(cpu, AMD_PSTATE_HIGHEST_PERF); + nominal_perf = acpi_cppc_get_data(cpu, NOMINAL_PERF); + + *support = highest_perf > nominal_perf ? 1 : 0; + if (!(*support)) + return; + + cpufreq_get_hardware_limits(cpu, &cpuinfo_min, &cpuinfo_max); + amd_pstate_max = amd_pstate_get_data(cpu, AMD_PSTATE_MAX_FREQ); + + *active = cpuinfo_max == amd_pstate_max ? 1 : 0; +} + /* AMD P-States Helper Functions ***************/ #endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/tools/power/cpupower/utils/helpers/helpers.h b/tools/power/cpupower/utils/helpers/helpers.h index e03cc97297aa..c03925bea655 100644 --- a/tools/power/cpupower/utils/helpers/helpers.h +++ b/tools/power/cpupower/utils/helpers/helpers.h @@ -140,6 +140,8 @@ extern int cpufreq_has_boost_support(unsigned int cpu, int *support, /* AMD P-States stuff **************************/ extern bool cpupower_amd_pstate_enabled(void); +extern void amd_pstate_boost_init(unsigned int cpu, + int *support, int *active); /* AMD P-States stuff **************************/ @@ -177,6 +179,9 @@ static inline int cpufreq_has_boost_support(unsigned int cpu, int *support, static inline bool cpupower_amd_pstate_enabled(void) { return false; } +static void amd_pstate_boost_init(unsigned int cpu, + int *support, int *active) +{ return; } /* cpuid and cpuinfo helpers **************************/ diff --git a/tools/power/cpupower/utils/helpers/misc.c b/tools/power/cpupower/utils/helpers/misc.c index 0c483cdefcc2..e0d3145434d3 100644 --- a/tools/power/cpupower/utils/helpers/misc.c +++ b/tools/power/cpupower/utils/helpers/misc.c @@ -41,6 +41,8 @@ int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active, if (ret) return ret; } + } else if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_PSTATE) { + amd_pstate_boost_init(cpu, support, active); } else if (cpupower_cpu_info.caps & CPUPOWER_CAP_INTEL_IDA) *support = *active = 1; return 0; From patchwork Tue Nov 30 12:36:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12647223 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB1C4C433EF for ; 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Tue, 30 Nov 2021 06:38:27 -0600 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 20/22] cpupower: move print_speed function into misc helper Date: Tue, 30 Nov 2021 20:36:39 +0800 Message-ID: <20211130123641.1449041-21-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 527f336d-a2b9-4cd2-5617-08d9b3fe51c6 X-MS-TrafficTypeDiagnostic: DM6PR12MB5533: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4125; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uXk6W9X6R8sgMg93Fwm2tMUye4W7Cdb5zAWlLEKM3MD+HR/iO30Xf7AwHPu/xweOzV0MxLFVearxSOudnG86XAhHqCuidyGxrUny9s3WbwvxzCCuYMHLQis3k4bCSWoWepBQiYSiuGDJK6RtAnApGAJg3U0KYNo1LVnRz0c7r36K0qmAJPyg+rTQnz6rZjLJHjUIOkAzbuEKB4w1Qnb71Y1JtHcAQmV2WXhvI20MLmfYrqsaKfk+5nkaN2R2uNOVm2eGy1KZKkjgjWQs9DxsOF7IAudrjXHabSHh8euWlMNEGVqGu+2d/5YdxrqO+KlRb8K8P969fyQBZVTlaaIY6CfmGq/1lTiskjFexBNuEdu9bGFdakrpPEe4D0pksgFDr/0DqyiNVnUGD8xXsJ0Z6XU2kJGG+CJlFsnV8DzA1bAP+mrYVRPURuIUe+kS5fhDIciDOY05KYAxT+LuoIZ/S/3e56iolHAFDQTc/SAAPw6gmDJJ/ey8EiIAhxaT7+nzfogtVw+QELe+CKfOWW7q8QJXMPx3JrmgIkB5YPcObYKlwPUVzJOOO836AppLMDPhgNGag9rDcFadwOWhQih6Vu9+bzHselO3AA0UX90rmtFKMwBePGpS3IYoufWvnUBq2oY/YhIBZIMl9kopxPFZh/db8x+kcDALvLyamgWVJSIim7iuZSuZcigpy3K/3yAxslVl222HSJ9KdeG5rgcFl3vXabc6wbA6yFWAVNqxDyHJKddwHwANK9wXGAeZseKR8tMAOeFktm7k3DqDsyNI+YDwknu4zKfc5uIhMWipjUs= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(40470700001)(36860700001)(47076005)(6666004)(36756003)(426003)(336012)(8676002)(186003)(26005)(2616005)(7416002)(7696005)(1076003)(16526019)(356005)(82310400004)(5660300002)(508600001)(4326008)(70206006)(83380400001)(2906002)(70586007)(8936002)(86362001)(316002)(81166007)(54906003)(110136005)(40460700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:38:32.4233 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 527f336d-a2b9-4cd2-5617-08d9b3fe51c6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB5533 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The print_speed can be as a common function, and expose it into misc helper header. Then it can be used on other helper files as well. Signed-off-by: Huang Rui --- tools/power/cpupower/utils/cpufreq-info.c | 59 ++++---------------- tools/power/cpupower/utils/helpers/helpers.h | 1 + tools/power/cpupower/utils/helpers/misc.c | 42 ++++++++++++++ 3 files changed, 54 insertions(+), 48 deletions(-) diff --git a/tools/power/cpupower/utils/cpufreq-info.c b/tools/power/cpupower/utils/cpufreq-info.c index f9895e31ff5a..b429454bf3ae 100644 --- a/tools/power/cpupower/utils/cpufreq-info.c +++ b/tools/power/cpupower/utils/cpufreq-info.c @@ -84,43 +84,6 @@ static void proc_cpufreq_output(void) } static int no_rounding; -static void print_speed(unsigned long speed) -{ - unsigned long tmp; - - if (no_rounding) { - if (speed > 1000000) - printf("%u.%06u GHz", ((unsigned int) speed/1000000), - ((unsigned int) speed%1000000)); - else if (speed > 1000) - printf("%u.%03u MHz", ((unsigned int) speed/1000), - (unsigned int) (speed%1000)); - else - printf("%lu kHz", speed); - } else { - if (speed > 1000000) { - tmp = speed%10000; - if (tmp >= 5000) - speed += 10000; - printf("%u.%02u GHz", ((unsigned int) speed/1000000), - ((unsigned int) (speed%1000000)/10000)); - } else if (speed > 100000) { - tmp = speed%1000; - if (tmp >= 500) - speed += 1000; - printf("%u MHz", ((unsigned int) speed/1000)); - } else if (speed > 1000) { - tmp = speed%100; - if (tmp >= 50) - speed += 100; - printf("%u.%01u MHz", ((unsigned int) speed/1000), - ((unsigned int) (speed%1000)/100)); - } - } - - return; -} - static void print_duration(unsigned long duration) { unsigned long tmp; @@ -254,11 +217,11 @@ static int get_boost_mode(unsigned int cpu) if (freqs) { printf(_(" boost frequency steps: ")); while (freqs->next) { - print_speed(freqs->frequency); + print_speed(freqs->frequency, no_rounding); printf(", "); freqs = freqs->next; } - print_speed(freqs->frequency); + print_speed(freqs->frequency, no_rounding); printf("\n"); cpufreq_put_available_frequencies(freqs); } @@ -277,7 +240,7 @@ static int get_freq_kernel(unsigned int cpu, unsigned int human) return -EINVAL; } if (human) { - print_speed(freq); + print_speed(freq, no_rounding); } else printf("%lu", freq); printf(_(" (asserted by call to kernel)\n")); @@ -296,7 +259,7 @@ static int get_freq_hardware(unsigned int cpu, unsigned int human) return -EINVAL; } if (human) { - print_speed(freq); + print_speed(freq, no_rounding); } else printf("%lu", freq); printf(_(" (asserted by call to hardware)\n")); @@ -316,9 +279,9 @@ static int get_hardware_limits(unsigned int cpu, unsigned int human) if (human) { printf(_(" hardware limits: ")); - print_speed(min); + print_speed(min, no_rounding); printf(" - "); - print_speed(max); + print_speed(max, no_rounding); printf("\n"); } else { printf("%lu %lu\n", min, max); @@ -350,9 +313,9 @@ static int get_policy(unsigned int cpu) return -EINVAL; } printf(_(" current policy: frequency should be within ")); - print_speed(policy->min); + print_speed(policy->min, no_rounding); printf(_(" and ")); - print_speed(policy->max); + print_speed(policy->max, no_rounding); printf(".\n "); printf(_("The governor \"%s\" may decide which speed to use\n" @@ -436,7 +399,7 @@ static int get_freq_stats(unsigned int cpu, unsigned int human) struct cpufreq_stats *stats = cpufreq_get_stats(cpu, &total_time); while (stats) { if (human) { - print_speed(stats->frequency); + print_speed(stats->frequency, no_rounding); printf(":%.2f%%", (100.0 * stats->time_in_state) / total_time); } else @@ -486,11 +449,11 @@ static void debug_output_one(unsigned int cpu) if (freqs) { printf(_(" available frequency steps: ")); while (freqs->next) { - print_speed(freqs->frequency); + print_speed(freqs->frequency, no_rounding); printf(", "); freqs = freqs->next; } - print_speed(freqs->frequency); + print_speed(freqs->frequency, no_rounding); printf("\n"); cpufreq_put_available_frequencies(freqs); } diff --git a/tools/power/cpupower/utils/helpers/helpers.h b/tools/power/cpupower/utils/helpers/helpers.h index c03925bea655..fbbfa6047c83 100644 --- a/tools/power/cpupower/utils/helpers/helpers.h +++ b/tools/power/cpupower/utils/helpers/helpers.h @@ -200,5 +200,6 @@ extern struct bitmask *offline_cpus; void get_cpustate(void); void print_online_cpus(void); void print_offline_cpus(void); +void print_speed(unsigned long speed, int no_rounding); #endif /* __CPUPOWERUTILS_HELPERS__ */ diff --git a/tools/power/cpupower/utils/helpers/misc.c b/tools/power/cpupower/utils/helpers/misc.c index e0d3145434d3..d693c96cd09c 100644 --- a/tools/power/cpupower/utils/helpers/misc.c +++ b/tools/power/cpupower/utils/helpers/misc.c @@ -164,3 +164,45 @@ void print_offline_cpus(void) printf(_("cpupower set operation was not performed on them\n")); } } + +/* + * print_speed + * + * Print the exact CPU frequency with appropriate unit + */ +void print_speed(unsigned long speed, int no_rounding) +{ + unsigned long tmp; + + if (no_rounding) { + if (speed > 1000000) + printf("%u.%06u GHz", ((unsigned int) speed/1000000), + ((unsigned int) speed%1000000)); + else if (speed > 1000) + printf("%u.%03u MHz", ((unsigned int) speed/1000), + (unsigned int) (speed%1000)); + else + printf("%lu kHz", speed); + } else { + if (speed > 1000000) { + tmp = speed%10000; + if (tmp >= 5000) + speed += 10000; + printf("%u.%02u GHz", ((unsigned int) speed/1000000), + ((unsigned int) (speed%1000000)/10000)); + } else if (speed > 100000) { + tmp = speed%1000; + if (tmp >= 500) + speed += 1000; + printf("%u MHz", ((unsigned int) speed/1000)); + } else if (speed > 1000) { + tmp = speed%100; + if (tmp >= 50) + speed += 100; + printf("%u.%01u MHz", ((unsigned int) speed/1000), + ((unsigned int) (speed%1000)/100)); + } + } + + return; +} From patchwork Tue Nov 30 12:36:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12647225 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13937C433F5 for ; Tue, 30 Nov 2021 12:39:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242081AbhK3Mmw (ORCPT ); Tue, 30 Nov 2021 07:42:52 -0500 Received: from mail-mw2nam10on2063.outbound.protection.outlook.com ([40.107.94.63]:4065 "EHLO NAM10-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S241976AbhK3MmB (ORCPT ); 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Tue, 30 Nov 2021 12:38:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT007.mail.protection.outlook.com (10.13.177.109) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Tue, 30 Nov 2021 12:38:36 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 30 Nov 2021 06:38:32 -0600 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 21/22] cpupower: print amd-pstate information on cpupower Date: Tue, 30 Nov 2021 20:36:40 +0800 Message-ID: <20211130123641.1449041-22-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bebddf80-2139-474c-c36e-08d9b3fe5466 X-MS-TrafficTypeDiagnostic: MWHPR1201MB0062: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:655; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: o78OyRIZBxwVqQpcDbJ9X43Sv1A0W+E3fYL9AHxTX96hW+99MenD4SrKrCEi0OpMffp5X56kPR6ltwV+e9mx0SEUE/Mb57nR17n1qYha8erlUmxYkH4RTCOblcsgVNodv5NB0oEwxSIZDt7bEcO5iiRxhNh2z9YxmARv4cw1N8EQ0yOV2VglJDoE20DJhV3wnc7P317gVwedjWzOM9vWGtniBNNS3g9zkIw9M754xYsMviYVDeO80nLHC3lN1dxcHoras2x2Pw0+3xE2nwp96LYlhe/0pYwSPYme3e9d86dY0Mu/k3H/qCwLmAERpQnn4w/5nmrpSYdaG+t57Ci1QswWwJKURykFt6K0vnmJOrS+UmAEDiEgr+mSGzT4IrUufEWkQfhn6NG6ngEqpGSMM1kL9x0xHOwucnCRE/fNxXFEPtcQkoq4hZVfvLaa3EOEdFqEPLbR4mRLcrQfaAW70Ab2Hi4gzi99o5CDluZ6N0FZu+5W9oa0mhrla/4TAd6Fj7NeeOR1qjcDBDypIaoTrH1adodfatUDjjee8hD9G6UC/ZjZl219MzN3cvqRk84GGPQtcdcC13zIwhUkrzWgWPc0cfb6T098Mo1+2DEmHu07z9YwwmNipJKQwd+aDf2J7eCLA48Sya+oGukwzaTi75HqVWuMzjGWgGXBp9nrl65mFuppERnEs2Mq2nEXdz1eWHDJKaNX5vMTdv71UIWBYwrz0Sa8lSKpKH9gLsYkqP5VtNZKjXnwrLgMPzS+gODC3WsKnvIbBYQEsmgkSq0joa0kS5aw+xHWvvnyxC2WDEY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(7696005)(110136005)(2616005)(508600001)(86362001)(83380400001)(54906003)(2906002)(8676002)(16526019)(6666004)(47076005)(336012)(36860700001)(70586007)(426003)(70206006)(8936002)(5660300002)(1076003)(316002)(7416002)(4326008)(356005)(82310400004)(36756003)(81166007)(26005)(186003)(40460700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:38:36.8272 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bebddf80-2139-474c-c36e-08d9b3fe5466 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT007.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1201MB0062 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org amd-pstate kernel module is using the fine grain frequency instead of acpi hardware pstate. So the performance and frequency values should be printed in frequency-info. Signed-off-by: Huang Rui --- tools/power/cpupower/utils/cpufreq-info.c | 9 ++++--- tools/power/cpupower/utils/helpers/amd.c | 28 ++++++++++++++++++++ tools/power/cpupower/utils/helpers/helpers.h | 5 ++++ 3 files changed, 39 insertions(+), 3 deletions(-) diff --git a/tools/power/cpupower/utils/cpufreq-info.c b/tools/power/cpupower/utils/cpufreq-info.c index b429454bf3ae..f828f3c35a6f 100644 --- a/tools/power/cpupower/utils/cpufreq-info.c +++ b/tools/power/cpupower/utils/cpufreq-info.c @@ -146,9 +146,12 @@ static int get_boost_mode_x86(unsigned int cpu) printf(_(" Supported: %s\n"), support ? _("yes") : _("no")); printf(_(" Active: %s\n"), active ? _("yes") : _("no")); - if ((cpupower_cpu_info.vendor == X86_VENDOR_AMD && - cpupower_cpu_info.family >= 0x10) || - cpupower_cpu_info.vendor == X86_VENDOR_HYGON) { + if (cpupower_cpu_info.vendor == X86_VENDOR_AMD && + cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_PSTATE) { + amd_pstate_show_perf_and_freq(cpu, no_rounding); + } else if ((cpupower_cpu_info.vendor == X86_VENDOR_AMD && + cpupower_cpu_info.family >= 0x10) || + cpupower_cpu_info.vendor == X86_VENDOR_HYGON) { ret = decode_pstates(cpu, b_states, pstates, &pstate_no); if (ret) return ret; diff --git a/tools/power/cpupower/utils/helpers/amd.c b/tools/power/cpupower/utils/helpers/amd.c index bde6065cabf4..a1115891d76d 100644 --- a/tools/power/cpupower/utils/helpers/amd.c +++ b/tools/power/cpupower/utils/helpers/amd.c @@ -193,5 +193,33 @@ void amd_pstate_boost_init(unsigned int cpu, int *support, int *active) *active = cpuinfo_max == amd_pstate_max ? 1 : 0; } +void amd_pstate_show_perf_and_freq(unsigned int cpu, int no_rounding) +{ + printf(_(" AMD PSTATE Highest Performance: %lu. Maximum Frequency: "), + amd_pstate_get_data(cpu, AMD_PSTATE_HIGHEST_PERF)); + /* If boost isn't active, the cpuinfo_max doesn't indicate real max + * frequency. So we read it back from amd-pstate sysfs entry. + */ + print_speed(amd_pstate_get_data(cpu, AMD_PSTATE_MAX_FREQ), no_rounding); + printf(".\n"); + + printf(_(" AMD PSTATE Nominal Performance: %lu. Nominal Frequency: "), + acpi_cppc_get_data(cpu, NOMINAL_PERF)); + print_speed(acpi_cppc_get_data(cpu, NOMINAL_FREQ) * 1000, + no_rounding); + printf(".\n"); + + printf(_(" AMD PSTATE Lowest Non-linear Performance: %lu. Lowest Non-linear Frequency: "), + acpi_cppc_get_data(cpu, LOWEST_NONLINEAR_PERF)); + print_speed(amd_pstate_get_data(cpu, AMD_PSTATE_LOWEST_NONLINEAR_FREQ), + no_rounding); + printf(".\n"); + + printf(_(" AMD PSTATE Lowest Performance: %lu. Lowest Frequency: "), + acpi_cppc_get_data(cpu, LOWEST_PERF)); + print_speed(acpi_cppc_get_data(cpu, LOWEST_FREQ) * 1000, no_rounding); + printf(".\n"); +} + /* AMD P-States Helper Functions ***************/ #endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/tools/power/cpupower/utils/helpers/helpers.h b/tools/power/cpupower/utils/helpers/helpers.h index fbbfa6047c83..5f6862502dbf 100644 --- a/tools/power/cpupower/utils/helpers/helpers.h +++ b/tools/power/cpupower/utils/helpers/helpers.h @@ -142,6 +142,8 @@ extern int cpufreq_has_boost_support(unsigned int cpu, int *support, extern bool cpupower_amd_pstate_enabled(void); extern void amd_pstate_boost_init(unsigned int cpu, int *support, int *active); +extern void amd_pstate_show_perf_and_freq(unsigned int cpu, + int no_rounding); /* AMD P-States stuff **************************/ @@ -182,6 +184,9 @@ static inline bool cpupower_amd_pstate_enabled(void) static void amd_pstate_boost_init(unsigned int cpu, int *support, int *active) { return; } +static inline void amd_pstate_show_perf_and_freq(unsigned int cpu, + int no_rounding) +{ return; } /* cpuid and cpuinfo helpers **************************/ From patchwork Tue Nov 30 12:36:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12647227 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5A81C433F5 for ; Tue, 30 Nov 2021 12:39:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232102AbhK3MnJ (ORCPT ); Tue, 30 Nov 2021 07:43:09 -0500 Received: from mail-dm3nam07on2063.outbound.protection.outlook.com ([40.107.95.63]:64808 "EHLO NAM02-DM3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231908AbhK3MmH (ORCPT ); Tue, 30 Nov 2021 07:42:07 -0500 ARC-Seal: i=1; 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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 22/22] Documentation: amd-pstate: add amd-pstate driver introduction Date: Tue, 30 Nov 2021 20:36:41 +0800 Message-ID: <20211130123641.1449041-23-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9d99d9be-38f7-4a62-e22a-08d9b3fe58a0 X-MS-TrafficTypeDiagnostic: BY5PR12MB4177: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: roc1r5sfucSDYGAUpqgax+Ghfcxe/0JkQ66nMMs3gQmUnkuCSbj+IEmUyiV1kd611++umqAsLjmmbXh/0502DL1Uy1jq3I4s0gAAsJLLOCPjQzFMJyWHg4t83Q+1qQPR9GMHvLyhEtJY3IKM00W11Njt2Fzj2sBJKG68Nw2do2S+33gmSuHF3JY9tPbiPAHuah7nfrqF4hhZZT7ZawQmtuI1bK5H/I0MEFgnHNJhJcAZPsHPNHq44z0oPhoyxcvzj3mY8AXIWc7zkJxR0GmLpxCw8on+A7OYH1AsclzzPdrIhGJmRuRCHJORzaJJdxQ2uR/VCYJjW7P5nCv/ILKU2W4o4EdLRnDmjzavP18izfep/aDYQIE8kqs4PuD0q9xs3hWfwKQVQaHxoFwZ0Fv6Y4UhJTGQto6pJGCIZ0cNtvsTBtwt7ZhCHG1d/zlA++jjPfnqTYNsrIyhN9X/1VIgvnluF9Zeh36odpU3Vjn4hxMNo6ZNDm2yqe5xf4qGldLxmstlhNEnXXCrw3eITiN+VIUigznSlRa3Hcj12v7umvhZn8WbxuMRKWBbcwJmbX0kg6/6Cnsxl6RiXO3QzOmQMxDPExaezwRyH4ApZac3KUJsLDg1ctcsYpnmUOagtRxPqWB+DfSv9eNggPw187+mB/2IzKqj+lyXK4g0pG+QPO/yPT9kz4b0p1sMAgE67VqOYcgaiPU4jMzIL5LgWxOerxJw9Rhvx/USxYQMyIKJ3/9zGdcRlw8K5UXT3gl2yEr2VORTDKyv9r8v6xf9WYUQIAXMyMqaJH5yq+n6Wn4qmgbW0dhKfCPfQs5m9FAuvsSAmCaLKsedjw7LBf4I0OHdRMF00VW3ZHIGTNChEM7nmVHts5UIxSz67jV6C6P9/IG0S/9TEU78Bh6MFVywdEjrbZ8IhFZEtEgsAWfwVUgsprLDejHy1QHA5T2Sij0tEB2ymptWKcuy30iKsPyWTkO51ln7kowHnHCR/femmmAA+FU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(83380400001)(8676002)(81166007)(82310400004)(110136005)(86362001)(70586007)(26005)(7416002)(186003)(4326008)(70206006)(54906003)(2906002)(16526019)(426003)(2616005)(8936002)(7696005)(1076003)(36860700001)(6666004)(36756003)(966005)(508600001)(316002)(356005)(30864003)(47076005)(336012)(5660300002)(40460700001)(21314003)(36900700001)(473944003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:38:43.8880 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9d99d9be-38f7-4a62-e22a-08d9b3fe58a0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4177 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce the amd-pstate driver design and implementation. Signed-off-by: Huang Rui --- Documentation/admin-guide/acpi/cppc_sysfs.rst | 2 + Documentation/admin-guide/pm/amd-pstate.rst | 383 ++++++++++++++++++ .../admin-guide/pm/working-state.rst | 1 + 3 files changed, 386 insertions(+) create mode 100644 Documentation/admin-guide/pm/amd-pstate.rst diff --git a/Documentation/admin-guide/acpi/cppc_sysfs.rst b/Documentation/admin-guide/acpi/cppc_sysfs.rst index fccf22114e85..e53d76365aa7 100644 --- a/Documentation/admin-guide/acpi/cppc_sysfs.rst +++ b/Documentation/admin-guide/acpi/cppc_sysfs.rst @@ -4,6 +4,8 @@ Collaborative Processor Performance Control (CPPC) ================================================== +.. _cppc_sysfs: + CPPC ==== diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst new file mode 100644 index 000000000000..6bafb9354ba0 --- /dev/null +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -0,0 +1,383 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. include:: + +=============================================== +``amd-pstate`` CPU Performance Scaling Driver +=============================================== + +:Copyright: |copy| 2021 Advanced Micro Devices, Inc. + +:Author: Huang Rui + + +Introduction +=================== + +``amd-pstate`` is the AMD CPU performance scaling driver that introduces a +new CPU frequency control mechanism on modern AMD APU and CPU series in +Linux kernel. The new mechanism is based on Collaborative Processor +Performance Control (CPPC) which provides finer grain frequency management +than legacy ACPI hardware P-States. Current AMD CPU/APU platforms are using +the ACPI P-states driver to manage CPU frequency and clocks with switching +only in 3 P-states. CPPC replaces the ACPI P-states controls, allows a +flexible, low-latency interface for the Linux kernel to directly +communicate the performance hints to hardware. + +``amd-pstate`` leverages the Linux kernel governors such as ``schedutil``, +``ondemand``, etc. to manage the performance hints which are provided by +CPPC hardware functionality that internally follows the hardware +specification (for details refer to AMD64 Architecture Programmer's Manual +Volume 2: System Programming [1]_). Currently ``amd-pstate`` supports basic +frequency control function according to kernel governors on some of the +Zen2 and Zen3 processors, and we will implement more AMD specific functions +in future after we verify them on the hardware and SBIOS. + + +AMD CPPC Overview +======================= + +Collaborative Processor Performance Control (CPPC) interface enumerates a +continuous, abstract, and unit-less performance value in a scale that is +not tied to a specific performance state / frequency. This is an ACPI +standard [2]_ which software can specify application performance goals and +hints as a relative target to the infrastructure limits. AMD processors +provides the low latency register model (MSR) instead of AML code +interpreter for performance adjustments. ``amd-pstate`` will initialize a +``struct cpufreq_driver`` instance ``amd_pstate_driver`` with the callbacks +to manage each performance update behavior. :: + + Highest Perf ------>+-----------------------+ +-----------------------+ + | | | | + | | | | + | | Max Perf ---->| | + | | | | + | | | | + Nominal Perf ------>+-----------------------+ +-----------------------+ + | | | | + | | | | + | | | | + | | | | + | | | | + | | | | + | | Desired Perf ---->| | + | | | | + | | | | + | | | | + | | | | + | | | | + | | | | + | | | | + | | | | + | | | | + Lowest non- | | | | + linear perf ------>+-----------------------+ +-----------------------+ + | | | | + | | Lowest perf ---->| | + | | | | + Lowest perf ------>+-----------------------+ +-----------------------+ + | | | | + | | | | + | | | | + 0 ------>+-----------------------+ +-----------------------+ + + AMD P-States Performance Scale + + +.. _perf_cap: + +AMD CPPC Performance Capability +-------------------------------- + +Highest Performance (RO) +......................... + +It is the absolute maximum performance an individual processor may reach, +assuming ideal conditions. This performance level may not be sustainable +for long durations and may only be achievable if other platform components +are in a specific state; for example, it may require other processors be in +an idle state. This would be equivalent to the highest frequencies +supported by the processor. + +Nominal (Guaranteed) Performance (RO) +...................................... + +It is the maximum sustained performance level of the processor, assuming +ideal operating conditions. In absence of an external constraint (power, +thermal, etc.) this is the performance level the processor is expected to +be able to maintain continuously. All cores/processors are expected to be +able to sustain their nominal performance state simultaneously. + +Lowest non-linear Performance (RO) +................................... + +It is the lowest performance level at which nonlinear power savings are +achieved, for example, due to the combined effects of voltage and frequency +scaling. Above this threshold, lower performance levels should be generally +more energy efficient than higher performance levels. This register +effectively conveys the most efficient performance level to ``amd-pstate``. + +Lowest Performance (RO) +........................ + +It is the absolute lowest performance level of the processor. Selecting a +performance level lower than the lowest nonlinear performance level may +cause an efficiency penalty but should reduce the instantaneous power +consumption of the processor. + +AMD CPPC Performance Control +------------------------------ + +``amd-pstate`` passes performance goals through these registers. The +register drives the behavior of the desired performance target. + +Minimum requested performance (RW) +................................... + +``amd-pstate`` specifies the minimum allowed performance level. + +Maximum requested performance (RW) +................................... + +``amd-pstate`` specifies a limit the maximum performance that is expected +to be supplied by the hardware. + +Desired performance target (RW) +................................... + +``amd-pstate`` specifies a desired target in the CPPC performance scale as +a relative number. This can be expressed as percentage of nominal +performance (infrastructure max). Below the nominal sustained performance +level, desired performance expresses the average performance level of the +processor subject to hardware. Above the nominal performance level, +processor must provide at least nominal performance requested and go higher +if current operating conditions allow. + +Energy Performance Preference (EPP) (RW) +......................................... + +Provides a hint to the hardware if software wants to bias toward performance +(0x0) or energy efficiency (0xff). + + +Key Governors Support +======================= + +``amd-pstate`` can be used with all the (generic) scaling governors listed +by the ``scaling_available_governors`` policy attribute in ``sysfs``. Then, +it is responsible for the configuration of policy objects corresponding to +CPUs and provides the ``CPUFreq`` core (and the scaling governors attached +to the policy objects) with accurate information on the maximum and minimum +operating frequencies supported by the hardware. Users can check the +``scaling_cur_freq`` information comes from the ``CPUFreq`` core. + +``amd-pstate`` mainly supports ``schedutil`` and ``ondemand`` for dynamic +frequency control. It is to fine tune the processor configuration on +``amd-pstate`` to the ``schedutil`` with CPU CFS scheduler. ``amd-pstate`` +registers adjust_perf callback to implement the CPPC similar performance +update behavior. It is initialized by ``sugov_start`` and then populate the +CPU's update_util_data pointer to assign ``sugov_update_single_perf`` as +the utilization update callback function in CPU scheduler. CPU scheduler +will call ``cpufreq_update_util`` and assign the target performance +according to the ``struct sugov_cpu`` that utilization update belongs to. +Then ``amd-pstate`` updates the desired performance according to the CPU +scheduler assigned. + + +Processor Support +======================= + +The ``amd-pstate`` initialization will fail if the _CPC in ACPI SBIOS is +not existed at the detected processor, and it uses ``acpi_cpc_valid`` to +check the _CPC existence. All Zen based processors support legacy ACPI +hardware P-States function, so while the ``amd-pstate`` fails to be +initialized, the kernel will fall back to initialize ``acpi-cpufreq`` +driver. + +There are two types of hardware implementations for ``amd-pstate``: one is +`Full MSR Support `_ and another is `Shared Memory Support +`_. It can use :c:macro:`X86_FEATURE_CPPC` feature flag (for +details refer to Processor Programming Reference (PPR) for AMD Family +19h Model 51h, Revision A1 Processors [3]_) to indicate the different +types. ``amd-pstate`` is to register different ``static_call`` instances +for different hardware implementations. + +Currently, some of Zen2 and Zen3 processors support ``amd-pstate``. In the +future, it will be supported on more and more AMD processors. + +Full MSR Support +----------------- + +Some new Zen3 processors such as Cezanne provide the MSR registers directly +while the :c:macro:`X86_FEATURE_CPPC` CPU feature flag is set. +``amd-pstate`` can handle the MSR register to implement the fast switch +function in ``CPUFreq`` that can shrink latency of frequency control on the +interrupt context. The functions with ``pstate_xxx`` prefix represent the +operations of MSR registers. + +Shared Memory Support +---------------------- + +If :c:macro:`X86_FEATURE_CPPC` CPU feature flag is not set, that means the +processor supports shared memory solution. In this case, ``amd-pstate`` +uses the ``cppc_acpi`` helper methods to implement the callback functions +that defined on ``static_call``. The functions with ``cppc_xxx`` prefix +represent the operations of acpi cppc helpers for shared memory solution. + + +AMD P-States and ACPI hardware P-States always can be supported in one +processor. But AMD P-States has the higher priority and if it is enabled +with :c:macro:`MSR_AMD_CPPC_ENABLE` or ``cppc_set_enable``, it will respond +to the request from AMD P-States. + + +User Space Interface in ``sysfs`` +================================== + +``amd-pstate`` exposes several global attributes (files) in ``sysfs`` to +control its functionality at the system level. They located in the +``/sys/devices/system/cpu/cpufreq/policyX/`` directory and affect all CPUs. :: + + root@hr-test1:/home/ray# ls /sys/devices/system/cpu/cpufreq/policy0/*amd* + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_highest_perf + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_lowest_nonlinear_freq + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_max_freq + + +``amd_pstate_highest_perf / amd_pstate_max_freq`` + +Maximum CPPC performance and CPU frequency that the driver is allowed to +set in percent of the maximum supported CPPC performance level (the highest +performance supported in `AMD CPPC Performance Capability `_). +In some of ASICs, the highest CPPC performance is not the one in the _CPC +table, so we need to expose it to sysfs. If boost is not active but +supported, this maximum frequency will be larger than the one in +``cpuinfo``. +This attribute is read-only. + +``amd_pstate_lowest_nonlinear_freq`` + +The lowest non-linear CPPC CPU frequency that the driver is allowed to set +in percent of the maximum supported CPPC performance level (Please see the +lowest non-linear performance in `AMD CPPC Performance Capability +`_). +This attribute is read-only. + +For other performance and frequency values, we can read them back from +``/sys/devices/system/cpu/cpuX/acpi_cppc/``, see :ref:`cppc_sysfs`. + + +``amd-pstate`` vs ``acpi-cpufreq`` +====================================== + +On majority of AMD platforms supported by ``acpi-cpufreq``, the ACPI tables +provided by the platform firmware used for CPU performance scaling, but +only provides 3 P-states on AMD processors. +However, on modern AMD APU and CPU series, it provides the collaborative +processor performance control according to ACPI protocol and customize this +for AMD platforms. That is fine-grain and continuous frequency range +instead of the legacy hardware P-states. ``amd-pstate`` is the kernel +module which supports the new AMD P-States mechanism on most of future AMD +platforms. The AMD P-States mechanism will be the more performance and energy +efficiency frequency management method on AMD processors. + +Kernel Module Options for ``amd-pstate`` +========================================= + +``shared_mem`` +Use a module param (shared_mem) to enable related processors manually with +**amd_pstate.shared_mem=1**. +Due to the performance issue on the processors with `Shared Memory Support +`_, so we disable it for the moment and will enable this by default +once we address performance issue on this solution. + +The way to check whether current processor is `Full MSR Support `_ +or `Shared Memory Support `_ : :: + + ray@hr-test1:~$ lscpu | grep cppc + Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf rapl pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate ssbd mba ibrs ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr rdpru wbnoinvd cppc arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif v_spec_ctrl umip pku ospke vaes vpclmulqdq rdpid overflow_recov succor smca fsrm + +If CPU Flags have cppc, then this processor supports `Full MSR Support +`_. Otherwise it supports `Shared Memory Support `_. + + +``cpupower`` tool support for ``amd-pstate`` +=============================================== + +``amd-pstate`` is supported on ``cpupower`` tool that can be used to dump the frequency +information. And it is in progress to support more and more operations for new +``amd-pstate`` module with this tool. :: + + root@hr-test1:/home/ray# cpupower frequency-info + analyzing CPU 0: + driver: amd-pstate + CPUs which run at the same hardware frequency: 0 + CPUs which need to have their frequency coordinated by software: 0 + maximum transition latency: 131 us + hardware limits: 400 MHz - 4.68 GHz + available cpufreq governors: ondemand conservative powersave userspace performance schedutil + current policy: frequency should be within 400 MHz and 4.68 GHz. + The governor "schedutil" may decide which speed to use + within this range. + current CPU frequency: Unable to call hardware + current CPU frequency: 4.02 GHz (asserted by call to kernel) + boost state support: + Supported: yes + Active: yes + AMD PSTATE Highest Performance: 166. Maximum Frequency: 4.68 GHz. + AMD PSTATE Nominal Performance: 117. Nominal Frequency: 3.30 GHz. + AMD PSTATE Lowest Non-linear Performance: 39. Lowest Non-linear Frequency: 1.10 GHz. + AMD PSTATE Lowest Performance: 15. Lowest Frequency: 400 MHz. + + +Diagnostics and Tuning +======================= + +Trace Events +-------------- + +There are two static trace events that can be used for ``amd-pstate`` +diagnostics. One of them is the cpu_frequency trace event generally used +by ``CPUFreq``, and the other one is the ``amd_pstate_perf`` trace event +specific to ``amd-pstate``. The following sequence of shell commands can +be used to enable them and see their output (if the kernel is generally +configured to support event tracing). :: + + root@hr-test1:/home/ray# cd /sys/kernel/tracing/ + root@hr-test1:/sys/kernel/tracing# echo 1 > events/amd_cpu/enable + root@hr-test1:/sys/kernel/tracing# cat trace + # tracer: nop + # + # entries-in-buffer/entries-written: 47827/42233061 #P:2 + # + # _-----=> irqs-off + # / _----=> need-resched + # | / _---=> hardirq/softirq + # || / _--=> preempt-depth + # ||| / delay + # TASK-PID CPU# |||| TIMESTAMP FUNCTION + # | | | |||| | | + -0 [015] dN... 4995.979886: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=15 changed=false fast_switch=true + -0 [007] d.h.. 4995.979893: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=7 changed=false fast_switch=true + cat-2161 [000] d.... 4995.980841: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=0 changed=false fast_switch=true + sshd-2125 [004] d.s.. 4995.980968: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=4 changed=false fast_switch=true + -0 [007] d.s.. 4995.980968: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=7 changed=false fast_switch=true + -0 [003] d.s.. 4995.980971: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=3 changed=false fast_switch=true + -0 [011] d.s.. 4995.980996: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=11 changed=false fast_switch=true + +The cpu_frequency trace event will be triggered either by the ``schedutil`` scaling +governor (for the policies it is attached to), or by the ``CPUFreq`` core (for the +policies with other scaling governors). + + +Reference +=========== + +.. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming, + https://www.amd.com/system/files/TechDocs/24593.pdf + +.. [2] Advanced Configuration and Power Interface Specification, + https://uefi.org/sites/default/files/resources/ACPI_Spec_6_4_Jan22.pdf + +.. [3] Processor Programming Reference (PPR) for AMD Family 19h Model 51h, Revision A1 Processors + https://www.amd.com/system/files/TechDocs/56569-A1-PUB.zip + diff --git a/Documentation/admin-guide/pm/working-state.rst b/Documentation/admin-guide/pm/working-state.rst index f40994c422dc..5d2757e2de65 100644 --- a/Documentation/admin-guide/pm/working-state.rst +++ b/Documentation/admin-guide/pm/working-state.rst @@ -11,6 +11,7 @@ Working-State Power Management intel_idle cpufreq intel_pstate + amd-pstate cpufreq_drivers intel_epb intel-speed-select