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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; Received: from SATLEXMB03.amd.com (165.204.84.17) by CO1NAM11FT015.mail.protection.outlook.com (10.13.175.130) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4755.13 via Frontend Transport; Thu, 2 Dec 2021 23:59:17 +0000 Received: from sos-ubuntu2004-quartz01.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 2 Dec 2021 17:59:14 -0600 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v2 1/3] KVM: SVM: Refactor AVIC hardware setup logic into helper function Date: Thu, 2 Dec 2021 17:58:23 -0600 Message-ID: <20211202235825.12562-2-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211202235825.12562-1-suravee.suthikulpanit@amd.com> References: <20211202235825.12562-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 80f307a1-a74a-4ae0-7660-08d9b5efc057 X-MS-TrafficTypeDiagnostic: DM6PR12MB3628: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:30; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2021 23:59:17.6772 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 80f307a1-a74a-4ae0-7660-08d9b5efc057 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3628 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org To prepare for upcoming AVIC changes. There is no functional change. Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/svm/avic.c | 10 ++++++++++ arch/x86/kvm/svm/svm.c | 8 +------- arch/x86/kvm/svm/svm.h | 1 + 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 8052d92069e0..6aca1682f4b7 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -1011,3 +1011,13 @@ void svm_vcpu_unblocking(struct kvm_vcpu *vcpu) kvm_vcpu_update_apicv(vcpu); avic_set_running(vcpu, true); } + +bool avic_hardware_setup(bool avic, bool npt) +{ + if (!avic || !npt || !boot_cpu_has(X86_FEATURE_AVIC)) + return false; + + pr_info("AVIC enabled\n"); + amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier); + return true; +} diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 989685098b3e..d23bc7a7c48e 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -1031,13 +1031,7 @@ static __init int svm_hardware_setup(void) nrips = false; } - enable_apicv = avic = avic && npt_enabled && boot_cpu_has(X86_FEATURE_AVIC); - - if (enable_apicv) { - pr_info("AVIC enabled\n"); - - amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier); - } + enable_apicv = avic = avic_hardware_setup(avic, npt_enabled); if (vls) { if (!npt_enabled || diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 5d30db599e10..1d2d72e56dd1 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -515,6 +515,7 @@ static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu) return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); } +bool avic_hardware_setup(bool avic, bool npt); int avic_ga_log_notifier(u32 ga_tag); void avic_vm_destroy(struct kvm *kvm); int avic_vm_init(struct kvm *kvm); From patchwork Thu Dec 2 23:58:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Suthikulpanit, Suravee" X-Patchwork-Id: 12653853 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D33CC433F5 for ; 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Thu, 2 Dec 2021 17:59:15 -0600 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v2 2/3] x86/apic: Add helper function to get maximum physical APIC ID Date: Thu, 2 Dec 2021 17:58:24 -0600 Message-ID: <20211202235825.12562-3-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211202235825.12562-1-suravee.suthikulpanit@amd.com> References: <20211202235825.12562-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 20121b59-ff1e-4c27-bcb9-08d9b5efc0bd X-MS-TrafficTypeDiagnostic: BN8PR12MB2897: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1148; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: i2ae/Kmb+gXcTamGnOchYMx4de3p3nbU2puQqNZizFK9/7o5MysmlWOy21xBATzyqxi7cSlFKKyGbd43r9+7DoV8hR+Pnh5isg/piDPYs9XHVHmlIjznlgRqPkKB1llxQfS1HzFSda4rt9c9SNS9A1H1+sFr5TkcIaL4SpCdUfAjSkHEkoWSdkI037HBz1LCktDMtLRLeFBZwfVOXPWsF2Kn6RaBhRIRfJ39W1H0qgipfO0leIx3E92ugAstkp2MZzOqggIMbh01wEpIXimxS9mfDFjkYWYHXOZ94/IYCjvxXn6MXXQ16BqgAFpg1wq+7xBixhvJsg+WMSUnEMyTnDTysoiZP9F18QyrWFNFKr3BZVyp5qxACRB1yVconPMIJcn3ycX5i+1WGanfSmcudklQu5adfFUemrTV46OoIUyjnZyyja9GlKmeyExf6ZWMeJ4bBqUxlfOWrgOKuy3EDfISN0IkrNkR2fja7KLhdGwSRn0JlbgXgyFvYZcBv+ZthWD5zF9USJeuaiXCTwOjDNKTrQDf4pLXEAftZ0TU/UYpPCkLhImtTGTi6cvGEFMplZSsm25XEgYZvE/CBC4ZxvZNdqO/BbK34xhH5XM1qM/4CTmkwu+DFmytt/MkmqbYnT69fmkAzacbaOR6+uPao77Oq07LX4fh+nyeQ5mvvOaxbzJMFXB6B1MUCLPnZlP9eUeg/h35L1H+xU1h8dj0Q/jtVnZYqfcXBqzyn2qBCsGuPv2LSLIkckj9lbCKC4Xa5oaNxy0KM5lpQ0SIKLy3vRx/gepL+wm06WSuJVK/wcM= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(70586007)(36756003)(426003)(316002)(6666004)(70206006)(2616005)(47076005)(86362001)(7696005)(82310400004)(336012)(7416002)(1076003)(508600001)(36860700001)(8936002)(4326008)(40460700001)(2906002)(110136005)(81166007)(356005)(44832011)(54906003)(16526019)(8676002)(26005)(186003)(5660300002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2021 23:59:18.3465 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20121b59-ff1e-4c27-bcb9-08d9b5efc0bd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB2897 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Export the max_physical_apicid via a helper function since this information is required by AMD SVM AVIC support. Signed-off-by: Suravee Suthikulpanit --- arch/x86/include/asm/apic.h | 1 + arch/x86/kernel/apic/apic.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 48067af94678..77d9cb2a7e28 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -435,6 +435,7 @@ static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} #endif /* CONFIG_X86_LOCAL_APIC */ extern void apic_ack_irq(struct irq_data *data); +extern u32 apic_get_max_phys_apicid(void); static inline void ack_APIC_irq(void) { diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index b70344bf6600..47653d8c05f2 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2361,6 +2361,12 @@ bool apic_id_is_primary_thread(unsigned int apicid) } #endif +u32 apic_get_max_phys_apicid(void) +{ + return max_physical_apicid; +} +EXPORT_SYMBOL_GPL(apic_get_max_phys_apicid); + /* * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids * and cpuid_to_apicid[] synchronized. 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; Received: from SATLEXMB03.amd.com (165.204.84.17) by CO1NAM11FT015.mail.protection.outlook.com (10.13.175.130) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4755.13 via Frontend Transport; Thu, 2 Dec 2021 23:59:19 +0000 Received: from sos-ubuntu2004-quartz01.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 2 Dec 2021 17:59:16 -0600 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v2 3/3] KVM: SVM: Extend host physical APIC ID field to support more than 8-bit Date: Thu, 2 Dec 2021 17:58:25 -0600 Message-ID: <20211202235825.12562-4-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211202235825.12562-1-suravee.suthikulpanit@amd.com> References: <20211202235825.12562-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d84b3865-4865-4444-d366-08d9b5efc12e X-MS-TrafficTypeDiagnostic: DM5PR12MB4662: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3968; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2021 23:59:19.0881 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d84b3865-4865-4444-d366-08d9b5efc12e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB4662 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The AVIC physical APIC ID table entry contains the host physical APIC ID field, which the hardware uses to keep track of where each vCPU is running. Originally, the field is an 8-bit value, which can only support physical APIC ID up to 255. To support system with larger APIC ID, the AVIC hardware extends this field to support up to the largest possible physical APIC ID available on the system. Therefore, replace the hard-coded mask value with the value calculated from the maximum possible physical APIC ID in the system. Signed-off-by: Suravee Suthikulpanit Reviewed-by: Maxim Levitsky --- arch/x86/kvm/svm/avic.c | 28 ++++++++++++++++++++-------- arch/x86/kvm/svm/svm.h | 1 - 2 files changed, 20 insertions(+), 9 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 6aca1682f4b7..2a0f58e6edf5 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -19,6 +19,7 @@ #include #include +#include #include #include "trace.h" @@ -63,6 +64,7 @@ static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS); static u32 next_vm_id = 0; static bool next_vm_id_wrapped = 0; +static u64 avic_host_physical_id_mask; static DEFINE_SPINLOCK(svm_vm_data_hash_lock); /* @@ -133,6 +135,20 @@ void avic_vm_destroy(struct kvm *kvm) spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); } +static void avic_init_host_physical_apicid_mask(void) +{ + if (!x2apic_mode) { + /* If host is in xAPIC mode, default to only 8-bit mask. */ + avic_host_physical_id_mask = 0xffULL; + } else { + u32 count = get_count_order(apic_get_max_phys_apicid()); + + avic_host_physical_id_mask = BIT(count) - 1; + } + pr_debug("Using AVIC host physical APIC ID mask %#0llx\n", + avic_host_physical_id_mask); +} + int avic_vm_init(struct kvm *kvm) { unsigned long flags; @@ -943,22 +959,17 @@ avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r) void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) { u64 entry; - /* ID = 0xff (broadcast), ID > 0xff (reserved) */ int h_physical_id = kvm_cpu_get_apicid(cpu); struct vcpu_svm *svm = to_svm(vcpu); - /* - * Since the host physical APIC id is 8 bits, - * we can support host APIC ID upto 255. - */ - if (WARN_ON(h_physical_id > AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK)) + if (WARN_ON(h_physical_id > avic_host_physical_id_mask)) return; entry = READ_ONCE(*(svm->avic_physical_id_cache)); WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); - entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; - entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK); + entry &= ~avic_host_physical_id_mask; + entry |= h_physical_id; entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; if (svm->avic_is_running) @@ -1018,6 +1029,7 @@ bool avic_hardware_setup(bool avic, bool npt) return false; pr_info("AVIC enabled\n"); + avic_init_host_physical_apicid_mask(); amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier); return true; } diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 1d2d72e56dd1..b4cb71c538b3 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -497,7 +497,6 @@ extern struct kvm_x86_nested_ops svm_nested_ops; #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) -#define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL) #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)