From patchwork Wed Dec 19 22:55:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10738269 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 50F5D6C2 for ; Wed, 19 Dec 2018 22:58:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 40E2A287BB for ; Wed, 19 Dec 2018 22:58:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 33622287CB; Wed, 19 Dec 2018 22:58:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A60B228746 for ; Wed, 19 Dec 2018 22:58:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728504AbeLSW6Q (ORCPT ); Wed, 19 Dec 2018 17:58:16 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:14263 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728285AbeLSW6Q (ORCPT ); Wed, 19 Dec 2018 17:58:16 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 19 Dec 2018 14:58:04 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 19 Dec 2018 14:58:14 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 19 Dec 2018 14:58:14 -0800 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 19 Dec 2018 22:58:13 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Wed, 19 Dec 2018 22:58:13 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.103.52]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 19 Dec 2018 14:55:58 -0800 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Sowjanya Komatineni Subject: [PATCH V2 1/3] dt-bindings: mmc: tegra: Add pinctrl for pad drive strength config Date: Wed, 19 Dec 2018 14:55:51 -0800 Message-ID: <1545260153-11338-1-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1545260285; bh=aeW5srTuVMljeFxTYLeI1rl+Rzz9wq/UVcb0OHGTpeg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=T2gvHZCBcLQzJV32jpHfhFz/AZ2Vku/MjlBQ+XsdAx6QvPb/DKuuSSzw82DoNGxMK 3yYYE5QTNzuccaas2lI2cQ5sgu5HaXrAwffsXAWg+YsrKPLuBusqTjkLjsxwwRTxpb DcWwRrcqdaT0THmm2fOGT53zDq6qQcgw9UB7dv17znBaKYW/rxV8BDNId0cJcJBjMu gAInb1qmL81mGPhbCovAYFq4LGEwxag4xpC4f+K4CZYygHDzYSPchLLLBRfrQ6IBdP 09olVGFQtIc27IUHxhFxxsCzYliAh92JKp02A0anGuH8qLDXCwvvPgdbVMyRadY/li e0exxLF1NpRTQ== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add pinctrl for 3V3 and 1V8 pad drive strength configuration for Tegra210 sdmmc which has pad configuration registers in the pinmux reigster domain. Signed-off-by: Sowjanya Komatineni --- Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt index 32b4b4e41923..2cecdc71d94c 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt @@ -39,12 +39,16 @@ sdhci@c8000200 { bus-width = <8>; }; -Optional properties for Tegra210 and Tegra186: +Optional properties for Tegra210, Tegra186 and Tegra194: - pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8" for controllers supporting multiple voltage levels. The order of names should correspond to the pin configuration states in pinctrl-0 and pinctrl-1. +- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for + Tegra210 where pad config registers are in the pinmux register domain + for pull-up-strength and pull-down-strength values configuration when + using pads at 3V3 and 1V8 levels. - nvidia,only-1-8-v : The presence of this property indicates that the controller operates at a 1.8 V fixed I/O voltage. - nvidia,pad-autocal-pull-up-offset-3v3, From patchwork Wed Dec 19 22:55:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10738271 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ABD646C2 for ; Wed, 19 Dec 2018 22:58:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 985A228746 for ; Wed, 19 Dec 2018 22:58:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8A15D2876D; Wed, 19 Dec 2018 22:58:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EC22A28746 for ; Wed, 19 Dec 2018 22:58:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728748AbeLSW6S (ORCPT ); Wed, 19 Dec 2018 17:58:18 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:14264 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728293AbeLSW6R (ORCPT ); Wed, 19 Dec 2018 17:58:17 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 19 Dec 2018 14:58:04 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 19 Dec 2018 14:58:14 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 19 Dec 2018 14:58:14 -0800 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 19 Dec 2018 22:58:13 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Wed, 19 Dec 2018 22:58:13 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.103.52]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 19 Dec 2018 14:56:02 -0800 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Sowjanya Komatineni Subject: [PATCH V2 2/3] arm64: dts: tegra210: Add SDMMC Auto-cal settings Date: Wed, 19 Dec 2018 14:55:52 -0800 Message-ID: <1545260153-11338-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545260153-11338-1-git-send-email-skomatineni@nvidia.com> References: <1545260153-11338-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1545260284; bh=upXbqvh8OsNTt3xEaujgxEKb32gDOotj2vmCgyrGlPk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=qctp7usBi65VfBUxYclhgJkdmNd+MpZWqGmjADJRibbpPpOoJzjEYETQ3qcRpNjN+ vh1kQ/iOX3quDtygYWAh0qbPg9QuwlJ5qTQxOpJ+Pkhmz3oP3R11RsnJMVbOasBgsc WnmsFaPiJCagaBHPy8EEeM/0r2fSPWTU4VXvTIl21XSWA9ev3BJ1OP2EMvX9T9M7ke PfFhhYb00x3VkULFhh+286q6gQtp8SgVC5Wi9fKfPivTsKl1WUGqFUvkYjuC2YVrMo zz79lLF+w9rS9X2uDd7BMeWgXI12pt78NDVovujGJoEGVehub2ehrn41iHGp7Gbynz VybQ8AS5nBlyw== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add SDMMC initial pad offsets used by auto calibration process. Add SDMMC fixed drive strengths used when calibration timeouts. Fixed drive strengths are based on Pre SI Analysis of the pads. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 ++ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 34 +++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 57 ++++++++++++++++++++++++++++++-- 3 files changed, 91 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 2f3c8e29520d..0631bb9bfcc3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -311,6 +311,8 @@ nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; + nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; + nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; nvidia,default-tap = <0x5>; nvidia,default-trim = <0x9>; nvidia,dqs-trim = <63>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index c2091bb16546..3fab6802c335 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -301,6 +301,17 @@ clock-names = "sdhci"; resets = <&bpmp TEGRA194_RESET_SDMMC1>; reset-names = "sdhci"; + nvidia,pad-autocal-pull-up-offset-3v3-timeout = + <0x07>; + nvidia,pad-autocal-pull-down-offset-3v3-timeout = + <0x07>; + nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; + nvidia,pad-autocal-pull-down-offset-1v8-timeout = + <0x07>; + nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; + nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; + nvidia,default-tap = <0x9>; + nvidia,default-trim = <0x5>; status = "disabled"; }; @@ -312,6 +323,18 @@ clock-names = "sdhci"; resets = <&bpmp TEGRA194_RESET_SDMMC3>; reset-names = "sdhci"; + nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; + nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; + nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; + nvidia,pad-autocal-pull-down-offset-3v3-timeout = + <0x07>; + nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; + nvidia,pad-autocal-pull-down-offset-1v8-timeout = + <0x07>; + nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; + nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; + nvidia,default-tap = <0x9>; + nvidia,default-trim = <0x5>; status = "disabled"; }; @@ -323,6 +346,17 @@ clock-names = "sdhci"; resets = <&bpmp TEGRA194_RESET_SDMMC4>; reset-names = "sdhci"; + nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; + nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; + nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; + nvidia,pad-autocal-pull-down-offset-1v8-timeout = + <0x0a>; + nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; + nvidia,pad-autocal-pull-down-offset-3v3-timeout = + <0x0a>; + nvidia,default-tap = <0x8>; + nvidia,default-trim = <0x14>; + nvidia,dqs-trim = <40>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 2205d66b0443..41408df9d4e9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -476,6 +476,48 @@ compatible = "nvidia,tegra210-pinmux"; reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ <0x0 0x70003000 0x0 0x294>; /* Mux registers */ + sdmmc1_3v3_drv: sdmmc1-3v3-drv { + sdmmc1 { + nvidia,pins = "drive_sdmmc1"; + nvidia,pull-down-strength = <0x8>; + nvidia,pull-up-strength = <0x8>; + }; + }; + sdmmc1_1v8_drv: sdmmc1-1v8-drv { + sdmmc1 { + nvidia,pins = "drive_sdmmc1"; + nvidia,pull-down-strength = <0x4>; + nvidia,pull-up-strength = <0x3>; + }; + }; + sdmmc2_1v8_drv: sdmmc2-1v8-drv { + sdmmc2 { + nvidia,pins = "drive_sdmmc2"; + nvidia,pull-down-strength = <0x10>; + nvidia,pull-up-strength = <0x10>; + }; + }; + sdmmc3_3v3_drv: sdmmc3-3v3-drv { + sdmmc3 { + nvidia,pins = "drive_sdmmc3"; + nvidia,pull-down-strength = <0x8>; + nvidia,pull-up-strength = <0x8>; + }; + }; + sdmmc3_1v8_drv: sdmmc3-1v8-drv { + sdmmc3 { + nvidia,pins = "drive_sdmmc3"; + nvidia,pull-down-strength = <0x4>; + nvidia,pull-up-strength = <0x3>; + }; + }; + sdmmc4_1v8_drv: sdmmc4-1v8-drv { + sdmmc4 { + nvidia,pins = "drive_sdmmc4"; + nvidia,pull-down-strength = <0x10>; + nvidia,pull-up-strength = <0x10>; + }; + }; }; /* @@ -1050,9 +1092,12 @@ clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", + "sdmmc-3v3-drv", "sdmmc-1v8-drv"; pinctrl-0 = <&sdmmc1_3v3>; pinctrl-1 = <&sdmmc1_1v8>; + pinctrl-2 = <&sdmmc1_3v3_drv>; + pinctrl-3 = <&sdmmc1_1v8_drv>; nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; @@ -1075,6 +1120,8 @@ clock-names = "sdhci"; resets = <&tegra_car 9>; reset-names = "sdhci"; + pinctrl-names = "sdmmc-1v8-drv"; + pinctrl-0 = <&sdmmc2_1v8_drv>; nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; nvidia,default-tap = <0x8>; @@ -1090,9 +1137,12 @@ clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", + "sdmmc-3v3-drv", "sdmmc-1v8-drv"; pinctrl-0 = <&sdmmc3_3v3>; pinctrl-1 = <&sdmmc3_1v8>; + pinctrl-2 = <&sdmmc3_3v3_drv>; + pinctrl-3 = <&sdmmc3_1v8_drv>; nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; @@ -1110,6 +1160,9 @@ clock-names = "sdhci"; resets = <&tegra_car 15>; reset-names = "sdhci"; + pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; + pinctrl-0 = <&sdmmc4_1v8_drv>; + pinctrl-1 = <&sdmmc4_1v8_drv>; nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; nvidia,default-tap = <0x8>; From patchwork Wed Dec 19 22:55:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10738273 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 469DB13BF for ; Wed, 19 Dec 2018 22:58:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3408D28758 for ; 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Wed, 19 Dec 2018 14:58:09 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 19 Dec 2018 14:58:15 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 19 Dec 2018 14:58:15 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 19 Dec 2018 22:58:15 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Wed, 19 Dec 2018 22:58:14 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.103.52]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 19 Dec 2018 14:56:04 -0800 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Sowjanya Komatineni Subject: [PATCH V2 3/3] mmc: tegra: SDMMC pads auto-calibration Date: Wed, 19 Dec 2018 14:55:53 -0800 Message-ID: <1545260153-11338-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545260153-11338-1-git-send-email-skomatineni@nvidia.com> References: <1545260153-11338-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1545260289; bh=tavZPryP9hpCrx4xFldGTcLpWrEs1LaHRmLHHTWogwc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=dgpNdq8n9bEZq8BSXrjKDVCcDey8nzpC7z654rv2/bFUkZ7va3F7HPt1/D/Hrrlh/ ZQV5gihlEt+8OCaeyLZabU4JhdO4mrtvHZ7ERqW9z7z/px8vkkQlRd+jLttvRENNPl fFi9hC/MKuwYaPinYMib8Wf8FgFCLxqqUIiuxLj81N1RlPE/5u/alWj0b7iAa1zg10 xLGDMq40giS+v6GL0hSvkd+pcTr4NGqvZ3s0a2kE3h1SzfpVtRCjldPsAc+3D7JQNC V7BhreruNb/UkoqgglwrChSZaizvYUlU4nUS/EmQIYctTBwL+YRJBGs9jW04fSB9M4 E2TJJy6xLEnZw== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Programs initial drive code offsets which will be used by auto calibration process. Programs fixed drive strengths for SDMMC pads when auto cal timeouts. Fixed settings are based on Pre-SI analysis of the pad design. Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci-tegra.c | 107 +++++++++++++++++++++++++++++++---------- 1 file changed, 81 insertions(+), 26 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 7b95d088fdef..f8361249cf57 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -75,6 +75,7 @@ #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) +#define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK 0x07FFF000 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) @@ -121,6 +122,8 @@ struct sdhci_tegra { struct pinctrl *pinctrl_sdmmc; struct pinctrl_state *pinctrl_state_3v3; struct pinctrl_state *pinctrl_state_1v8; + struct pinctrl_state *pinctrl_state_3v3_drv; + struct pinctrl_state *pinctrl_state_1v8_drv; struct sdhci_tegra_autocal_offsets autocal_offsets; ktime_t last_calib; @@ -130,6 +133,9 @@ struct sdhci_tegra { u32 dqs_trim; }; +static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage, + bool state_drvupdn); + static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); @@ -437,6 +443,7 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; } + /* Set initial offset before auto-calibration */ tegra_sdhci_set_pad_autocal_offset(host, pdpu); card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); @@ -460,19 +467,15 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) if (ret) { dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); - if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) - pdpu = offsets.pull_down_1v8_timeout << 8 | - offsets.pull_up_1v8_timeout; - else - pdpu = offsets.pull_down_3v3_timeout << 8 | - offsets.pull_up_3v3_timeout; - - /* Disable automatic calibration and use fixed offsets */ + /* Disable automatic cal and use fixed Drive Strengths */ reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); reg &= ~SDHCI_AUTO_CAL_ENABLE; sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); - tegra_sdhci_set_pad_autocal_offset(host, pdpu); + ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false); + if (ret < 0) + dev_err(mmc_dev(host->mmc), + "Setting drive strengths failed %d\n", PTR_ERR(ret)); } } @@ -743,27 +746,73 @@ static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) return mmc_send_tuning(host->mmc, opcode, NULL); } -static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage) +static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage, + bool state_drvupdn) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); - int ret; + struct sdhci_tegra_autocal_offsets offsets = + tegra_host->autocal_offsets; + struct pinctrl_state *pinctrl_drvupdn = NULL; + int ret = 0; + u8 drvup = 0, drvdn = 0; + u32 reg; - if (!tegra_host->pad_control_available) - return 0; + if (!state_drvupdn) { + /* PADS Drive Strength */ + if (voltage == MMC_SIGNAL_VOLTAGE_180) { + if (!IS_ERR(tegra_host->pinctrl_state_1v8_drv) && + (tegra_host->pinctrl_state_1v8_drv != NULL)) { + pinctrl_drvupdn = + tegra_host->pinctrl_state_1v8_drv; + } else { + drvup = offsets.pull_up_1v8_timeout; + drvdn = offsets.pull_down_1v8_timeout; + } + } else { + if (!IS_ERR(tegra_host->pinctrl_state_3v3_drv) && + (tegra_host->pinctrl_state_3v3_drv != NULL)) { + pinctrl_drvupdn = + tegra_host->pinctrl_state_3v3_drv; + } else { + drvup = offsets.pull_up_3v3_timeout; + drvdn = offsets.pull_down_3v3_timeout; + } + } + + if (pinctrl_drvupdn != NULL) { + ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, + pinctrl_drvupdn); + if (ret < 0) + dev_err(mmc_dev(host->mmc), + "failed pads drvupdn, ret: %d\n", ret); + } else if ((drvup) || (drvdn)) { + reg = sdhci_readl(host, + SDHCI_TEGRA_SDMEM_COMP_PADCTRL); + reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK; + reg |= (drvup << 20) | (drvdn << 12); + sdhci_writel(host, reg, + SDHCI_TEGRA_SDMEM_COMP_PADCTRL); + } - if (voltage == MMC_SIGNAL_VOLTAGE_180) { - ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, - tegra_host->pinctrl_state_1v8); - if (ret < 0) - dev_err(mmc_dev(host->mmc), - "setting 1.8V failed, ret: %d\n", ret); } else { - ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, - tegra_host->pinctrl_state_3v3); - if (ret < 0) - dev_err(mmc_dev(host->mmc), - "setting 3.3V failed, ret: %d\n", ret); + /* Dual Voltage PADS Voltage selection */ + if (!tegra_host->pad_control_available) + return 0; + + if (voltage == MMC_SIGNAL_VOLTAGE_180) { + ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, + tegra_host->pinctrl_state_1v8); + if (ret < 0) + dev_err(mmc_dev(host->mmc), + "setting 1.8V failed, ret: %d\n", ret); + } else { + ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, + tegra_host->pinctrl_state_3v3); + if (ret < 0) + dev_err(mmc_dev(host->mmc), + "setting 3.3V failed, ret: %d\n", ret); + } } return ret; @@ -778,7 +827,7 @@ static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, int ret = 0; if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { - ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); + ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); if (ret < 0) return ret; ret = sdhci_start_signal_voltage_switch(mmc, ios); @@ -786,7 +835,7 @@ static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, ret = sdhci_start_signal_voltage_switch(mmc, ios); if (ret < 0) return ret; - ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); + ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); } if (tegra_host->pad_calib_required) @@ -805,6 +854,12 @@ static int tegra_sdhci_init_pinctrl_info(struct device *dev, return -1; } + tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state( + tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv"); + + tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state( + tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv"); + tegra_host->pinctrl_state_3v3 = pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); if (IS_ERR(tegra_host->pinctrl_state_3v3)) {