From patchwork Wed Dec 19 23:55:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 10738343 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4B03413B5 for ; Wed, 19 Dec 2018 23:56:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 38EE128882 for ; Wed, 19 Dec 2018 23:56:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2BCEA286B0; Wed, 19 Dec 2018 23:56:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C855A286B0 for ; Wed, 19 Dec 2018 23:56:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730121AbeLSXzq (ORCPT ); Wed, 19 Dec 2018 18:55:46 -0500 Received: from mail-pl1-f195.google.com ([209.85.214.195]:46460 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730111AbeLSXzn (ORCPT ); Wed, 19 Dec 2018 18:55:43 -0500 Received: by mail-pl1-f195.google.com with SMTP id t13so10181445ply.13 for ; Wed, 19 Dec 2018 15:55:43 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6RPkl4pipXk1xl7KCOzzXlRGedEKRmNbPEbbe0d6v+o=; b=cGoeKamKlJDOUz3lBIdjH1lwl/GwvlF6O0AFizYiP8qovoJ9LLdKNfXQIRLOgp7wLn BbD7OIEbGHG1sUbCjJYlOKezVn6TMczEDnIKvJf6/oqVJSQOOriZJy0Q0VGtbUVbIgTi Fa0mbyEUKUGtFEdVbOrn6GLDO4jVu4/ZAejyUgJUYgnw6brEFoHQvQT4PSRCWsTYsssi 1HUn7sVUlHbjqXVSNZtYc31F2Edw50UDzEun0FRFWQTCBOqOHqnmtbTA1jWBV76NaYty KISQ+MtCKxNkVsC/u0Qwr3aSeBEy9vONwW669LK7THx0fDNKH2NmhCDxaGntsCoKViMX AW/w== X-Gm-Message-State: AA+aEWZLgyxgK3pzGKdEzCLO6KIPZeZ7o8s5CSNCykRkYcXQPXB8yftF Ui3D21E0BjVHG4TpZTJuYTZBsxsm1h/aCw== X-Google-Smtp-Source: AFSGD/UKJT1Kky5I7L4k2n7TdBxZMtKEFew7iEcgcE7+cqmttR/md9vFTrG6RsWMbMoYLtmlhf7B+A== X-Received: by 2002:a17:902:108a:: with SMTP id c10mr13392636pla.131.1545263742601; Wed, 19 Dec 2018 15:55:42 -0800 (PST) Received: from mka.mtv.corp.google.com ([2620:15c:202:1:75a:3f6e:21d:9374]) by smtp.gmail.com with ESMTPSA id t67sm37045048pfd.90.2018.12.19.15.55.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 15:55:41 -0800 (PST) From: Matthias Kaehlcke To: Rob Clark , David Airlie , Rob Herring , Mark Rutland , Andy Gross , David Brown Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Archit Taneja , Sean Paul , Rajesh Yadav , Douglas Anderson , Stephen Boyd , Jeykumar Sankaran , Matthias Kaehlcke , Rob Herring Subject: [PATCH v5 1/8] dt-bindings: msm/dsi: Add ref clock for PHYs Date: Wed, 19 Dec 2018 15:55:21 -0800 Message-Id: <20181219235528.114830-2-mka@chromium.org> X-Mailer: git-send-email 2.20.1.415.g653613c723-goog In-Reply-To: <20181219235528.114830-1-mka@chromium.org> References: <20181219235528.114830-1-mka@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Allow the PHY drivers to get the ref clock from the DT. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Reviewed-by: Rob Herring --- Changes in v5: - added "Reviewed-by: Rob Herring " tag Changes in v4: - added "Reviewed-by" tags from Stephen and Doug Changes in v3: - added note that the ref clock is only required for new DTS files/entries Changes in v2: - add the ref clock for all PHYs, not only the 10nm one - updated commit message --- Documentation/devicetree/bindings/display/msm/dsi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index dfc743219bd88..9ae9469427207 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -106,6 +106,7 @@ Required properties: - clocks: Phandles to device clocks. See [1] for details on clock bindings. - clock-names: the following clocks are required: * "iface" + * "ref" (only required for new DTS files/entries) For 28nm HPM/LP, 28nm 8960 PHYs: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: From patchwork Wed Dec 19 23:55:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 10738313 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4638814DE for ; Wed, 19 Dec 2018 23:55:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3676A28882 for ; Wed, 19 Dec 2018 23:55:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2A28228897; Wed, 19 Dec 2018 23:55:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B6C2A28882 for ; Wed, 19 Dec 2018 23:55:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730119AbeLSXzq (ORCPT ); Wed, 19 Dec 2018 18:55:46 -0500 Received: from mail-pl1-f194.google.com ([209.85.214.194]:32809 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730100AbeLSXzp (ORCPT ); Wed, 19 Dec 2018 18:55:45 -0500 Received: by mail-pl1-f194.google.com with SMTP id z23so10206047plo.0 for ; Wed, 19 Dec 2018 15:55:44 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KugJw0T6WpNIgN6GeDyzlbgkEP0KJTcUcd6c7Oo1r4A=; b=reTfKYHAbeZtvZWN6QduYlOTALBpVsfy3IYqvANoHOQ2kJtsosI3NkEYVs+aIN4TxC AzHLZ6u9wVdBpvAcyQhf8+EFw90rBIneS6Q6xor4+4WR+K/4J/78T871AnJfixH4neKi Fu+pZKx+6X6oqQ8aTZThAoCyLEEvPfKvTjMUVVOeeVPxjRLM3rvMjaRqxJpIl77f7Tx2 iaynVaogUARitgfOgpFJK1KpJSt4pSDWDTOyOnNxeoXoWUV+fNpph7Dc2XmNeMOrMnxZ MNMy+AmSVJ0Q5F9hDOMgXDS+E7u7rTDCkl2tTRqvRiKDcPrReYykg5Z47jQgNshGS87O fJ+A== X-Gm-Message-State: AA+aEWb8EBxjQ5CL3rnuHg+7bvYGj5tZuDGzEVUd4uL3wCh/VMPz6pzW jI3PzDHtqTOcqRIRqnbHRGXebg== X-Google-Smtp-Source: AFSGD/UlJRsTVEYMAMX1t4IhY5Z2sB1XzBGmrU/ulxs7aUZyMyZ1XvmkaDf1dAaFvYzPkh0ynK/bKA== X-Received: by 2002:a17:902:3f81:: with SMTP id a1mr21827005pld.258.1545263744466; Wed, 19 Dec 2018 15:55:44 -0800 (PST) Received: from mka.mtv.corp.google.com ([2620:15c:202:1:75a:3f6e:21d:9374]) by smtp.gmail.com with ESMTPSA id t67sm37045048pfd.90.2018.12.19.15.55.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 15:55:43 -0800 (PST) From: Matthias Kaehlcke To: Rob Clark , David Airlie , Rob Herring , Mark Rutland , Andy Gross , David Brown Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Archit Taneja , Sean Paul , Rajesh Yadav , Douglas Anderson , Stephen Boyd , Jeykumar Sankaran , Matthias Kaehlcke Subject: [PATCH v5 2/8] drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT Date: Wed, 19 Dec 2018 15:55:22 -0800 Message-Id: <20181219235528.114830-3-mka@chromium.org> X-Mailer: git-send-email 2.20.1.415.g653613c723-goog In-Reply-To: <20181219235528.114830-1-mka@chromium.org> References: <20181219235528.114830-1-mka@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Get the ref clock of the PHY from the device tree instead of hardcoding its name and rate. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd --- Changes in v5: - added "Reviewed-by: Stephen Boyd " tag Changes in v4: - always use parent rate in dsi_pll_28nm_clk_set_rate() - pass name of VCO ref clock to pll_28nm_register() instead of storing it in a struct field - updated commit message Changes in v3: - use default name and rate if the ref clock is not specified in the DT - store vco_ref_clk_name instead of vco_ref_clk - fixed check for EPROBE_DEFER - renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE Changes in v2: - patch added to the series --- .../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 24 +++++++++++++++---- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c index 49008451085b8..76e5188169b91 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c @@ -47,7 +47,6 @@ #define NUM_PROVIDED_CLKS 2 -#define VCO_REF_CLK_RATE 27000000 #define VCO_MIN_RATE 600000000 #define VCO_MAX_RATE 1200000000 @@ -125,7 +124,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, DBG("rate=%lu, parent's=%lu", rate, parent_rate); temp = rate / 10; - val = VCO_REF_CLK_RATE / 10; + val = parent_rate / 10; fb_divider = (temp * VCO_PREF_DIV_RATIO) / val; fb_divider = fb_divider / 2 - 1; pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1, @@ -406,11 +405,12 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll) pll_28nm->clks, pll_28nm->num_clks); } -static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) +static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, + const char *ref_clk_name) { char *clk_name, *parent_name, *vco_name; struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "pxo" }, + .parent_names = &ref_clk_name, .num_parents = 1, .flags = CLK_IGNORE_UNUSED, .ops = &clk_ops_dsi_pll_28nm_vco, @@ -494,6 +494,8 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev, { struct dsi_pll_28nm *pll_28nm; struct msm_dsi_pll *pll; + struct clk *vco_ref_clk; + const char *vco_ref_clk_name; int ret; if (!pdev) @@ -506,6 +508,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev, pll_28nm->pdev = pdev; pll_28nm->id = id + 1; + vco_ref_clk = devm_clk_get(&pdev->dev, "ref"); + if (!IS_ERR(vco_ref_clk)) { + vco_ref_clk_name = __clk_get_name(vco_ref_clk); + } else { + ret = PTR_ERR(vco_ref_clk); + if (ret == -EPROBE_DEFER) + return ERR_PTR(ret); + + dev_warn(&pdev->dev, "'ref' clock is not specified, using default name\n"); + vco_ref_clk_name = "pxo"; + } + pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); if (IS_ERR_OR_NULL(pll_28nm->mmio)) { dev_err(&pdev->dev, "%s: failed to map pll base\n", __func__); @@ -524,7 +538,7 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev, pll->en_seq_cnt = 1; pll->enable_seqs[0] = dsi_pll_28nm_enable_seq; - ret = pll_28nm_register(pll_28nm); + ret = pll_28nm_register(pll_28nm, vco_ref_clk_name); if (ret) { dev_err(&pdev->dev, "failed to register PLL: %d\n", ret); return ERR_PTR(ret); From patchwork Wed Dec 19 23:55:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 10738341 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 420D91399 for ; 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Wed, 19 Dec 2018 15:55:46 -0800 (PST) Received: from mka.mtv.corp.google.com ([2620:15c:202:1:75a:3f6e:21d:9374]) by smtp.gmail.com with ESMTPSA id t67sm37045048pfd.90.2018.12.19.15.55.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 15:55:45 -0800 (PST) From: Matthias Kaehlcke To: Rob Clark , David Airlie , Rob Herring , Mark Rutland , Andy Gross , David Brown Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Archit Taneja , Sean Paul , Rajesh Yadav , Douglas Anderson , Stephen Boyd , Jeykumar Sankaran , Matthias Kaehlcke Subject: [PATCH v5 3/8] drm/msm/dsi: 28nm PHY: Get ref clock from the DT Date: Wed, 19 Dec 2018 15:55:23 -0800 Message-Id: <20181219235528.114830-4-mka@chromium.org> X-Mailer: git-send-email 2.20.1.415.g653613c723-goog In-Reply-To: <20181219235528.114830-1-mka@chromium.org> References: <20181219235528.114830-1-mka@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Get the ref clock of the PHY from the device tree instead of hardcoding its name and rate. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd tag --- Changes in v5: - added missing return keyword in msm_dsi_pll_28nm_init() - added "Reviewed-by: Stephen Boyd " tag Changes in v4: - always use parent rate in dsi_pll_28nm_clk_set_rate() and dsi_pll_28nm_clk_recalc_rate() - pass name of VCO ref clock to pll_28nm_register() instead of storing it in a struct field - updated commit message Changes in v3: - use default name and rate if the ref clock is not specified in the DT - store vco_ref_clk_name instead of vco_ref_clk - dsi_pll_28nm_clk_set_rate: changed data type of ref_clk_rate to unsigned long - fixed check for EPROBE_DEFER - renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE Changes in v2: - patch added to the series --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 36 +++++++++++++++------- 1 file changed, 25 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c index 26e3a01a99c2b..c839464741927 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c @@ -40,7 +40,6 @@ #define NUM_PROVIDED_CLKS 2 -#define VCO_REF_CLK_RATE 19200000 #define VCO_MIN_RATE 350000000 #define VCO_MAX_RATE 750000000 @@ -166,17 +165,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); - rem = rate % VCO_REF_CLK_RATE; + rem = rate % parent_rate; if (rem) { refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR; frac_n_mode = 1; - div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500); - gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500); + div_fbx1000 = rate / (parent_rate / 500); + gen_vco_clk = div_fbx1000 * (parent_rate / 500); } else { refclk_cfg = 0x0; frac_n_mode = 0; - div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000); - gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000); + div_fbx1000 = rate / (parent_rate / 1000); + gen_vco_clk = div_fbx1000 * (parent_rate / 1000); } DBG("refclk_cfg = %d", refclk_cfg); @@ -265,7 +264,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, void __iomem *base = pll_28nm->mmio; u32 sdm0, doubler, sdm_byp_div; u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3; - u32 ref_clk = VCO_REF_CLK_RATE; + u32 ref_clk = parent_rate; unsigned long vco_rate; VERB("parent_rate=%lu", parent_rate); @@ -273,7 +272,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, /* Check to see if the ref clk doubler is enabled */ doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) & DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR; - ref_clk += (doubler * VCO_REF_CLK_RATE); + ref_clk += (doubler * ref_clk); /* see if it is integer mode or sdm mode */ sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0); @@ -514,11 +513,12 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll) pll_28nm->clk_data.clk_num = 0; } -static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) +static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, + const char *ref_clk_name) { char clk_name[32], parent1[32], parent2[32], vco_name[32]; struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "xo" }, + .parent_names = &ref_clk_name, .num_parents = 1, .name = vco_name, .flags = CLK_IGNORE_UNUSED, @@ -593,6 +593,8 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev, { struct dsi_pll_28nm *pll_28nm; struct msm_dsi_pll *pll; + struct clk *vco_ref_clk; + const char *vco_ref_clk_name; int ret; if (!pdev) @@ -605,6 +607,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev, pll_28nm->pdev = pdev; pll_28nm->id = id; + vco_ref_clk = devm_clk_get(&pdev->dev, "ref"); + if (!IS_ERR(vco_ref_clk)) { + vco_ref_clk_name = __clk_get_name(vco_ref_clk); + } else { + ret = PTR_ERR(vco_ref_clk); + if (ret == -EPROBE_DEFER) + return ERR_PTR(ret); + + dev_warn(&pdev->dev, "'ref' clock is not specified, using default name\n"); + vco_ref_clk_name = "xo"; + } + pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); if (IS_ERR_OR_NULL(pll_28nm->mmio)) { dev_err(&pdev->dev, "%s: failed to map pll base\n", __func__); @@ -637,7 +651,7 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev, return ERR_PTR(-EINVAL); } - ret = pll_28nm_register(pll_28nm); + ret = pll_28nm_register(pll_28nm, vco_ref_clk_name); if (ret) { dev_err(&pdev->dev, "failed to register PLL: %d\n", ret); return ERR_PTR(ret); From patchwork Wed Dec 19 23:55:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 10738339 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E59351399 for ; Wed, 19 Dec 2018 23:56:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D621B286B0 for ; Wed, 19 Dec 2018 23:56:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C803A28895; Wed, 19 Dec 2018 23:56:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6345C286B0 for ; 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Wed, 19 Dec 2018 15:55:48 -0800 (PST) Received: from mka.mtv.corp.google.com ([2620:15c:202:1:75a:3f6e:21d:9374]) by smtp.gmail.com with ESMTPSA id t67sm37045048pfd.90.2018.12.19.15.55.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 15:55:47 -0800 (PST) From: Matthias Kaehlcke To: Rob Clark , David Airlie , Rob Herring , Mark Rutland , Andy Gross , David Brown Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Archit Taneja , Sean Paul , Rajesh Yadav , Douglas Anderson , Stephen Boyd , Jeykumar Sankaran , Matthias Kaehlcke Subject: [PATCH v5 4/8] drm/msm/dsi: 14nm PHY: Get ref clock from the DT Date: Wed, 19 Dec 2018 15:55:24 -0800 Message-Id: <20181219235528.114830-5-mka@chromium.org> X-Mailer: git-send-email 2.20.1.415.g653613c723-goog In-Reply-To: <20181219235528.114830-1-mka@chromium.org> References: <20181219235528.114830-1-mka@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Get the ref clock of the PHY from the device tree instead of hardcoding its name and rate. Note: This change could break old out-of-tree DTS files that use the 14nm PHY. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd --- Changes in v5: - pass the ref clock name to _register() instead of storing a point to the clk object in the PLL data structure Changes in v4: - none Changes in v3: - fixed check for EPROBE_DEFER - added note to commit message about breaking old DTS files - added 'Reviewed-by: Douglas Anderson ' tag Changes in v2: - patch added to the series --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c | 23 +++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c index 71fe60e5f01f1..9a647d93a7e0b 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c @@ -40,7 +40,6 @@ #define NUM_PROVIDED_CLKS 2 -#define VCO_REF_CLK_RATE 19200000 #define VCO_MIN_RATE 1300000000UL #define VCO_MAX_RATE 2600000000UL @@ -591,7 +590,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, parent_rate); pll_14nm->vco_current_rate = rate; - pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE; + pll_14nm->vco_ref_clk_rate = parent_rate; dsi_pll_14nm_input_init(pll_14nm); @@ -947,11 +946,12 @@ static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm, return &pll_postdiv->hw; } -static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm) +static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, + const char *ref_clk_name) { char clk_name[32], parent[32], vco_name[32]; struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "xo" }, + .parent_names = &ref_clk_name, .num_parents = 1, .name = vco_name, .flags = CLK_IGNORE_UNUSED, @@ -1050,6 +1050,8 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id) { struct dsi_pll_14nm *pll_14nm; struct msm_dsi_pll *pll; + struct clk *vco_ref_clk; + const char *vco_ref_clk_name; int ret; if (!pdev) @@ -1065,6 +1067,17 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id) pll_14nm->id = id; pll_14nm_list[id] = pll_14nm; + vco_ref_clk = devm_clk_get(&pdev->dev, "ref"); + if (IS_ERR(vco_ref_clk)) { + ret = PTR_ERR(vco_ref_clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "couldn't get 'ref' clock: %d\n", + ret); + return ERR_PTR(ret); + } + + vco_ref_clk_name = __clk_get_name(vco_ref_clk); + pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) { dev_err(&pdev->dev, "failed to map CMN PHY base\n"); @@ -1094,7 +1107,7 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id) pll->en_seq_cnt = 1; pll->enable_seqs[0] = dsi_pll_14nm_enable_seq; - ret = pll_14nm_register(pll_14nm); + ret = pll_14nm_register(pll_14nm, vco_ref_clk_name); if (ret) { dev_err(&pdev->dev, "failed to register PLL: %d\n", ret); return ERR_PTR(ret); From patchwork Wed Dec 19 23:55:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 10738335 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 233F013B5 for ; Wed, 19 Dec 2018 23:56:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 13D1D28895 for ; Wed, 19 Dec 2018 23:56:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 084E728897; Wed, 19 Dec 2018 23:56:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 994B2286B0 for ; Wed, 19 Dec 2018 23:56:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730217AbeLSXzy (ORCPT ); Wed, 19 Dec 2018 18:55:54 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:34630 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730197AbeLSXzw (ORCPT ); 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Wed, 19 Dec 2018 15:55:50 -0800 (PST) Received: from mka.mtv.corp.google.com ([2620:15c:202:1:75a:3f6e:21d:9374]) by smtp.gmail.com with ESMTPSA id t67sm37045048pfd.90.2018.12.19.15.55.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 15:55:49 -0800 (PST) From: Matthias Kaehlcke To: Rob Clark , David Airlie , Rob Herring , Mark Rutland , Andy Gross , David Brown Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Archit Taneja , Sean Paul , Rajesh Yadav , Douglas Anderson , Stephen Boyd , Jeykumar Sankaran , Matthias Kaehlcke Subject: [PATCH v5 5/8] drm/msm/dsi: 10nm PHY: Get ref clock from the DT Date: Wed, 19 Dec 2018 15:55:25 -0800 Message-Id: <20181219235528.114830-6-mka@chromium.org> X-Mailer: git-send-email 2.20.1.415.g653613c723-goog In-Reply-To: <20181219235528.114830-1-mka@chromium.org> References: <20181219235528.114830-1-mka@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Get the ref clock of the PHY from the device tree instead of hardcoding its name and rate. Note: This change could break old out-of-tree DTS files that use the 10nm PHY Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd --- Changes in v5: - pass the ref clock name to _register() instead of storing a point to the clk object in the PLL data structure Changes in v4: - none Changes in v3: - fixed check for EPROBE_DEFER - added note to commit message about breaking old DTS files - added 'Reviewed-by: Douglas Anderson ' tag Changes in v2: - remove anonymous array in clk_init_data assignment - log error code if devm_clk_get() fails - don't log devm_clk_get() failures for -EPROBE_DEFER - updated commit message --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c index 4c03f0b7343ed..adbe5395f4f38 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c @@ -625,12 +625,14 @@ static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll) * state to follow the master PLL's divider/mux state. Therefore, we don't * require special clock ops that also configure the slave PLL registers */ -static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm) +static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, + const char *ref_clk_name) { char clk_name[32], parent[32], vco_name[32]; char parent2[32], parent3[32], parent4[32]; + struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "xo" }, + .parent_names = &ref_clk_name, .num_parents = 1, .name = vco_name, .flags = CLK_IGNORE_UNUSED, @@ -771,6 +773,8 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) { struct dsi_pll_10nm *pll_10nm; struct msm_dsi_pll *pll; + struct clk *vco_ref_clk; + const char *vco_ref_clk_name; int ret; if (!pdev) @@ -786,6 +790,16 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) pll_10nm->id = id; pll_10nm_list[id] = pll_10nm; + vco_ref_clk = devm_clk_get(&pdev->dev, "ref"); + if (IS_ERR(vco_ref_clk)) { + ret = PTR_ERR(vco_ref_clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "couldn't get 'ref' clock: %d\n", + ret); + return ERR_PTR(ret); + } + vco_ref_clk_name = __clk_get_name(vco_ref_clk); + pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) { dev_err(&pdev->dev, "failed to map CMN PHY base\n"); @@ -811,7 +825,7 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) pll_10nm->vco_delay = 1; - ret = pll_10nm_register(pll_10nm); + ret = pll_10nm_register(pll_10nm, vco_ref_clk_name); if (ret) { dev_err(&pdev->dev, "failed to register PLL: %d\n", ret); return ERR_PTR(ret); From patchwork Wed Dec 19 23:55:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 10738337 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 418C014DE for ; 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Wed, 19 Dec 2018 15:55:52 -0800 (PST) Received: from mka.mtv.corp.google.com ([2620:15c:202:1:75a:3f6e:21d:9374]) by smtp.gmail.com with ESMTPSA id t67sm37045048pfd.90.2018.12.19.15.55.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 15:55:51 -0800 (PST) From: Matthias Kaehlcke To: Rob Clark , David Airlie , Rob Herring , Mark Rutland , Andy Gross , David Brown Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Archit Taneja , Sean Paul , Rajesh Yadav , Douglas Anderson , Stephen Boyd , Jeykumar Sankaran , Matthias Kaehlcke Subject: [PATCH v5 6/8] arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY Date: Wed, 19 Dec 2018 15:55:26 -0800 Message-Id: <20181219235528.114830-7-mka@chromium.org> X-Mailer: git-send-email 2.20.1.415.g653613c723-goog In-Reply-To: <20181219235528.114830-1-mka@chromium.org> References: <20181219235528.114830-1-mka@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add 'xo_board' as ref clock for the DSI PHYs, it was previously hardcoded in the PLL 'driver' for the 28nm PHY. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd --- Changes in v5: - none Changes in v4: - added 'Reviewed-by: Stephen Boyd ' tag Changes in v3: - added 'Reviewed-by: Douglas Anderson ' tag Changes in v2: - patch added to the series --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d302d8d639a12..89f30f34ff896 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -959,8 +959,9 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = <&gcc GCC_MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&xo_board>; + clock-names = "iface", "ref"; }; }; From patchwork Wed Dec 19 23:55:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 10738331 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 42FA613B5 for ; Wed, 19 Dec 2018 23:56:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3390A286B0 for ; Wed, 19 Dec 2018 23:56:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 27DAF28895; Wed, 19 Dec 2018 23:56:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C8B05286B0 for ; Wed, 19 Dec 2018 23:56:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730248AbeLSX4I (ORCPT ); Wed, 19 Dec 2018 18:56:08 -0500 Received: from mail-pg1-f196.google.com ([209.85.215.196]:45033 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730223AbeLSXzz (ORCPT ); Wed, 19 Dec 2018 18:55:55 -0500 Received: by mail-pg1-f196.google.com with SMTP id t13so10157437pgr.11 for ; Wed, 19 Dec 2018 15:55:54 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AXxeztkvnTPrUp8Mh5hCSNZcHtzvPvc1DezVXLHEkIU=; b=JLGCVgDzo9s+qHD8BsKLDF53V6RM8HunbVPnuQW4t5TilHbrW6346+Lwb9y6ELIosG ioq4sjUzCZxQKVmj1CWz2vf8OH//NddEi1hhA6rJfNbJvLW2733rqaZuzRdxii/ulD0b 2udromzEu/ZfTfOCcscum6LNliSXRtg9Zj273uyafcXORplvRzM7dCokrNOudxMAMt+6 ZSESg+eAjuj/o0Ipr6Tl8efV+/ZGPT7Xxk88VyLFyEtDwiAy9xz+BVYy6rCZGlRkoZpr 8c+sKGlhwMGPo7ltIkNK/kPq50pivvhsyf2wA5QlhNlvnBA6t0JE4vCxAKobRq15eq2P bB6g== X-Gm-Message-State: AA+aEWZQgyK4TVMQekHr1zwKPszyopP6oZ5OUSm4fy/VyHHtGIEva/Pf chPgLn9XM9x6xikRTe4OJj+hXQ== X-Google-Smtp-Source: AFSGD/VxMIvkKMJN20PrlNmfRQsnh87soyoztJ0soSmpfPjVKjwELaTQjCWXdKAYpnkQNJyv1EA85g== X-Received: by 2002:a62:5a03:: with SMTP id o3mr22188333pfb.19.1545263754440; Wed, 19 Dec 2018 15:55:54 -0800 (PST) Received: from mka.mtv.corp.google.com ([2620:15c:202:1:75a:3f6e:21d:9374]) by smtp.gmail.com with ESMTPSA id t67sm37045048pfd.90.2018.12.19.15.55.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 15:55:53 -0800 (PST) From: Matthias Kaehlcke To: Rob Clark , David Airlie , Rob Herring , Mark Rutland , Andy Gross , David Brown Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Archit Taneja , Sean Paul , Rajesh Yadav , Douglas Anderson , Stephen Boyd , Jeykumar Sankaran , Matthias Kaehlcke Subject: [PATCH v5 7/8] arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs Date: Wed, 19 Dec 2018 15:55:27 -0800 Message-Id: <20181219235528.114830-8-mka@chromium.org> X-Mailer: git-send-email 2.20.1.415.g653613c723-goog In-Reply-To: <20181219235528.114830-1-mka@chromium.org> References: <20181219235528.114830-1-mka@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously hardcoded in the PLL 'driver' for the 10nm PHY. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd --- based on "[v6] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file" (https://patchwork.kernel.org/patch/10712827/) Changes in v5: - rebased on v6 of DPU DT patch Changes in v4: - added 'Reviewed-by: Stephen Boyd ' tag Changes in v3: - added 'Reviewed-by: Douglas Anderson ' tag Changes in v2: - patch added to the series --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 3e3ffe096f18a..f278f08906d21 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1378,8 +1378,9 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; status = "disabled"; }; @@ -1444,8 +1445,9 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; status = "disabled"; }; From patchwork Wed Dec 19 23:55:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 10738329 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5C61413B5 for ; Wed, 19 Dec 2018 23:56:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4CF5C286B0 for ; Wed, 19 Dec 2018 23:56:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 40F3D28895; Wed, 19 Dec 2018 23:56:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E8C87286B0 for ; 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Wed, 19 Dec 2018 15:55:56 -0800 (PST) Received: from mka.mtv.corp.google.com ([2620:15c:202:1:75a:3f6e:21d:9374]) by smtp.gmail.com with ESMTPSA id t67sm37045048pfd.90.2018.12.19.15.55.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 15:55:55 -0800 (PST) From: Matthias Kaehlcke To: Rob Clark , David Airlie , Rob Herring , Mark Rutland , Andy Gross , David Brown Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Archit Taneja , Sean Paul , Rajesh Yadav , Douglas Anderson , Stephen Boyd , Jeykumar Sankaran , Matthias Kaehlcke Subject: [PATCH v5 8/8] ARM: dts: qcom-apq8064: Set 'xo_board' as ref clock of the DSI PHY Date: Wed, 19 Dec 2018 15:55:28 -0800 Message-Id: <20181219235528.114830-9-mka@chromium.org> X-Mailer: git-send-email 2.20.1.415.g653613c723-goog In-Reply-To: <20181219235528.114830-1-mka@chromium.org> References: <20181219235528.114830-1-mka@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add 'xo_board' as ref clock for the DSI PHY, it was previously hardcoded in the PLL 'driver' for the 28nm 8960 PHY. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd --- Changes in v5: - none Changes in v4: - added 'Reviewed-by: Stephen Boyd ' tag Changes in v3: - patch added to the series --- arch/arm/boot/dts/qcom-apq8064.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 48c3cf4276101..d337ae9326cd8 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1338,8 +1338,9 @@ <0x04700300 0x200>, <0x04700500 0x5c>; reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; - clock-names = "iface_clk"; - clocks = <&mmcc DSI_M_AHB_CLK>; + clock-names = "iface_clk", "ref"; + clocks = <&mmcc DSI_M_AHB_CLK>, + <&xo_board>; };