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Sun, 05 Dec 2021 15:16:24 -0800 (PST) Received: from localhost.localdomain ([2a01:e34:ed2f:f020:1cec:4235:bb04:b944]) by smtp.gmail.com with ESMTPSA id c10sm10715312wrb.81.2021.12.05.15.16.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Dec 2021 15:16:24 -0800 (PST) From: Daniel Lezcano To: daniel.lezcano@linaro.org, robh@kernel.org Cc: arnd@linaro.org, heiko@sntech.de, ulf.hansson@linaro.org, rjw@rjwysocki.net, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, lukasz.luba@arm.com, Robin Murphy , Rob Herring , Johan Jonker , Helen Koike , Brian Norris , Elaine Zhang , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support) Subject: [PATCH v4 2/5] arm64: dts: rockchip: Add powerzones definition for rock960 Date: Mon, 6 Dec 2021 00:15:54 +0100 Message-Id: <20211205231558.779698-2-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211205231558.779698-1-daniel.lezcano@linaro.org> References: <20211205231558.779698-1-daniel.lezcano@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211205_151627_446225_5A93C8B3 X-CRM114-Status: GOOD ( 10.39 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add the powerzones description. This first step introduces the big, the little as powerzone places. Cc: Robin Murphy Reviewed-by: Ulf Hansson Signed-off-by: Daniel Lezcano --- V4: - Added missing powerzone-cells - Changed powerzone name to comply with the pattern property V3: - Remove GPU section as no power is available (yet) - Remove '#powerzone-cells' conforming to the bindings change V2: - Move description in the SoC dtsi specific file V1: Initial post --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index d3cdf6f42a30..901515898b5e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -76,6 +76,7 @@ cpu_l0: cpu@0 { #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + powerzone = <&PKG_PZ>; }; cpu_l1: cpu@1 { @@ -88,6 +89,7 @@ cpu_l1: cpu@1 { #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + powerzone = <&PKG_PZ>; }; cpu_l2: cpu@2 { @@ -100,6 +102,7 @@ cpu_l2: cpu@2 { #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + powerzone = <&PKG_PZ>; }; cpu_l3: cpu@3 { @@ -112,6 +115,7 @@ cpu_l3: cpu@3 { #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + powerzone = <&PKG_PZ>; }; cpu_b0: cpu@100 { @@ -124,6 +128,7 @@ cpu_b0: cpu@100 { #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + powerzone = <&PKG_PZ>; thermal-idle { #cooling-cells = <2>; @@ -142,6 +147,7 @@ cpu_b1: cpu@101 { #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + powerzone = <&PKG_PZ>; thermal-idle { #cooling-cells = <2>; @@ -791,6 +797,18 @@ spi5: spi@ff200000 { status = "disabled"; }; + powerzones { + + PKG_PZ: powerzone-pkg { + #powerzone-cells = <0>; + powerzone = <&SOC_PZ>; + }; + + SOC_PZ: powerzone-soc { + #powerzone-cells = <0>; + }; + }; + thermal_zones: thermal-zones { cpu_thermal: cpu-thermal { polling-delay-passive = <100>;