From patchwork Wed Dec 8 04:04:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12663455 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81BC4C4332F for ; Wed, 8 Dec 2021 04:04:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232306AbhLHEIL (ORCPT ); Tue, 7 Dec 2021 23:08:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244077AbhLHEIK (ORCPT ); Tue, 7 Dec 2021 23:08:10 -0500 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75F76C061574; Tue, 7 Dec 2021 20:04:39 -0800 (PST) Received: by mail-pg1-x535.google.com with SMTP id r5so952081pgi.6; Tue, 07 Dec 2021 20:04:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4HXxSu2gPMhcps5sa6jyk5e2IIZg5iM9c1rXs+VhM6A=; b=iqOfLIN7fCiWY7C+553okIzVz1isalKGAq39L/xo9MHJg+7Xg8sJ3fhzbJUDk62Vzz o7VtgLVuunOQl4Yry45IF+HKpQxT6I5YC4yL11OcqS+WsPPzLPNL0NUJ1Rtyv6x92Qsz D4pUFl2LL1VRH2sGvlpOaDwTpmeSA+R7bkgSMvbfnYjh3Lv7++CQuI5iymiih8ATJsfN 8Jk1x2wFbfbSTs9OAITPBbp4zwLznjL5IoXp3WQd2q+Hf/tRIFtIJEKUipPgu1SMc+JH WzECqubp33RMJX4Rcas2PCtaDv9HDFT99kYm95XueBT4GGhuFSFhM/tzA+Q6xPTioyXi 5uDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4HXxSu2gPMhcps5sa6jyk5e2IIZg5iM9c1rXs+VhM6A=; b=a5Emq9tNo1pdfVcPtxVa8Ssa9xdtb5hFmWicb9EPFOIgFRCOj13NchkB/tYLjwAyJQ c9Bt9ynfFA+ZyTxbGvm7YqR7VN+tJQf3lcZOwTrk/QO1jlLtnS1W5DenMY0VXxVzQe4l ViuP29hN7mi5CId8w/6CxffkCbe9K2lwzIoLtYtdxB5/HZedDyfoq4bpkiejwZoWIJJQ ugb3Q04OCLH2RNMzRyfqzaRsuZ+MgXknhJEir0lbnKSzyyMWsahUuONZpjn9Se6ioTeK kDPhWyV8ZYPvu5wYUW54Git30F/z5IoRArXbrb97r1bWTqwSzkhpU2CJ4PG4rtZ5ihe5 GgMw== X-Gm-Message-State: AOAM5328ZfJoEIWHhRSxn6/Jku2k3yWoGj2c2Zceb/kfphXf6CWwN1ze O3KXxO5+nCRsVUvW5OMYRV1QfZgNOyQ= X-Google-Smtp-Source: ABdhPJw3Z63ln1wMYmIq8JnnWDgqOMGmdjyelgUJgU/3ubh8JNENwUyXKiDRafZp+CM5D0lKgBcjxQ== X-Received: by 2002:a63:85c3:: with SMTP id u186mr27255326pgd.201.1638936278516; Tue, 07 Dec 2021 20:04:38 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id c18sm1320684pfl.201.2021.12.07.20.04.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Dec 2021 20:04:38 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Bjorn Helgaas , Rob Herring , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM IPROC ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 1/6] ARM: dts: Cygnus: Fixed iProc PCIe controller properties Date: Tue, 7 Dec 2021 20:04:27 -0800 Message-Id: <20211208040432.3658355-2-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211208040432.3658355-1-f.fainelli@gmail.com> References: <20211208040432.3658355-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property and add the missing 'interrupt-controller' property which is necessary. We also need to re-arrange the 'ranges' property to show the two cells as being separate instead of combined since the DT checker is not able to differentiate otherwise. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 8ecb7861ce10..d6e2b2ba3a19 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -274,8 +274,8 @@ pcie0: pcie@18012000 { #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0 0x28000000 0 0x00010000 - 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; + ranges = <0x81000000 0 0 0x28000000 0 0x00010000>, + <0x82000000 0 0x20000000 0x20000000 0 0x04000000>; phys = <&pcie0_phy>; phy-names = "pcie-phy"; @@ -283,7 +283,7 @@ pcie0: pcie@18012000 { status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -298,6 +298,7 @@ pcie1: pcie@18013000 { compatible = "brcm,iproc-pcie"; reg = <0x18013000 0x1000>; + interrupt-controller; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; @@ -309,8 +310,8 @@ pcie1: pcie@18013000 { #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0 0x48000000 0 0x00010000 - 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; + ranges = <0x81000000 0 0 0x48000000 0 0x00010000>, + <0x82000000 0 0x40000000 0x40000000 0 0x04000000>; phys = <&pcie1_phy>; phy-names = "pcie-phy"; @@ -318,7 +319,7 @@ pcie1: pcie@18013000 { status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; From patchwork Wed Dec 8 04:04:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12663457 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EC01C4332F for ; Wed, 8 Dec 2021 04:04:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244077AbhLHEIN (ORCPT ); Tue, 7 Dec 2021 23:08:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232257AbhLHEIM (ORCPT ); Tue, 7 Dec 2021 23:08:12 -0500 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1B8FC061756; Tue, 7 Dec 2021 20:04:40 -0800 (PST) Received: by mail-pg1-x529.google.com with SMTP id k4so944719pgb.8; Tue, 07 Dec 2021 20:04:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=a9TA9nZ89a//BemP2uNfcdJdyv/5bJCk0Nuq1NhjtJE=; b=EdYzLhY2O7I+PIs0LpAAJf/zEUszq2DAtC8dRvwY9yXaOwKKTdeFd8Sf+tbhtD4Nyo zVwlHYEjeUohtYuGg0FJMWWpFmKdmfR1EkO9wB66LQ9H5OolGCUHCx2Bi3rePRtMsfC/ nXjGXOsMrNrlR82VQZgMxgmthlnU9usTR0sXsXhc2TUAO9wDV3qWF/E7MfF2hBx9zU2R U5UFp7cVAhSgeKnDXU2yXRryEC7xs4kFGKMOv50s4bDcoK7NY6EPJCbAw6xT4KqSNEbG n9Vo6okpuYWlGsNAX6vzFdfC3FIa6Vsm84XdWgvXOkMkaLocoPrOhZfdaqOiso7DKuOl UM1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a9TA9nZ89a//BemP2uNfcdJdyv/5bJCk0Nuq1NhjtJE=; b=yfut3hV/OVDVw9TuVmoOqxu+hY/tZx9sYOpTnc3ORJDog5RdOE0dyEOJ4PrhntUtLu /t1WYqojbe7Rxe+Ch/DeOag/Rrok+j/OKALAsPhegR2bBO/wNITkeCZ79oCP38gMvHzC n9+qciC8URVefUjvK9ENSao1E4UpbAu4n++oYjSRiREl0JsN0FEmiWmemhrTcDH4VVlR 0eK36FZ8B07rDptnGyD7y59gSzA0wnfhNkYC5/fnj7fwon3S81ZroV4gfnN9Mj3oxWUk +HQt41PcSF5/884HU8gX6gNcljZAy/a+qwX2RwadpKGgU3tYSfYdImRZLSuEECrHvdTL K4lA== X-Gm-Message-State: AOAM531mVIU1rsYqMsw04rjeGUNrafo6gbA/9L25My1RovnYYFfooSN4 6pHuyOmElIUc0UN577PJxcCujF4z2I0= X-Google-Smtp-Source: ABdhPJzGkKR5b+RzpkMH3/mBvr034Po/exe+doSkL1WfXQ54wpUHZ9xmtBGjRpiG2xFzW/3wCcXZQg== X-Received: by 2002:a63:150c:: with SMTP id v12mr27426514pgl.442.1638936279988; Tue, 07 Dec 2021 20:04:39 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id c18sm1320684pfl.201.2021.12.07.20.04.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Dec 2021 20:04:39 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Bjorn Helgaas , Rob Herring , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM IPROC ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 2/6] ARM: dts: Cygnus: Update PCIe PHY node unit name(s) Date: Tue, 7 Dec 2021 20:04:28 -0800 Message-Id: <20211208040432.3658355-3-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211208040432.3658355-1-f.fainelli@gmail.com> References: <20211208040432.3658355-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Update the PCIe PHY node unit name and its sub-nodes to help with upcoming changes converting the Cygnus PCIe PHY DT binding to YAML and later the iProc PCIe controller binding to YAML. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index d6e2b2ba3a19..8153b60c87b7 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -112,18 +112,18 @@ otp: otp@301c800 { status = "disabled"; }; - pcie_phy: phy@301d0a0 { + pcie_phy: pcie_phy@301d0a0 { compatible = "brcm,cygnus-pcie-phy"; reg = <0x0301d0a0 0x14>; #address-cells = <1>; #size-cells = <0>; - pcie0_phy: phy@0 { + pcie0_phy: pcie-phy@0 { reg = <0>; #phy-cells = <0>; }; - pcie1_phy: phy@1 { + pcie1_phy: pcie-phy@1 { reg = <1>; #phy-cells = <0>; }; From patchwork Wed Dec 8 04:04:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12663459 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 984D7C433FE for ; Wed, 8 Dec 2021 04:04:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232257AbhLHEIP (ORCPT ); Tue, 7 Dec 2021 23:08:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244082AbhLHEIN (ORCPT ); Tue, 7 Dec 2021 23:08:13 -0500 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63C98C061574; Tue, 7 Dec 2021 20:04:42 -0800 (PST) Received: by mail-pg1-x52f.google.com with SMTP id 71so963881pgb.4; Tue, 07 Dec 2021 20:04:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1v15Gl8TJzLJfCjgx7PA4whHDDqL64AFLHw1EUfuQI4=; b=FU1QcCpCE7EGNyFNHu48B9UcmAm3UYXrZkZ7MaZceXZGKkJcGLY67bUXNYtkDe9Zw/ hZJxeySLlkSjRAUKEZLe3xDC+BboqUmaiIQvrkCs/3+oNKsIMiN6h2fn5LnxCwn3rUw/ 3kr9fIiCLyEh6hDFOZmWvNoAUfCjSfVah2qct3XseCiO2AeADtvHP8zKUw4Ias+05cKz Ptc7i82BmQl6OZH6pJs+XMhXhveakvPPZP5F6fXiHx2HeCw+Sa+OdXQZVob8J9aEVmoS wMFib8k576EvJNz2JH7HoZ6tciWsE/HZct24LmRP7z7bpsfgah2Wfy0GRT8L2ZAI5RTQ tp9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1v15Gl8TJzLJfCjgx7PA4whHDDqL64AFLHw1EUfuQI4=; b=CaVQE9ZUzCdAOS+/Balo5uesdEx8zbW01LVPV9kUDJ+rWM4YGje6JjI3pV/4yaNPmA 9jNyghVYSZb2LWTUTZM76KUkvHUBweoeqsmVOJQlap7KlTNSav8VfGh7EgTSkLbtfms7 iciNwQttURGkpN4p8aryu7kRD5nthCfUrhKZge1uK1N9z5CfmZ2fm3KAPaNbOHmJgyuW HTUuiwytdJSsf+eHpBe0B3zD35GB1PxZr51EvORI6s7lP6GmJGSgBH47sL1HKqDWqs3L p7yiWg2pBDK2bL5MgjSJUxneYfSZsOx6KV3QCjG04HzdfBbyK3kZJzeXoE9YXOSmiuTA 2HZw== X-Gm-Message-State: AOAM532OEkUz0ePZq0GYZ+p+eFELzspn7HxtUj3On4oy6oE2DStb2StG 9Ni5RskgdOU8kRnYqcdc/P9mIynRLIY= X-Google-Smtp-Source: ABdhPJzh2O808XvLmB994pj/JZZ0i94ctZlVmqhtaGF16YifWsv51Gg/0FN2yWXb5KskySsIbn0SHQ== X-Received: by 2002:a63:81c8:: with SMTP id t191mr27145508pgd.369.1638936281529; Tue, 07 Dec 2021 20:04:41 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id c18sm1320684pfl.201.2021.12.07.20.04.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Dec 2021 20:04:41 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Bjorn Helgaas , Rob Herring , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM IPROC ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 3/6] ARM: dts: HR2: Fixed iProc PCIe MSI sub-node Date: Tue, 7 Dec 2021 20:04:29 -0800 Message-Id: <20211208040432.3658355-4-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211208040432.3658355-1-f.fainelli@gmail.com> References: <20211208040432.3658355-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-hr2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi index 84cda16f68a2..33e6ba63a1ee 100644 --- a/arch/arm/boot/dts/bcm-hr2.dtsi +++ b/arch/arm/boot/dts/bcm-hr2.dtsi @@ -318,7 +318,7 @@ pcie0: pcie@18012000 { status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -354,7 +354,7 @@ pcie1: pcie@18013000 { status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; From patchwork Wed Dec 8 04:04:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12663461 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BA71C433EF for ; Wed, 8 Dec 2021 04:04:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244087AbhLHEIQ (ORCPT ); Tue, 7 Dec 2021 23:08:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244092AbhLHEIP (ORCPT ); Tue, 7 Dec 2021 23:08:15 -0500 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC764C061574; Tue, 7 Dec 2021 20:04:43 -0800 (PST) Received: by mail-pl1-x62b.google.com with SMTP id z6so695997plk.6; Tue, 07 Dec 2021 20:04:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6PtQ+iCOtg8wKI/383IxFyqZ9i0rudNbH4n4NHCffbA=; b=hiBHP3RLA2HLAaYLJqIfsdqkg/LQ3RY9Gjy0+4n0PnQsg6ccgRNSmdzhVtUDqSZ8kd QqMiTvwyURKDFr/t4rWZxhVPA4nVVwq5PxEpIf77EFetpEx6ATh2mwNSY80dNT0GRefP 1A3V36zjGo4/QsjmRsYxC67yK1sk6S68DFiRJja4niRFx48BcMSKe+eYNx+K1PRrsIhW GUmrWNALFT6ktpZX+noXJxa8u77g1ajAoXVlFJLD8/lFJB8Csn+iz19Gn6Grti4tvvYH zVF4MAUAwRsimQxpIQc5T1AVEo3T0NxYmaDRPla3kUh8njqr7mCNowFK9kmxE806Zb7B YZNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6PtQ+iCOtg8wKI/383IxFyqZ9i0rudNbH4n4NHCffbA=; b=GQs5WSl5/SNoUngYM93HxuFnz/2TEeTo2zBxP2Q6ANsOu8Szw/27KuNOtA00Np7RkV AVbxhlypsRHQIXvllUYGw+m5iOpVyBMgtDCTFc818lKezyzmMYILLJ+2i9c7xEJZZbja /H9uXZVugCf2jJVuc7mjbetmS//Juf57g/+mlgCmO/GhiYjy7QigAFtZA9AyHyn0VD16 RWJNZ4m5LT564grHSjc2MW7NUZiextzpHvAffPDfswrlra5SikpyBAkuapoG1FignQ+R k5yuQ0CwtGHFghSB7BsUYA80KqiB9kyV/lmh7KsQYNXl40x111iGoktGBUiQCm+AdMb6 ukRw== X-Gm-Message-State: AOAM530o9pOxkabdQQPdNznm+yqOIrY6jW8mQemdtBgwKX89AVxrYGuD lvD3+zjn+R9HUDSE6EKhfpa0f3s16JI= X-Google-Smtp-Source: ABdhPJxmAPfb0esNolnSCnGT4tzw+ApkU7E/3KxYmMLFUg/Cq7uItECQ35tWeSoqBDIDX/2iXQRRoA== X-Received: by 2002:a17:90b:4b03:: with SMTP id lx3mr4182432pjb.18.1638936283046; Tue, 07 Dec 2021 20:04:43 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id c18sm1320684pfl.201.2021.12.07.20.04.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Dec 2021 20:04:42 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Bjorn Helgaas , Rob Herring , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM IPROC ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 4/6] ARM: dts: NSP: Fixed iProc PCIe MSI sub-node Date: Tue, 7 Dec 2021 20:04:30 -0800 Message-Id: <20211208040432.3658355-5-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211208040432.3658355-1-f.fainelli@gmail.com> References: <20211208040432.3658355-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 1c08daa18858..f242763c3bde 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -587,7 +587,7 @@ pcie0: pcie@18012000 { status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -624,7 +624,7 @@ pcie1: pcie@18013000 { status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -661,7 +661,7 @@ pcie2: pcie@18014000 { status = "disabled"; msi-parent = <&msi2>; - msi2: msi-controller { + msi2: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; From patchwork Wed Dec 8 04:04:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12663463 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87242C433EF for ; Wed, 8 Dec 2021 04:04:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244104AbhLHEIU (ORCPT ); Tue, 7 Dec 2021 23:08:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232536AbhLHEIQ (ORCPT ); Tue, 7 Dec 2021 23:08:16 -0500 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D0AFC061756; Tue, 7 Dec 2021 20:04:45 -0800 (PST) Received: by mail-pf1-x431.google.com with SMTP id k64so1292703pfd.11; Tue, 07 Dec 2021 20:04:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ew71xhC4xQ/czNjt0atU4xfLjLk+tfPXgytWCNx3psE=; b=FD8jk+RGxtkV5gLd8PNnst18NdpASQ+oqiVppQhVBHHlQjvKC5t0g9/eReu9F0pFwl TQ4L1GlZB51VECXEbj7JfhAE4L7gleM0eF1sZMIQdnLFmAglipuCFlzOZyL/1kUUde7x Deb2XYeje5su0L9LYdejYVIF9L0aE6jl8kPRwl5BO+tdhTQIok31IAzTIhgc7y1JTR03 c2KcYuyD4KJ5AWJn/jYWrJRtaX9E7gCCr+v76lwvox6gmJU31s9cCVhRJD/yFpef06+e Lh3zQNYeyVfJ6jU6pLRbuvLNLRuFwA2UKGzfCO+zrtLZ8xeORH8omTyMxpciRqzwVq5M 0Zqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ew71xhC4xQ/czNjt0atU4xfLjLk+tfPXgytWCNx3psE=; b=4kyQ7KHlCd0DVyNtBEsD63VOBIA70epmR9fqs3ajpNzA6jqEoBTaWIzE3Bbz/19ogi xvOLnXvfg6lzUEiO2566eXC2e7TLhdTXXLfK/tN14NKt12OAn48Y/7d4RzPX952Zm4Iy HsWqOD1bGlID5ZMIfi+bwgbsJdwVZdSoXeJtGw9D7ktDJgb8e+QL1Vk8ZRD/10tbg4F/ 8IX25B7yU5EZS3VoZksKeDbYyuE4TY9l1QLZfeWRwP9mVuKmfb3cQAj62Jj2pa7JadHc 98xW/cHnSEV0Im2uAKq24RjRce5o2QYY96HWTHtm+kEH0cxG7AyeUORhIqTh+bYO/LJX 5pAQ== X-Gm-Message-State: AOAM5339fFDfuZAS8wY7hjcz9Iv2wz4EduQCIMo1mJK4nbt5Fg/Pbv2w W3n9yO81BRHAFae/+5PV0YiDwWmiuM0= X-Google-Smtp-Source: ABdhPJzfOnYFR8mgGOmbEWPXYM9+Iqwkas0/pMPuHNBApD/gbRwxD7NUtSaQ8YnelpBkf3dFGyYpQA== X-Received: by 2002:a63:4f22:: with SMTP id d34mr26659724pgb.415.1638936284540; Tue, 07 Dec 2021 20:04:44 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id c18sm1320684pfl.201.2021.12.07.20.04.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Dec 2021 20:04:44 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Bjorn Helgaas , Rob Herring , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM IPROC ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 5/6] dt-bindings: phy: Convert Cygnus PCIe PHY to YAML Date: Tue, 7 Dec 2021 20:04:31 -0800 Message-Id: <20211208040432.3658355-6-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211208040432.3658355-1-f.fainelli@gmail.com> References: <20211208040432.3658355-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Convert the Broadcom Cygnus PCIe PHY Device Tree binding t YAML to help with validation. Signed-off-by: Florian Fainelli --- .../bindings/phy/brcm,cygnus-pcie-phy.txt | 47 ------------ .../bindings/phy/brcm,cygnus-pcie-phy.yaml | 76 +++++++++++++++++++ 2 files changed, 76 insertions(+), 47 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt create mode 100644 Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt b/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt deleted file mode 100644 index 10efff28b52b..000000000000 --- a/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt +++ /dev/null @@ -1,47 +0,0 @@ -Broadcom Cygnus PCIe PHY - -Required properties: -- compatible: must be "brcm,cygnus-pcie-phy" -- reg: base address and length of the PCIe PHY block -- #address-cells: must be 1 -- #size-cells: must be 0 - -Each PCIe PHY should be represented by a child node - -Required properties For the child node: -- reg: the PHY ID -0 - PCIe RC 0 -1 - PCIe RC 1 -- #phy-cells: must be 0 - -Example: - pcie_phy: phy@301d0a0 { - compatible = "brcm,cygnus-pcie-phy"; - reg = <0x0301d0a0 0x14>; - - pcie0_phy: phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - - pcie1_phy: phy@1 { - reg = <1>; - #phy-cells = <0>; - }; - }; - - /* users of the PCIe phy */ - - pcie0: pcie@18012000 { - ... - ... - phys = <&pcie0_phy>; - phy-names = "pcie-phy"; - }; - - pcie1: pcie@18013000 { - ... - ... - phys = ; - phy-names = "pcie-phy"; - }; diff --git a/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.yaml new file mode 100644 index 000000000000..045699c65779 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/brcm,cygnus-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Cygnus PCIe PHY + +maintainers: + - Ray Jui + - Scott Branden + +properties: + $nodename: + pattern: "^pcie[-|_]phy(@.*)?$" + + compatible: + items: + - const: brcm,cygnus-pcie-phy + + reg: + maxItems: 1 + description: > + Base address and length of the PCIe PHY block + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^pcie-phy@[0-9]+$": + type: object + description: > + PCIe PHY child nodes + + properties: + reg: + maxItems: 1 + description: > + The PCIe PHY port number + + "#phy-cells": + const: 0 + + required: + - reg + - "#phy-cells" + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + pcie_phy: pcie_phy@301d0a0 { + compatible = "brcm,cygnus-pcie-phy"; + reg = <0x0301d0a0 0x14>; + #address-cells = <1>; + #size-cells = <0>; + + pcie0_phy: pcie-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + pcie1_phy: pcie-phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; From patchwork Wed Dec 8 04:04:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12663465 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0245DC433F5 for ; Wed, 8 Dec 2021 04:04:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244135AbhLHEIU (ORCPT ); Tue, 7 Dec 2021 23:08:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244117AbhLHEIS (ORCPT ); Tue, 7 Dec 2021 23:08:18 -0500 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C46EC061746; Tue, 7 Dec 2021 20:04:47 -0800 (PST) Received: by mail-pj1-x102c.google.com with SMTP id fv9-20020a17090b0e8900b001a6a5ab1392so1103956pjb.1; Tue, 07 Dec 2021 20:04:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g6aBobBZLV580q2x9akXwvTNH0acamOZoRmazf1DKgk=; b=hSI06FZkaUly2AXBn62J71FSc2crmJMa1QQXAsLdw6N5mzwn9NDnlrzDAKLPUnqDvj RyivxOJKFDwsN//IVXQlTDplGg9igbs2Vej59lF5Kry3aoSMcW0sa0cxZM9VrMTEKgDY FEi+KfiEUPF4Aew9/FxUkIUSOZjBCEcaNEqX0GRhDM2AaV1Wg+aPQUDnpkT8QZZQtqny gTr8EfBtpmgiX0uom/GhHgyXvIoxEVNDe+R9H4jHlUsODflyJICyo/LSr4GRPxHjKb8x wnk5NOBVBwDsWPfDPAMvY9L6bP2DyoN1RlA2nkbRDshVrcNeUBU9OP9aKKaKZTTOIpGH MB+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g6aBobBZLV580q2x9akXwvTNH0acamOZoRmazf1DKgk=; b=zZRufGTvS1sv2o/nDYYBxP30z6Y3v/DklDNiYobvXg+ZltlQOjKmoxNKpQ56VanaXN DILumOYsAodkoMC7xe+raCIazykFyx6R+cYU54sF/gtw3+7mubeWm4wxXU4AE8S0ck6+ zGtmCUFyU/0h031zf0sZ4lK38yjBrQoMO5hG55EAj4HFN79X2j+n0fJGAx18VoJCJrxg Yoa+tkySuAGo48nQoSLVsMgxi5uR32zLACW1Pj+HOaPFGU2u5JrpJo2HlIS9nla5WXCW N8jFR9/2X6GKlu8v4aAoxILPpwy12SnhzOJ+CG0wELrYYa30aTUHbSF4U+/GCEf90m0y 53uQ== X-Gm-Message-State: AOAM531IqMn9GnmUSPBV0b/w7nBBqWAnty2QkIAX3h2zArdDPamsZlOL 4eANn6L8kqf6uZBZzLGT2x7siZ79BUo= X-Google-Smtp-Source: ABdhPJwq1WhNY8jRUICV+NwDPToKXPwn5xZzgPGFjIAeO87p7aWko8jtw5mX3GPhdqRZLrDkcFB0rg== X-Received: by 2002:a17:903:32c7:b0:141:eb39:30b7 with SMTP id i7-20020a17090332c700b00141eb3930b7mr55942027plr.41.1638936286241; Tue, 07 Dec 2021 20:04:46 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id c18sm1320684pfl.201.2021.12.07.20.04.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Dec 2021 20:04:45 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Bjorn Helgaas , Rob Herring , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM IPROC ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 6/6] dt-bindings: pci: Convert iProc PCIe to YAML Date: Tue, 7 Dec 2021 20:04:32 -0800 Message-Id: <20211208040432.3658355-7-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211208040432.3658355-1-f.fainelli@gmail.com> References: <20211208040432.3658355-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Conver the iProc PCIe controller Device Tree binding to YAML now that all DTS in arch/arm and arch/arm64 have been fixed to be compliant. Signed-off-by: Florian Fainelli --- .../bindings/pci/brcm,iproc-pcie.txt | 133 ------------- .../bindings/pci/brcm,iproc-pcie.yaml | 176 ++++++++++++++++++ 2 files changed, 176 insertions(+), 133 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt deleted file mode 100644 index df065aa53a83..000000000000 --- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt +++ /dev/null @@ -1,133 +0,0 @@ -* Broadcom iProc PCIe controller with the platform bus interface - -Required properties: -- compatible: - "brcm,iproc-pcie" for the first generation of PAXB based controller, -used in SoCs including NSP, Cygnus, NS2, and Pegasus - "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based -controllers, used in Stingray - "brcm,iproc-pcie-paxc" for the first generation of PAXC based -controller, used in NS2 - "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based -controller, used in Stingray - PAXB-based root complex is used for external endpoint devices. PAXC-based -root complex is connected to emulated endpoint devices internal to the ASIC -- reg: base address and length of the PCIe controller I/O register space -- #interrupt-cells: set to <1> -- interrupt-map-mask and interrupt-map, standard PCI properties to define the - mapping of the PCIe interface to interrupt numbers -- linux,pci-domain: PCI domain ID. Should be unique for each host controller -- bus-range: PCI bus numbers covered -- #address-cells: set to <3> -- #size-cells: set to <2> -- device_type: set to "pci" -- ranges: ranges for the PCI memory and I/O regions - -Optional properties: -- phys: phandle of the PCIe PHY device -- phy-names: must be "pcie-phy" -- dma-coherent: present if DMA operations are coherent -- dma-ranges: Some PAXB-based root complexes do not have inbound mapping done - by the ASIC after power on reset. In this case, SW is required to configure -the mapping, based on inbound memory regions specified by this property. - -- brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done -by the ASIC after power on reset. In this case, SW needs to configure it - -If the brcm,pcie-ob property is present, the following properties become -effective: - -Required: -- brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal -address used by the iProc PCIe core (not the PCIe address) - -MSI support (optional): - -For older platforms without MSI integrated in the GIC, iProc PCIe core provides -an event queue based MSI support. The iProc MSI uses host memories to store -MSI posted writes in the event queues - -On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used - -- msi-map: Maps a Requester ID to an MSI controller and associated MSI -sideband data - -- msi-parent: Link to the device node of the MSI controller, used when no MSI -sideband data is passed between the iProc PCIe controller and the MSI -controller - -Refer to the following binding documents for more detailed description on -the use of 'msi-map' and 'msi-parent': - Documentation/devicetree/bindings/pci/pci-msi.txt - Documentation/devicetree/bindings/interrupt-controller/msi.txt - -When the iProc event queue based MSI is used, one needs to define the -following properties in the MSI device node: -- compatible: Must be "brcm,iproc-msi" -- msi-controller: claims itself as an MSI controller -- interrupts: List of interrupt IDs from its parent interrupt device - -Optional properties: -- brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that -require the interrupt enable registers to be set explicitly to enable MSI - -Example: - pcie0: pcie@18012000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18012000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; - - linux,pci-domain = <0>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x28000000 0 0x00010000 - 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; - - phys = <&phy 0 5>; - phy-names = "pcie-phy"; - - brcm,pcie-ob; - brcm,pcie-ob-axi-offset = <0x00000000>; - - msi-parent = <&msi0>; - - /* iProc event queue based MSI */ - msi0: msi@18012000 { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - }; - }; - - pcie1: pcie@18013000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18013000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; - - linux,pci-domain = <1>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x48000000 0 0x00010000 - 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; - - phys = <&phy 1 6>; - phy-names = "pcie-phy"; - }; diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml new file mode 100644 index 000000000000..a9d21d89a970 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml @@ -0,0 +1,176 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom iProc PCIe controller with the platform bus interface + +maintainers: + - Ray Jui + - Scott Branden + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + items: + - enum: + # for the first generation of PAXB based controller, used in SoCs + # including NSP, Cygnus, NS2, and Pegasus + - brcm,iproc-pcie + # for the second generation of PAXB-based controllers, used in + # Stingray + - brcm,iproc-pcie-paxb-v2 + # For the first generation of PAXC based controller, used in NS2 + - brcm,iproc-pcie-paxc + # For the second generation of PAXC based controller, used in Stingray + - brcm,iproc-pcie-paxc-v2 + + reg: + maxItems: 1 + description: > + Base address and length of the PCIe controller I/O register space + + interrupt-map: true + + interrupt-map-mask: true + + "#interrupt-cells": + const: 1 + + ranges: + minItems: 1 + maxItems: 2 + description: > + Ranges for the PCI memory and I/O regions + + phys: + maxItems: 1 + + phy-names: + items: + - const: pcie-phy + + dma-coherent: true + + "brcm,pcie-ob": + type: boolean + description: > + Some iProc SoCs do not have the outbound address mapping done by the + ASIC after power on reset. In this case, SW needs to configure it + + "brcm,pcie-ob-axi-offset": + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The offset from the AXI address to the internal address used by the + iProc PCIe core (not the PCIe address) + + msi: + type: object + properties: + compatible: + items: + - const: brcm,iproc-msi + + msi-parent: true + + msi-controller: true + + "brcm,pcie-msi-inten": + type: boolean + description: > + Needs to be present for some older iProc platforms that require the + interrupt enable registers to be set explicitly to enable MSI + +dependencies: + "brcm,pcie-ob-axi-offset": ["brcm,pcie-ob"] + "brcm,pcie-msi-inten": [msi-controller] + +required: + - compatible + - reg + - ranges + +if: + properties: + compatible: + contains: + enum: + - brcm,iproc-pcie +then: + required: + - interrupt-map + - interrupt-map-mask + +unevaluatedProperties: false + +examples: + - | + #include + + bus { + #address-cells = <1>; + #size-cells = <1>; + pcie0: pcie@18012000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18012000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; + + linux,pci-domain = <0>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x28000000 0 0x00010000>, + <0x82000000 0 0x20000000 0x20000000 0 0x04000000>; + + phys = <&phy 0 5>; + phy-names = "pcie-phy"; + + brcm,pcie-ob; + brcm,pcie-ob-axi-offset = <0x00000000>; + + msi-parent = <&msi0>; + + /* iProc event queue based MSI */ + msi0: msi { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + }; + + pcie1: pcie@18013000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18013000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; + + linux,pci-domain = <1>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x48000000 0 0x00010000>, + <0x82000000 0 0x40000000 0x40000000 0 0x04000000>; + + phys = <&phy 1 6>; + phy-names = "pcie-phy"; + }; + };